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    JJJJJ

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    Amandeep
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    JJJJJ

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    of 2

    CA-3 CSE 211 Computer Organization and Design

    Attempt all the questions 6 * 5=30


    SET-1 for odd roll numbers

    1) In certain scientific computations it is necessary to perform the arithmetic


    operation (Ai + Bi) (Ci + Di) with a stream of numbers. Specify a pipeline
    configuration to carry out this task. list the contents of all registers in the
    pipeline for i = 1 through 6. 5M
    2)
    Draw a space-time diagram for a six-segment pipeline showing the time it
    takes to process eight tasks. Determine the number of clock cycles that it
    takes to process 200 tasks in a six-segment pipeline. 5M

    3) Draw the architectural block diagram of ARM and explain data flow
    referring each unit. 5M
    4) A virtual memory has a page size of 2K(words). There are eight pages
    and four blocks. The associative memory page table contains the following
    entries:
    Page Block
    0 3
    2 1
    5 2
    6 0
    Make a list of all virtual addresses (In decimal) that will cause a page
    fault if used by the CPU. 5M
    5) Explain set (with 2-set) associative mapping cache. Consider a 4-way set
    associative mapped cache of size 64 KB with block size 512 bytes. The size
    of main memory is 256 KB. Find-
    a) Number of bits in tag
    b) Tag directory size 5M

    6) Consider page reference string of 1 2 3 0 5 0 1 2 1 4 5 0 7 1 2


    Using the first in first out (FIFO) page replacement algorithm, draw THREE
    (3) page frames (3 pages can be in memory at a time during process) for the
    above-mentioned page reference string. b Calculate the hit rate and fault rate
    for your answer. 5M
    CA-3 CSE 211 Computer Organization and Design
    Attempt all the questions 6 * 5=30
    SET-2 for even roll numbers

    1.`In certain scientific computations it is necessary to perform the arithmetic


    operation (Ai. Bi) + (Ci.Di) with a stream of numbers. Specify a pipeline
    configuration to carry out this task. list the contents of all registers in the
    pipeline for i = 1 through 6. 5M

    2.
    Draw a space-time diagram for a six-segment pipeline showing the time it
    takes to process ten tasks. Determine the number of clock cycles that it takes
    to process 200 tasks in a six-segment pipeline. 5M

    3. Brief about Graphics processing unit and differentiate CPU and GPU 5M

    4. Consider page reference string of 1 2 3 0 5 0 1 2 1 4 5 0 7 1 2


    Using the LRU page replacement algorithm, draw THREE (3) page frames
    (3 pages can be in memory at a time during process) for the above-
    mentioned page reference string. b Calculate the hit rate and fault rate for
    your answer. 5M

    5. Explain direct mapping cache. Consider a fully associative mapped cache of


    size 512 KB with block size 1 KB. There are 17 bits in the tag. Find- Size of
    main memory
    Tag directory size 5M

    6. A virtual memory has a page size of 2K(words). There are eight pages
    and four blocks. The associative memory page table contains the following
    entries:
    Page Block
    0 3
    2 1
    5 2
    6 0
    Make a list of all virtual addresses (In decimal) that will cause a page fault
    if used by the CPU. 5M

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