SacPower 智联创新 Preliminary RT7257E

3A, 17V, 340kHz Synchronous Step-Down Converter

General Description Features
The RT7257E is a high efficiency, monolithic z ±1.5% High Accuracy Feedback
synchronous step-down DC/DC converter that can Voltage z 4.5V to 17V Input Voltage
deliver up to 3A output current from a 4.5V to 17V Range
input supply. The RT7257E's current mode z 3A Output Current

architecture and external compensation allow the z Integrated N-MOSFET Switches

transient response to be optimized over a wide z Current Mode Control

range of loads and output capacitors. Cycle-by-cycle z Fixed Frequency Operation : 340kHz

current limit provides protection against shorted z Output Adjustable from 0.8V to 15V

outputs, and soft-start eliminates input current surge z Up to 95% Efficiency

during start-up. The RT7257E provides thermal z Programmable Soft-Start

shutdown protection. The low current (<3mA) shutdown z Stable with Low ESR Ceramic Output Capacitors

mode provides output disconnection, enabling easy z Cycle-by-Cycle Over Current Protection

power management in battery-powered systems. The z Input Under Voltage Lockout

RT7257E is available in an SOP-8 (Exposed Pad) z Thermal Shutdown Protection

package. z RoHS Compliant and Halogen Free

Ordering Information Applications

RT7257EN z Wireless AP/Router
z Set-Top-Box
Package Type
z Industrial and Commercial Low Power Systems
SP : SOP-8 (Exposed Pad-Option 2)
z LCD Monitors and TVs
Lead Plating System
z Green Electronics/Appliances
Z : ECO (Ecological Element with
Halogen Free and Pb free) z Point of Load Regulation of High-Performance DSPs

Note : Pin Configurations

Richtek products are :
(TOP VIEW)
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes. BOOT 8 SS
GND 7
VIN 2 EN
6 COMP
SW 9
3
5 FB
Marking Information GND 4

For marking information, contact our sales representative SOP-8 (Exposed Pad)
directly or through a Richtek distributor located in your
area.

联系人:钟先生 0755-83983280 E-mail:nikozhong@hotmail.com http//www.sacpower.net

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RT7257E Preliminary

Typical Application Circuit

2 1
VIN VIN BOOT
4.5V to 17V CBOOT
CIN L
10µF x 2 RT7257E
SW 3 100nF 10µH
Chip Enable VOUT
3.3V
7 EN R1
8 SS FB 5 75k COUT x 2
22µF
C CC
SS
0.1µF 4, 9 (Exposed Pad) 6 RC R2
COMP 4.7nF 12k
GND 24k

CP
Open

Table 1. Recommended Components Selection

V OUT (V) R1 (kW) R2 (kW) RC (kW) CC (nF) L (mH) COUT (mF)
8 27 3 24 4.7 22 22 x 2
5 62 11.8 18 4.7 15 22 x 2
3.3 75 24 12 4.7 10 22 x 2
2.5 25.5 12 8.2 4.7 6.8 22 x 2
1.5 10.5 12 3.6 4.7 3.6 22 x 2
1.2 12 24 3 4.7 3.6 22 x 2
1 3 12 2.7 4.7 3.6 22 x 2

Functional Pin Description

Pin No. Pin Name Pin Function
Bootstrap for High Side Gate Driver. Connect a 0.1mF or greater
1 BOOT ceramic capacitor from BOOT to SW pins.
Input Supply Voltage, 4.5V to 17V. Must bypass with a suitably large
2 VIN ceramic capacitor.
3 SW Switch Node. Connect this pin to an external L-C filter.
4, Ground. The exposed pad must be soldered to a large PCB and connected
GND
9 (Exposed to GND for maximum power dissipation.
Pad) Feedback Input. It is used to regulate the output of the converter to a set
FB value via an internal resistive voltage divider.
5
Compensation Node. COMP is used to compensate the regulation
COMP control loop. Connect a series RC network from COMP to GND. In some
6 cases, an additional capacitor from COMP to GND is required.
Enable Input. A logic high enables the converter; a logic low forces
EN the RT7257E into shutdown mode reducing the supply current to less than
7 3mA. Attach this pin to VIN with a 100kW pull up resistor for automatic
startup.
SS Soft-Start Control Input. SS controls the soft-start period. Connect a
8 capacitor from SS to GND to set the soft-start period. A 0.1mF
capacitor sets the soft-start period to 13.5ms.

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 Preliminary RT7257E
Function Block Diagram

VIN

Internal
Regulator Oscillator
Current Sense
Shutdown Slope Comp Amplifier
Comparator VA VCC Foldback + VA
1.2V + Control -
-
0.4V + BOOT
Lockout -
Comparator UV S Q 110mW
5k Comparator SW
EN - +
R Q 90mW
1.8V + -
Current
Comparator GND
VCC

6µA
0.8V +
SS +EA
-

FB COMP

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RT7257E Preliminary

Absolute Maximum (Note 1)

Ratings
z Supply Input Voltage, VIN ------------------------------------------------------------------------------------------ −0.3V to 20V
z Switch Voltage, SW ------------------------------------------------------------------------------------------------ −0.3V to (VIN +
0.3V) z VBOOT − VSW ---------------------------------------------------------------------------------------------------------- −0.3V to 6V
z Other Pins Voltage ------------------------------------------------------------------------------------------------- −0.3V to 20V

z Power Dissipation, PD @ TA = 25°C

SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------------------

1.333W z Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), qJA ----------------------------------------------------------------------------------------
75°C/W SOP-8 (Exposed Pad), qJC ---------------------------------------------------------------------------------------
15°C/W
z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260°C

z Junction Temperature ----------------------------------------------------------------------------------------------- 150°C

z Storage Temperature Range -------------------------------------------------------------------------------------- −65°C to

150°C z ESD Susceptibility (Note 3)

HBM (Human Body Mode) ---------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------
200V

Recommended Operating Conditions (Note 4)

z Supply Input Voltage, VIN ------------------------------------------------------------------------------------------ 4.5V to 17V
z Junction Temperature Range -------------------------------------------------------------------------------------- −40°C to
125°C z Ambient Temperature Range -------------------------------------------------------------------------------------- −40°C
to 85°C

Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Min Typ Max Unit
Conditions
Shutdown Supply -- 0.5 3 mA
Current VEN = 0V 1.2 mA
-- 0.8
Supply Current VEN = 3 V, V FB = 0.9V
0.788 0.8 0.812 V
Feedback Voltage VFB 4.5V £ VIN £ 17V
Error Amplifier G EA DIC = ±10mA -- 940 -- mA/V
T ransconductance
High Side Switch
On-Resistance RDS(ON )1 -- 110 -- mW

Low Side Switch

RDS(ON)2 -- 90 -- mW
On-Resistance
High Side Switch Leakage
VEN = 0V, VSW = 0V -- 0 10 mA
Current
Upper Switch Current Min. Duty Cycle, VBOOT − VSW = 4.8V -- 5.1 -- A
Limit
GCS -- 4.7 -- A/V
COMP to Current Sense
Transconductance 300 340 380 kHz
fOSC1
Oscillation Frequency
fOSC2 VFB = 0V -- 100 -- kHz
Short Circuit Oscillation
Frequency VFB = 0.7V -- 93 -- %
DMAX
Maximum Duty Cycle -- 100 -- ns
tON
Minimum On Time

To be continued
4
 Preliminary RT7257E
Parameter Symbol Test Conditions Min Typ Max Unit
EN Input Threshold Logic-High VIH 2 -- 5.5
Voltage V
Logic-Low VIL -- -- 0.4
Input Under Voltage Lockout Threshold VUVLO VIN Rising 3.8 4.2 4.5 V
Input Under Voltage Lockout Hysteresis -- 320 --
DVUVLO Soft-Start Current I SS VSS = 0V mV -- 6 --
Soft-Start Period t SS CSS = 0.1mF mA -- 13.5 --
Thermal Shutdown TSD ms
-- 150 -- °C

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. qJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of qJC is on the exposed pad of
the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

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RT7257E Preliminary

Typical Operating Characteristics

Efficiency vs. Load Current Reference Voltage vs. Input Voltage
100 0.820

90 0.815

Reference Voltage (V)

80 VIN = 4.5V
0.810
70 VIN = 12V
VIN = 17V
Efficiency (%)

60 0.805

50 0.800

40 0.795
30
0.790
20
0.785
10
VOUT = 3.3V VIN = 4.5V to 17V, VOUT = 3.3V, IOUT =
0 1A 0.780
0.01 0.1 1 10 4.5 7 9.5 12 14.5 17
Load Current (A) Input Voltage (V)

Reference Voltage vs. Temperature Output Voltage vs. Load Current

0.820 3.380

0.815
3.354
Reference Voltage (V)

0.810
Output Voltage (V)

0.805
3.328
VIN =
0.800 4.5V VIN = 12V
VIN = 17V
0.795 3.302

0.790
3.276
0.785
VIN = 12V, VOUT = 3.3V, IOUT = VOUT = 3.3V
1A 0.780 3.250
-50 -25 0 25 50 75 100 125 0 0.5 1 1.5 2 2.5 3
Temperature (°C) Load Current (A)

Switching Frequency vs. Input Switching Frequency vs. Temperature

Voltage 380 370

370 360

360 350
Switching Frequency
Switching Frequency

350
340
340
330
330
320
(kHz)1
(kHz)1

320
310
310
VOUT = 3.3V, IOUT = 0.3A VIN = 12V, VOUT = 3.3V, IOUT =
300 0.5A 300
4.5 7 9.5 12 14.5 17 -50 -25 0 25 50 75 100 125
Input Voltage (V) Temperature (°C)

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 Preliminary RT7257E

Current Limit vs. Temperature Load Transient Response

8

7
VOUT
(100mV/Div)
Current Limit (A)

4
IOUT
(2A/Div)
3

VIN = 12V, VOUT = 3.3V VIN = 12V, VOUT = 3.3V, IOUT = 0.2A to 3A
2
-50 -25 0 25 50 75 100 125 Time (250ms/Div)
Temperature (°C)

Load Transient Response Switching

VOUT
(10mV/Div)
VOUT
(100mV/Div)

VSW
(10V/Div)

IOUT
(2V/Div) IL
VIN = 12V, VOUT = 3.3V, IOUT = 1.5A to
(2A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 3A
3A
Time (1ms/Div)
Time (250ms/Div)

Power On from VIN Power Off from VIN

VIN VIN
(5V/Div) (5V/Div)

VOUT VOUT
(2V/Div) (2V/Div)

IL IL
(2A/Div) (2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = VIN = 12V, VOUT = 3.3V, IOUT = 3A
3A
Time (5ms/Div)
Time (5ms/Div)

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RT7257E Preliminary

Power On from EN Power Off from EN

VEN VEN
(5V/Div) (5V/Div)

VOUT VOUT
(2V/Div) (2V/Div)

IL IL
(2A/Div) (2A/Div)

VIN = 12V, VOUT = 3.3V, IOUT = VIN = 12V, VOUT = 3.3V, IOUT = 2A
2A
Time (5ms/Div)
Time (5ms/Div)

8
 Preliminary RT7257E
Application Information
The RT7257E is a synchronous high voltage buck Soft-Start
converter that can support the input voltage range from The RT7257E contains an external soft-start clamp that
4.5V to 17V and the output current can be up to 3A. gradually raises the output voltage. The soft-start
timing can be programmed by the external capacitor
Output Voltage Setting
between SS pin and GND. The chip provides a 6mA
The resistive divider allows the FB pin to sense the charge current for the external capacitor. If 0.1mF
output voltage as shown in Figure 1. capacitor is used to set the soft-start, it's period will be
VOUT 13.5ms (typ.).

Chip Enable Operation

R1
FB The EN pin is the chip enable input. Pulling the EN pin
low (<0.4V) will shutdown the device. During shutdown
RT7257E R2 mode, the RT7257E quiescent current drops to lower
GND than 3mA. Driving the EN pin high (>2V, < 17V) will turn
on the
device again. For external timing control (e.g.RC), the
EN
Figure 1. Output Voltage Setting pin can also be externally pulled high by adding a REN*
resistor and CEN* capacitor from the VIN pin (see
The output voltage is set by an external resistive Figure 5).
voltage divider according to the following equation : An external MOSFET can be added to implement
digital control on the EN pin when no system voltage
VOUT = VFB æç 1+ R1 ö÷
è R2 ø above 2V is available, as shown in Figure 3. In this
Where VFB is the feedback reference voltage (0.8V case, a 100kW pull-up resistor, REN, is connected
typ.). between VIN and the EN pin. MOSFET Q1 will be
under logic control to pull
External Bootstrap Diode down the EN pin.
1
Connect a 100nF low ESR ceramic capacitor VIN
2
VIN BOOT
CBOOT VOUT
CIN
between the BOOT pin and SW pin. This capacitor REN RT7257E
L
100k 3
SW
provides the gate driver voltage for the high side Chip Enable 7 EN
R1 COUT
MOSFET. Q1
5
8 FB
It is recommended to add an external bootstrap SS
CSS CC R2
4, RC
6
diode between an external 5V and BOOT pin for 9 (Exposed Pad)
GND
COMP
CP
efficiency improvement when input voltage is lower
than 5.5V or duty
ratio is higher than 65% .The bootstrap diode can be
a
low cost one such as IN4148 or BAT54. The external
Figure 3. Enable Control Circuit for Logic Control with
5V can be a 5V fixed input from system or a 5V output
Low Voltage
of the
RT7257E. Note that the external boot voltage must be
lower than 5.5V
To prevent enabling circuit when VIN is smaller than the
5V
VOUT target value, a resistive voltage divider can be
placed
between the input voltage and ground and connected to
BOOT the EN pin to adjust IC lockout threshold, as shown in
RT7257E 100nF Figure 4. For example, if an 8V output voltage is
SW regulated from a 12V input voltage, the resistor REN2
can be selected to set input lockout threshold larger than 8V.
Figure 2. External Bootstrap Diode

9
RT7257E Preliminary
VIN Table 2. Suggested Inductors for Typical
12V 2 1
VIN BOOT VOUT
CIN 8V Application Circuit
REN1 10µF x 2 RT7257E CBOOT
100k 3 L
7 EN SW Component Dimensions
Series
R1 Supplier (mm)
REN2 COUT
TDK VLF10045 10 x 9.7 x 4.5
8 FB 5
SS
CSS 4, CC R2 TDK SLF12565 12.5 x 12.5 x 6.5
6 RC
9 (Exposed Pad) COMP TAIYO
GND
CP NR8040 8x8x4
YUDEN

Figure 4. The Resistors can be Selected to Set

IC Lockout Threshold CIN and COUT Selection
The input capacitance, C IN, is needed to filter the
Inductor Selection trapezoidal current at the source of the high side
MOSFET. To prevent large ripple current, a low ESR
The inductor value and operating frequency determine
input capacitor sized for the maximum RMS current
the ripple current according to a specific input and
should be used. The
output voltage. The ripple current DIL increases with
RMS current is given by :
higher VIN and decreases with higher inductance.
VIN
IRMS = IOUT(MAX) VOU T −1
éV ù é V ù VIN VOUT
DIL = ê OUT ú ´ê 1− OUT
ú û
ë f ´L û ë V
IN This formula has a maximum at VIN = 2VOUT, where
Having a lower ripple current reduces not only the ESR IRMS = I OUT / 2. This simple worst case condition is
losses in the output capacitors but also the output commonly used for design because even significant
voltage ripple. High frequency with small ripple current deviations do not offer much relief.
can achieve the highest efficiency operation. However,
Choose a capacitor rated at a higher temperature
it requires a large inductor to achieve this goal.
than required. Several capacitors may also be
For the ripple current selection, the value of DIL = paralleled to meet size or height requirements in the
0.24(IMAX) will be a reasonable starting point. The design.
largest ripple current occurs at the highest VIN. To For the input capacitor, two 10mF low ESR
guarantee that the ripple current stays below the ceramic capacitors are recommended. For the
specified maximum, the inductor value should be recommended capacitor, please refer to Table 3 for
chosen according to the following equation : more details.
é V ù é
L =ê ´ 1 OUT The selection of COUT is determined by the required
I
VOUT ù ë úf ´êD L(MAX)
V û úë
IN(MAX) û ESR to minimize voltage ripple.
Moreover, the amount of bulk capacitance is also a
The inductor's current rating (caused a 40°C
key for COUT selection to ensure that the control loop is
temperature rising from 25°C ambient) should be
stable. Loop stability can be checked by viewing the
greater than the maximum load current and its
load transient response as described in a later section.
saturation current should be greater than the short
circuit peak current limit. Please The output ripple, DVOUT , is determined by :
see Table 2 for the inductor selection reference. DVOUT £ DI é ù
L ê ESR + 1 ú û
ë 8fCOUT

10
 Preliminary RT7257E
The output ripple will be the highest at the maximum EMI Consideration
input voltage since DIL increases with input voltage. Since parasitic inductance and capacitance effects in
Multiple capacitors placed in parallel may be needed to PCB circuitry would cause a spike voltage on SW pin
meet the ESR and RMS current handling requirement. when high side MOSFET is turned-on/off, this spike
Higher values, lower cost ceramic capacitors are now voltage on SW may impact on EMI performance in the
becoming available in smaller case sizes. Their high system. In order to enhance EMI performance, there
ripple current, high voltage rating and low ESR make are two methods to suppress the spike voltage. One
them ideal for switching regulator applications. is to place an R-C snubber between SW and GND
However, care must be taken when these capacitors and make them as close as possible to the SW pin
are used at input and output. When a ceramic (see Figure 5). Another method is adding a resistor
capacitor is used at the input and the power is in series with the bootstrap capacitor, CBOOT. But
supplied by a wall adapter through long wires, a load this method will decrease the driving capability to the
step at the output can induce ringing at the input, VIN. high side MOSFET. It is strongly recommended to
At best, this ringing can couple to the output and be reserve the R-C snubber during PCB layout for EMI
mistaken as loop instability. At worst, a sudden inrush improvement. Moreover, reducing the SW trace area
of current through the long wires can potentially cause and keeping the main power in a small loop will be
a voltage spike at helpful on EMI performance. For detailed PCB layout
VIN large enough to damage the part. guide, please refer to the section of Layout
VIN Consideration.

4.5V 2 1
VIN BOOT RBOOT*
to 17V C
IN
CBOOT L
10µF x 2 RT7257E
REN *
SW
3 100nF 10µH VOUT
Chip Enable 7
EN 3.3V/3A
CEN* RS* R1
COUT
CS* 75k 22µFx2
8
CSS 4, SS FB 5 CC
0.1µF 9 (Exposed Pad) RC R2
GND 6 4.7nF 12k
COMP 24k
P

* : Optional C
NC

Figure 5. Reference Circuit with Snubber and Enable Timing Control

Thermal Considerations For recommended operating conditions specification of

For continuous operation, do not exceed the maximum RT7257E, the maximum junction temperature is 125°C.
operation junction temperature 125°C. The maximum The junction to ambient thermal resistance qJA is layout
power dissipation depends on the thermal resistance of dependent. For SOP-8 (Exposed Pad) package, the
IC package, PCB layout, the rate of surroundings thermal resistance qJA is 75°C/W on the standard
airflow and temperature difference between junction to JEDEC 51-7 four-layers thermal test board. The
ambient. The maximum power dissipation can be maximum power dissipation at TA = 25°C can be
calculated by following formula : calculated by following formula :
P D(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
PD(MAX) = (TJ(MAX) − TA ) / qJA
(min.copper area PCB layout)
Where T J(MAX) is the maximum operation junction
P D(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
temperature , TA is the ambient temperature and the
qJA is (70mm2copper area PCB layout)

the junction to ambient thermal resistance.

11
RT7257E Preliminary

The thermal resistance qJA of SOP-8 (Exposed Pad) is

determined by the package architecture design and the
PCB layout design. However, the package
architecture design had been designed. If possible,
it's useful to increase thermal performance by the PCB
layout copper
design. The thermal resistance qJA can be decreased by
adding copper area under the exposed pad of SOP-8 (a) Copper Area = (2.3 x 2.3) mm2, qJA = 75°C/W
(Exposed Pad) package.
As shown in Figure 6, the amount of copper area to
which the SOP-8 (Exposed Pad) is mounted affects
thermal performance. When mounted to the
standard
SOP-8 (Exposed Pad) pad (Figure 6.a), qJA is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 6.b) reduces the qJA to 64°C/W. Even
further, increasing the copper area of pad to 70mm2 (b) Copper Area = 10mm2, qJA = 64°C/W
(Figure 6.e) reduces the qJA to 49°C/W.
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance qJA. For RT7257E packages, the Figure 7
of derating curves allows the designer to see the effect
of rising ambient temperature on the maximum
power
(c) Copper Area = 30mm2 , qJA = 54°C/W
dissipation allowed.
2.2
Four-Layer PCB
2.0
1.8
Power Dissipation (W)

1.6 Copper Area

70mm2
1.4
50mm2
1.2 30mm2
1.0 10mm2
Min.Layout
0.8 (d) Copper Area = 50mm2 , qJA = 51°C/W
0.6
0.4
0.2
0.0
0 25 50 75 100 125

Ambient Temperature (°C)

Figure 7. Derating Curves for RT7257E

Package (e) Copper Area = 70mm2 , qJA = 49°C/W

Figure 6. Themal Resistance vs. Copper Area Layout

Design

12
 Preliminary RT7257E
Layout Consideration ` Connect feedback network behind the output
Follow the PCB layout guidelines for optimal capacitors. Keep the loop area small. Place
performance of the RT7257E. the feedback components near the RT7257E.

` Keep the traces of the main current paths as short ` Connect all analog grounds to a command node
and wide as possible. and then connect the command node to the power
ground behind the output capacitors.
` Put the input capacitor as close as possible to the
device pins (VIN and GND). ` An example of PCB layout guide is shown in Figure 8
for reference.
` SW node is with high frequency voltage swing and
should be kept at small area. Keep analog
components away from the SW node to prevent stray
capacitive noise
pick-up.

GND VIN SW GND VIN The feedback components

must be connected as close
CBOOT REN to the device as
Input capacitor must CSS
CIN C
be placed as close possible. C
to the IC as possible. BOOT 8
SS
GND 7
VIN EN CP RC
VOUT L 2 SW 3 6
9 COMP R1
CS* GND 4 5
FB

S* R2
R VOUT

G
COUT
ND

SW nods is with high frequency voltage swing and should

be kept at small area. Keep analog components away from
the SW node to prevent stray capacitive noise pick-up

Figure 8. PCB Layout Guide

Table 3. Suggested Capacitors for CIN and COUT

Location Component Supplier Part No. Capacitance (mF) Case Size
CIN MURATA GRM31CR61E106K 10 1206
CIN TDK C3225X5R1E106K 10 1206
CIN TAIYO YUDEN TMK316BJ106ML 10 1206
COUT MURATA GRM31CR60J476M 47 1206

COUT TDK C3225X5R0J476M 47 1210

COUT MURATA GRM32ER71C226M 22 1210

TDK C3225X5R1C22M 22 1210
COUT

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RT7257E Preliminary

Outline Dimension
H
A

EXPOSED THERMAL PAD Y

(Bottom of Package)
J X B

C
I
D

Dimensions In Inches
imensions In Millimeters
Symbol D Min Max
Min Max
A 4.801 5.004 0.189 0.197
B 3.810 4.000 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.510 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.000 0.152 0.000 0.006
J 5.791 6.200 0.228 0.244
M 0.406 1.270 0.016 0.050
X 2.000 2.300 0.079 0.091
Option 1
Y 2.000 2.300 0.079 0.091
X 2.100 2.500 0.083 0.098
Option 2
Y 3.000 3.500 0.118 0.138

8-Lead SOP (Exposed Pad) Plastic Package

14
 Preliminary RT7257E
Datasheet Revision History
Versio Data Page No. Item Description
n 2011/10/19 First Edition
P00

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