COMPLEX STATIC CMOS

GATES
 Static CMOS
● Pull-Up Network (PUN) and Pull-Down
Network (PDN)
o PUN and PDN are complementary
o PUN: PMOS devices only
o PDN: NMOS devices only

● PUN and PDN are dual networks

o Dual networks: parallel connection in one =
series connection in the other, vice versa

● Only one network is on at a time

● If CMOS gate implements logic function F:
o PUN implements function F
o PDN implements function G=F’

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 Example

NAND Gate NOR Gate

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 Analysis of CMOS Gates
● Transistors in parallel → resistances
in parallel
o Effective resistance = R/2
o Effective width = 2W

● Transistors in series → resistances

in series
o Effective resistance=2R
o Effective length = 2L (equivalent to
W/2)

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 Example: Transistor Sizing
● Draw circuit, size transistors for equal rise/fall times. Assume 2:1
mobility ratio and equal threshold.

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Start from shortest path Start from longest path
• Smaller widths.
• Larger output cap.

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 Equivalent Inverter
● CMOS gates: many paths to Vdd and Gnd
o Multiple values for VM, VIL, VIH, etc
o Different delays for each input combination

● Equivalent inverter
o Represent each gate as an inverter with appropriate device width
o Include only transistors which are on or switching
o Calculate VM, delays, etc using inverter equations

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Static Properties of Complementary CMOS Gates

● Full rail-to-rail swing with VOH = VDD and VOL = GND

● Symmetrical VTC

● Propagation delay function of load capacitance and resistance of

transistors

● No static power dissipation, since the circuits are designed such that
the pull-down and pullup networks are mutually exclusive

● Direct path (short circuit) current during switching

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● Three possible input combinations switch the
output of the gate from high-to-low:
o (a) A = B = 0 ->1,
o (b) A = 0 -> 1, B = 1
o (c) A = 1, B = 0 -> 1,

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 Propagation Delay of Complementary CMOS
Gates
● For a 2 input NAND gate,
o If both inputs are driven low, the two PMOS devices are on. The delay in this case
is 0.69(Rp/2) CL, since the two resistors are in parallel.
o When only one PMOS device turns on, delay is given by 0.69(Rp)CL – Worst case
o For the pull-down path, the output is discharged only if both A and B are switched
high, and the delay is given by 0.69(2RN) CLto a first order.
● Adding devices in series slows down the circuit, and devices must be made
wider to avoid a performance penalty.
● When sizing the transistors in a gate with multiple fan-in’s, we should pick the
combination of inputs that triggers the worst-case conditions.
● For example, for a NAND gate to have the same pull-down delay (tphl ) as a
minimum-sized inverter, the NMOS devices in the NAND stack must be made
twice as wide so that the equivalent resistance the NAND pull-down is the
same as the inverter. The PMOS devices can remain unchanged.

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● The delay dependence on input patterns

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● The delay dependence on input patterns

Similiarly, worst case tphL occurs for A = B = 0 -> 1

best case tphL occurs for A= 0 -> 1, B = 1

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 NOR Gate

● In the case of a NOR gate,

o The NMOS devices (M1 and M2 ) can have the same device widths as
the NMOS device in the inverter.
o The PMOS devices must be made two times larger compared to the
PMOS in the inverter.

● Since PMOS devices have a lower mobility relative to NMOS devices,

stacking devices in series must be avoided as much as possible. A
NAND implementation is preferred over a NOR implementation for
implementing generic logic.

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Propagation delay of complex gates
● In more complex logic gates that have large fan-in, the internal node
capacitances can become significant

tpHL = 0.69(R1C1 + (R1 + R2) C2 + (R1 + R2+ R3) C3 + (R1 + R2+ R3 + R4) CL)
M1 appears in all the terms, which makes this device important when
attempting to minimize delay.
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 Elmore Delay Model
● Consider an RC network with the
following properties
o The network has a single input
node (labeled s)
o All the capacitors are between a
node and the ground
o The network does not contain
any resistive loops.

● In this topology, there exists a unique resistive path between the source node s and
any node i of the network.
● For the circuit given, the Elmore delay at node 7 is given by:
τD7 = R1C1 + R1C2 + R1C3 + R1C4 + R1C5 + (R1 + R6) C6 + (R1 + R6+ R7) C7 + (R1 + R6+ R7) C8
● The Elmore delay at node 5 is given by:
τD5 = R1C1 + R1C6 + R1C7 + R1C8 + (R1 + R2) C2 + (R1 + R2) C3 + (R1 + R2+ R4) C4 + (R1 + R2+
R 4+ R 5) C 5

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 Fan In and Fan out
● A CMOS gate with N inputs requires 2N transistors.
o Other circuit styles require at most N+1 transistors, which can be a substantial
advantage in area, e.g., 8 versus 5 for a 4-input gate.
● The propagation delay of a complementary gate deteriorates rapidly as a
function of fan-in.
o Internal capacitance become significant
o First, the larger number of transistors increases the overall capacitance of the gate.
● For an N -input NAND gate, the output capacitance increases linearly with the fan-in, since
the number of PMOS devices connected to the output node increases linearly with the fan-
in.
o Second, the series connection in the PUN and PDN slows the gate because the
effective (dis)charging resistance increase linearly with the fan-in.
● Widening does not improve the performance as much as predicted, since widening
increases gate and diffusion capacitance.

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 Fan In and Fan out (Cont..)
● Fan-out in complementary gates has a larger impact on gate delay
than in other circuit styles.
o Downstream gate capacitance is always two per fan-out in contrast to one
in other styles.

● For an N -input NAND gate,

o The low-to-high delay only increases linearly since the pull-up resistance
remains unchanged and only the capacitance increases linearly.
o Since the output capacitance increase linearly and the pull-down
resistance increases linearly, the high-to-low delay can increase in a
quadratic fashion.

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Reduction of delays for Large Fan-in
● Transistor sizing
o Increasing size decreases the second-order factor in the tp expression.
o However, if load is dominated by intrinsic capacitance (self-loading),
propagation delay is not improved.
● increasing the transistor size, results in larger parasitic capacitors, which affect
the propagation delay of the gate and also present a larger load to the
preceding gate.

● Progressive transistor sizing

o The important resistance is reduced while reducing capacitance.

M1 > M2 > M3 > …. > MN

Distributed RC-line

Can Reduce Delay by more than 30%!

It is not simple in a real layout

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Reduction of delays for Large Fan-in (Cont..)
● Transistor ordering
o Not all input signals to a gate arrive at the same time.
o An input signal to a gate is called critical if it is the last signal of all inputs
to assume a stable value.
o The path through the logic which determines the ultimate speed of the
structure is called the critical path.

● Putting the critical-path transistor closer to the output of the gate can
result in a speed-up.

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Reduction of delays for Large Fan-in (Cont..)

● Logic Restructuring
o Partitioning large fan-in gates into small fan-in gates

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● Buffering: Isolate Fan-in from Fan-out

o Keeps high fan-in resistance isolated from large capacitive load CL

● Use another circuit style - To reduce the number of transistors

o Ratioed
o Pass-transistor logic etc…

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 Optimizing performance in
Combinational Networks - Logical Effort
● Systematic method for optimizing CMOS circuits for speed
o Balances gate delays and logic depth
o Enables systematic method of finding minimum sizes to achieve delay
specification
o Implicitly assumes switch RC model for propagation delay.

● Ability of a logic gate to deliver output current compared to an inverter

with same PU and PD resistances.

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 8-input AND

Which implementation is best?

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 Review: Inverter Delay Model
● Inverter Delay Expression:

with tp0 represents the intrinsic delay of an inverter, and f the ratio between
the external load and the input capacitance of the gate. f is often called the
electrical effort .

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 Logical Effort
● For the complex gates, the basic delay equation of the inverter can be
modified as

● p represents the ratio of the intrinsic (or unloaded) delays of the

complex gate and the simple inverter.
o The more involved structure of the multiple-input gate, combined with its
series devices, increases its intrinsic delay.
o p is a function of gate topology as well as layout style.
Gate p
Inverter 1 Estimates of intrinsic delay factors of various
logic types, and a fixed PMOS/NMOS ratio
NAND n
NOR n
MULTIPLEXER 2n
XOR/XNOR n2n-1

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 Logical Effort (Cont..)
● The factor g is called the logical effort,
o For a given load, complex gates have to work harder than an inverter to
produce a similar response.
o The logical effort of a logic gate tells how much worse it is at producing
output current than an inverter, given that each of its inputs may contain
only the same input capacitance as the inverter.
● Reduced output current means slower operation, and thus the logical effort
number for a logic gate tells how much more slowly it will drive a load than
would an inverter.
o Logical effort is how much more input capacitance a gate presents to
deliver the same output current as an inverter.
o Logical effort is a useful parameter, because it depends only on circuit
topology

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 Logical Effort (Cont..)

Logic efforts of common logic gates, assuming a PMOS/NMOS ratio of 2.

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 Logical Effort (Cont..)
• The slope of the line is the logical
effort of the gate;
• Its intercept is the intrinsic delay.
• The graph shows that we can adjust
the delay by adjusting the effective
fanout (by transistor sizing) or by
choosing a logic gate with a different
logical effort.
• The fanout and logical effort
contribute to the delay in a similar
way.
• The gate effort/effort delay is given by
Delay as a function of fanout for an h = fg
inverter and a 2-input NAND

Assuming γ = 1, the gate delay,

Intrinsic Delay Effort Delay

(Parasitic Delay)
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 General Signal Path with N Stages
● The total delay of a path through a combinational logic block can be
expressed as

● To determine the minimum delay of the path, N – 1 partial derivatives

are found out and set them to zero,
f1g1 = f2g2= … = fNgN
i.e.., each stage should bear the same ‘gate effort’:
● The path effective fanout/electrical effort, F = CL /Cg1
● Path logical effort: G = g1g2…gN

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● Branching effort,

● Con-path is the load capacitance of the gate along the path we are
analyzing and Coff-path is the capacitance of the connections that lead
off the path.

● The path Branching effort,

B = b1b2b3……bN

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● The path electrical effort can be written as

● The total path effort

● The gate effort that minimizes the path delay is found to equal

● The minimum delay through the path is

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 8-input AND

Which implementation is best?

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● Case a: 2*(3.33F)1/2 + 9pinv
● Case b: 2*(3.33F)1/2 + 6pinv
● Case c: 4*(2.96F)1/4 + 7pinv
o pinv – Parasitic delay of the inverter
o Case b is always better than Case a
o When F = 1, Case b will be the best
o For higher values of F, Case c will be the best
 How wide should the gates be for least delay?

● Assume that a unit-size gate has a driving capacity equal to a

minimum sized inverter, i.e., this means that its input capacitance is g
times larger than that of the reference inverter, Cref.

● s1 is the sizing factor of the first gate in chain, the input capacitance of
the chain, Cg1 = g1s1Cref

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 Example
Consider the network given below. The output of the network is loaded
with a capacitance which is 5 times larger than the input capacitance of
the first gate, which is a minimum-sized inverter.

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Effective fanout, F = 5

First find out the input capacitances of each stage

5 𝑐
∗ 1 = 1.93 ⇒ 𝑐 = 2.6 ∗ 5/3 = 1.93 ⇒ 𝑏 = 2.24
𝑐 𝑏
𝑏
∗ 5/3 = 1.93 ⇒ 𝑎 = 1.93
𝑎
Sizing of c => gcscCref = 2.6 => sc = 2.6
Sizing of b => gbsbCref = 2.24 => sb = 1.34
Sizing of a => gasaCref = 1.93 => sa = 1.16
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● Select gate sizes x and y for least delay from A to B
● Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27
● Electrical Effort F = 45/8
● Branching Effort B = 3 * 2 = 6
● Path Effort H = GBF = 125
● Best Stage Effort = H1/3 = 5
● Parasitic Delay P = 2 + 3 + 2 = 7
● Delay D = 3*5 + 7 = 22
● y = 45 * (5/3) / 5 = 15
● x = (15*2) * (5/3) / 5 = 10
● Now size last stage: x = 15
o 2 input NOR has unit input cap of 5
o To get an input cap of 15 => widths 15/5 = 3X unit!
● Now size 2nd stage: y = 10;
o 3 input NAND unit input cap of 5 => widths 10/5 = 2X unit!
● Now size 1st stage: Cin = 8;
o 2 input NAND has unit input cap of 4 => widths 8/4 = 2X
unit!
● For the circuit given below
o What is the path effort from In to Out?
o What electrical effort/stage minimizes the delay of this chain of gates?
o Size the gates to minimize the delay from In to Out

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 Power Consumption in CMOS Logic Gates
● The power dissipation is a strong function of
o Transistor sizing (which affects physical capacitance),
o Input and output rise/fall times (which affects the short-circuit power)
o Device thresholds and temperature (which affect leakage power)
o Switching activity

● The dynamic power dissipation is given

Pd = CLVDD2α0->1f

● Making a gate more complex mostly affects the switching activity α0->1,
which has two components:
o a static component that is only a function of the topology of the logic
network, and
o a dynamic one that results from the timing behavior of the circuit—the
latter factor is also called glitching.

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● The transition activity is a strong function of the logic function being
implemented.
α0->1 = p0 (1 - p0)
● Assuming that the inputs are independent and uniformly distributed,
any N -input static gate has a transition probability

● N0 is the number of zero entries and N1 is the number of one entries

in the output column of the truth table of the function

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● Using a uniform input distribution to compute activity is not a good
one, since the propagation through logic gates can significantly modify
the signal statistics.

● The switching activity of a logic gate is a strong function of the input

signal statistics.

● For a 2-input static NOR gate, and let pa and pb be the probabilities
that the inputs A and B are one . Also assume that the inputs are not
correlated. The probability that the output node equals one is given by

● Therefore, the probability of a transition from 0 to 1 is

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 α0->1

AND

OR

XOR

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 α0->1

AND (1-pApB)pApB

OR (1-pA)(1-pB)[1-(1-pA)(1-pB)]

XOR [1-(pA+pB-2pApB)] (pA+pB-2pApB)

Dr. Bindiya T. S., Assistant Professor, ECED Basics of VLSI 58

● Inter-signal Correlations

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Dynamic or Glitching Transitions
● The finite propagation delay from one logic block to the next can
cause spurious transitions, called glitches, critical races, or dynamic
hazards , to occur
o a node can exhibit multiple transitions in a single clock cycle before
settling to the correct logic level.

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61
 Design Techniques to Reduce
Switching Activity
● Glitch Reduction by balancing signal paths

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 Design Techniques to Reduce Switching Activity
(Cont..)
Logic Restructuring

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Design Techniques to Reduce Switching Activity
(Cont..)

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 Design Techniques to Reduce Switching Activity
(Cont..)
● The chain implementation will have an overall lower switching activity
than the tree implementation for random inputs.

● However, the timing behavior and glitching also need to be

considered.
o In this example the tree topology will have lower (no) glitching activity
since the signal paths are balanced to all the gates

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 Design Techniques to Reduce Switching Activity
(Cont..)
● Input ordering

● Since both circuits implement identical logic functionality, it is clear that the
activity at the output node Z is equal in both cases.

● The difference is in the activity at the intermediate node. In the first circuit, this
activity equals (1 - 0.5 x 0.2) (0.5 x 0.2) = 0.09.

● In the second case, the probability that a 0 -> 1 transition occurs equals (1 –
0.2x0.1) (0.2 x 0.1)= 0.0196. This is substantially lower.

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 CMOS disadvantages
● For N-input CMOS gate, 2N transistors required
o Each input connects to an NMOS and PMOS transistor
o Large input capacitance: limits fan-out
o Large fan-in gates: always have long transistor stack

● in PUN or PDN
o Limits pull-up or pull-down delay
o Requires very large transistors

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 Ratioed Logic
● To reduce the number of transistors
required to implement a given logic
function,
o Reduced robustness
o Extra power dissipation.

● In ratioed logic, the entire PUN is

replaced with a single unconditional
load device that pulls up the output
for a high output
o Consists of an NMOS pull-down
network that realizes the logic
function , and a simple load device.

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 pseudo-NMOS Logic
● Uses a grounded PMOS load, known as a
pseudo-NMOS gate.
● Reduced number of transistors (N +1 versus 2N
for complementary CMOS)
● VOH = VDD
● VOL ≠ 0
o There is a fight between the devices in the PDN
and the grounded PMOS load device.
o This results in reduced noise margins and more
importantly static power dissipation.

RATIOED LOGIC - The sizing of the load device relative to the pull-down
devices can be used to trade-off parameters such a noise margin ,
propagation delay and power dissipation.
• CMOS – Ratioless - The low and high levels do not depend upon transistor
sizes.
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 pseudo-NMOS Logic
● The value of VOL is obtained by equating the currents through the
driver and load devices for Vin = VDD

● In order to make VOL as small as possible, the PMOS device should

be sized much smaller than the NMOS pull-down devices.
o Affects the propagation delay for charging up the output node since the
current provided by the PMOS device is reduced.

● A major disadvantage of the pseudo-NMOS gate is the static power

dissipation when the output is low through the direct current path that
exists between VDD and GND.

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VTC of pseudo-NMOS inverter

Voltage-transfer curves of the pseudo-

NMOS inverter as a function of the
PMOS size.

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 Differential Cascode Voltage Switch Logic
(DCVSL)

● The required logic function and its inverse are simultaneously

implemented.

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 DCVSL - Examples

AND – NAND Gate

XOR – XNOR Gate

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 DCVSL – Advantages
● The resulting circuit exhibits a rail-to-rail swing

● The static power dissipation is eliminated:

o in steady state, none of the stacked pull-down networks and load devices are
simultaneously conducting.

● Both the output signal (Vout1) and its inverted value (Vout2) are
simultaneously available.
o This is a distinct advantage, as it eliminates the need for an extra inverter to
produce the complementary signal.

● This approach prevents some of the time-differential problems introduced by

additional inverters.
o For example, in logic design it often happens that both a signal and its complement
are needed simultaneously. When the complementary signal is generated using an
inverter, the inverted signal is delayed with respect to the original. This causes
timing problems, especially in very high-speed designs.

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 DCVSL – Disadvantages
● The circuit is still ratioed
o The sizing of the PMOS devices relative to the pull-down devices is critical
to functionality, not just performance.

● Increase complexity in design

o The differential nature virtually doubles the number of wires that has to be
routed.

● Power-dissipation problem that is due to cross-over currents.

o During the transition, there is a period of time when PMOS and PDN are
turned on simultaneously, producing a short circuit path.

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 Pass-Transistor Logic
● Implement logic by allowing the primary inputs to drive gate terminals
as well as source/drain terminals.

● Fewer transistors are required to implement a given function

● When the pass transistor pulls a node high, the output only charges
up to VDD -VTn

● The pass-transistor gates cannot be cascaded by connecting the

output of a pass gate to the gate input of another pass transistor.

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Complementary/Differential pass-transistor logic
(CPL or DPL)

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78
 Pass-Transistor Logic- Solution 1:
Level Restoring Transistor

• Advantages: Full Swing, No static power dissipation

• Restorer adds capacitance, takes away pull down current at X
• Ratio problem
 Transmission Gate Logic

● NMOS and PMOS connected in parallel

● Allows full rail transition – ratioless logic

● Equivalent resistance relatively constant during transition

● Some gates can be efficiently implemented using transmission gate

logic (XOR in particular)

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● For a rising transition at the output (step input)
o NMOS sat, PMOS sat until output reaches |VTP|
o NMOS sat, PMOS linear until output reaches VDD - VTN
o NMOS off, PMOS linear for the final VDD – VTN to VDD voltage swing

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 Equivalent resistance
● Equivalent resistance Req is
parallel combinaton of Req,n
and Req,p

● Req is relatively constant

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2:1 Mux

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Transmission Gate Full Adder

Propagate signal

Similar delays for sum and carry

24 transistors
 Clocking Schemes
● Single phase clocking with latches

● Single phase clocking with Flip Flops

● Two phase clocking

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Positive latch using
transmission gates

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Edge-Triggered Flip-Flop

87
● Race condition may occur due to overlapping of clocks

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Two-phase non-overlapping clocks

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 C2MOS Edge Triggered Flip-Flop
● Clocked CMOS

● Clock skew insensitive approach

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91
True Single-Phase Clocked Register (TSPCR)

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