a Complete 8-Bit, 32 MSPS, 95 mW

CMOS A/D Converter

AD9280
FEATURES A single clock input is used to control all internal conversion
CMOS 8-Bit 32 MSPS Sampling A/D Converter cycles. The digital output data is presented in straight binary
Pin-Compatible with AD876-8 output format. An out-of-range signal (OTR) indicates an over-
Power Dissipation: 95 mW (3 V Supply) flow condition which can be used with the most significant bit
Operation Between +2.7 V and +5.5 V Supply to determine low or high overflow.
Differential Nonlinearity: 0.2 LSB
The AD9280 can operate with a supply range from +2.7 V to
Power-Down (Sleep) Mode
+5.5 V, ideally suiting it for low power operation in high speed
Three-State Outputs
applications.
Out-of-Range Indicator
Built-In Clamp Function (DC Restore) The AD9280 is specified over the industrial (–40°C to +85°C)
Adjustable On-Chip Voltage Reference temperature range.
IF Undersampling to 135 MHz
PRODUCT HIGHLIGHTS
PRODUCT DESCRIPTION Low Power
The AD9280 is a monolithic, single supply, 8-bit, 32 MSPS The AD9280 consumes 95 mW on a 3 V supply (excluding the
analog-to-digital converter with an on-chip sample-and-hold reference power). In sleep mode, power is reduced to below
amplifier and voltage reference. The AD9280 uses a multistage 5 mW.
differential pipeline architecture at 32 MSPS data rates and
Very Small Package
guarantees no missing codes over the full operating temperature
The AD9280 is available in a 28-lead SSOP package.
range.
Pin Compatible with AD876-8
The input of the AD9280 has been designed to ease the devel-
The AD9280 is pin compatible with the AD876-8, allowing
opment of both imaging and communications systems. The user
older designs to migrate to lower supply voltages.
can select a variety of input ranges and offsets and can drive the
input either single-ended or differentially. 300 MHz Onboard Sample-and-Hold
The versatile SHA input can be configured for either single-
The sample-and-hold amplifier (SHA) is equally suited for both
ended or differential inputs.
multiplexed systems that switch full-scale voltage levels in suc-
cessive channels and sampling single-channel inputs at frequen- Out-of-Range Indicator
cies up to and beyond the Nyquist rate. AC-coupled input The OTR output bit indicates when the input signal is beyond
signals can be shifted to a predetermined level, with an onboard the AD9280’s input range.
clamp circuit. The dynamic performance is excellent. Built-In Clamp Function
The AD9280 has an onboard programmable reference. An Allows dc restoration of video signals.
external reference can also be chosen to suit the dc accuracy and
temperature drift requirements of the application.
FUNCTIONAL BLOCK DIAGRAM
CLAMP
CLAMP IN CLK AVDD DRVDD

STBY

SHA SHA GAIN SHA GAIN SHA GAIN SHA GAIN MODE
VINA A/D
REFTF
A/D D/A A/D D/A A/D D/A A/D D/A THREE-
REFTS STATE

REFBS CORRECTION LOGIC

REFBF
OUTPUT BUFFERS OTR
VREF
REFSENSE 1V AD9280 D7 (MSB)

D0 (LSB)

AVSS DRVSS

REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999
 (AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input
AD9280–SPECIFICATIONS Span from 0.5 V to 2.5 V, External Reference, TMIN to TMAX unless otherwise noted)
Parameter Symbol Min Typ Max Units Condition
RESOLUTION 8 Bits
CONVERSION RATE FS 32 MHz
DC ACCURACY
Differential Nonlinearity DNL ± 0.2 ± 1.0 LSB REFTS = 2.5 V, REFBS = 0.5 V
Integral Nonlinearity INL ± 0.3 ± 1.5 LSB
Offset Error EZS ± 0.2 ± 1.8 % FSR
Gain Error EFS ± 1.2 ± 3.9 % FSR
REFERENCE VOLTAGES
Top Reference Voltage REFTS 1 AVDD V
Bottom Reference Voltage REFBS GND AVDD – 1 V
Differential Reference Voltage 2 V p-p
Reference Input Resistance1 10 kΩ REFTS, REFBS: MODE = AVDD
4.2 kΩ Between REFTF & REFBF: MODE = AVSS
ANALOG INPUT
Input Voltage Range AIN REFBS REFTS V REFBS Min = GND: REFTS Max = AVDD
Input Capacitance CIN 1 pF Switched
Aperture Delay tAP 4 ns
Aperture Uncertainty (Jitter) tAJ 2 ps
Input Bandwidth (–3 dB) BW
Full Power (0 dB) 300 MHz
DC Leakage Current 43 µA Input = ± FS
INTERNAL REFERENCE
Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF
Output Voltage Tolerance (1 V Mode) ± 10 ± 25 mV
Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND
Load Regulation (1 V Mode) 0.5 2 mV 1 mA Load Current
POWER SUPPLY
Operating Voltage AVDD 2.7 3 5.5 V
DRVDD 2.7 3 5.5 V
Supply Current IAVDD 31.7 36.7 mA AVDD = 3 V, MODE = AVSS
Power Consumption PD 95 110 mW AVDD = DRVDD = 3 V, MODE = AVSS
Power-Down 4 mW STBY = AVDD, MODE and CLOCK
= AVSS
Gain Error Power Supply Rejection PSRR 1 % FS
DYNAMIC PERFORMANCE (AIN = 0.5 dBFS)
Signal-to-Noise and Distortion SINAD
f = 3.58 MHz 46.4 49 dB
f = 16 MHz 48 dB
Effective Bits
f = 3.58 MHz 7.8 Bits
f = 16 MHz 7.7 Bits
Signal-to-Noise SNR
f = 3.58 MHz 47.8 49 dB
f = 16 MHz 48 dB
Total Harmonic Distortion THD
f = 3.58 MHz –62 –49.5 dB
f = 16 MHz –58 dB
Spurious Free Dynamic Range SFDR
f = 3.58 MHz 66 51.4 dB
f = 16 MHz 61 dB
Differential Phase DP 0.2 Degree NTSC 40 IRE Mod Ramp
Differential Gain DG 0.08 %

–2– REV. D
 AD9280
Parameter Symbol Min Typ Max Units Condition
DIGITAL INPUTS
High Input Voltage VIH 2.4 V
Low Input Voltage VIL 0.3 V
DIGITAL OUTPUTS
High-Z Leakage IOZ –10 +10 µA Output = GND to VDD
Data Valid Delay tOD 25 ns CL = 20 pF
Data Enable Delay tDEN 25 ns
Data High-Z Delay tDHZ 13 ns
LOGIC OUTPUT (with DRVDD = 3 V)
High Level Output Voltage (IOH = 50 µA) VOH +2.95 V
High Level Output Voltage (IOH = 0.5 mA) VOH +2.80 V
Low Level Output Voltage (IOL = 1.6 mA) VOL +0.4 V
Low Level Output Voltage (IOL = 50 µA) VOL +0.05 V
LOGIC OUTPUT (with DRVDD = 5 V)
High Level Output Voltage (IOH = 50 µA) VOH +4.5 V
High Level Output Voltage (IOH = 0.5 mA) VOH +2.4 V
Low Level Output Voltage (IOL = 1.6 mA) VOL +0.4 V
Low Level Output Voltage (IOL = 50 µA) VOL +0.1 V
CLOCKING
Clock Pulsewidth High tCH 14.7 ns
Clock Pulsewidth Low tCL 14.7 ns
Pipeline Latency 3 Cycles
CLAMP
Clamp Error Voltage EOC ± 60 ± 80 mV CLAMPIN = +0.5 V to +2.0 V,
RIN = 10 Ω
Clamp Pulsewidth tCPW 2 µs CIN = 1 µF (Period = 63.5 µs)
NOTES
1
See Figures 1a and 1b.
Specifications subject to change without notice.

10kV REFTS
REFTS AD9280 AD9280
REFTF
4.2kV
10kV
REFBS REFBF

0.4 3 VDD
REFBS
MODE MODE
AVDD

a. b.

Figure 1. Equivalent Input Load

REV. D –3–
AD9280
ABSOLUTE MAXIMUM RATINGS* *Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
With device at these or any other conditions above those indicated in the operational
Respect sections of this specification is not implied. Exposure to absolute maximum
Parameter to Min Max Units ratings for extended periods may effect device reliability.

AVDD AVSS –0.3 +6.5 V ORDERING GUIDE

DRVDD DRVSS –0.3 +6.5 V
Temperature Package Package
AVSS DRVSS –0.3 +0.3 V
Model Range Description Option*
AVDD DRVDD –6.5 +6.5 V
MODE AVSS –0.3 AVDD + 0.3 V AD9280ARS –40°C to +85°C 28-Lead SSOP RS-28
CLK AVSS –0.3 AVDD + 0.3 V AD9280ARSRL –40°C to +85°C 28-Lead SSOP (Reel) RS-28
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V AD9280-EB Evaluation Board
AIN AVSS –0.3 AVDD + 0.3 V
*RS = Shrink Small Outline.
VREF AVSS –0.3 AVDD + 0.3 V
REFSENSE AVSS –0.3 AVDD + 0.3 V
REFTF, REFTB AVSS –0.3 AVDD + 0.3 V
REFTS, REFBS AVSS –0.3 AVDD + 0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature
10 sec +300 °C

AVDD

DRVDD
AVDD AVDD AVDD AVDD

DRVSS
DRVSS AVSS AVSS AVSS AVSS
AVSS

a. D0–D7, OTR b. Three-State, Standby, Clamp c. CLK

AVDD AVDD

REFTF 22
REFBS 25
AVDD
AVSS
AVSS
AVDD
AVDD

REFBF 24 REFTS 21

AVSS AVSS AVSS

d. AIN e. Reference

AVDD AVDD
AVDD AVDD

AVSS AVSS AVSS AVSS

f. CLAMPIN g. MODE h. REFSENSE i. VREF

Figure 2. Equivalent Circuits

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD9280 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. D
 AD9280
PIN CONFIGURATION
28-Lead Wide Body (SSOP)

AVSS 1 28 AVDD
DRVDD 2 27 AIN
NC 3 26 VREF
NC 4 25 REFBS
D0 5 24 REFBF
AD9280
D1 6 TOP VIEW 23 MODE
D2 7 (Not to Scale) 22 REFTF
D3 8 21 REFTS
D4 9 20 CLAMPIN
D5 10 19 CLAMP
D6 11 18 REFSENSE

D7 12 17 STBY
OTR 13 16 THREE-STATE
DRVSS 14 15 CLK

NC = NO CONNECT

PIN FUNCTION DESCRIPTIONS

SSOP
Pin No. Name Description
1 AVSS Analog Ground
2 DRVDD Digital Driver Supply
3 NC No Connect
4 NC No Connect
5 D0 Bit 0
6 D1 Bit 1
7 D2 Bit 2
8 D3 Bit 3
9 D4 Bit 4
10 D5 Bit 5
11 D6 Bit 6
12 D7 Bit 7, Most Significant Bit
13 OTR Out-of-Range Indicator
14 DRVSS Digital Ground
15 CLK Clock Input
16 THREE-STATE HI: High Impedance State. LO: Normal Operation
17 STBY HI: Power-Down Mode. LO: Normal Operation
18 REFSENSE Reference Select
19 CLAMP HI: Enable Clamp Mode. LO: No Clamp
20 CLAMPIN Clamp Reference Input
21 REFTS Top Reference
22 REFTF Top Reference Decoupling
23 MODE Mode Select
24 REFBF Bottom Reference Decoupling
25 REFBS Bottom Reference
26 VREF Internal Reference Output
27 AIN Analog Input
28 AVDD Analog Supply

REV. D –5–
AD9280
DEFINITIONS OF SPECIFICATIONS Offset Error
Integral Nonlinearity (INL) The first transition should occur at a level 1 LSB above “zero.”
Integral nonlinearity refers to the deviation of each individual Offset is defined as the deviation of the actual first code transi-
code from a line drawn from “zero” through “full scale.” The tion from that point.
point used as “zero” occurs 1/2 LSB before the first code transi- Gain Error
tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last The first code transition should occur for an analog value 1 LSB
code transition. The deviation is measured from the center of above nominal negative full scale. The last transition should
each particular code to the true straight line. occur for an analog value 1 LSB below the nominal positive full
Differential Nonlinearity (DNL, No Missing Codes) scale. Gain error is the deviation of the actual difference be-
An ideal ADC exhibits code transitions that are exactly 1 LSB tween first and last code transitions and the ideal difference
apart. DNL is the deviation from this ideal value. It is often between the first and last code transitions.
specified in terms of the resolution for which no missing codes Pipeline Delay (Latency)
(NMC) are guaranteed. The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every rising edge.

(AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input

Typical Characterization Curves Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted)
1.0 60

55

0.5 50
–0.5 AMPLITUDE
45
–6.0 AMPLITUDE
SNR– dB
DNL

0 40

35

–0.5 30
–20.0 AMPLITUDE
25

–1.0 20
0 32 64 96 128 160 192 224 240 1.00E+05 1.00E+06 1.00E+07 1.00E+08
CODE OFFSET INPUT FREQUENCY – Hz

Figure 3. Typical DNL Figure 5. SNR vs. Input Frequency

1.0 60

55

0.5 50
–0.5 AMPLITUDE
45
SINAD – dB

–6.0 AMPLITUDE
INL

0 40

35

–0.5 30
–20.0 AMPLITUDE
25

–1.0 20
0 32 64 96 128 160 192 224 240 1.00E+05 1.00E+06 1.00E+07 1.00E+08
CODE OFFSET INPUT FREQUENCY – Hz

Figure 4. Typical INL Figure 6. SINAD vs. Input Frequency

–6– REV. D
 AD9280
–30 105

–35
100

POWER CONSUMPTION – mW
–40
95
–45
THD – dB

–20.0 AMPLITUDE
–50 90

–55
–6.0 AMPLITUDE 85
–60
80
–65
–0.5 AMPLITUDE
–70 75
1.00E+05 1.00E+06 1.00E+07 1.00E+08 0 5 10 15 20 25 30 35 40
INPUT FREQUENCY – Hz CLOCK FREQUENCY – MHz

Figure 7. THD vs. Input Frequency Figure 10. Power Consumption vs. Clock Frequency
(MODE = AVSS)

–80 1M
1M

–70 900k

AIN = –0.5dBFS 800k

–60
700k
–50
600k
THD – dB

HITS
–40 500k

400k
–30
300k
–20
200k
–10 100k
0 0
0 0
1.00E+06 1.00E+07 1.00E+08 N–1 N N+1
CLOCK FREQUENCY – Hz CODE

Figure 8. THD vs. Clock Frequency Figure 11. Grounded Input Histogram

1.01 30
20
CLOCK = 32MHz FIN = 1MHz
10
FUND FS = 32MHz
1.009 0
–10
–20
1.008 –30
VREF – V

–40
–50
–60 2nd3rd
1.007 9th
5th
–70 7th
6th 8th
–80
4th
1.006 –90
–100
–110
1.005 –120
–50 –30 –10 10 30 50 70 90 0E+0 4E+6 8E+6 12E+6 16E+6
TEMPERATURE – °C SINGLE-TONE FREQUENCY DOMAIN

Figure 9. Voltage Reference Error vs. Temperature Figure 12. Single-Tone Frequency Domain

REV. D –7–
AD9280
0 APPLYING THE AD9280
–3
THEORY OF OPERATION
The AD9280 implements a pipelined multistage architecture to
–6 achieve high sample rate with low power. The AD9280 distrib-
SIGNAL AMPLITUDE – dB

utes the conversion over several smaller A/D subblocks, refining

–9
the conversion with progressively higher accuracy as it passes
–12 the results from stage to stage. As a consequence of the distrib-
uted conversion, the AD9280 requires a small fraction of the
–15
256 comparators used in a traditional flash type A/D. A sample-
–18 and-hold function within each of the stages permits the first
stage to operate on a new input sample while the second, third
–21 and fourth stages operate on the three preceding samples.
–24
1.0E+6 1.0E+7 1.0E+8 1.0E+9 OPERATIONAL MODES
FREQUENCY – Hz
The AD9280 is designed to allow optimal performance in a
Figure 13. Full Power Bandwidth wide variety of imaging, communications and instrumentation
applications, including pin compatibility with the AD876-8 A/D.
50 To realize this flexibility, internal switches on the AD9280 are
40
used to reconfigure the circuit into different modes. These modes
are selected by appropriate pin strapping. There are three parts
30
of the circuit affected by this modality: the voltage reference, the
20 reference buffer, and the analog input. The nature of the appli-
REFBS = 0.5V
10 REFTS = 2.5V cation will determine which mode is appropriate: the descrip-
IB – mA

CLOCK = 32MHz tions in the following sections, as well as Table I should assist in
0
selecting the desired mode.
–10

–20

–30

–40

–50
0 0.5 1.0 1.5 2.0 2.5 3.0
INPUT VOLTAGE – V

Figure 14. Input Bias Current vs. Input Voltage

Table I. Mode Selection

Input Input MODE REFSENSE

Modes Connect Span Pin Pin REF REFTS REFBS Figure
TOP/BOTTOM AIN 1V AVDD Short REFSENSE, REFTS and VREF Together AGND 18
AIN 2V AVDD AGND Short REFTS and VREF Together AGND 19
CENTER SPAN AIN 1V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 20
AIN 2V AVDD/2 AGND No Connect AVDD/2 AVDD/2
Differential AIN Is Input 1 1V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 29
REFTS and
REFBS Are
Shorted Together
for Input 2 2V AVDD/2 AGND No Connect AVDD/2 AVDD/2
External Ref AIN 2 V max AVDD AVDD No Connect Span = REFTS 21, 22
– REFBS (2 V max)
AGND Short to Short to 23
VREFTF VREFBF
AD876-8 AIN 2V Float or AVDD No Connect Short to Short to 30
AVSS VREFTF VREFBF

–8– REV. D
 AD9280
SUMMARY OF MODES
VOLTAGE REFERENCE
AIN
1 V Mode the internal reference may be set to 1 V by connect- SHA A/D
CORE
REFTS
ing REFSENSE and VREF together.
2 V Mode the internal reference my be set to 2 V by connecting
REFSENSE to analog ground AD9280
External Divider Mode the internal reference may be set to a
point between 1 V and 2 V by adding external resistors. See REFBS

Figure 16f.
External Reference Mode enables the user to apply an exter- Figure 15. AD9280 Equivalent Functional Input Circuit
nal reference to REFTS, REFBS and VREF pins. This mode In single-ended operation, the input spans the range,
is attained by tying REFSENSE to VDD. REFBS ≤ AIN ≤ REFTS
REFERENCE BUFFER where REFBS can be connected to GND and REFTS con-
Center Span Mode midscale is set by shorting REFTS and nected to VREF. If the user requires a different reference range,
REFBS together and applying the midscale voltage to that point REFBS and REFTS can be driven to any voltage within the
The MODE pin is set to AVDD/2. The analog input will swing power supply rails, so long as the difference between the two is
about that midscale point. between 1 V and 2 V.
Top/Bottom Mode sets the input range between two points. In differential operation, REFTS and REFBS are shorted to-
The two points are between 1 V and 2 V apart. The Top/Bottom gether, and the input span is set by VREF,
Mode is enabled by tying the MODE pin to AVDD. (REFTS – VREF/2) ≤ AIN ≤ (REFTS + VREF/2)
where VREF is determined by the internal reference or brought
ANALOG INPUT
in externally by the user.
Differential Mode is attained by driving the AIN pin as one
differential input, shorting REFTS and REFBS together and The best noise performance may be obtained by operating the
driving them as the second differential input. The MODE pin AD9280 with a 2 V input range. The best distortion perfor-
is tied to AVDD/2. Preferred mode for optimal distortion mance may be obtained by operating the AD9280 with a 1 V
performance. input range.
Single-Ended is attained by driving the AIN pin while the
REFERENCE OPERATION
REFTS and REFBS pins are held at dc points. The MODE pin is
The AD9280 can be configured in a variety of reference topolo-
tied to AVDD.
gies. The simplest configuration is to use the AD9280’s onboard
Single-Ended/Clamped (AC Coupled) the input may be bandgap reference, which provides a pin-strappable option to
clamped to some dc level by ac coupling the input. This is done generate either a 1 V or 2 V output. If the user desires a refer-
by tying the CLAMPIN to some dc point and applying a pulse ence voltage other than those two, an external resistor divider
to the CLAMP pin. MODE pin is tied to AVDD. can be connected between VREF, REFSENSE and analog
ground to generate a potential anywhere between 1 V and 2 V.
SPECIAL Another alternative is to use an external reference for designs
AD876-8 Mode enables users of the AD876-8 to drop the requiring enhanced accuracy and/or drift performance. A
AD9280 into their socket. This mode is attained by floating or third alternative is to bring in top and bottom references,
grounding the MODE pin. bypassing VREF altogether.
Figures 16d, 16e and 16f illustrate the reference and input ar-
INPUT AND REFERENCE OVERVIEW
chitecture of the AD9280. In tailoring a desired arrangement,
Figure 16, a simplified model of the AD9280, highlights the
the user can select an input configuration to match drive circuit.
relationship between the analog input, AIN, and the reference
Then, moving to the reference modes at the bottom of the
voltages, REFTS, REFBS and VREF. Like the voltages applied
figure, select a reference circuit to accommodate the offset and
to the resistor ladder in a flash A/D converter, REFTS and
amplitude of a full-scale signal.
REFBS define the maximum and minimum input voltages to
the A/D. Table I outlines pin configurations to match user requirements.
The input stage is normally configured for single-ended opera-
tion, but allows for differential operation by shorting REFTS
and REFBS together to be used as the second input.

REV. D –9–
AD9280
V*
MIDSCALE
+FS AIN AD9280 MODE
SHA AVDD/2
–FS AIN AD9280 MODE
SHA
+F/S RANGE (AVDD) 10kV 0.1mF
REFTF
OBTAINED FROM
VREF PIN OR 10kV 0.1mF
REFTF 10kV
EXTERNAL REF
REFTS
REFTS 10kV A2 0.1mF 10mF
REFBS A/D 4.2kV
REFBS A2 0.1mF 10kV CORE TOTAL
A/D 4.2kV 10mF
10kV CORE TOTAL INTERNAL
10kV 0.1mF
–F/S RANGE REF
OBTAINED FROM 10kV 0.1mF REFBF
VREF PIN OR
EXTERNAL REF MIDSCALE OFFSET
REFBF VOLTAGE IS DERIVED * MAXIMUM MAGNITUDE OF V IS DETERMINED
FROM INTERNAL OR BY INTERNAL REFERENCE
EXTERNAL REF

a. Top/Bottom Mode b. Center Span Mode

MAXIMUM MAGNITUDE OF V
IS DETERMINED BY INTERNAL
REFERENCE AND TURNS RATIO

V AD9280 MODE
AIN
SHA AVDD/2

AVDD/2
10kV 0.1mF
REFTF

10kV
REFTS
A2 10mF
REFBS A/D 4.2kV 0.1mF
10kV CORE TOTAL

INTERNAL
10kV 0.1mF
REF
REFBF

c. Differential Mode

VREF
(2V)
VREF
A1 (1V)
1V A1 0.1mF 1.0mF
1V
10kV REFSENSE
0.1mF 1.0mF
REFSENSE
AD9280 AVSS 10kV
AD9280 AVSS

d. 1 V Reference e. 2 V Reference

VREF
(= 1 + RA/RB)
A1
1V 1.0mF A1 VREF
RA 0.1mF
1V
REFSENSE REFSENSE
RB AVDD
AD9280
AD9280 AVSS

INTERNAL 10K REF RESISTORS ARE

SWITCHED OPEN BY THE PRESENSE
OF RA AND RB.
g. Internal Reference Disable
f. Variable Reference (Power Reduction)
(Between 1 V and 2 V)

Figure 16.

–10– REV. D
 AD9280
The actual reference voltages used by the internal circuitry of Figure 19 shows the single-ended configuration for 2 V p-p
the AD9280 appear on REFTF and REFBF. For proper opera- operation. REFSENSE is connected to GND, resulting in a 2 V
tion, it is necessary to add a capacitor network to decouple these reference output.
pins. The REFTF and REFBF should be decoupled for all
internal and external configurations as shown in Figure 17.
2V AIN
AD9280 MODE
0V SHA AVDD

REFTF 10kV REFTF 0.1mF

10mF 0.1mF AD9280 REFTS 10kV

REFBF REFBS A2 10mF

A/D 4.2kV 0.1mF
0.1mF 0.1mF 10kV CORE TOTAL

10kV 0.1mF

Figure 17. Reference Decoupling Network REFBF

VREF
A1
Note: REFTF = reference top, force 1.0mF 0.1mF REF
1V

REFBF = reference bottom, force SENSE

REFTS = reference top, sense

REFBS = reference bottom, sense

INTERNAL REFERENCE OPERATION Figure 19. Internal Reference, 2 V p-p Input Span
Figures 18, 19 and 20 show sample connections of the AD9280 (Top/Bottom Mode)
internal reference in its most common configurations. (Figures Figure 20 shows the single-ended configuration that gives the
18 and 19 illustrate top/bottom mode while Figure 20 illustrates good high frequency dynamic performance (SINAD, SFDR).
center span mode). Figure 29 shows how to connect the AD9280 To optimize dynamic performance, center the common-mode
for 1 V p-p differential operation. Shorting the VREF pin voltage of the analog input at approximately 1.5 V. Connect the
directly to the REFSENSE pin places the internal reference shorted REFTS and REFBS inputs to a low impedance 1.5 V
amplifier, A1, in unity-gain mode and the resultant reference source. In this configuration, the MODE pin is driven to a volt-
output is 1 V. In Figure 18 REFBS is grounded to give an input age at midsupply (AVDD/2).
range from 0 V to 1 V. These modes can be chosen when the
supply is either +3 V or +5 V. The VREF pin must be bypassed to Maximum reference drive is 1 mA. An external buffer is re-
AVSS (analog ground) with a 1.0 µF tantalum capacitor in quired for heavier loads.
parallel with a low inductance, low ESR, 0.1 µF ceramic capacitor.
2V AIN
AD9280 MODE
1V SHA AVDD/2
1V AIN
AD9280 MODE
0V SHA AVDD 0.1mF
10kV REFTF

10kV REFTF 0.1mF

REFTS 10kV

+1.5V REFBS A2 0.1mF 10mF

REFTS 10kV A/D 4.2kV
CORE TOTAL
REFBS A2
A/D 4.2kV 0.1mF 10mF
10kV CORE TOTAL 10kV 0.1mF
10kV

0.1mF REFBF
10kV
VREF
REFBF A1
REF 1V
VREF 1.0mF 0.1mF
SENSE
A1
1V
1.0mF 0.1mF REF
SENSE
Figure 20. Internal Reference 1 V p-p Input Span
(Center Span Mode)
Figure 18. Internal Reference—1 V p-p Input Span
(Top/Bottom Mode)

REV. D –11–
AD9280
EXTERNAL REFERENCE OPERATION Figure 23a shows an example of the external references driving
Using an external reference may provide more flexibility and the REFTF and REFBF pins that is compatible with the
improve drift and accuracy. Figures 21 through 23 show ex- AD876. REFTS is shorted to REFTF and driven by an external
amples of how to use an external reference with the AD9280. 4 V low impedance source. REFBS is shorted to REFBF and
To use an external reference, the user must disable the internal driven by a 2 V source. The MODE pin is connected to GND
reference amplifier by connecting the REFSENSE pin to VDD. in this configuration.
The user then has the option of driving the VREF pin, or driv-
ing the REFTS and REFBS pins. 4V
VIN
The AD9280 contains an internal reference buffer (A2), that 2V
simplifies the drive requirements of an external reference. The REFTS

external reference must simply be able to drive a 10 kΩ load. 4V REFTF

10mF 0.1mF AD9280
Figure 21 shows an example of the user driving the top and bottom
2V REFBF
references. REFTS is connected to a low impedance 2 V source 0.1mF 0.1mF
REFBS
and REFBS is connected to a low impedance 1 V source. REFTS
and REFBS may be driven to any voltage within the supply as long VREF
as the difference between them is between 1 V and 2 V.
AVDD REFSENSE

MODE
2V AIN
AD9280
1V SHA
Figure 23a. External Reference—2 V p-p Input Span
10kV 0.1mF
REFTF

REFTS 10kV REFTS

2V
+5V
REFBS A2 0.1mF 10mF C4
1V A/D 4.2kV 6 0.1mF
10kV CORE TOTAL 8
7
REFTF
REF 5
REFT C3 C6
SENSE 10kV 0.1mF 0.1mF
AVDD C2
0.1mF AD9280
MODE REFBF 10mF
REFBS
C5
2 0.1mF
Figure 21. External Reference Mode—1 V p-p Input Span 6
REFBF
3
REFB 4 C1
Figure 22 shows an example of an external reference generating 0.1mF
2.5 V at the shorted REFTS and REFBS inputs. In this in-
stance, a REF43 2.5 V reference drives REFTS and REFBS. A
Figure 23b. Kelvin Connected Reference Using the AD9280
resistive divider generates a 1 V VREF signal that is buffered by
A3. A3 must be able to drive a 10 kΩ, capacitive load. Choose
STANDBY OPERATION
this op amp based on noise and accuracy requirements.
The ADC may be placed into a powered down (sleep) mode by
driving the STBY (standby) pin to logic high potential and
AD9280
holding the clock at logic low. In this mode the typical power
3.0V drain is approximately 4 mW.
2.5V AIN
2.0V AVDD AVDD
REFTS
The ADC will “wake up” in 400 ns (typ) after the standby pulse
REFBS 0.1mF goes low.
10mF 1.5kV 0.1mF REFTF
CLAMP OPERATION
0.1mF 10mF
A3 VREF The AD9280ARS features an optional clamp circuit for dc
1.0mF 0.1mF
0.1mF restoration of video or ac coupled signals. Figure 24 shows the
0.1mF 1kV REFBF internal clamp circuitry and the external control signals needed
AVDD/2 MODE
+5V
for clamp operation. To enable the clamp, apply a logic high to
AVDD REFSENSE the CLAMP pin. This will close the switch SW1. The clamp
REF43 amplifier will then servo the voltage at the AIN pin to be equal
0.1mF
to the clamp voltage applied at the CLAMPIN pin. After the
desired clamp level is attained, SW1 is opened by taking
Figure 22. External Reference Mode—1 V p-p Input CLAMP back to a logic low. Ignoring the droop caused by the
Span 2.5 VCM input bias current, the input capacitor CIN will hold the dc
voltage at AIN constant until the next clamp interval. The input
resistor RIN has a minimum recommended value of 10 Ω, to
maintain the closed-loop stability of the clamp amplifier.

–12– REV. D
 AD9280
The allowable voltage range that can be applied to CLAMPIN back porch to truncate the SYNC below the AD9280’s mini-
depends on the operational limits of the internal clamp ampli- mum input voltage. With a CIN = 1 µF, and RIN = 20 Ω, the
fier. The recommended clamp range is between 0.5 volts and acquisition time needed to set the input dc level to one volt
2.0 volts. with 1 mV accuracy is about 140 µs, assuming a full 1 volt VC.
The input capacitor should be sized to allow sufficient acquisi- With a 1 µF input coupling capacitor, the droop across one
tion time of the clamp voltage at AIN within the CLAMP inter- horizontal can be calculated:
val, but also be sized to minimize droop between clamping IBIAS = 22 µA, and t = 63.5 µs, so dV = 1.397 mV, which is less
intervals. Specifically, the acquisition time when the switch is than one LSB.
closed will equal:
After the input capacitor is initially charged, the clamp pulse
V  width only needs to be wide enough to correct small voltage
T ACQ = RIN CIN ln  C 
 VE  errors such as the droop. The fine scale settling characteristics
of the clamp circuitry are shown in Table II.
where VC is the voltage change required across CIN, and VE is
Depending on the required accuracy, a CLAMP pulse width of
the error voltage. VC is calculated by taking the difference be-
1 µs–3 µs should work in most applications. The OFFSET val-
tween the initial input dc level at the start of the clamp interval
ues ignore the contribution of offset from the clamp amplifier;
and the clamp voltage supplied at CLAMPIN. VE is a system
they simply compare the output code with a “final value” mea-
dependent parameter, and equals the maximum tolerable devia-
sured with a much longer CLAMP pulse duration.
tion from VC. For example, if a 2-volt input level needs to be
clamped to 1 volt at the AD9280’s input within 10 millivolts,
Table II.
then VC equals 2 – 1 or 1 volt, and VE equals 10 mV. Note that
once the proper clamp level is attained at the input, only a very CLAMP OFFSET
small voltage change will be required to correct for droop.
8 µs <1 LSB
The voltage droop is calculated with the following equation:
4 µs <2 LSBs
3 µs
()
I BIAS 2 LSBs
dV = t 2 µs 5 LSBs
CIN
1 µs 9 LSBs
where t = time between clamping intervals.
The bias current of the AD9280 will depend on the sampling
rate, FS, and the difference between the reference midpoint, AD9280
(REFTS–REFBS)/2 and the input voltage. For a fixed sampling CLAMP IN
rate of 32 MHz, Figure 14 shows the input bias current for a
given input. For a 1 V input range, the maximum input bias
current from Figure 14 is 22 µA. For lower sampling rates the CLAMP
SW1
input bias current will scale proportionally. CIN RIN AIN TO
If droop is a critical parameter, then the minimum value of CIN SHA
should be calculated first based on the droop requirement.
Acquisition time—the width of the CLAMP pulse—can be
Figure 24a. Clamp Operation
adjusted accordingly once the minimum capacitor value is cho-
sen. A tradeoff will often need to be made between droop and
acquisition time, or error voltage VE.
AIN
Clamp Circuit Example
0.1mF
A single supply video amplifier outputs a level-shifted video REFTF

signal between 2 and 3 volts with the following parameters: REFTS

horizontal period = 63.56 µs, AD9280

10mF 0.1mF
0.1mF
horizontal sync interval = 10.9 µs,
REFBF

horizontal sync pulse = 4.7 µs, REFBS

sync amplitude = 0.3 volts, AVDD

MODE
2
video amplitude of 0.7 volts,
CLAMP
reference black level = 2.3 volts
SHORT TO REFBS
The video signal must be dc restored from a 2- to 3-volt range OR EXTERNAL DC
CLAMPIN

down to a 1- to 2-volt range. Configuring the AD9280 for a

one volt input span with an input range from 1 to 2 volts (see
Figure 24b. Video Clamp Circuit
Figure 24), the CLAMPIN voltage can be set to 1 volt with an
external voltage or by direct connection to REFBS. The CLAMP
pulse may be applied during the SYNC pulse, or during the

REV. D –13–
AD9280
DRIVING THE ANALOG INPUT In many cases, particularly in single-supply operation, ac cou-
Figure 25 shows the equivalent analog input of the AD9280, a pling offers a convenient way of biasing the analog input signal
sample-and-hold amplifier (switched capacitor input SHA). at the proper signal range. Figure 27 shows a typical configura-
Bringing CLK to a logic low level closes Switches 1 and 2 and tion for ac-coupling the analog input signal to the AD9280.
opens Switch 3. The input source connected to AIN must Maintaining the specifications outlined in the data sheet
charge capacitor CH during this time. When CLK transitions requires careful selection of the component values. The most
from logic “low” to logic “high,” Switches 1 and 2 open, placing important is the f –3 dB high-pass corner frequency. It is a function of
the SHA in hold mode. Switch 3 then closes, forcing the output R2 and the parallel combination of C1 and C2. The f –3 dB point
of the op amp to equal the voltage stored on CH. When CLK can be approximated by the equation:
transitions from logic “high” to logic “low,” Switch 3 opens f –3 dB = 1/(2 × pi × [R2] CEQ)
first. Switches 1 and 2 close, placing the SHA in track mode.
where CEQ is the parallel combination of C1 and C2. Note that
The structure of the input SHA places certain requirements on C1 is typically a large electrolytic or tantalum capacitor that
the input drive source. The combination of the pin capacitance, becomes inductive at high frequencies. Adding a small ceramic
CP, and the hold capacitance, CH, is typically less than 5 pF. or polystyrene capacitor (on the order of 0.01 µF) that does not
The input source must be able to charge or discharge this ca- become inductive until negligibly higher frequencies, maintains
pacitance to 8-bit accuracy in one half of a clock cycle. When a low impedance over a wide frequency range.
the SHA goes into track mode, the input source must charge or
discharge capacitor CH from the voltage already stored on CH NOTE: AC coupled input signals may also be shifted to a desired
to the new voltage. In the worst case, a full-scale voltage step on level with the AD9280’s internal clamp. See Clamp Operation.
the input, the input source must provide the charging current
through the RON (50 Ω) of Switch 1 and quickly (within 1/2 CLK C1 R1
period) settle. This situation corresponds to driving a low input VIN AIN
impedance. On the other hand, when the source voltage equals R2 IB
AD9280
the value previously stored on CH, the hold capacitor requires C2
VBIAS
no input current and the equivalent input impedance is ex-
tremely high.
Adding series resistance between the output of the source and Figure 27. AC Coupled Input
the AIN pin reduces the drive requirements placed on the
There are additional considerations when choosing the resistor
source. Figure 26 shows this configuration. The bandwidth of
values. The ac-coupling capacitors integrate the switching tran-
the particular application limits the size of this resistor. To
sients present at the input of the AD9280 and cause a net dc
maintain the performance outlined in the data sheet specifica-
bias current, IB, to flow into the input. The magnitude of the
tions, the resistor should be limited to 20 Ω or less. For applica-
bias current increases as the signal magnitude deviates from
tions with signal bandwidths less than 16 MHz, the user may
V midscale and the clock frequency increases; i.e., minimum
proportionally increase the size of the series resistor. Alterna-
bias current flow when AIN = V midscale. This bias current
tively, adding a shunt capacitance between the AIN pin and
will result in an offset error of (R1 + R2) × IB. If it is necessary
analog ground can lower the ac load impedance. The value of
to compensate this error, consider making R2 negligibly small or
this capacitance will depend on the source resistance and the
modifying VBIAS to account for the resultant offset.
required signal bandwidth.
In systems that must use dc coupling, use an op amp to level-
The input span of the AD9280 is a function of the reference
shift a ground-referenced signal to comply with the input re-
voltages. For more information regarding the input range, see
quirements of the AD9280. Figure 28 shows an AD8041 config-
the Internal and External Reference sections of the data sheet.
ured in noninverting mode.

CH
+VCC
AIN 0.1mF
S1
CP
S3 SHA NC
0VDC 1V p-p 7 AD9280
(REFTS S2 2
CH 1
REFBS) 20V
CP AD8041 6 AIN
5
AD9280 3
MIDSCALE 4
OFFSET NC
VOLTAGE
Figure 25. AD9280 Equivalent Input Structure
Figure 28. Bipolar Level Shift
< 20V
AIN

VS AD9280

Figure 26. Simple AD9280 Drive Configuration

–14– REV. D
 AD9280
DIFFERENTIAL INPUT OPERATION The pipelined architecture of the AD9280 operates on both
The AD9280 will accept differential input signals. This function rising and falling edges of the input clock. To minimize duty
may be used by shorting REFTS and REFBS and driving them cycle variations the recommended logic family to drive the clock
as one leg of the differential signal (the top leg is driven into input is high speed or advanced CMOS (HC/HCT, AC/ACT)
AIN). In the configuration below, the AD9280 is accepting a logic. CMOS logic provides both symmetrical voltage threshold
1 V p-p signal. See Figure 29. levels and sufficient rise and fall times to support 32 MSPS
operation. The AD9280 is designed to support a conversion rate
AD9280 of 32 MSPS; running the part at slightly faster clock rates may
2V
AIN be possible, although at reduced performance levels. Conversely,
0.1mF
1V AVDD/2 REFTF
some slight performance improvements might be realized by
REFTS clocking the AD9280 at slower clock rates.
0.1mF 10mF
REFBS
0.1mF S1 S2
VREF REFBF ANALOG S4
1.0mF 0.1mF INPUT tC
S3
REFSENSE tCH tCL

AVDD/2 MODE INPUT

CLOCK
25ns
Figure 29. Differential Input DATA
DATA 1
OUTPUT

AD876-8 MODE OF OPERATION

The AD9280 may be dropped into the AD876-8 socket. This Figure 31. Timing Diagram
will allow AD876-8 users to take advantage of the reduced The power dissipated by the output buffers is largely propor-
power consumption realized when running the AD9280 on a tional to the clock frequency; running at reduced clock rates
3.0 V analog supply. provides a reduction in power consumption.
Figure 30 shows the pin functions of the AD876-8 and AD9280.
The grounded REFSENSE pin and floating MODE pin effec- DIGITAL INPUTS AND OUTPUTS
tively put the AD9280 in the external reference mode. The Each of the AD9280 digital control inputs, THREE-STATE
external reference input for the AD876-8 will now be placed and STBY are reference to analog ground. The clock is also
on the reference pins of the AD9280. referenced to analog ground.

The clamp controls will be grounded by the AD876-8 socket. The format of the digital output is straight binary (see Figure
The AD9280 has a 3 clock cycle delay compared to a 3.5 cycle 32). A low power mode feature is provided such that for STBY
delay of the AD876-8. = HIGH and the clock disabled, the static power of the AD9280
will drop below 5 mW.
4V
AIN OTR
AD9280
2V
REFTS
4V REFTF
10mF 0.1mF
2V REFBF
0.1mF 0.1mF
REFBS
NC MODE
AVDD REFSENSE
–FS+1LSB +FS
CLAMP +FS–1LSB
–FS
CLAMPIN
OTR VREF Figure 32. Output Data Format
0.1mF

THREE-
STATE
Figure 30. AD876 Mode tDHZ tDEN
DATA
CLOCK INPUT (D0–D9)
HIGH
The AD9280 clock input is buffered internally with an inverter IMPEDANCE
powered from the AVDD pin. This feature allows the AD9280
to accommodate either +5 V or +3.3 V CMOS logic input sig- Figure 33. Three-State Timing Diagram
nal swings with the input threshold for the CLK pin nominally
at AVDD/2.

REV. D –15–
AD9280
APPLICATIONS that the bandlimited IF signal aliases back into the center of the
DIRECT IF DOWN CONVERSION USING THE AD9280 ADC’s baseband region (i.e., FS/4). For example, if an IF sig-
Sampling IF signals above an ADC’s baseband region (i.e., dc nal centered at 45 MHz is sampled at 20 MSPS, an image of
to FS/2) is becoming increasingly popular in communication this IF signal will be aliased back to 5.0 MHz which corre-
applications. This process is often referred to as Direct IF Down sponds to one quarter of the sample rate (i.e., FS/4). This
Conversion or Undersampling. There are several potential ben- demodulation technique typically reduces the complexity of the
efits in using the ADC to alias (i.e., or mix) down a narrowband post digital demodulator ASIC which follows the ADC.
or wideband IF signal. First and foremost is the elimination of a To maximize its distortion performance, the AD9280 is config-
complete mixer stage with its associated amplifiers and filters, ured in the differential mode with a 1 V span using a transformer.
reducing cost and power dissipation. Second is the ability to The center tap of the transformer is biased at midsupply via a
apply various DSP techniques to perform such functions as resistor divider. Preceding the AD9280 is a bandpass filter as
filtering, channel selection, quadrature demodulation, data well as a 32 dB gain stage. A large gain stage may be required
reduction, detection, etc. A detailed discussion on using this to compensate for the high insertion losses of a SAW filter used
technique in digital receivers can be found in Analog Devices for image rejection. The gain stage will also provide adequate
Application Notes AN-301 and AN-302. isolation for the SAW filter from the charge “kick back” currents
In Direct IF Down Conversion applications, one exploits the associated with AD9280’s input stage.
inherent sampling process of an ADC in which an IF signal The gain stage can be realized using one or two cascaded
lying outside the baseband region can be aliased back into the AD8009 op amps amplifiers. The AD8009 is a low cost, 1 GHz,
baseband region in a similar manner that a mixer will down- current-feedback op amp having a 3rd order intercept character-
convert an IF signal. Similar to the mixer topology, an image ized up to 250 MHz. A passive bandpass filter following the
rejection filter is required to limit other potential interfering AD8009 attenuates its dominant 2nd order distortion products
signals from also aliasing back into the ADC’s baseband region. which would otherwise be aliased back into the AD9280’s
A tradeoff exists between the complexity of this image rejection baseband region. Also, it reduces any out-of-band noise which
filter and the sample rate as well as dynamic range of the ADC. would also be aliased back due to the AD9280’s noise band-
The AD9280 is well suited for various narrowband IF sampling width of 220+ MHz. Note, the bandpass filters specifications
applications. The AD9280’s low distortion input SHA has a are application dependent and will affect both the total distor-
full-power bandwidth extending to 300 MHz thus encompassing tion and noise performance of this circuit.
many popular IF frequencies. The AD9280 will typically yield The distortion and noise performance of an ADC at the given
an improvement in SNR when configured for the 2 V span, the IF frequency is of particular concern when evaluating an ADC
1 V span provides the optimum full-scale distortion perfor- for a narrowband IF sampling application. Both single-tone and
mance. Furthermore, the 1 V span reduces the performance dual-tone SFDR vs. amplitude are very useful in assessing an
requirements of the input driver circuitry and thus may be ADC’s noise performance and noise contribution due to aper-
more practical for system implementation purposes. ture jitter. In any application, one is advised to test several units
Figure 34 shows a simplified schematic of the AD9280 config- of the same device under the same conditions to evaluate the
ured in an IF sampling application. To reduce the complexity of given applications sensitivity to that particular device.
the digital demodulator in many quadrature demodulation ap-
plications, the IF frequency and/or sample rate are selected such

G1 = 20dB G2 = 12dB L-C

SAW BANDPASS MINI CIRCUITS
FILTER 50V
AD9280
FILTER T4 - 6T
OUTPUT 50V 1:4 AIN
50V
200V 200V
280V REFTS

22.1V REFBS
93.1V
VREF
1.0mF 0.1mF
REFSENSE

1kV
AVDD
1kV 0.1mF

Figure 34. Simplified AD9280 IF Sampling Circuit

–16– REV. D
 AD9280
Figures 35–38 combine the dual-tone SFDR as well as single is referenced to dBc. The AD9280 was operated in the differen-
tone SFDR and SNR performance at IF frequencies of 45 MHz, tial mode (via transformer) with a 1 V span. The analog sup-
70 MHz, 85 MHz and 135 MHz. Note, the SFDR vs. ampli- ply (AVDD) and the digital supply (DRVDD) were set to +5 V
tude data is referenced to dBFS while the single tone SNR data and 3.3 V, respectively.

70 80
DUAL TONE SFDR

60 70 SINGLE TONE SFDR

WORST CASE SPURIOUS – dBFS

SINGLE TONE SFDR

WORST CASE SPURIOUS – dBFS

60
50 DUAL TONE SFDR
50
SNR – dBc

40

SNR – dBc
40
30
SNR 30
SNR
20 CLK = 25.7MHz
20 CLK = 30.9MHz
SINGLE TONE = 45.5MHz
SINGLE TONE = 85.5MHz
DUAL TONE F1 = 44.5MHz
DUAL TONE F1 = 84.5MHz
10 F2 = 45.5MHz
10 F2 = 85.5MHz

0 0
–0.5 –5 –10 –15 –20 –25 –30 –35 –40 –0.5 –5 –10 –15 –20 –25 –30 –35 –40
INPUT POWER LEVEL – dBFS INPUT POWER LEVEL – dBFS

Figure 35. SNR/SFDR for IF @ 45 MHz Figure 37. SNR/SFDR for IF @ 85 MHz

70 70

DUAL TONE SFDR SINGLE TONE SFDR

60 60
WORST CASE SPURIOUS – dBFS

SINGLE TONE SFDR DUAL TONE SFDR

WORST CASE SFDR – dBFS

50 50
SNR – dBc
SNR – dBc

40 40

30 30
SNR SNR
20 20 FS = 32MHz
CLK = 31.1MHz SINGLE TONE = 135.5MHz
SINGLE TONE = 70.5MHz F1 = 134.5MHz
10 DUAL TONE F1 = 69.5MHz 10 F2 = 135.5MHz
F2 = 70.5MHz
0 0
–0.5 –5 –10 –15 –20 –25 –30 –35 –40 –0.5 –5 –10 –15 –20 –25 –30 –35 –40
INPUT POWER LEVEL – dBFS INPUT POWER LEVEL – dBFS

Figure 36. SNR/SFDR for IF @ 70 MHz Figure 38. SNR/SFDR for IF @ 135 MHz

REV. D –17–
AD9280
R10 R11
5kV 15kV +3–5A
+3–5A TP14 AD822 R17
AD822 5 R15 316V 0.626V TO 4.8V
R7 1kV
5.49kV 2 4 7 Q1 TP16
XXXX U2
1 6 2N3906
ADJ. U2
R8 3
8 C7 EXTT
D1 10kV 0.1mF
AD1580 CW C8 C11 C12 C13
10/10V 0.1mF R19 0.1mF 10/10V
178V
R9 +3–5A
1.5kV CM
R13
11kV
R20
R12 178V TP17
AD822 C29
10kV
XXXX 2 0.1mF
4 AD822
ADJ. 1 6 EXTB
U3
3 7 C14 C15
U3 Q2
8 0.1mF 10/10V
CW C10 5 R16 2N3904
C9
0.1mF 1kV R18
10/10V
316kV

TP11 +3–5A
J7
JP5
CLAMP
R37
1kV DRVDD
R53
49.9V B1
JP17 S3 2
3 THREE-STATE
R38
1kV A
B1
GND S4 2
JP18 3 STBY
A
R39
1kV

7 10
13 J8
RN1
AVDD DRVDD 22V
27 J8
C16 C19 6 11
0.1mF 0.1mF 11 J8 25 J8
RN1
22V 3 J8
C17 C18 5 12 2 J8
10/10V 10/10V 9 J8
RN1 4 J8
28 2 22V 6 J8
OTR 16 8 4 13
AVDD DRVDD TP19 B U4 A 8 J8
15 9 7 J8
B U4 A
WHITE D5 21 3 RN1 10 J8
B U4 A
AD9280 D6 20 B U4 A 4 22V
13 12 J8
U1 OTR D7 19 B U4 A 5 2 15
D8 18 6 5 J8 14 J8
B U4 A
15 3 D0 D9 17 7 RN1
DUTCLK CLK NC B U4 A 16 J8
16 4 D1 14 10 B 1 S2 22V
THREE-STATE THREE-STATE NC B U4 A 2
17 5 D2 DRVDD 24 1 +3–5D 18 J8
STBY STBY BIT0 23 VCCB VCCA 2 3 1 16
18 6 D3 NC1 T/R C20 1 J8
REFSENSE REFSENSE BIT1 C40 22 11 20 J8
19 7 D4 GD2 0.1mF A RN1
CLAMP CLAMP BIT2 0.1mF 13 OE 12
20 8 D5 GD1 U4 GD3 22V 22 J8
CLAMPIN 21 CLAMPIN BIT3 9 D6 GND
REFTS REFTS BIT4 GND 24 J8
22 10 D7 GND GND 74LVXC4245WM JP21 CLK
REFTF 23 REFTF BIT5 11 D8 1
3 WHITE 26 J8
MODE 24 MODE BIT6 12 D9 +3–5D
REFBF REFBF BIT7 19 5 2 6 11 NC 39 J8
25 CLK B U5 A 33 J8
REFBS 26 REFBS 20 4 C42
VREF VREF 21 B U5 A RN2 CLK_OUT 28 J8
27 3 0.1mF
AIN AIN B U5 A 22V 5 12
D0 18 B U5 6 29 J8
A 23 J8
D1 17 U5 7
C33 + AVSS DRVSS
D2 16
B A
8
RN2 30 J8
10/10V 1 14 B U5 A 22V
D3 15 9 31 J8
14 B U5 A
D4 10 4 13
24 B U5 A 21 J8 32 J8
1 +3–5D
23 VCCB VCCA 2 RN2
NC1 T/R 34 J8
DRVDD 22 11 C21 22V
NOTE: OE GD2 0.1mF NC 35 J8
C41 13 12 3 14
THE AD9280 IS EXERCISED IN GD1 U5 GD3
0.1mF 19 J8 36 J8
AN AD9200 EVALUATION BOARD GND
74LVXC4245WM RN2
GND 22V NC 37 J8
GND
2 15 38 J8
3 2 1 17 J8
40 J8
JP20 C43 RN2
0.1mF 22V
GND 1 16
15 J8
GND RN2
22V

Figure 39a. Evaluation Board Schematic

–18– REV. D
 AD9280
REFSENSE
JP1
JP10 JP14
EXTB AVDD
AVDD TP3
JP2 C3
TP1 0.1mF
R5 MODE
REFBF
10kV
C5 C4 TP4
10/10V JP15
+ 0.1mF
JP3 JP9
REFTF
C6 R6
JP4 0.1mF 10kV
VREF B JP16
TP5 GND
1 EXTT
S5
2
CLAMPIN
3 JP11 GND
TP6
A EXTT
JP6
REFTS

GND JP22
JP12 AVDD AVDDCLK
C35 C36 C37 C38
10/10V 0.1mF 0.1mF 0.1mF
TP7 R35
REFBS
4.99kV
JP7 JP13 GND
EXTB R34
2kV CW
T1–1T U6 U6
AIN 1 2 5 6
J1 A 3 R36
2 4.99kV
3 4
S8 2 TP12
1 B
R1 TP8 1B
49.9V 6 S6 2
P C30 1B 3
JP8 S 1 0.1mF S7 2
REFBS
T1 TP9 3 A R51
JP26 R2 J5 49.9V
C1 100V A
0.1mF CM ADC_CLK
CLK

A TP10 R4
R3 TP13
2 100V DCIN 49.9V R52
3 U6
3 4 49.9V
C2 S1 1 DUTCLK
47/10V B

TP29

L4
J9 +3–5D
C32 C31
0.1mF 10/10V
TP20
U6 DECOUPLING U6
L1 AVDDCLK 9 8
J2 DRVDD
C22 C23
0.1mF 10/10V U6
TP21 14 11 10
74AHC14 PWR
L2 U6 C28 U6
J3 AVDD 0.1mF 13 12
GND
C24 C25
0.1mF 33/16V 7
TP22

L3
J4 +3–5A
C26 C27
0.1mF 10/10V

TP23 TP24 TP25 TP26 TP27 TP28

GND J6

GND J10

Figure 39b. Evaluation Board Schematic

REV. D –19–
AD9280

Figure 40a. Evaluation Board, Component Signal (Not to Scale)

Figure 40b. Evaluation Board, Solder Signal (Not to Scale)

–20– REV. D
 AD9280

Figure 40c. Evaluation Board Power Plane (Not to Scale)

Figure 40d. Evaluation Board Ground Plane (Not to Scale)

REV. D –21–
AD9280

Figure 40e. Evaluation Board Component Silk (Not to Scale)

C33 C6
C18 C19 C4

C5

C3
C16
C17

Figure 40f. Evaluation Board Solder Silk (Not to Scale)

–22– REV. D
 AD9280
GROUNDING AND LAYOUT RULES DIGITAL OUTPUTS
As is the case for any high performance device, proper ground- Each of the on-chip buffers for the AD9280 output bits
ing and layout techniques are essential in achieving optimal (D0–D7) is powered from the DRVDD supply pins, separate
performance. The analog and digital grounds on the AD9280 from AVDD. The output drivers are sized to handle a variety
have been separated to optimize the management of return of logic families while minimizing the amount of glitch energy
currents in a system. Grounds should be connected near the generated. In all cases, a fan-out of one is recommended to
ADC. It is recommended that a printed circuit board (PCB) of keep the capacitive load on the output data bits below the speci-
at least four layers, employing a ground plane and power planes, fied 20 pF level.
be used with the AD9280. The use of ground and power planes For DRVDD = 5 V, the AD9280 output signal swing is com-
offers distinct advantages: patible with both high speed CMOS and TTL logic families.
1. The minimization of the loop area encompassed by a signal For TTL, the AD9280 on-chip, output drivers were designed to
and its return path. support several of the high speed TTL families (F, AS, S). For
applications where the clock rate is below 32 MSPS, other TTL
2. The minimization of the impedance associated with ground
families may be appropriate. For interfacing with lower voltage
and power paths.
CMOS logic, the AD9280 sustains 32 MSPS operation with
3. The inherent distributed capacitor formed by the power plane, DRVDD = 3 V. In all cases, check your logic family data sheets
PCB insulation and ground plane. for compatibility with the AD9280 Digital Specification table.
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in THREE-STATE OUTPUTS
performance. The digital outputs of the AD9280 can be placed in a high
impedance state by setting the THREE-STATE pin to HIGH.
It is important to design a layout that prevents noise from cou- This feature is provided to facilitate in-circuit testing or evaluation.
pling onto the input signal. Digital signals should not be run in
parallel with the input signal traces and should be routed away
from the input circuitry. Separate analog and digital grounds
should be joined together directly under the AD9280 in a solid
ground plane. The power and ground return currents must be
carefully managed. A general rule of thumb for mixed signal
layouts dictates that the return currents from digital circuitry
should not pass through critical analog circuitry.

REV. D –23–
AD9280
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

28-Lead Shrink Small Outline Package (SSOP)

(RS-28)

C3118d–0–8/99
0.407 (10.34)
0.397 (10.08)

28 15

0.212 (5.38)
0.205 (5.21)
0.301 (7.64)
0.311 (7.9)

1 14

0.078 (1.98) PIN 1 0.07 (1.79)

0.068 (1.73) 0.066 (1.67)

8° 0.03 (0.762)
0.008 (0.203) 0.0256 0.015 (0.38)
SEATING 0.009 (0.229) 0° 0.022 (0.558)
(0.65) 0.010 (0.25)
0.002 (0.050) BSC PLANE
0.005 (0.127)

PRINTED IN U.S.A.

–24– REV. D