LTC4101

Smart Battery
Charger Controller
FEATURES DESCRIPTION
n Single Chip Smart Battery Charger Controller The LTC®4101 Smart Battery Charger is a single chip
n 100% Compliant (Rev. 1.1) SMBus Support Allows charging solution that dramatically simplifies construction
for Operation with or without Host of an SBS compliant system. The LTC4101 implements
n Up to 4A Charging Current Capability a Level 2 charger function whereby the charger can be
n High Efficiency Synchronous Buck Charger programmed by the battery or by the host. A SafetySignal
n VBAT Optimized 3V to 5.5V on the battery being charged is monitored for temperature,
n SMBus Accelerator Improves SMBus Timing connectivity and battery type information. The SMBus
n Hardware Interrupt and SMBAlert Response interface remains alive when the AC power adapter is
Eliminate Interrupt Polling removed and responds to all SMBus activity directed to
n 0.5V Dropout Voltage; Maximum Duty Cycle > 98% it, including SafetySignal status (via the ChargerStatus
n AC Adapter Current Limit Maximizes Charge Rate command). The charger also provides an interrupt to the
n ±0.8% Voltage Accuracy; ±4% Current Accuracy host whenever a status change is detected (e.g., battery
n 10-Bit DAC for Charge Current Programming removal, AC adapter connection).
n 11-Bit DAC for Charger Voltage Programming
n
Charging current and voltage are restricted to chemistry-
User-Selectable Overvoltage and Overcurrent Limits
n
specific limits for improved system safety and reliability.
High Noise Immunity SafetySignal Sensor
n
Limits are programmable by two external resistors. Ad-
Available in a 24-Pin SSOP Package
ditionally, the maximum average current from the AC
APPLICATIONS adapter is programmable to avoid overloading the adapter
n
when simultaneously supplying load current and charging
Portable Instruments and Computers
n
current. When supplying system load current, charg-
Data Storage Systems and Battery Backup Servers
ing current is automatically reduced to prevent adapter
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
overload.
Protected by U.S. Patents including 6650174, 5723970.

TYPICAL APPLICATION
DCIN
9V to 12V, 2A 0.1μF VBAT PART
6.04k
3V 1.21k < 5.5V LTC4101
TO 5.5V > 5.5V LTC4100
LTC4101 0.1μF 0.05Ω
17 5
VDD DCIN
11 4
DCDIV INFET 5k
6 24
CHGEN CHGEN CLP SYSTEM LOAD
10 23
ACP ACP CLN 5μF SMART BATTERY
7 1 0.1Ω 1%
SMBALERT TGATE
9 3 24μH
SCL BGATE
8 2
SDA PGND 5μF
15 21
THB CSP
16 22
THA BAT
13 18
ILIM VSET
1.13k 14 19 100Ω
VLIM ITH 0.03μF
20 12
10k IDC GND 6.04k
54.9k 0.0015μF
0.068μF 0.12μF 0.1μF

SMBALERT# SafetySignal
SMBCLK SMBCLK
SMBDAT SMBDAT 4101 F01a

Figure 1. 1A Smart Battery Charger

4101fa

1
LTC4101
ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION
(Note 1)
TOP VIEW
Voltage from VDD to GND ................................. 7V/–0.3V
TGATE 1 24 CLP
Voltage from CHGEN, DCDIV, SDA,
PGND 2 23 CLN
SCL and SMBALERT to GND ............................ 7V/–0.3V BGATE 3 22 BAT
Voltage from DCIN, CLP, CLN to GND............. 32V/–0.3V INFET 4 21 CSP
Voltage from CLP to CLN .......................................±0.3V DCIN 5 20 IDC
PGND wrt. GND..................................................... ±0.3V CHGEN 6 19 ITH

CSP, BAT to GND ............................................... 28V/–5V SMBALERT 7 18 VSET

Operating Ambient Temperature Range (Note 4) SDA 8 17 VDD

SCL 9 16 THA
.................................................................–40°C to 85°C
ACP 10 15 THB
Junction Temperature Range ................ –40°C to 125°C DCDIV 11 14 VLIM
Storage Temperature Range...................–65°C to 150°C GND 12 13 ILIM
Lead Temperature (Soldering, 10 sec) .................. 300°C
G PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 90°C/W

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4101EG#PBF LTC4101EG#TRPBF LTC4101EG 24-Lead Plastic SSOP –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4101EG LTC4101EG#TR LTC4101EG 24-Lead Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 4V unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DCIN Operating Range l 6 28 V
IDCIN DCIN Operating Current Charging, Sum of Currents on 3 5 mA
DCIN, CLP and CLN
VTOL Charge Voltage Accuracy (Note 2) –1.1 1.1 %
l –1.3 1.3 %
ITOL Charge Current Accuracy (Note 3) VCSP – VBAT Target = 102.3mV –2 6 %
IDAC = 0xFFFF l –3 7 %
VDD VDD Operating Voltage 0V ≤ VDCIN ≤ 28V l 3 5.5 V
Shutdown
Battery Leakage Current DCIN = 0V, VCLP = VCLN = VCSP = VBAT l 15 35 μA
UVLO Undervoltage Lockout Threshold DCIN Rising, VBAT = 0V l 4.2 4.7 5.5 V
VDD Power-Fail Part Held in Reset Until this VDD Present l 3 V
DCIN Current in Shutdown VCHGEN = 0V 2 3 mA
4101fa

2
 LTC4101
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 4V unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Sense Amplifier, CA1
Input Bias Current into BAT Pin 11.66 μA
CMSL CA1/I1 Input Common Mode Low l 0 V
CMSH CA1/I1 Input Common Mode High VDCIN ≤ 28V l VCLN –0.2 V
Current Comparators IREV
ITREV Reverse Current Threshold (VCSP-VBAT) –30 mV
Current Sense Amplifier, CA2
Transconductance 1 mmho
Source Current Measured at ITH, VITH = 1.4V –40 μA
Sink Current Measured at ITH, VITH = 1.4V 40 μA
Current Limit Amplifier
Transconductance 1.5 mmho
VCLP Current Limit Threshold l 93 100 107 mV
ICLN CLN Input Bias Current 50 nA
Voltage Error Amplifier, EA
Transconductance 1 mmho
Sink Current Measured at ITH, VITH = 1.4V 36 μA
OVSD Overvoltage Shutdown Threshold as a Percent l 102 107 110 %
of Programmed Charger Voltage
Input P-Channel FET Driver (INFET)
DCIN Detection Threshold (VDCIN-VCLP) DCIN Voltage Ramping Up l 0 0.17 0.25 V
from VCLP-0.05V
Forward Regulation Voltage (VDCIN-VCLP) l 25 50 mV
Reverse Voltage Turn-Off Voltage (VDCIN-VCLP) l –60 –25 mV
INFET ON Clamping Voltage (VDCIN-VINFET) IINFET = 1μA l 5 5.8 6.5 V
INFET OFF Clamping Voltage (VDCIN-VINFET) IINFET = –25μA 0.25 V
Oscillator
fOSC Regulator Switching Frequency 255 300 345 kHz
fMIN Regulator Switching Frequency in Drop Out Duty Cycle ≥ 98% 20 25 kHz
DCMAX Regulator Maximum Duty Cycle VCSP = VBAT 98 99 %
Gate Drivers (TGATE, BGATE)
VTGATE High (VCLP-VTGATE) ITGATE = –1mA 50 mV
VBGATE High CLOAD = 3000pF 4.5 5.6 10 V
VTGATE Low (VCLP-VTGATE) CLOAD = 3000pF 4.5 5.6 10 V
VBGATE Low IBGATE = 1mA 50 mV
TGATE Transition Time
TGTR TGATE Rise Time CLOAD = 3000pF, 10% to 90% 50 110 ns
TGTF TGATE Fall Time CLOAD = 3000pF, 10% to 90% 50 100 ns
BGATE Transition Time
BGTR BGATE Rise Time CLOAD = 3000pF, 10% to 90% 40 90 ns
BGTF BGATE Fall Time CLOAD = 3000pF, 10% to 90% 40 80 ns
VTGATE at Shutdown (VCLN-VTGATE) ITGATE = –1μA 100 mV
4101fa

3
LTC4101
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 4V unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VBGATE at Shutdown ITGATE = 1μA 100 mV
AC Present Comparator
VACP DCDIV Threshold VDCDIV Rising from 1V to 1.4V l 1.14 1.20 1.26 V
DCDIV Hysteresis 25 mV
DCDIV Input Bias Current VDCDIV = 1.2V –1 1 μA
ACP VOH IACP = –2mA 2 V
ACP VOL IACP = 1mA 0.5 V
DCDIV to ACP Delay VDCDIV = 1.3V 10 μs
SafetySignal Decoder
SafetySignal Trip (RES_COLD/RES_OR) RTHA = 1130Ω ±1%, CTH = 1nF (Note 6) l 95 100 105 kΩ
RTHB = 54.9Ω ±1%
SafetySignal Trip (RES_IDEAL/RES_COLD) RTHA = 1130Ω ±1%, CTH = 1nF (Note 6) l 28.5 30 31.5 kΩ
RTHB = 54.9Ω ±1%
SafetySignal Trip (RES_HOT/RES_IDEAL) RTHA = 1130Ω ±1%, CTH = 1nF (Note 6) l 2.85 3 3.15 kΩ
RTHB = 54.9Ω ±1%
SafetySignal Trip (RES_UR/RES_HOT) RTHA = 1130Ω ±1%, CTH = 1nF (Note 6) l 425 500 575 Ω
RTHB = 54.9Ω ±1%
Time Between SafetySignal Measurements DCDIV = 1.3V 32 ms
DCDIV = 1V 250 ms
DACs
Charging Current Resolution Guaranteed Monotonic Above IMAX/16 10 Bits
Charging Current Granularity RILIM = 0 1 mA
RILIM = 10k ±1% 2 mA
RILIM = 33k ±1% 4 mA
RILIM = Open (or Short to VDD) 4 mA
Wake-Up Charging Current (IWAKE-UP) All Values of RILIM 80 (Note mA
All Values of RVLIM 5)
Charging Current Limit RILIM = 0 (0-1A) 97.3 107.3 mV
CSP – BAT Charging Current = 0x03FF (0x0400 Note 7)
RILIM = 10k ±1% (0-2A) 97.3 107.3 mV
Charging Current = 0x07FE (0x0800 Note 7)
RILIM = 33k ±1% (0-3A) 72.3 82.3 mV
Charging Current = 0x0BFC (0x0C00 Note 7)
RILIM = 0pen (or Short to VDD) (0-4A) l 97.3 107.3 mV
Charging Current = 0x0FFC (0x1000 Note 7)
Charging Voltage Resolution Guaranteed Monotonic (2.9V ≤ VBAT ≤ 5.6V) 11 Bits
Charging Voltage Granularity 16 mV
Charging Voltage Limit RVLIM = 0 4.206 4.240 4.274 V
Charging Voltage = 0x1090 (Note 7)
RVLIM = 10k ±1% 4.270 4.304 4.338 V
Charging Voltage = 0x10D0 (Note 7)
RVLIM = 33k ±1% 4.397 4.432 4.467 V
Charging Voltage = 0x1150 (Note 7)
RVLIM = 100k ±1% 4.476 4.512 4.548 V
Charging Voltage = 0x11A0 (Note 7)
RVLIM = 0pen (or Short to VDD) 5.460 5.504 5.548 V
Charging Voltage = 0x1580 (Note 7)
4101fa

4
 LTC4101
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 4V unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Logic Levels
VIL SCL/SDA Input Low Voltage VDD = 3V and VDD = 5.5V l 0.8 V
VIH SCL/SDA Input High Voltage VDD = 3V and VDD = 5.5V l 2.1 V
VOL SDA Output Low Voltage IPULL-UP = 350μA l 0.4 V
IIL SCL/SDA Input Current VSDA, VSCL = VIL –1 1 μA
IIH SCL/SDA Input Current VSDA, VSCL = VIH –1 1 μA
VOL SMBALERT Output Low Voltage IPULL-UP = 500μA l 0.4 V
SMBALERT Output Pull-Up Current VSMBALERT = VOL –17.5 –10 –3.5 μA
ILEAK SDA/SCL/SMBALERT Power Down Leakage VSDA, VSCL, VSMBALERT = 5.5V, VDD = OV l –2 2 μA
VOL CHGEN Output Low Voltage IOL = 100μA l 0.5 V
CHGEN Output Pull-Up Current VCHGEN = VOL –17.5 –10 –3.5 μA
VIL CHGEN Input Low Voltage l 0.9 V
VIH CHGEN Input High Voltage VDD = 3V l 2.5 V
VDD = 5.5V 3.9 V
Power-On Reset Duration VDD Ramp from 0V to >3V in <5μs 100 μs
SMBus Timing (Refer to System Management Bus Specification, Revision 1.1, Section 2.1 for Timing Diagrams)
tHIGH SCL Serial Clock High Period IPULL-UP = 350μA, CLOAD = 250pF, RPU = 9.31k, l 4 μs
VDD = 3V and VDD = 5.5V
tLOW SCL Serial Clock Low Period IPULL-UP = 350μA, CLOAD = 250pF, RPU = 9.31k, l 4.7 15000 μs
VDD = 3V and VDD = 5.5V
tR SDA/SCL Rise Time CLOAD = 250pF, RPU = 9.31k, VDD = 3V l 1000 ns
and VDD = 5.5V
tF SDA/SCL Fall Time CLOAD = 250pF, RPU = 9.31k, VDD = 3V l 300 ns
and VDD = 5.5V
tSU:STA Start Condition Setup Time VDD = 3V and VDD = 5.5V l 4.7 μs
tHD:STA Start Condition Hold Time VDD = 3V and VDD = 5.5V l 4 μs
tHD:DAT SDA to SCL Falling-Edge Hold Time, VDD = 3V and VDD = 5.5V l 300 ns
Slave Clocking in Data
tTIMEOUT Time Between Receiving Valid VDD = 3V and VDD = 5.5V l 140 175 210 sec
ChargingCurrent() and
ChargingVoltage() Commands

Note 1: Stresses beyond those listed under Absolute Maximum Ratings temperature range are assured by design, characterization and correlation
may cause permanent damage to the device. Exposure to any Absolute with statistical process controls.
Maximum Rating condition for extended periods may affect device Note 5: Current accuracy dependent upon circuit compensation and sense
reliability and lifetime. resistor.
Note 2: See Test Circuit. Note 6: CTH is defined as the sum of capacitance on THA, THB and
Note 3: Does not include tolerance of current sense resistor. SafetySignal.
Note 4: The LTC4101E is guaranteed to meet performance specifications Note 7: The corresponding overrange bit will be set when a HEX value
from 0°C to 85°C. Specifications over the –40°C to 85°C operating greater than or equal to this value is used.

4101fa

5
LTC4101
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

INFET Response Time to

Reverse Current Output Voltage vs Output Current PWM Frequency vs Duty Cycle
0 350
Vgs OF PFET (2V/DIV)
Vgs = 0 –0.5
300

OUTPUT VOLTAGE ERROR (%)

–1.0

PWM FREQUENCY (kHz)

–1.5 250

–2.0 200
Vs OF PFET (5V/DIV)
–2.5
150
–3.0
PROGRAMMED CURRENT = 10%
–3.5 100
Vs = 0V
–4.0 VDCIN = 20V
Id (REVERSE) OF 50 DCIN = 9V
PFET (5A/DIV) –4.5 VPROG = 4.176V DCIN = 12V
IPROG = 4V DCIN = 24V
Id = 0A –5.0 0
1.25μs/DIV 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TEST PERFORMED ON DEMOBOARD OUTPUT CURRENT (A) DUTY CYCLE (VOUT/VIN)
VIN = 15VDC VCHARGE = 4.2V 4101 G02 4101 G03
CHARGER = ON INFET = 1/2 Si4925DY
ICHARGE = <10mA 4101 G01

Disconnect/Reconnect Battery Battery Leakage Current

(Load Dump) vs Battery Voltage Efficiency at VPROG = 4.208V
40 100
VDCIN = 0V
3A STEP 35 96 VIN = 8V
BATTERY LEAKAGE CURRENT (μA)

30
POWER EFFICIENCY (%)
1A STEP 1A STEP 92
VFLOAT
25
1V/(DIV)
88
20 VIN = 20V
84
15
3A STEP
LOAD 10 80
STATE DISCONNECT RECONNECT
5 76

0 72
LOAD CURRENT = 1A, 2A, 3A 0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
DCIN = 12V BATTERY VOLTAGE (V) IOUT (A)
VFLOAT = 4.2V
4101 G05 4101 G06
4101 G04

SMBus Accelerator Operation Low Current Operation

0.6
VDD = 5V VDD = 5V
5V CBUS = 200pF VBAT = 4V
0.5 VDCIN = 20V
VPROG = 4.208V
0.4
ICHARGE (A)

LTC4101 NO LOW
0.3 CURRENT
MODE
RPULLUP = 15k PROGRAMMED
0.2 CURRENT
0V LOW
0.1 CURRENT
MODE

0
0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
1μs/DIV IPROG (A)
4101 G07 4101 G08

4101fa

6
 LTC4101
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Charging Current Error Transfer Function of Charger

200 50
VDD = 5V VDD = 5V
IBAT = 0.120A
OUTPUT CURRENT ERROR (mA)

OUTPUT VOLTAGE ERROR (V)

100 0 VDCIN = 9V
VDCIN = 20V
VDCIN = 20V
0 VDCIN = 9V –50
VDCIN = 28V

–100 –100

–200 –150
0 1 2 3 4 0 1 2 3 4 5 6
CHARGING CURRENT (A) CHARGING VOLTAGE (V)
4101 G09 4101 G10

PIN FUNCTIONS
TGATE (Pin 1): Drives the Top External P-MOSFET of the SMBALERT (Pin 7): Active Low Interrupt Output to Host
Battery Charger Buck Converter. (referred to as the SMBALERT signal in the SMBus Revi-
PGND (Pin 2): High Current Ground Return for BGATE sion 1.1 specification). Signals host that there has been a
Driver. change of status in the charger registers and that the host
should read the LTC4101 status registers to determine
BGATE (Pin 3): Drives the Bottom External N-MOSFET of if any action on its part is required. This signal can be
the Battery Charger Buck Converter. connected to the optional SMBALERT line of the SMBus.
INFET (Pin 4): Drives the Gate of the External Input Open drain with weak current source pull-up to VDD (with
P-MOSFET. Schottky to allow it to be pulled to 5V externally).

DCIN (Pin 5): External DC Power Source Input. Bypass to SDA (Pin 8): SMBus Data Signal from Main (host-con-
ground with a 0.1μF capacitor. trolled) SMBus. External pull-up resistor is required.

CHGEN (Pin 6): Digital Bidirectional Pin to Enable Charger SCL (Pin 9): SMBus Clock Signal from Main (host-con-
Function. This pin is connected as a wired AND bus. trolled) SMBus. External pull-up resistor is required.

The following events will cause the POWER_FAIL bit in ACP (Pin 10): This Output Indicates the Value of the
the ChargerStatus register to become set: DCDIV Comparator. It can be used to indicate whether
AC is present or not.
1. An external device pulling the CHGEN signal to within
0.9V to GND; DCDIV (Pin 11): Supply Divider Input. This is a high im-
pedance comparator input with a 1.2V threshold (rising
2. The AC adapter voltage is not above the battery edge) and hysteresis.
voltage.
GND (Pin 12): Ground for Digital and Analog Circuitry.

4101fa

7
LTC4101
PIN FUNCTIONS
ILIM (Pin 13): An external resistor is connected between this ITH (Pin 19): Control Signal of the Inner Loop of the Current
pin and GND. The value of the external resistor programs Mode PWM. Higher ITH corresponds to higher charging
the range and resolution of the programmed charger current in normal operation. A 0.0015μF capacitor to GND
current. This is a digital, not an analog, function. filters out PWM ripple. Typical full-scale output current is
40μA. Nominal voltage range for this pin is 0V to 3V.
VLIM (Pin 14): An external resistor is connected between
this pin and GND. The value of the external resistor IDC (Pin 20): Bypass to GND with a 0.068μF Capacitor.
programs the range and resolution of the charging CSP (Pin 21): Current Amplifier CA1 Input. This pin
voltage. This is a digital, not an analog, function. and the BAT pin measure the voltage across the sense
THB (Pin 15): SafetySignal Force/Sense Pin to Smart resistor, RSENSE, to provide the instantaneous current
Battery. See description of operation for more detail. The signals required for both peak and average current mode
maximum allowed combined capacitance on THA, THB and operation.
SafetySignal is 1nF (see Figure 4). A series resistor 54.9k BAT (Pin 22): Battery Sense Input and the Negative Refer-
needs to be connected between this pin and the battery’s ence for the Current Sense Resistor. A bypass capacitor
SafetySignal for this circuit to work correctly. of at least 10μF is required.
THA (Pin 16): SafetySignal Force/Sense Pin to Smart CLN (Pin 23): Negative Input to the Input Current Limiting
Battery. See description of operation for more detail. The Circuit Block. If no current limit function is desired, connect
maximum allowed combined capacitance on THA, THB this pin to CLP. The threshold is set at 100mV below the
and SafetySignal is 1nF (see Figure 4). A series resistor voltage at the CLP pin. When used to limit supply current,
1130Ω needs to be connected between this pin and the a filter is needed to filter out the switching noise.
battery’s SafetySignal for this circuit to work correctly.
CLP (Pin 24): Positive Input to the Input Current Limiting
VDD (Pin 17): Power Supply Input for the LTC4101 Digital Circuit Block. This pin also serves as a power supply for
Circuitry. Bypass this pin with 0.1μF. Typically between the IC.
3.3V and 5VDC.
VSET (Pin 18): Tap Point of the Programmable Resistor
Divider, which Provides Battery Voltage Feedback to the
Charger.

4101fa

8
 LTC4101
BLOCK DIAGRAM

C4 VBAT
R4 0.03μF
100Ω – 3k BAT
VSET 22
VBAT 18
+ 11.67μA
C5, 0.1μF 11-BIT RSENSE
VDAC 20μF
GND –
12 CA1 3k CSP
DCIN + 21
1.28V
0V
OSCILLATOR CSP
9k
WATCHDOG
DETECT tON gm = 1m
Ω BUFFERED
SYSTEM – ITH
LOAD 20μF EA ÷5
1.19V +
CLP +
–
L1 S
TGATE ICMP
CSP Q2 1 Q R

PWM IREV –
17mV
D1 BGATE LOGIC IDC
Q3 3 + 20
R1 PGND C8
2 –
CA2 0.068μF
100mV Ω
CLN gm = 1.5m Ω + 1.19V
RCL C9 23 + gm = 1m ITH
CLP CL1 19
24 –
10-BIT R5, 6.04k C7
DCIN
5 IDAC 0.0015μF
C6, 0.12μF
5.8V
INFET 10 ACP
Q1 4
CLP DCDIV
11 VIN
VIN CHGEN 6 R10
VDD 1.2V R11
C1, 0.1μF
10μA
SMBALERT 7 17 VDD TO SMBUS
POWER SUPPLY

TO HOST AND BATTERY SMBus

INTERFACE
SDA 8 AND CONTROL ILIM
13
SCL 9 LIMIT
1.13k DECODER VLIM
14
16
THA THERMISTER
15 INTERFACE RVLIM RILIM
54.9k THB

10k

Figure 2.

4101fa

9
LTC4101
TEST CIRCUIT
LTC4101
1.19V +
– EA VBAT – VVDAC
– VTOL = • 100
+
VVDAC
VDAC FOR VVDAC = 4.176V(0 x1050)
21 22 18 19
CSP BAT VSET BAT ITH DCIN = 21V
+ CLN = CLP = 20V
LT1055
–
0.7V VDD = 3.3V

4101 TC01

OPERATION
Overview (Refer to Block Diagram) the commands exceed the programmed limits these limits
The LTC4101 is composed of a battery charger section, a are substituted and overrange flags are set.
charger controller, a 10-bit DAC to control charger current, The charger controller will assert SMBALERT whenever
an 11-bit DAC to control charger voltage, a SafetySignal a status change is detected, namely: AC_PRESENT, BAT-
decoder, limit decoder and an SMBus controller block. If TERY_PRESENT, ALARM_INHIBITED, or VDD power-fail.
no battery is present, the SafetySignal decoder indicates The host may query the charger, via the SMBus, to obtain
a RES_OR condition and charging is disabled by the ChargerStatus() information. SMBALERT will be deasserted
charger controller (CHGEN = Low). Charging will also be upon a successful read of ChargerStatus() or a successful
disabled if DCDIV is low, or the SafetySignal is decoded Alert Response Address (ARA) request.
as RES_HOT. If a battery is inserted and AC power is
connected, the battery will be charged with an 80mA Battery Charger Controller
“wake-up” current. The wake-up current is discontinued The LTC4101 charger controller uses a constant off-time,
after tTIMEOUT if the SafetySignal is decoded as RES_UR current mode step-down architecture. During normal
or RES_C0LD, and the battery or host doesn’t transmit operation, the top MOSFET is turned on each cycle when
charging commands. the oscillator sets the SR latch and turned off when the
The SMBus interface and control block receives Charg- main current comparator ICMP resets the SR latch. While
ingCurrent() and ChargingVoltage() commands via the the top MOSFET is off, the bottom MOSFET is turned
SMBus. If ChargingCurrent() and ChargingVoltage() on until either the inductor current trips the current
command pairs are received within a tTIMEOUT interval, the comparator IREV, or the beginning of the next cycle.
values are stored in the current and voltage DACs and the The oscillator uses the equation,
charger controller asserts the CHGEN line if the decoded (VDCIN – VBAT )
SafetySignal value will allow charging to commence. Charg- tOFF =
(VDCIN • fOSC )
ingCurrent() and ChargingVoltage() values are compared
against limits programmed by the limit decoder block; if

4101fa

10
 LTC4101
OPERATION
to set the bottom MOSFET on time. The result is quasi- Charger Start-Up
constant frequency operation: the converter frequency
remains nearly constant over a wide range of output When the charger is enabled, it will not begin switching
voltages. This activity is diagrammed in Figure 3. until the ITH voltage exceeds a threshold that assures initial
current will be positive. This threshold is 5% to 15% of the
OFF maximum programmed current. After the charger begins
TGATE
ON switching, the various loops will control the current at a
level that is higher or lower than the initial current. The
ON
BGATE tOFF duration of this transient condition depends upon the loop
OFF
TRIP POINT SET compensation, but is typically less than 1ms.
BY ITH VOLTAGE
INDUCTOR
CURRENT SMBus Interface
4101 F01

All communications over the SMBus are interpreted by the

Figure 3.
SMBus interface block. The SMBus interface is a SMBus
The peak inductor current, at which ICMP resets the SR slave device at address 0x12. All internal LTC4101 reg-
latch, is controlled by the voltage on ITH. ITH is in turn isters may be updated and accessed through the SMBus
controlled by several loops, depending upon the situation interface, and charger controller as required. The SMBus
at hand. The average current control loop converts the protocol is a derivative of the I2C bus (Reference “I 2C-
voltage between CSP and BAT to a representative current. Bus and How to Use It, V1.0” by Philips, and “System
Error amp CA2 compares this current against the desired Management Bus Specification,” Version 1.1, from the
current programmed by the IDAC at the IDC pin and adjusts SBS Implementers Forum, for a complete description of
ITH for the desired voltage across RSENSE. the bus protocol requirements.)
The voltage at BAT is divided down by an internal resis- All data is clocked into the shift register on the rising edge
tor divider set by the VDAC and is used by error amp EA of SCL. All data is clocked out of the shift register on the
to decrease ITH if the divider voltage is above the 1.19V falling edge of SCL. Detection of an SMBus Stop condi-
reference. tion, or power-on reset via the VDD power-fail, will reset
The amplifier CL1 monitors and limits the input current, the SMBus interface to an initial state at any time.
normally from the AC adapter, to a preset level (100mV/RCL). The LTC4101 command set is interpreted by the SMBus
At input current limit, CL1 will decrease the ITH voltage to interface and passed onto the charger controller block as
reduce charging current. control signals or updates to internal registers.
An overvoltage comparator, OV, guards against transient
overshoots (>7%). In this case, the top MOSFET is turned Description of Supported Battery Charger Functions
off until the overvoltage condition is cleared. This feature The functions are described as follows (see Table 1 also):
is useful for batteries that “load dump” themselves by
opening their protection switch to perform functions such FunctionName() 'hnn (command code)
as calibration or pulse mode charging. Description: A brief description of the function.
PWM Watchdog Timer Purpose: The purpose of the function, and an example
where appropriate.
There is a watchdog timer that observes the activity on the
TGATE pin. If TGATE stops switching for more than 40μs, • SMBus Protocol: Refer to Section 5 of the Smart
the watchdog activates and turns off the top MOSFET for Battery Charger specification for more details.
about 400ns. The watchdog engages to prevent very low
frequency operation in dropout – a potential source of audible
noise when using ceramic input and output capacitors. *http://www.SBS-FORUM.org
4101fa

11
LTC4101
OPERATION
Input, Output or Input/Output: A description of the data ChargerStatus() ('h13)
supplied to or returned by the function. Description: The SMBus Host uses this command to read
ChargerSpecInfo() ('h11) the LTC4101’s status bits.
Description: The SMBus Host uses this command to read Purpose: Allows the SMBus Host to determine the status
the LTC4101’s extended status bits. and level of the LTC4101.
Purpose: Allows the System Host to determine the • SMBus Protocol: Read Word.
specification revision the charger supports as well as Output: The CHARGE_INHIBITED bit reflects the status
other extended status information. of the LTC4101 set by the INHIBIT_CHARGE bit in the
• SMBus Protocol: Read Word. ChargerMode() function.
Output: The CHARGER_SPEC indicates that the LTC4101 The POLLING_ENABLED, VOLTAGE_NOTREG, and CUR-
supports Version 1.1 of the Smart Battery Charger RENT_NOTREG are not supported by the LTC4101.
Specification. The SELECTOR_SUPPORT indicates that The LTC4101 always reports itself as a Level 2 Smart
the LTC4101 does not support the optional Smart Battery Battery Charger.
Selector Commands.
CURRENT_OR bit is set only when ChargingCurrent() is
ChargerMode() ('h12) set to a value outside the current regulation range of the
Description: The SMBus Host uses this command to set LTC4101. This bit may be used in conjunction with the
the various charger modes. The default values are set to INHIBIT_CHARGE bit of the ChargerMode() and Charg-
allow a Smart Battery and the LTC4101 to work in concert ingCurrent() to determine the current capability of the
without requiring an SMBus Host. LTC4101. When ChargingCurrent() is set to ILIM + 1, the
CURRENT_OR bit will be set.
Purpose: Allows the SMBus Host to configure the charger
and change the default modes. This is a write only function, VOLTAGE_OR bit is set only when ChargingVoltage() is
but the value of the “mode” bit, INHIBIT_CHARGE may be set to a value outside the voltage regulation range of the
determined using the ChargerStatus() function. LTC4101. This bit may be used in conjunction with the
INHIBIT_CHARGE bit of the ChargerMode() and Charg-
• SMBus Protocol: Write Word. ingVoltage() to determine the voltage capability of the
Input: The INHIBIT_CHARGE bit allows charging to be LTC4101. When ChargingVoltage() is set to the VLIM, the
inhibited without changing the ChargingCurrent() and VOLTAGE_OR bit will be set.
ChargingVoltage() values. The charging may be resumed The RES_OR bit is set only when the SafetySignal resis-
by clearing this bit. This bit is automatically cleared when tance value is greater than 95kΩ. This indicates that the
power is reapplied or when a battery is reinserted. SafetySignal is to be considered as an open circuit.
The ENABLE_POLLING bit is not supported by the LTC4101. The RES_COLD bit is set only when the SafetySignal re-
Values written to this bit are ignored. sistance value is greater than 28.5kΩ. The SafetySignal
The POR_RESET bit sets the LTC4101 to its power-on indicates a cold battery. The RES_COLD bit will be set
default condition. whenever the RES_OR bit is set.
The RESET_TO_ZERO bit sets the ChargingCurrent()and The RES_HOT bit is set only when the SafetySignal resis-
ChargingVoltage() values to zero. This function ALWAYS tance is less than 3150Ω, which indicates a hot battery.
clears the ChargingVoltage() and ChargingCurrent() values The RES_HOT bit will be set whenever the RES_UR bit
to zero even if the INHIBIT_CHARGE bit is set. is set.

4101fa

12
 LTC4101
OPERATION
Table 1: Summary of Supported Charger Functions
SMBus Command Data
Function Access Address Code Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO

SELECTOR_SUPPORT
ChargerSpecInfo() 7'b0001_001 8'h11 Info
0x12

Reserved CHARGER_SPEC

Return
Read Values 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

ENABLE_POLLING

INHIBIT_CHARGE
RESET_TO_ZERO
ChargerMode() 7'b0001_001 8'h12 Control

POR_RESET
Reserved

Permitted
Write Values Ignored 1/0 1/0 Ign 1/0

CHARGE_INHIBITED
ChargerStatus() 7'b0001_001 8'h13 Status

POLLING_ENABLED
CURRENT_NOTREG
BATTERY_PRESENT

ALARM_INHIBITED

VOLTAGE_NOTREG
LEVEL:3/LEVEL:2
CURRENT_OR
AC_PRESENT

VOLTAGE_OR
POWER_FAIL

RES_COLD
RES_HOT
RES_UR

RES_OR
Return
Read Values 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0 1 0 0 0 1/0

ChargingCurrent() 7'b0001_001 8'h14 Value CHARGING_CURRENT[15:0]

Permitted
Unsigned integer representing current in mA
Write Values

ChargingVoltage() 7'b0001_001 8'h15 Value CHARGING_VOLTAGE[15:0]

Permitted Unsigned integer representing voltage in mV

Write Values
TERMINATE_DISCHARGE_ALARM

REMAINING_CAPACITY_ALARM

AlarmWarning() 7'b0001_001 8'h16 Control

TERMINATE_CHARGE_ALARM

REMAINING_TIME_ALARM
OVER_CHARGED_ALARM

OVER_TEMP_ALARM

FULLY DISCHARGED
RESERVED_ALARM

FULLY_CHARGED
DISCHARGING
INITIALIZED
Reserved

ERROR

Permitted
Write Values 1/0 1/0 1/0 1/0 Ignored
NO_LOWI

LTCO() 7'b0001_001 8'h3C Register

Reserved LTC4101's Version Identification

Permitted Ignored 1/0 Ignored

Write Values
Return
Read Values 0 1 0 1/0 0 0 0 0 0 1 0 0 0 0 0 0
Undefined

Alert Response 7'b0001_100 N/A Status LTC4101's Address

Address 0x18
Not Supported
Read Return
Byte Values 0 0 0 1 0 0 1 X

4101fa

13
LTC4101
OPERATION
The RES_UR bit is set only when the SafetySignal resis- ChargingCurrent() ('h14)
tance value is less than 575Ω. Description: The Battery, System Host or other master de-
ALARM_INHIBITED bit is set if a valid AlarmWarning() vice sends the desired charging current (mA) to the LTC4101.
message has been received and charging is inhibited as Purpose: The LTC4101 uses RILIM, the granularity of the
a result. This bit is cleared if both ChargingVoltage() and IDAC, and the value of the ChargingCurrent() function to
ChargingCurrent() are rewritten to the LTC4101, power is determine its charging current supplied to the battery. The
removed (DCDIV < VACP), or if a battery is removed. The charging current will never exceed the maximum current
setting of the ALARM_INHIBITED will activate the LTC4101 permitted by RILIM. The ChargingCurrent() value will be
SMBALERT pull-down. truncated to the granularity of the IDAC. The charging cur-
POWER_FAIL bit is set if the LTC4101 does not have suf- rent will also be reduced if the battery voltage exceeds the
ficient DCIN voltage to charge the battery or if an external programmed charging voltage.
device is pulling the CHGEN input signal low. Charging is • SMBus Protocol: Write Word.
disabled whenever this bit is set. The setting of this bit
does not clear the values in the ChargingVoltage() and Input: The CHARGING_CURRENT is an unsigned 16 bit
ChargingCurrent() function values, nor does it necessarily integer specifying the requested charging current in mA.
affect the charging modes of the LTC4101. The following table defines the maximum permissible
value of CHARGING_CURRENT that will not set the CUR-
BATTERY_PRESENT is set if a battery is present other- RENT_OR in the ChargerStatus() function for a given
wise it is cleared. The LTC4101 uses the SafetySignal value of the RILIM:
in order to determine battery presence. If the LTC4101
RILIM ChargingCurrent() Current
detects a RES_OR condition, the BATTERY_PRESENT
bit is cleared immediately. The LTC4101 will not set the Short to GND 0x0000 through 0x03FF 0mA through 1023mA
BATTERY_PRESENT bit until it successfully samples the 10kΩ ±1% 0x0000 through 0x07FF 0mA through 2047mA
SafetySignal twice and does not detect a RES_OR condi- 33kΩ ±1% 0x0000 through 0x0BFF 0mA through 3071mA
tion on either sampling. If AC is not present (e.g. DCDIV Open (or short to VDD) 0x0000 through 0x0FFF 0mA through 4095mA
< VACP), this bit may not be set for up to one-half second
after the battery is connected to the SafetySignal. The ChargingVoltage() ('h15)
ChargingCurrent() and ChargingVoltage() function val- Description: The Battery, SMBus Host or other master
ues are immediately cleared whenever this bit is cleared. device sends the desired charging voltage (mV) to the
Charging will never be allowed if this bit is cleared. A LTC4101.
change in BATTERY_PRESENT will activate the LTC4101
SMBALERT pull-down. Purpose: The LTC4101 uses RVLIM, the granularity of the
VDAC, and the value of the ChargingVoltage() function to
AC_PRESENT is set if the voltage on DCDIV is greater than determine its charging voltage supplied to the battery. The
VACP. This does not necessarily indicate that the voltage charging voltage will never be forced beyond the voltage
on DCIN is sufficient to charge the battery. A change in permitted by RVLIM. The ChargingVoltage() value will be
AC_PRESENT will activate the LTC4101 SMBALERT pull- truncated to the granularity of the VDAC. The charging
down. voltage will also be reduced if the battery current exceeds
the programmed charging current.
• SMBus Protocol: Write Word.
Input: The CHARGING_VOLTAGE is an unsigned 16-bit
integer specifying the requested charging voltage in mV.
The LTC4101 considers any value from 0x0001 through
0x044F the same as writing 0x0000. The following
4101fa

14
 LTC4101
OPERATION
table defines the maximum permissible value of CHARG- the LOWI current mode of the IDAC.
ING_VOLTAGE that will not set the VOLTAGE_OR in the • SMBus Protocol: Write Word.
ChargerStatus() function for a given value of RVLIM:
Input: The NO_LOWI is the only bit recognized by this
RILIM Maximum ChargingVoltage() function. The default value of NO_LOWI is zero. The
Short to GND 0x1090 (4240mV) LTC4101 LOWI current mode provides a more accurate
10kΩ ±1% 0x10D0 (4304mV) average charge current when the charge current is less
33kΩ ±1% 0x1150 (4432mV) than 1/16 of the full-scale IDAC value. When the NO_LOWI
100kΩ ± 1% 0x11A0 (4512mV) is set, a less accurate IDAC algorithm is used to generate
Open (or short to VDD) 0x1580 (5504mV) the charging current, but because the charger is not pulsed
on and off, it may be preferred.
AlarmWarning() ('h16) • SMBus Protocol: Read Word.
Description: The Smart Battery, acting as a bus master Output: The NO_LOWI indicates the IDAC mode of opera-
device, sends the AlarmWarning() message to the LTC4101 tion. If clear, then the LOWI current mode will be used
to notify it that one or more alarm conditions exist. Alarm when the charging current is less than 1/16 of the full-
indications are encoded as bit fields in the Battery’s Status scale IDAC value.
register, which is then sent to the LTC4101 by this func-
The LTC Version Identification will always be 0x4040 for
tion. the LTC4101.
Purpose: The LTC4101 will use the information sent by Alert Response Address (ARA)
this function to properly charge the battery. The LTC4101
will only respond to certain alarm bits. Writing to this Description: The SMBus system host uses the Alert
function does not necessarily cause an alarm condition Response Address to quickly identify the generator of an
that inhibits battery charging. SMBALERT# event.
• SMBus Protocol: Write Word. Purpose: The LTC4101 will respond to an ARA address
0x18 if the SMBALERT signal is actively pulling down the
Input: Only the OVER_CHARGED_ALARM, TERMINATE SMBALERT# bus. The LTC4101 will follow the prioritiza-
_CHARGE_ALARM, reserved (0x2000), and OVER tion reporting as defined in the System Management Bus
_TEMP_ALARM bits are supported by the LTC4101. Specification, Version 1.1, from the SBS Implementers
Writing a one to any of these specified bits will inhibit Forum.
the charging by the LTC4101 and will set the ALARM_
INHIBITED bit in the ChargerStatus() function. The • SMBus Protocol: A 7-bit Addressable Device Re-
TERMINATE_DISCHARGE_ALARM, REMAINING_ sponds to an ARA.
CAPACITY_ALARM, REMAINING_TIME_ALARM, and the Output: The Device Address will be sent to the SMBus
ERROR bits are ignored by the LTC4101. system host. The LTC4101 Device address is 0x12.
LTC0() ('h3C) The following events will cause the LTC4101 to pull-down
Description: The SMBus Host uses this command to the SMBALERT# bus through the SMBALERT pin:
determine the version number of the LTC4101 and set • Change of AC_PRESENT in the ChargerStatus() func-
extended operation modes not defined by the Smart Bat- tion.
tery Charger Specification.
• Change of BATTERY_PRESENT in the ChargerStatus()
Purpose: This function allows the SMBus Host to deter- function.
mine if the battery charger is an LTC4101. Identifying the
• Setting ALARM_INHIBITED in the ChargerStatus()
manufacturer and version of the Smart Battery Charger function.
permits software to perform tasks specific to a given
charger. The LTC4101 also provides a means of disabling • Internal power-on reset condition.
4101fa

15
LTC4101
OPERATION
SMBus Accelerator Pull-Ups Wake-up Charging Mode
Both SCL and SDA have SMBus accelerator circuits The following conditions must be met in order to allow
which reduce the rise time on systems with significant wake-up charging of the battery:
capacitance on the two SMBus signals. The dynamic pull-up
1. The SafetySignal must be RES_COLD, RES_IDEAL, or
circuitry detects a rising edge on SDA or SCL and applies
RES_UR.
1mA to 10mA pull-up to VDD when VIN > 0.8V until VIN
< VDD – 0.8V (external pull-up resistors are still required 2. AC must be present. This is qualified by DCDIV > VACP.
to supply DC current). This action allows the bus to meet Wake-up charging initiates when a newly inserted battery
SMBus rise time requirements with as much as 250pF on does not send ChargingCurrent() and ChargingVoltage()
each SMBus signal. The improved rise time will benefit functions to the LTC4101.
all of the devices which use the SMBus, especially those
devices that use the I2C logic levels. Note that the dynamic The following conditions will terminate the Wake-up
pull-up circuits only pull to VDD, so some SMBus devices Charging Mode.
that are not compliant to the SMBus specifications may still 1. A TTIMEOUT period is reached when the SafetySignal is
have rise time compliance problems if the SMBus pull-up RES_COLD or RES_UR.
resistors are terminated with voltages higher than VDD.
2. The SafetySignal is registering RES_OR.
The Control Block 3. The successful writing of the ChargingCurrent() AND
The LTC4101 charger operations are handled by the con- ChargingVoltage() function. The LTC4101 will proceed
trol block. This block is capable of charging the selected to the controlled charging mode after these two func-
battery autonomously or under SMBus Host control. tions are written.
The control block can request communications with the 4. The SafetySignal is registering RES_HOT.
system management host (SMBus Host) by asserting
SMBALERT = 0; this will cause the SMBus Host, if present, 5. The AC power is no longer present. (DCDIV < VACP)
to poll the LTC4101. 6. The ALARM_INHIBITED becomes set in the Charger-
Status() function.
The control block receives SMBus slave commands from
the SMBus interface block. 7. The INHIBIT_CHARGE is set in the ChargerMode()
function.
The control block allows the LTC4101 to meet the fol-
lowing Smart Battery-controlled (Level 2) charger 8. The CHGEN pin is pulled low by an external device. The
requirements: LTC4101 will resume wake-up charging, if the CHGEN
1. Implements the Smart Battery’s critical warning mes- pin is released by the external device. Toggling the
sages over the SMBus. CHGEN pin will not reset the TTIMEOUT timer.
2. Operates as an SMBus slave device that responds to 9. There is insufficient DCIN voltage to charge the battery.
ChargingVoltage() and ChargingCurrent() commands and The LTC4101 will resume wake-up charging when there
adjusts the charger output parameters accordingly. is sufficient DCIN voltage to charge the battery. This
condition will not reset the TTIMEOUT timer.
3. The host may control charging by disabling the Smart
Battery’s ability to transmit ChargingCurrent() and
ChargingVoltage() request functions and broadcast-
ing the charging commands to the LTC4101 over the
SMBus.
4. The LTC4101 will still respond to Smart Battery critical
warning messages without host intervention.
4101fa

16
 LTC4101
OPERATION
Controlled Charging Algorithm Overview 7. RESET_TO_ZERO is set in the ChargerMode() function.
The following conditions must be met in order to allow 8. CHGEN pin is pulled low by an external device. The
controlled charging to start on the LTC4101: LTC4101 will resume charging using the previous
ChargingVoltage() AND ChargingCurrent() function
1. The ChargingVoltage() AND ChargingCurrent() function
values, if the CHGEN pin is released by the external
must be written to non-zero values. device.
2. The SafetySignal must be RES_COLD, RES_IDEAL, or 9. Insufficient DCIN voltage to charge the battery. The
RES_UR. LTC4101 will resume charging using the previous
3. AC must be present. This is qualified by DCDIV > VACP. ChargingVoltage() AND ChargingCurrent() function
values, when there is sufficient DCIN voltage to charge
The following conditions will stop the Controlled Charging the battery.
Algorithm and will cause the Battery Charger Controller
to stop charging: 10. Writing a zero value to ChargingVoltage() function.
1. The ChargingCurrent() AND ChargingVoltage() func- 11. Writing a zero value to ChargingCurrent() function.
tions have not been written for TTIMEOUT.
The SafetySignal Decoder Block
2. The SafetySignal is registering RES_OR.
This block measures the resistance of the SafetySignal and
3. The SafetySignal is registering RES_HOT. features high noise immunity at critical trip points. The low
4. The AC power is no longer present. (DCDIV < VACP) power standby mode supports only battery presence SMB
charger reporting requirements when AC is not present.
5. ALARM_INHIBITED is set in the ChargerStatus() The SafetySignal decoder is shown in Figure 4. The value
function. of RTHA is 1.13k and RTHB is 54.9k.
6. INHIBIT_CHARGE is set in the ChargerMode() function. SafetySignal sensing is accomplished by a state machine
Clearing INHIBIT_CHARGE will cause the LTC4101 to that reconfigures the switches of Figure 4 using THA_SELB
resume charging using the previous ChargingVoltage() and THB_SELB, a selectable reference generator, and two
AND ChargingCurrent() function values. comparators. This circuit has two modes of operation
based upon whether AC is present.

VDD

THA_SELB
RTHA
1.13k
16 +
MUX TH_HI
THA –

HI_REF +
TH_LO
REF –
VDD LO_REF

THB_SELB SafetySignal
RTHB CONTROL
54.9k
15 RES_OR
THB
CSS RSafetySignal RES_COLD

LATCH
RES_H0T

RES_UR

4101 F04

Figure 4. SafetySignal Decoder Block

4101fa

17
LTC4101
OPERATION
When AC is present, the LTC4101 samples the value of The SafetySignal impedance is interpreted according to
the SafetySignal and updates the ChargerStatus register Table 4.
approximately every 32ms. The state machine successively
samples the SafetySignal value starting with the RES_OR Table 4. SafetySignal State Ranges
≥ RES_COLD threshold, then RES_C0LD ≥ RES_IDEAL SafetySignal CHARGE
threshold, RES_IDEAL ≥ RES_HOT threshold, and finally RESISTANCE STATUS BITS DESCRIPTION
the RES_HOT ≥ RES_UR threshold. Once the SafetySig- 0Ω to 500Ω RES_UR, Underrange
RES_HOT
nal range is determined, the lower value thresholds are BATTERY_PRESENT
not sampled. The SafetySignal decoder block uses the 500Ω to 3kΩ RES_HOT Hot
previously determined SafetySignal value to provide the BATTERY_PRESENT
appropriate adjustment in threshold to add hysteresis. 3kΩ to 30kΩ BATTERY_PRESENT Ideal
The RTHB resistor value is used to measure the RES_OR 30kΩ to 100kΩ RES_COLD Cold
≥ RES_COLD and RES_COLD ≥ RES_IDEAL thresholds by BATTERY_PRESENT
connecting the THB pin to VDD and measuring the voltage Above 100kΩ RES_OR Overrange
RES_COLD
resultant on the THA pin. The RTHA resistor value is used
Note: The underrange detection scheme is a very important feature of the
to measure the RES_IDEAL ≥ RES_HOT and RES_HOT ≥ LTC4101. The RTHA/RSafetySignal divider trip point of 0.333 • VDD (1V) is well
RES_UR thresholds by connecting the THA pin to VDD and above the 0.047 • VDD (140mV) threshold of a system using a 10k pull-up.
measuring the voltage resultant on the THB pin. A system using a 10k pull-up would not be able to resolve the important
underrange to hot transition point with a modest 100mV of ground offset
The SafetySignal decoder block uses a voltage divider between battery and SafetySignal detection circuitry. Such offsets are
network between VDD and GND to determine SafetySig- anticipated when charging at normal current levels.
nal range thresholds. Since the THA and THB inputs are
sequentially connected to VDD, this provides VDD noise The required values for RTHA and RTHB are shown in
immunity during SafetySignal measurement. Table 5.
When AC power is not available the SafetySignal block
Table 5. SafetySignal External Resistor Values
supports the following low power operating features:
EXTERNAL RESISTOR VALUE (Ω)
1. The SafetySignal is sampled every 250ms or less, RTHA 1130 ±1%
instead of 32ms. RTHB 54.9k ±1%
2. A full SafetySignal status is sampled every 30s or less,
instead of every 32ms. CSS represents the capacitance between the SafetySignal
and GND. CSS may be added to provide additional noise
immunity from transients in the application. CSS cannot
exceed 1nF if the LTC4101 is to properly sense the value
of RSafetySignal.

4101fa

18
 LTC4101
OPERATION
The ILIM Decoder Block The VLIM Decoder Block
The value of an external resistor connected from this pin The value of an external resistor connected from this pin
to GND determines one of four current limits that are used to GND determines one of five voltage limits that are ap-
for maximum charging current value. These limits provide plied to the charger output value. These limits provide a
a measure of safety with a hardware restriction on charging measure of safety with a hardware restriction on charging
current which cannot be overridden by software. voltage which cannot be overridden by software.
Table 6. ILIM Trip Points and Ranges Table 7. VLIM Trip Points and Ranges (See Figure 5)
EXTERNAL CONTROLLED EXTERNAL CONTROLLED
RESISTOR CHARGING RESISTOR CHARGING
(RILIM) ILIM VOLTAGE CURRENT RANGE GRANULARITY (RILIM) ILIM VOLTAGE CURRENT RANGE GRANULARITY
Short to GND VILIM < 0.09VDD 0 < I < 1023mA 1mA Short to VVLIM < 0.09VVCCP 2900mV < VOUT 16mV
GND < 4240mV
10k ±1% 0.17VVDD < VILIM 0 < I < 2046mA 2mA
< 0.34VVDD 10k ±1% 0.17VVDD < VVLIM 2900mV < VOUT 16mV
< 0.34VVDD < 4304mV
33k ±1% 0.42VVDD < VILIM 0 < I < 3068mA 4mA
< 0.59V 33k ±1% 0.42VVCCP < VVLIM 2900mV < VOUT 16mV
< 0.59VVDD < 4432mV
Open (>250k, 0.66VVDD < VILIM 0 < I < 4092mA 4mA
or Short to VDD) 100k ±1% 0.66VVDD < VVLIM 2900mV < VOUT 16mV
< 0.84VVDD < 4512mV
Open or 0.91VVDD < VVLIM 2900mV < VOUT 16mV
Tied to VDD < 5504mV

VDD

AC_PRESENT

12.5k
+
33k –
25k
+ 4
VLIM – VLIM [3:0]
14 25k ENCODER
+
RVLIM
25k –
+
–
12.5k

4101 F05

Figure 5. Simplified VLIM Circuit Concept (ILIM is Similar)

4101fa

19
LTC4101
OPERATION
The Voltage DAC Block IPROG
(FROM CA1 AMP)
IDC
Note that the charger output voltage is offset by VREF. – ITH
20
Therefore, the value of VREF is subtracted from the SMBus VREF + 19
RSET
ChargingVoltage() value in order for the output voltage to
be programmed properly (without offset). If the Charging- Δ-∑ CHARGING_CURRENT
Voltage() value is below the nominal reference voltage of MODULATOR VALUE

the charger, nominally 1.104V, the charger output voltage

is programmed to zero. In addition, if the ChargingVolt- 4101 F07

age() value is above the limit set by the VLIM pin, then the
Figure 7. Current DAC Operation
charger output voltage is set to the value determined by
the VLIM resistor and the VOLTAGE_OR bit is set. These When a value less than 1/16th of the maximum current
limits are demonstrated in Figure 6. allowed by ILIM is applied to the current DAC input, the
current DAC enters a different mode of operation called
6
RVLIM = 33k
LOWI. The current DAC output is pulse width modulated
5
with a high frequency clock having a duty cycle value of
1/8. Therefore, the maximum output current provided by
the charger is IMAX/8. The delta-sigma output gates this
CHARGER VBAT (V)

4
low duty cycle signal on and off. The delta-sigma shift
3
registers are then clocked at a slower rate, about 45ms/bit,
2 so that the charger has time to settle to the IMAX/8 value.
The resulting average charging current is equal to that
1 requested by the ChargingCurrent() value.
0
0 1 2 3 4 5 6
Note: The LOWI mode can be disabled by setting the
PROGRAMMED VALUE (V) 4101 F06
NO_LOWI bit in the LTC0() function.
When wake-up is asserted to the current DAC block, the
NOTE: THE LTC4101 CAN BE PROGRAMMED WITH ChargingVoltage() FUNCTION VALUES
BETWEEN 1.104V AND 2.9V, HOWEVER, THE BATTERY CHARGER CONTROLLER OUTPUT
delta-sigma is then fixed at a value equal to 80mA, inde-
VOLTAGE MAY BE ZERO WITH PROGRAMMED VALUES BELOW 2.9V. pendent of the ILIM setting.

Figure 6. Transfer Function of Charger Input FET

The input FET circuit performs two functions. It enables
The Current DAC Block the charger if the input voltage is higher than the CLP pin,
The current DAC is a delta-sigma modulator which controls and provides an indication of this condition at both the
the effective value of an external resistor, RSET, used to CHGEN pin and the PWR_FAIL bit in the ChargerStatus()
set the current limit of the charger. Figure 7 is a simplified register. It also controls the gate of the input FET to keep
diagram of the DAC operation. The delta-sigma modulator a low forward voltage drop when charging and prevents
and switch convert the ChargingCurrent() value, received reverse current flow through the input FET.
via the SMBus, to a variable resistance equal to: If the input voltage is less than VCLP, it must go at least
1.25RSET/[ChargingCurrent()/ILIM[x]] = RIDC 130mV higher than VCLP to activate the charger. The CHGEN
pin is forced low unless this condition is met. The gate
Therefore, programmed current is equal to: of the input FET is driven to a voltage sufficient to keep
ICHARGE = (102.3mV/RSENSE) (ChargingCurrent()/ILIM[x]), a low forward voltage drop from drain to source. If the
for ChargingCurrent() < ILIM[x]. voltage between DCIN and CLP drops to less than 25mV,
the input FET is turned off slowly. If the voltage between
4101fa

20
 LTC4101
OPERATION
DCIN and CLP is ever less than –25mV, then the input FET This feature is created by sensing total adapter output cur-
is turned off quickly to prevent significant reverse current rent and adjusting charging current downward if a preset
from flowing in the input FET. In this condition the CHGEN adapter current limit is exceeded. True analog control is
pin is driven low and the charger is disabled. used, with closed loop feedback ensuring that adapter load
current remains within limits. Amplifier CL1 in Figure 9
The AC Present Block (AC_PRESENT) senses the voltage across RCL, connected between the
The DCDIV pin is used to determine AC presence. If the CLP and CLN pins. When this voltage exceeds 100mV, the
amplifier will override programmed charging current to limit
DCDIV voltage is above the DCDIV comparator threshold
adapter current to 100mV/RCL. A lowpass filter formed by
(VACP), then the ACP output pin will be switched to VDD
4.99k and 0.1μF is required to eliminate switching noise.
and the AC_PRESENT bit in the ChargerStatus() func-
If the current limit is not used, CLP should be connected
tion will be set. If the DCDIV voltage is below the DCDIV
to CLP, but leave CLN connected to power.
comparator threshold minus the DCDIV comparator
hysteresis, then the ACP output pin is switched to GND Setting Input Current Limit
and the AC_PRESENT bit in the ChargerStatus() function
is cleared. The ACP output pin is designed to drive 2mA To set the input current limit, you need to know the mini-
continuously. mum wall adapter current rating. Subtract 7% for the input
current limit tolerance and use that current to determine
Adapter Limiting the resistor value.
An important feature of the LTC4101 is the ability to auto- RCL = 100mV/ILIM
matically adjust charging current to a level which avoids ILIM = Adapter Min Current –
overloading the wall adapter. This allows the product to (Adapter Min Current • 7%)
operate at the same time that batteries are being charged As is often the case, the wall adapter will usually have at
without complex load management algorithms. Addition- least a +10% current limit margin and many times one
ally, batteries will automatically be charged at the maximum can simply set the adapter current limit value to the actual
possible rate of which the adapter is capable. adapter rating (see Figure 9).

AVERAGE CHARGER CURRENT

ILIMIT/8
0
4101 F08
~40ms

Figure 8. Charging Current Waveform in Low Current Mode

LTC4101
CLP
– 24 VIN
C9
CL1 0.1μF RCL*
CLN
+ + 23
R1
100mV 4.99k
INFET TO LOAD
4

100mV
*RCL =
ADAPTER CURRENT LIMIT 4101 F09

Figure 9. Adapter Current Limiting

4101fa

21
LTC4101
APPLICATIONS INFORMATION
Table 8. Recommended Resistor Values
Adapter –7% Adapter RCL Value* RCL RCLPower RCL Power
Rating (A) Rating (A) (Ω)1% Limit (A) Dissipation (W) Rating(W)
1.5 1.40 0.068 1.47 0.15 0.25
1.8 1.67 0.062 1.61 0.16 0.25
2.0 1.86 0.051 1.96 0.20 0.25
2.3 2.14 0.047 2.13 0.21 0.25
2.5 2.33 0.043 2.33 0.23 0.50
2.7 2.51 0.039 2.56 0.26 0.50
3.0 2.79 0.036 2.79 0.28 0.50
3.3 3.07 0.033 3.07 0.31 0.50
3.6 3.35 0.030 3.35 0.33 0.50
4.0 3.72 0.027 3.72 0.37 0.50
* Rounded to nearest 5% standard step value. Many non standard values are popular.

Charge Termination Issues Inductor Selection

Batteries with constant current charging and voltage-based Higher operating frequencies allow the use of smaller
charger termination might experience problems with re- inductor and capacitor values. A higher frequency gener-
ductions of charger current caused by adapter limiting. It ally results in lower efficiency because of MOSFET gate
is recommended that input limiting feature be defeated in charge losses. In addition, the effect of inductor value
such cases. Consult the battery manufacturer for informa- on ripple current and low current operation must also be
tion on how your battery terminates charging. considered. The inductor ripple current ΔIL decreases with
higher frequency and increases with higher VIN.
Setting Output Current Limit (Refer to Figure 1)
1 ⎛ V ⎞
The LTC4101 current DAC and the PWM analog circuitry ΔIL = VOUT ⎜ 1− OUT ⎟
must coordinate the setting of the charger current. Failure ( f )(L ) ⎝ VIN ⎠
to do so will result in incorrect charge currents. Accepting larger values of ΔIL allows the use of low
Table 9. Recommended Resistor Values inductances, but results in higher output voltage ripple
IMAX (A) RSENSE (Ω) 1% RSENSE (W) RILIM (Ω) 1% and greater core losses. A reasonable starting point for
1.023 0.100 0.25 0
setting ripple current is ΔIL = 0.4(IMAX). Remember the
maximum ΔIL occurs at the maximum input voltage. The
2.046 0.05 0.25 10k
inductor value also has an effect on low current operation.
3.068 0.025 0.5 33k
The transition to low current operation begins when the
4.092 0.025 0.5 Open inductor current reaches zero while the bottom MOSFET
is on. Lower inductor values (higher ΔIL) will cause this
Warning to occur at higher load currents, which can cause a dip in
DO NOT CHANGE THE VALUE OF RILIM DURING OPERA- efficiency in the upper range of low current operation.
TION. The value must remain fixed and track the RSENSE
value at all times. Changing the current setting can result
in currents that greatly exceed the requested value and
potentially damage the battery or overload the wall adapter
if no input current limiting is provided.

4101fa

22
 LTC4101
APPLICATIONS INFORMATION
Table 10. Recommended Inductor Values The MOSFET power dissipations at maximum output
Inductance
IMAX (A)
current are given by:
VIN Range (V) 1 2 3* and 4
PMAIN = VOUT/VIN(IMAX)2(1 + δΔT)RDS(ON)
≤ 7.5 16μH ± 20% 8μH ± 20% 4μH ± 20% + k(VIN)2(IMAX)(CRSS)(fOSC)
≤ 9.0 20μH ± 20% 10μH ± 20% 5μH ± 20%
PSYNC = (VIN – VOUT)/VIN(IMAX)2(1 + δΔT)RDS(ON)
≤ 12.0 24μH ± 20% 12μH ± 20% 6μH ± 20%
≤ 15.0 26μH ± 20% 13μH ± 20% 6.5μH ± 20% Where δΔT is the temperature dependency of RDS(ON) and
≤ 28.0 30μH ± 20% 15μH ± 20% 7.5μH ± 20% k is a constant inversely related to the gate drive current.
RSENSE 0.1Ω 0.05Ω 0.025Ω Both MOSFETs have I2R losses while the PMAIN equation
* 3 Amp uses the same RSENSE that 4 amps uses. Thus the inductance
includes an additional term for transition losses, which
can be the same. are highest at high input voltages. For VIN < 20V the high
current efficiency generally improves with larger MOSFETs,
Choose and inductor who’s inductance value is equal to
while for VIN > 20V the transition losses rapidly increase to
or greater than the value shown. Values assume:
the point that the use of a higher RDS(ON) device with lower
CRSS actually provides higher efficiency. The synchronous
1. –32% RSS result from –20% inductance tolerance MOSFET losses are greatest at high input voltage or during
and a –25% inductance loss at IMAX. a short circuit when the duty cycle in this switch in nearly
2. Inductor ripple current ratio of 0.51 of IOUT across 100%. The term (1 + δΔT) is generally given for a MOSFET
RSENSE. in the form of a normalized RDS(ON) vs temperature curve,
but δ = 0.005/°C can be used as an approximation for low
3. VOUT is at 4.2V
voltage MOSFETs. CRSS = QGD /ΔVDS is usually specified
Charger Switching Power MOSFET in the MOSFET characteristics. The constant k = 2 can be
used to estimate the contributions of the two terms in the
and Diode Selection
main switch dissipation equation.
Two external power MOSFETs must be selected for use
If the charger is to operate in low dropout mode or with
with the charger: a P-channel MOSFET for the top (main)
a high duty cycle less than 50%, then the bottomside
switch and an N-channel MOSFET for the bottom (syn-
N-Channel efficiency generally improves with a larger
chronous) switch.
MOSFET. Using asymmetrical MOSFETs may achieve cost
The peak-to-peak gate drive levels are set internally. This savings or efficiency gains.
voltage is typically 6V. Consequently, logic-level threshold
Both of the LTC4101 MOSFET drivers are optimized to
MOSFETs must be used. Pay close attention to the BVDSS take advantage of MOSFETs QG values of less than 22nC
specification for the MOSFETs as well; many of the logic and a TD-off delay specification of around 60ns or less.
level MOSFETs are limited to 30V or less. Larger FETs may work, but you must qualify them and
Selection criteria for the power MOSFETs include the “ON” monitor LTC4101 temperature rise.
resistance RDS(ON), total gate capacitance QG, reverse Using excessively large MOSFETs relative to the IMAX
transfer capacitance CRSS, input voltage and maximum charge current they are working with will actually reduce
output current. The charger is operating in continuous efficiency at lighter current levels with very limited gain
mode so the duty cycles for the top and bottom MOSFETs at high currents. A good place to start looking for a suit-
are given by: able MOSFET in a data sheet is to look for a part with
Main Switch Duty Cycle = VOUT/VIN an ID rating a little over 2 times the IMAX charge current
rating. For the LTC4101, the P-channel FET can typically
Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN. be scaled down a bit to take advantage of the lower duty
cycle limits. However make sure you never exceed the PD
rating of the device.
4101fa

23
LTC4101
APPLICATIONS INFORMATION
The Schottky diode D1, shown in the Typical Application current the LTC4101 burns, rather than the SCL rate.
on the back page, conducts during the dead-time between In the equation below, IQ is the static current the IC
the conduction of the two power MOSFETs. This prevents consumes as a function of the VDD voltage when not
the body diode of the bottom MOSFET from turning on and active. Since it is hard to quantify the actual messages
storing charge during the dead-time, which could cost as going down the SMBus, one must estimate the SMBus
much as 1% in efficiency. A 1A Schottky is generally a good activity level in term of bus utilization per second.
size for 4A regulators due to the relatively small average IRUN = Message Duty Cycle • 950μA
current. Larger diodes can result in additional transition + (1 – Message Duty Cycle) • IQ
losses due to their larger junction capacitance.
where IQ(TYP) = VDD /47.2k
The diode may be omitted if the efficiency loss can be
tolerated. b) ITHRM current is due to SafetySignal (thermistor pin)
sampling that will vary with the presence of DC power
Calculating IC Power Dissipation being on or off. DCDIV is detected every 32ms. RTHX
is the value of the safety signal resistance, which will
The power dissipation of the LTC4101 is dependent upon vary with temperature or battery configuration.
the gate charge of the top and bottom MOSFETs (Q2 &
Q3 respectively) The gate charge (QG) is determined from b1) ITHRM(ON) when DC is on:
the manufacturer’s data sheet and is dependent upon both ITHRM(ON)_OVERRANGE = 1/16 • VDD /(54.9k + RTHX)
the gate voltage swing and the drain voltage swing of the
MOSFET. Use 6V for the gate voltage swing and VDCIN for where RTHX > 100k
the drain voltage swing. ITHRM(ON)_COLD = 1/8 • VDD /(54.9k + RTHX)
PD = VDCIN • (fOSC (QGQ2 + QGQ3) + IDCIN) + VDD • IDD where RTHX > 30k
Example: VDCIN = 12V, fOSC = 345kHz, QGQ2 = 25nC, ITHRM(ON)_NORMAL = 1/8 • VDD /(54.9k + RTHX)
QGQ3 = 15nC, IDCIN = 5mA, VDD = 5.5V, + 1/16 • VDD /(1.13k + RTHX)
IDD = 1mA.
ITHRM(ON)_HOT* = 1/8 • VDD /(54.9k + RTHX) + 1/8
PD = 231mW • VDD /(1.13k + RTHX) RTHX < 3k
* includes underrange
Calculating VDD Current
b2) ITHRM(OFF) when DC is off, the thermistor monitoring
The LTC4101 VDD current, or IDD, consist of three parts: rate is reduced to every 250ms or less.
a. IRUN = Current due to active clocking and bias inside ITHRM(OFF)_OVERRANGE = 1/50 • VDD /(54.9k + RTHX)
the IC.
where RTHX > 100k
b. ITHRM = Current due to thermistor circuit activity.
ITHRM(OFF)_COLD = 1/50 • VDD /(54.9k + RTHX)
c. IACCEL = Current due to SMBus acceleration activity. + 1/1000 • VDD /(54.9k + RTHX) RTHX > 30k
IDD = IRUN + ITHRM + IACCEL ITHRM(OFF)_NORMAL = 1/50 • VDD /(54.9k + RTHX)
a) IRUN current is basically independent of SCL clock rate. + 1/500 • VDD /(54.9k + RTHX) + 1/1000
Once the LTC4101 determines that there is activity on • VDD /(1.13k + RTHX)
the SMBus, it turns on its internal HF oscillator. This ITHRM(OFF)_HOT* = 1/50 • VDD /(54.9k + RTHX)
HF oscillator remains on until a stop event occurs or + 1/500 • VDD /(54.9k + RTHX) + 1/500
SDA and SCL are at logic level 1 for the SMBus timeout • VDD /(1.13k + RTHX)
period. Then it shuts off the HF oscillator. Thus, the
length of the transmission and the rate of transmission where RTHX < 3k
bursts are more important in determining how much * includes underrange
4101fa

24
 LTC4101
APPLICATIONS INFORMATION
c) IACCEL is the current used by the SMBus accelerators. and full current is achieved with ITH at 2V. With a 0.12μF
This directly depends on the SMBus frequency, duty capacitor, time to reach full charge current is about 2ms and
cycle of messages sent on the SMBus and how long it is assumed that input voltage to the charger will reach
it takes to drive the SMBus to VDD. full value in less than 2ms. The capacitor can be increased
up to 1μF if longer input start-up times are needed.
IACCEL = IPULL-UP • 2 • SMBus Frequency •
Message Duty Cycle •VDD/2.25V •Rise Time In any switching regulator, conventional timer-based
soft-starting can be defeated if the input voltage rises much
Complete Examples slower than the time out period. This happens because
1) Battery thermistor = 400Ω, VDD = 5.0V the switching regulators in the battery charger and the
computer power supply are typically supplying a fixed
Battery mode (DC is off), SMBus activity is 10kHz amount of power to the load. If input voltage comes up
and a 2% SMBus duty cycle, which represents a slowly compared to the soft-start time, the regulators will
suspended or sleep condition of a notebook. try to deliver full power to the load when the input voltage
ITOTAL = IRUN + ITHRM(OFF) + IACCEL is still well below its final value. If the adapter is current
= 121.9μA + 5.26μA + 2.44μA = 130μA limited, it cannot deliver full power at reduced output
Battery mode and a 10% SMBus duty cycle, which voltages and the possibility exists for a quasi “latch” state
represents an active notebook at idle. where the adapter output stays in a current limited state at
ITOTAL = IRUN + ITHRM(OFF) + IACCEL reduced output voltage. For instance, if maximum charger
= 189.5μA + 5.26μA + 12.2μA = 207μA plus computer load power is 30W, a 15V adapter might
be current limited at 2.5A. If adapter voltage is less than
DCIN = ON and a 20% SMBus duty cycle which (30W/2.5A = 12V) when full power is drawn, the adapter
represents an active notebook charging. voltage will be pulled down by the constant 30W load
ITOTAL = IRUN + ITHRM(ON) + IACCEL until it reaches a lower stable state where the switching
= 274μA + 215.6μA + 24.4μA = 514μA regulators can no longer supply full load. This situation
2) Battery thermistor = 10k, VDD = 5.0V can be prevented by utilizing the DCDIV resistor divider,
set higher than the minimum adapter voltage where full
Battery mode (DC is off), SMBus activity is 10kHz
power can be achieved.
and a 2% SMBus duty cycle:
ITOTAL = IRUN + ITHRM(OFF) + IACCEL Input and Output Capacitors
= 121.9μA + 2.14μA + 2.44μA = 126μA
We recommend the use of high capacity low ESR/ESL X5R
Battery mode and a 10% SMBus duty cycle: type ceramic capacitors. Alternative capacitors include
ITOTAL = IRUN + ITHRM(OFF) + IACCEL OSCON or POSCAP type capacitors. Aluminum electrolytic
= 189.5μA + 2.14μA + 12.2μA = 204μA capacitors are not recommended for poor ESR and ESL
DCIN = ON and a 20% SMBus duty cycle: reasons. Solid tantalum low ESR capacitors are acceptable,
ITOTAL = IRUN + ITHRM(ON) + IACCEL but caution must be used when tantalum capacitors are
= 274μA + 37.7μA + 24.4μA = 336μA used for input or output bypass. High input surge currents
can be created when the power adapter is hot-plugged
Soft-Start and Undervoltage Lockout into the charger or when a battery is connected to the
The LTC4101 is soft-started by the 0.12μF capacitor on charger. Use only “surge robust” low ESR tantalums. Re-
the ITH pin. On start-up, ITH pin voltage will rise quickly gardless of which type of capacitor you use, after voltage
to 0.5V, then ramp up at a rate set by the internal 30μA selection, the most important thing to meet is the ripple
pull-up current and the external capacitor. Battery charging current requirements followed by the capacitance value.
current starts ramping up when ITH voltage reaches 0.8V By the time you solve the ripple current requirements,
the minimum capacitance value is often met by default.
4101fa

25
LTC4101
APPLICATIONS INFORMATION
The following equation shows the minimum COUT (±20% tive terminal makes contact to the connector before the
tolerance) capacitance values for stability when used with negative terminal, the SMBus inputs can be forced below
the compensation shown in the typical application on the ground with the full battery potential, causing a potential
back page. for latch-up in any of the devices connected to the SMBus
COUT(MIN) = 120/L1 inputs. Therefore it is good design practice to protect the
SMBus inputs as shown in Figure 10.
The use of aluminum electrolytic for C1, located at the VDD
AC adapter input terminal, is helpful in reducing ringing
during the hot-plug event. Refer to Application Note 88
for more information.
CONNECTOR
In the 4A lithium battery charger (typical application on TO BATTERY
TO SYSTEM

back page), the input capacitor (C2) is assumed to absorb

all input switching ripple current in the converter, so it
must have adequate ripple current rating. Worst-case RMS
ripple current will be equal to one half of output charging 4101 F13

current. C2 is recommended to be equal to or greater than Figure 10. Recommended SMBus Transient Protection
C4 (output capacitor) in capacitance value.
SafetySignal (Thermistor) Value
The output capacitor (C4) is also assumed to absorb
output switching current ripple. The general formula for The SafetySignal (typical application on back page), is a
capacitor current is: multifunction signal that communicates three pieces of
⎛ V ⎞ information in order of importance:
0.29(VBAT ) ⎜ 1– BAT ⎟ 1) Presence of the smart battery
⎝ VDCIN ⎠
IRMS = 2) The maximum time duration of the wake-up charge
(L1)(f)
allowed.
For example, VDCIN = 12V, VBAT = 4.2V, L1 = 10μH, and
3) An optional and redundant temperature measurement
f = 300kHz, IRMS = 0.26A.
system.
EMI considerations usually make it desirable to minimize
The value of the resistance to ground communicates all
ripple current in the battery leads, and beads or induc-
this information. The resistance ranges and what it does
tors may be added to increase battery impedance at the
is covered by the SBS Smart Battery Charger standard in
300kHz switching frequency. Switching ripple current splits
Section 6. Basically if you have a battery chemistry, such
between the battery and the output capacitor depending
as Li-ion, that cannot safely withstand an infinite dura-
on the ESR of the output capacitor and the battery imped-
tion wake-up charge, the SafetySignal resistance value
ance. If the ESR of C3 is 0.2Ω and the battery impedance
needs to be less than 425Ω. The popular value to use is
is raised to 4Ω with a bead or inductor, only 5% of the
a fixed 300Ω resistor. Otherwise the resistance value is
current ripple will flow in the battery.
10k which is normally expected to be done using a 10k
Protecting SMBus Inputs NTC resistor.

The SMBus inputs, SCL and SDA, are exposed to uncon- PCB Layout Considerations
trolled transient signals whenever a battery is connected
For maximum efficiency, the switch node rise and fall times
to the system. If the battery contains a static charge, the
should be minimized. To prevent magnetic and electrical
SMBus inputs are subjected to transients which can cause
field radiation and high frequency resonant problems,
damage after repeated exposure. Also, if the battery’s posi-
proper layout of the components connected to the IC is
4101fa

26
 LTC4101
APPLICATIONS INFORMATION
essential. (See Figure 11.) Here is a PCB layout priority long. The feedback traces need to be routed together
list for proper layout. Layout the PCB using this specific as a single pair on the same layer at any given time
order. with smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at
1. Input capacitors need to be placed as close as possible
the sense resistor location.
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These 5. Place output capacitors next to the sense resistor
parts must be on the same layer of copper. Vias must output and ground.
not be used to make this connection. 6. Output capacitor ground connections need to feed
2. The control IC needs to be close to the switching FET’s into same copper that connects to the input capacitor
gate terminals. Keep the gate drive signals short for ground before tying back into system ground.
a clean FET drive. This includes IC supply pins that
connect to the switching FET source pins. The IC can Interfacing with a Selector
be placed on the opposite side of the PCB relative to The LTC4101 is designed to be used with a true analog
above. multiplexer for the SafetySignal sensing path. Some
3. Place inductor input as close as possible to switching selector ICs from various manufacturers may not imple-
FET’s output connection. Minimize the surface area of ment this. Consult LTC applications department for more
this trace. Make the trace width the minimum amount information.
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in Electronic Loads
parallel. Minimize capacitance from this node to any The LTC4101 is designed to work with a real battery.
other trace or plane. Electronic loads will create instability within the LTC4101
4. Place the output current sense resistor right next to preventing accurate programming currents and volt-
the inductor output but oriented such that the IC’s ages. Consult LTC applications department for more
current sense feedback traces going to resistor are not information.

SWITCH NODE
L1
DIRECTION OF CHARGING CURRENT
VBAT

HIGH
FREQUENCY RSENSE
VIN C2 D1 C4 BAT
CIRCULATING
PATH

VIAS TO CSP AND BAT

4101 F14
4101 F15

Figure 11. High Speed Switching Path Figure 12. Kelvin Sensing of Charging Current

4101fa

27
LTC4101
PACKAGE DESCRIPTION
G Package
24-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)

7.90 – 8.50*
1.25 ±0.12
(.311 – .335)
24 23 22 21 20 19 18 17 16 15 14 13

7.8 – 8.2 5.3 – 5.7

7.40 – 8.20
(.291 – .323)

0.42 ±0.03 0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10 11 12
5.00 – 5.60** 2.0
(.197 – .221) (.079)
MAX

0° – 8°

0.65
0.09 – 0.25 0.55 – 0.95
(.0256)
(.0035 – .010) (.022 – .037)
BSC 0.05
0.22 – 0.38 (.002)
NOTE:
(.009 – .015) MIN
1. CONTROLLING DIMENSION: MILLIMETERS
TYP G24 SSOP 0204
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

4101fa

28
 LTC4101
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 11/09 Text Added to Pin Functions 8
Text Changes to Operation Section 11, 12, 15
Changes to Table 1 13
Added ‘Calculating VDD Current’ Section 24
Updated ‘Input and Output Capacitors’ Section 26
Added ‘SafetySignal (Thermistor) Value’ Section 27
Changes to Typical Application 31

4101fa

29
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC4101
TYPICAL APPLICATION
LTC4101 Li-Ion Battery Charger ILIM = 4A/VLIM = 4.240V, Adapter Rating = 2.7A
RCL
DCIN 0.033Ω
0.5W
Q1 1%
9V TO 12V
SYSTEM
DCIN
C9 LOAD
FROM WALL C1 R1
0.1μF
ADAPTER 0.1μF 4.9k
10V

R10 4 24 23
6.04k
INFET CLP CLN
1% 5 1
DCIN TGATE Q2
C2, C3
11 10μF s2
DCDIV 16V
R11 R5 X5R
1.21k 6.04k 3
BGATE Q3 D1
1% 1% 19
ITH PGND
C6, 0.12μF
L1 DCIN
10V, X7R
6μH
C7, 0.0015μF LTC4101
4A 100k
10V, X7R Q4
20 21 C4,C5 1/2 Si790IEDN
IDC CSP 10μF s2
C8, 0.068μF RSNS
10V, X7R 12 0.025Ω 10V
GND 0.5W, 1% X5R
0.1μF 22
17 BAT
10V
VDD
C4
14 0.03μF
VLIM R4
25V 1 CELL Li-Ion BATTERY
13 18 100Ω
ILIM VSET
C5
10 0.1μF RTHA 300Ω
ACP 1.13k
10V
3V TO 5.5V 6 1% SafetySignal
16
CHGEN THA
10k 10k D2 SDA
7 15
SDA SMBALERT THB SCL
RTHB
D3 8
SDA 54.9k 4101 TA02
D4 1%
9 D1: MBRM140T3
SCL SCL
D2-D5: SMALL SIGNAL SCHOTTKY
D5 Q1: 1/2 Si790IEDN
Q2: FDS6685
Q3: Si7804DN

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1760 Smart Battery System Manager Autonomous Power Management and Battery Charging for Two Smart
Batteries, SMBus Rev 1.1 Compliant
LTC4006 Small, High Efficiency, Fixed Voltage, Constant Current/Constant Voltage Switching Regulator with Termination
Lithium-Ion Battery Charger Timer, AC Adapter Current Limit and SafetySignal Sensor
in a Small 16-Pin Package
LTC4007 High Efficiency, Programmable Voltage Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter
Battery Charger with Termination Current Limit, SafetySignal Sensor and Indicator Outputs
LTC4008 High Efficiency, Programmable Voltage/Current Constant Current/Constant Voltage Switching Regulator; Resistor Voltage/
Battery Charger Current Programming, AC Adapter Current Limit and SafetySignal Sensor
LTC4010 High Efficiency Standalone Nickel Battery Charger Complete NiMH/NiCd Charger in a 16-Pin TSSOP Package, Constant-Current
Switching Regulator
LTC4011 High Efficiency Standalone Nickel Battery Charger Complete NiMH/NiCd Charger in a 20-Pin TSSOP Package, PowerPath™
Control. Constant-Current Switching Regulator
LTC4060 Standalone Linear NiMH/NiCd Fast Charger Complete NiMH/NiCd Charger in a Small Leaded or Leadless 16-Pin Package,
No Sense Resistor or Blocking Diode Required
LTC4100 Smart Battery Charger Controller For Smart Batteries with Voltages Above 5.5V
LTC4412 Low Loss PowerPath Controller Very Low Loss Replacement for Power Supply OR’ing Diodes Using
Minimal External Components
PowerPath is a trademark of Linear Technology Corporation.
4101fa

30 Linear Technology Corporation

LT 1109 REV A • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006