SITAMARHI INSTITUTE OF TECHNOLOGY,

SITAMARHI

Department of Electrical Engineering

Lab Manual

B.Tech(VI sem)
VLSI Lab
(Code:100607P)
 List of Experiments

Ex Experiment Name Virtual Lab Link Page no.

No.
To aim of this experiment is to plot (i) https://vlsi-
the output characteristics and (ii) the iitg.vlabs.ac.in/MOSFET_simulato 1-5
1
transfer characteristics of an n-channel r.html
and p-channel MOSFET.
To aim of this experiment is to design https://vlsi-
and plot the static (VTC) and dynamic iitg.vlabs.ac.in/CMOS_simulator.h 6-9
2
characteristics of a digital CMOS tml
inverter.
To aim of this experiment is to design https://vlsi-
3
and plot the output characteristics of 3- iitg.vlabs.ac.in/RingOscillator_sim 10-12
inverter and 5-inverter ring oscillator. ulator.html
To aim of this experiment is to design https://vlsi-
and plot the characteristics of a positive iitg.vlabs.ac.in/Latches_simulator. 13-15
4
and negative multiplexers based html
latches.
To aim of this experiment is to design https://vlsi-
and plot the characteristics of a master- iitg.vlabs.ac.in/Registers_simulato
5
slave positive and negative edge r.html 16-20
triggered registers based on
multiplexers.
 Experiment No:-1

Objective: The aim of this experiment is to plot (i) the output characteristics and, (ii) the
transfer characteristics of an n-channel and p-channel MOSFET.
Theory:
The metal–oxide–semiconductor field-effect transistor (MOSFET) is a transistor used for
amplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated gate
electrode can induce a conducting channel between the two other contacts called source and
drain. The channel can be of n-type or p-type, and is accordingly called an n-MOSFET or a p-
MOSFET. Figure 1 shows the schematic diagram of the structure of an n-MOS device before and
after channel formation.

Figure 2 shows symbols commonly used for MOSFETs where the bulk terminal is either labeled
(B) or implied (not drawn).

Fig. (2): Circuit symbols for nMOS and pMOS respectively

Output Characteristics
MOSFET output characteristics plot ID versus VDS for several values of VGS.

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The characteristics of an n-MOS transistor can be explained as follows. As the voltage on the top
electrode increases further, electrons are attracted to the surface. At a particular voltage level,
which we will shortly define as the threshold voltage, the electron density at the surface exceeds
the hole density. At this voltage, the surface has inverted from the p-type polarity of the original
substrate to an n-type inversion layer, or inversion region, directly underneath the top plate as
indicated in Fig. 1(b). This inversion region is an extremely shallow layer, existing as a charge
sheet directly below the gate. In the MOS capacitor, the high density of electrons in the inversion
layer is supplied by the electron–hole generation process within the depletion layer. The positive
charge on the gate is balanced by the combination of negative charge in the inversion layer plus
negative ionic acceptor charge in the depletion layer. The voltage at which the surface inversion
layer just forms plays an extremely important role in field-effect transistors and is called the
threshold voltage Vtn. The region of output characteristics where VGStn and no current flows is
called the cutt-off region. When the channel forms in the nMOS (pMOS) transistor, a positive
(negative) drain voltage with respect to the source creates a horizontal electric field moving the
electrons (holes) toward the drain forming a positive (negative) drain current coming into the
transistor. The positive current convention is used for electron and hole current, but in both cases
electrons are the actual charge carriers. If the channel horizontal electric field is of the same
order or smaller than the vertical thin oxide field, then the inversion channel remains almost
uniform along the device length. This continuous carrier profile from drain to source puts the
transistor in a bias state that is equivalently called either the non-saturated, linear, or ohmic bias

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state. The drain and source are effectively short-circuited. This happens when VGS > VDS +
Vtn for n-MOS transistor and VGS < VDS +Vtp for p-MOS transistor. Drain current is linearly
related to drain-source voltage over small intervals in the linear bias state.

But if the n-MOS drain voltage increases beyond the limit, so that VGS < VDS + Vtn, then the
horizontal electric field becomes stronger than the vertical field at the drain end, creating an
asymmetry of the channel carrier inversion distribution shown in Figure 4.

Fig. 4: Channel pinchoff for (a) nMOS and (b) pMOS transistor devices.
If the drain voltage rises,while the gate voltage remains the same, then VGD can go below the
threshold voltage in the drain region. There can be no carrier inversion at the drain-gate oxide
region, so the inverted portion of the channel retracts from the drain, and no longer “touches”
this terminal. The pinched-off portion of the channel forms a depletion region with a high
electric field. The n-drain and p-bulk form a p-n junction. When this happens the inversion
channel is said to be “pinched-off” and the device is in the saturation region. The characteristics
can be loosely modeled by the following equations.

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Transfer Characteristics

The transfer characteristic relates drain current (ID) response to the input gate-source driving
voltage (VGS). Since the gate terminal is electrically isolated from the remaining terminals (drain,
source, and bulk), the gate current is essentially zero, so that gate current is not part of device
characteristics. The transfer characteristic curve can locate the gate voltage at which the
transistor passes current and leaves the OFF-state. This is the device threshold voltage (Vtn).
Figure 5 shows measured input characteristics for an nMOS and pMOS transistor with a small
0.1V potential across their drain to source terminals.

The transistors are in their non-saturated bias states. As VGS increases for the n-MOS transistor
in Figure 5a, the threshold voltage is reached where drain current elevates. For V GS between 0V
and 0.7V, ID is nearly zero indicating that the equivalent resistance between the drain and source
terminals is extremely high. Once VGS reaches 0.7V, the current increases rapidly with
VGS indicating that the equivalent resistance at the drain decreases with increasing gate-source
voltage. Therefore, the threshold voltage of the given n-MOS transistor is about Vtn ≈ 0.7V. The
p-MOS transistor input characteristic in Figure 5b is analogous to the n-MOS transistor except
the ID and VGS polarities are reversed.
Procedure:
1. Go to the simulator tab and click on any of the link provided. Multiple links may be available
on the page corresponding to different sub-experiments and methods of implementation. Once
you click on any link, a new web page will pop-up which will form the platform for conducting
the virtual experiment.

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2. On the new window, provisions are available to change the default input settings (frequency,
phase, voltage ...etc) by editing the code section.

3. Click on the simulate button for starting the simulation experiment.

4. Wait until the output waveforms are displayed on the window. This delay depends on the
speed of the internet connectivity.

5. Once the output appear, check for its logical validity. Compare it with its theoretical
expectation.

6. Repeat the experiment with different set of inputs.

Simulation Link:
https://vlsi-iitg.vlabs.ac.in/MOSFET_simulator.html

Assignment :-
1. How will you determine the threshold voltage (Vtn) from transfer characteristics? Find the
value of Vtn from the characteristics obtained in your simulation experiment.

2. How will you determine K (µ Cox), the transconductance parameter from the output
characteristics? Find this value from the simulation outputs you got.

3. What is the fundamental difference between a MOSFET and BJT?

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 Experiment No:-2

Objective:
The aim of this experiment is to design and plot the static (VTC) and dynamic characteristics of
a digital CMOS inverter.
Theory:
The inverter is universally accepted as the most basic logic gate doing a Boolean operation on a
single input variable. Fig.1 depicts the symbol, truth table and a general structure of a CMOS
inverter. As shown, the simple structure consists of a combination of a p-MOS transistor at the
top and an n-MOS transistor at the bottom.

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor.

The words "complementary-symmetry" refer to the fact that the typical digital design style with
CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide
semiconductor field effect transistors (MOSFETs) for logic functions. Two important
characteristics of CMOS devices are high noise immunity and low static power consumption.
Significant power is only drawn while the transistors in the CMOS device are switching between
on and off states. Consequently, CMOS devices do not produce as much waste heat as other
forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all n-
channel devices without p-channel devices.

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Inverter Static Characteristics (VTC)
Digital inverter quality is often measured using the Voltage Transfer Curve (VTC), which is a
plot of input vs. output voltage. From such a graph, device parameters including noise tolerance,
gain, and operating logic-levels can be obtained.

Ideally, the voltage transfer curve (VTC) appears as an inverted step-function - this would
indicate precise switching between on and off - but in real devices, a gradual transition region
exists. The VTC indicates that for low input voltage, the circuit outputs high voltage; for high
input, the output tapers off towards 0 volts. The slope of this transition region is a measure of
quality - steep (close to -Infinity) slopes yield precise switching. The tolerance to noise can be
measured by comparing the minimum input to the maximum output for each region of operation
(on / off). This is more explicitly shown in the fig.3.

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Noise margin: It is a parameter intimately related to the transfer characteristics. It allows one to
estimate the allowable noise voltage on the input of a gate so that the output will not be affected.
Noise margin (also called noise immunity) is specified in terms of two parameters - the low noise
margin NL, and the high noise margin NH . Referring to above figure, NL is defined as the
difference in magnitude between the maximum LOW input voltage recognized by the driven
gate and the maximum LOW output voltage of the driving gate. That is, NL =|VIL - VOL|.
Similarly, the value of NH is the difference in magnitude between the minimum HIGH output
voltage of the driving gate and the minimum HIGH input voltage recognizable by the driven
gate. That is, NMH =|VOH - VIH|. Where VIH|: minimum HIGH input voltage, V IL: maximum
LOW input voltage, VOH: minimum HIGH output voltage, VOL: maximum LOW output voltage.

Inverter Dynamic Characteristics

Fig.4 shows the dynamic characteristics of a CMOS inverter. The following are some formal
definitions of temporal parameters of digital circuits. All percentages are of the steady state
values.

Rise Time (tr) : Time taken to rise from 10% to 90%.

Fall Time (tf): Time taken to fall from 90% to 10%.
Edge Rate (trf): (tr + tf )/2.
High-to-Low propagation delay (tpHL): Time taken to fall from VOH to 50%.
Low-to-High propagation delay (tpLH): Time taken to rise from 50% to VOL.
Propagation Delay (tp): (tpHL + tpLH)/2.
Contamination Delay (tcd): Minimum time from the input crossing 50% to the output crossing
50%.

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Procedure:
Step by Step Procedure
1. Go to the simulator tab and click on any of the link provided. Multiple links may be available
on the page corresponding to different sub-experiments and methods of implementation. Once
you click on any link, a new web page will pop-up which will form the platform for conducting
the virtual experiment.
2. On the new window, provisions are available to change the default input settings (frequency,
phase, voltage ...etc) by editing the code section.
3. Click on the simulate button for starting the simulation experiment.
4. Wait until the output waveforms are displayed on the window. This delay depends on the
speed of the internet connectivity.
5. Once the output appear, check for its logical validity. Compare it with its theoretical
expectation.
6. Repeat the experiment with different set of inputs.
Simulation Link:
https://vlsi-iitg.vlabs.ac.in/CMOS_simulator.html
Assignment on Inverter

1. How will you determine NML and NMH from voltage transfer characteristics (VTC)?
2.If you increase the size of the pMOS transistor with respect to the nMOS transistor, what
change do you expect in the VTC?
3. For CMOS Logic, give the various techniques you know to minimize power consumption?

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 Experiment No:-3
Objective:
The aim of this experiment is to design and plot the output characteristics of 3-inverter and 5-
inverter ring oscillator.
Theory:
A ring oscillator is a device composed of an odd number of NOT gates whose output oscillates
between two voltage levels, representing true and false. A schematic diagram of a simple three
inverter ring oscillator is shown in Fig.1.

The NOT gates, or inverters, are attached in a chain; the output of the last inverter is fed back
into the first. Because a single inverter computes the logical NOT of its input, it can be shown
that the last output of a chain of an odd number of inverters is the logical NOT of the first input.
This final output is asserted a finite amount of time after the first input is asserted; the feedback
of this last output to the input causes oscillation. A real ring oscillator only requires power to
operate; above a certain threshold voltage, oscillations begin spontaneously. To increase the
frequency of oscillation, two methods may be used. Firstly, the applied voltage may be
increased; this increases both the frequency of the oscillation and the power consumed, which is
dissipated as heat.

Operation:
To understand the operation of a ring oscillator, one must first understand gate delay. In a
physical device, no gate can switch instantaneously; in a device fabricated with MOSFETs, for
example, the gate capacitance must be charged before current can flow between the source and
the drain. Thus, the output of every inverter of a ring oscillator changes a finite amount of time
after the input has changed. From here, it can be easily seen that adding more inverters to the
chain increases the total gate delay, reducing the frequency of oscillation. The switching
frequency at each gate is inversely proportional to both the number of gates in the ring and the
gate delay of each individual gate. A typical simulation output for a ring oscillator is shown in
Fig. 2.

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The simulation in Fig.2 shows the "warm-up" of the inverter circuit followed by a stable
frequency oscillation. The main problem of this type of oscillator is the very strong dependence
of the output frequency with virtually all process parameters (like W, L etc) and operating
conditions. As an example, the power supply voltage VDD has a very significant importance on
the oscillating frequency. The output frequency of a 3-inverter ring oscillator can be written as
1/(6×inverter delay). Thus the propagation delay of an inverter circuit can be obtained by
measuring the time period of the oscillator.
Procedure:

1. Go to the simulator tab and click on any of the link provided. Multiple links may be available
on the page corresponding to different sub-experiments and methods of implementation. Once
you click on any link, a new web page will pop-up which will form the platform for conducting
the virtual experiment.
2. On the new window, provisions are available to change the default input settings (frequency,
phase, voltage ...etc) by editing the code section.
3. Click on the simulate button for starting the simulation experiment.
4. Wait until the output waveforms are displayed on the window. This delay depends on the
speed of the internet connectivity.
5. Once the output appear,check for its logical validity. Compare it with its theoretical
expectation.

6. Repeat the experiment with different set of inputs.

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Simulation Link:
https://vlsi-iitg.vlabs.ac.in/RingOscillator_simulator.html

Assignment :-
1. How will you design the sizes of nMOS and pMOS transistors for equal tpHLand tpLH
values?

2. Find the oscillation frequency of a ring oscillator with N number of inverter stages each
having equal equal tpHL and tpLH values?

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 Experiment No:-4

Objective:
The aim of this experiment is to design and plot the characteristics of a positive and negative
multiplexers based latches .

Theory:

A bistable circuit- a circuit having two stable states that represent 0 and 1, can be designed using
a positive feedback. The basic idea is shown in fig.1, which shows two inverters connected in
cascade along with the voltage-transfer characteristic typical of such a circuit.

The above circuit has only three possible operation points (A, B, and C), as demonstrated on the
combined VTC. Out of these, A and B are the only stable operating points, and C is a metastable
point; therefore, the name bistable. The circuit serves as a memory, storing either a 1 or a 0
corresponding to positions A and B. We can change the state of such a circuit by cutting the
feedback loop or by overpowering the feedback loop. The first is called a multiplexer based
Latch and it realizes the following multiplexer equation:

MUX based Latches

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Fig.2 shows an implementation of positive and negative static latches based on multiplexers. For
a negative latch input D is selected when the CLK is 0 whereas when the CLK is high, output is
held. This is reversed for a positive latch.

A transistor-level implementation of a positive latch based on multiplexers is shown in Fig.3.

When the CLK is high, the bottom transmission gate is on and the latch is transparent- that is, the
D input is copied to the Q output. During this phase, the feedback loop is open, since the top
transmission gate is off.

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Procedure:
1. Go to the simulator tab and click on any of the link provided. Multiple links may be available
on the page corresponding to different sub-experiments and methods of implementation. Once
you click on any link, a new web page will pop-up which will form the platform for conducting
the virtual experiment.
2. On the new window, provisions are available to change the default input settings (frequency,
phase, voltage ...etc) by editing the code section.
3. Click on the simulate button for starting the simulation experiment.
4. Wait until the output waveforms are displayed on the window. This delay depends on the
speed of the internet connectivity.
5. Once the output appear, check for its logical validity. Compare it with its theoretical
expectation.
6. Repeat the experiment with different set of inputs.
Simulation Link:
https://vlsi-iitg.vlabs.ac.in/Latches_simulator.html

Assignment:
1. What is the difference between static and dynamic latch design?

2. Mention two specific applications of latches.

3. What is the difference between static and dynamic latches?

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 Experiment No:-5

Objective:
The aim of this experiment is to design and plot the characteristics of a master-slave positive and
negative edge triggered registers based on multiplexers.
Theory:
A register consists of cascading a negative latch (master stage) with a positive one (slave stage).
Fig. 1 shows a multiplexer-latch based implementation of register. On the low phase of the clock,
the master stage is transparent, and the D input is passed to the master stage output, QM. During
this period, the slave stage is in the hold mode, keeping its previous value by using feedback. On
the rising edge of the clock, the master stage stops sampling the input, and the slave stage starts
sampling. During the high phase of the clock, the slave stage samples the output of the master
stage (QM), while the master stage remains in a hold mode. Since QM is constant during the high
phase of the clock, the output Q makes only one transition per cycle. The value of Q is the value
of D right before the rising edge of the clock, achieving the positive edge-triggered effect.

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A negative edge-triggered register can be constructed by using the same principle by simply
switching the order of the positive and negative latches (i.e., placing the positive latch first). Fig.
2 shows the transmission gate based implementation of the above register.

Procedure:

1. Go to the simulator tab and click on any of the link provided. Multiple links may be available
on the page corresponding to different sub-experiments and methods of implementation. Once
you click on any link, a new web page will pop-up which will form the platform for conducting
the virtual experiment.
2. On the new window, provisions are available to change the default input settings (frequency,
phase, voltage ...etc) by editing the code section.
3. Click on the simulate button for starting the simulation experiment.
4. Wait until the output waveforms are displayed on the window. This delay depends on the
speed of the internet connectivity.

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5. Once the output appear, check for its logical validity. Compare it with its theoretical
expectation.
6. Repeat the experiment with different set of inputs.
Simulation Link:
https://vlsi-iitg.vlabs.ac.in/Registers_simulator.html

Assignment:

1. What is the basic difference between a latch and a register?

2. Why non-overlapping clocks are required for the proper working of a register?

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