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SLVS426 − MAY 2002

 
     




 
 



FEATURES APPLICATIONS
D Three Independent Step-Down DC/DC D Notebook PCs, PDAs
Controllers and One LDO Controller D Consumer Game Systems
D Input Voltage Range D DSP Application
− Switcher: 4.5 V ~ 28 V DESCRIPTION
− LDO: 1.1 V ~ 3.6 V
The TPS5130 is composed of three independent
D Output Voltage Range synchronous buck regulator controllers (SBRC) and
− Switcher: 0.9 V ~ 5.5 V one low drop-out (LDO) regulator controller. On-chip
− LDO: 0.9 V ~ 2.5 V high-side and low-side synchronous rectifier drivers are
D Synchronous for High Efficiency integrated to drive less expensive N-channel
MOSFETs. The LDO controller can also drive an
D Precision Vref (±1.5%) external N-channel MOSFET. Since the input current
D PWM Mode Control : Max. 500 kHz Operation ripple is minimized by operating 180 degree out of
phase, it allows a smaller input capacitance resulting in
D Auto PWM/SKIP Mode Available reduced power supply cost. The SBRC of the TPS5130
D High Speed Error Amplifier automatically adjusts from PWM mode to SKIP mode
to maintain high efficiency under light load conditions.
D Over Current Protection With Temperature Resistor-less current protection for the synchronous
Compensation Circuit for Each Channel buck controller and the fixed high-side driver voltage
simplifies the system design and reduces the external
D Overvoltage and Undervoltage Protection
parts count. The LDO controller has a current limit
D Programmable Short-Circuit Protection protection and overshoot protection to suppress output
voltage hump at load transient. To further extend
D Powergood With Programmable Delay Time
battery life, the TPS5130 features dead-time control
D 5-V and 3.3-V Linear Regulators and very low quiescent current.
VIN

VIN
OUT3_u OUT1_u

Vo3 LL3 LL1 Vo1

5V
OUT3_d OUT1_d

TPS5130
INV3 INV1

REG5V_IN
LDO_IN

OUT2_u
LDO_CUR
LL2 Vo3
LDO_GATE
OUT2_d
Vo_LDO INV_LDO

GND INV2

See application section of this data sheet for more detailed information.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.


 
  ! "#$ !  %#&'" ($) (#"! Copyright  2002, Texas Instruments Incorporated
"  !%$""! %$ *$ $! 
$+! !#$! !(( ,-)
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SLVS426 − MAY 2002

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION
PACKAGED DEVICES
TA
PLASTIC TQFP (PT)(1)
−40°C to 85°C TPS5130PT
(1) The PT package is also available taped and reeled. Add an R suffix to the device type (i.e.,
TPS5130PTR).

PACKAGE DISSIPATION RATINGS

TA ≤ 25°C DERATING FACTOR TA = 85°C
PACKAGE(1)
POWER RATING ABOVE TA = 25°C POWER RATING
48 pin PT 3210 mW 25.7 mW/°C 1670 mW
(1) These devices are mounted on a JEDEC high-k board (2 oz. traces on surface, 2-layer 1 oz. plane
inside). (Assumes the maximum junction temperature is 150°C)

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)
TPS5130
Supply voltage, (2) VIN −0.3 V to 30 V
LH1/2/3 −0.3 V to 35 V
VIN_SENSE12/3, LL1/2/3, STBY_LDO,
−0.3 V to 30 V
STBY_VREF3.3/5, TRIP1/2/3
Input voltage range(2), VI INV1/2/3, CT, SS_STBY1/2/3,
INV_LDO, LDO_OUT, FLT,
PG_DELAY, VREF3.3/5, −0.3 V to 7 V
LDO_IN, LDO_CUR, PWM_SEL,
REG5V_IN
OUT1/2/3_u −0.3 V to 35 V
FB1/2/3, PGOUT, OUT1/2/3_d −0.3 V to 7 V
Output voltage range, VO (2)
LDO_GATE −0.3 V to 9 V
REF −0.3 V to 3 V
Operating ambient temperature range, TA −40°C to 85°C
Storage temperature, Tstg −55°C to 150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal.

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RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT
VIN 4.5 28
Supply voltage LDO_IN 1.1 3.6 V
REG5V_IN 4.5 5.5
OUT1/2/3_u, LH1/2/3 −0.1 33
VIN_SENSE1/2/3 4.5 28
STBY_LDO, LL1/2/3, TRIP, STBY_VREF3.3/5 −0.1 28
Input voltage, VI LDO_GATE −0.1 8 V
INV1/2/3, INV_LDO, CT, PWM_SEL, FLT, PG_DELAY, SS_STBY1/2/3 −0.1 6
PGOUT, FB1/2/3, OUT1/2/3_d −0.1 5.5
LDO_CUR, LDO_OUT −0.1 3.5
Oscillator frequency, fosc 300 500 kHz
Operating free-air temperature, TA −40 85 °C

ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted)

Supply Current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = 25°C, V(LDO_IN) = 3.6 V,
ICC Supply current 2 3 mA
V(CT) = V(INVx) = V(INV_LDO) = 0 V, V(PWM_SEL) = 0 V
V(SS_STBYx) = 0 V, V(STBY_LDO) = 0V,
ICC(STBY) Standby current 150 250 µA
V(STBY_VREF3.3/5) = 5 V
V(SS_STBYx) = 0 V, V(STBY_LDO) = 0V,
ICC(S) Shutdown current 0.001 10 µA
V(STBY_VREF3.3/5) = 0 V

Reference Voltage
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vref Reference voltage 0.85 V
TA = 25°C, Iref = 50 µA −1.5% 1.5%
Vref(tol) Reference voltage tolerance TA = 0°C to 85°C, Iref = 50 µA −2% 2%
TA = −40°C to 85°C, Iref = 50 µA −2.5% 2.5%
Line regulation V(VIN) = 4.5 V to 28 V, Iref = 50 µA 0.05 5 mV
Load regulation Iref = 0.1 µA to 1 mA 0.15 5 mV

5 V Internal Switch
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VT(LH) High 4.2 4.8
Threshold voltage REG5V_IN voltage V
VT(HL) Low 4.1 4.7
Vhys Hysteresis REG5V_IN voltage 30 200 mV

VREF5
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IO = 0 mA to 50 mA,
VO Output voltage 4.8 5.2 V
V(VIN) = 5.5 V to 28 V, TA = 25°C
Line regulation V(VIN) = 5.5 V to 28 V, IO = 10 mA 20 mV
Load regulation IO = 1 mA to 10 mA, V(VIN) = 5.5 V 40 mV
IOS Short-circuit output current V(VREF5) = 0 V, TA = 25°C 65 mA
VT(LH) High 3.6 4.2
UVLO threshold voltage VREF5 voltage V
VT(HL) Low 3.5 4.1
Vhys Hysteresis VREF5 voltage 30 200 mV

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted)
VREF3.3
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IO = 0 mA to 30 mA, V(VIN) = 5.5 V to 28 V,
VO Output voltage 3.15 3.30 3.45 V
TA = 25°C
Line regulation V(VIN) = 5.5 V to 28 V, IO = 10 mA 20 mV
Load regulation IO = 1 mA to 10 mA, V(VIN) = 5.5 V 40 mV
IOS Short circuit output current V(VREF3.3) = 0 V, TA = 25°C −30 mA
Control
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage SS_STBYx, STBY_LDO, PWM_SEL, STBY_VREF3.3/5 2.2 V
VIL Low-level input voltage SS_STBYx, STBY_LDO, PWM_SEL, STBY_VREF3.3/5 0.3 V
Output Voltage Monitor
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OVP comparator threshold SBRC, LDO 0.91 0.95 0.99 V
UVP comparator threshold SBRC, LDO 0.51 0.55 0.59 V
PG comparator low-level threshold 0.75 0.79 0.81 V
PG comparator high-level threshold 0.88 0.91 0.94 V
Powergood H to L 6.5
PG propagation delay from INVx, INV_LDO to PGOUT (no load at PG_DELAY) µss
Powergood L to H 16
I(PG_DELAY) PG_DELAY source current −1.8 µA
UVP protection −1.5 −2.3 −3.1 µA
Timer latch current source
OVP protection −80 −125 −180
Oscillator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fosc Oscillation frequency PWM mode, C(CT) = 44 pF, TA = 25°C 300 kHz
dc 1 1.1 1.2
VOH High level output voltage V
fosc = 300 kHz 1.17
dc 0.4 0.5 0.6
VOL Low level output voltage V
fosc = 300 kHz 0.43
Error Amplifier for SBRC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage INVx voltage, TA = 25°C 2 10 mV
Open loop voltage gain 50 dB
Unity-gain bandwidth 2.5 MHz
IO(snk) Output sink current V(FBx) = 1 V 0.2 0.7 mA
IO(src) Output source current V(FBx) = 1 V −0.2 −0.9 mA
Duty Control
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CH1/3, fosc = 300 kHz, V(INVx) = 0 V 82%
Maximum duty control
CH2, fosc = 300 kHz, V(INVx) = 0 V 97%

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted)
Output Drivers
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUT_u sink current V(OUTx_u) – V(LLx) = 3 V 1.2 A
OUT_u source current V(LHx) − V(OUTx_u) = 3 V −1.2 A
OUT_d sink current V(OUTx_d) = 3 V 1.5 A
OUT_d source current V(OUTx_d) = 2 V −1.5 A
LDO_GATE sink current V(LDO_GATE) = 2 V 2 mA
LDO_GATE source current V(LDO_GATE) = 2 V −1.4 mA
I(TRIPx) TRIP current TA = 25°C 11 13 15 µA
Soft Start
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(SS_STBYx) Soft start current V(SS_STBYx) = 0.7 V −1.6 −2.3 −2.9 µA
Error Amplifier for LDO Controller
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage V(LDO_IN) = 3.3 V, TA = 25 °C 2 10 mV
Open loop voltage gain V(LDO_IN) = 3.3 V 50 dB
Unity-gain bandwidth V(LDO_IN) = 3.3 V, CL = 2000 pF 1.4 MHz
Current Limit for LDO Controller
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current limit comparator threshold voltage V(LDO_IN) = 3.3 V 40 50 60 mV
Overshoot Protection for LDO Controller
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LDO_OUT sink current V(LDO_OUT) = V(LDO_GATE) = 1.5 V 25 mA

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PIN ASSIGNMENTS
PT
(TOP VIEW)

VIN_SENSE12
OUTGND1

OUTGND2
OUT1_u

OUT1_d

OUT2_d
TRIP1

TRIP2
INV1

LH1
FLT

LL1
48 47 46 45 44 43 42 41 40 39 38 37

FB1 1 36 LL2
SS_STBY1 2 35 OUT2_u
INV2 3 34 LH2
FB2 4 33 VIN
SS_STBY2 5 32 VREF3.3
PWM_SEL 6 31 VREF5
CT 7 30 REG5V_IN
GND 8 29 LDO_IN
REF 9 28 LDO_CUR
STBY_VREF5 10 27 LDO_GATE
STBY_VREF3.3 11 26 LDO_OUT
STBY_LDO 12 25 INV_LDO

13 14 15 16 17 18 19 20 21 22 23 24
OUTGND3
SS_STBY3

VIN_SENSE3
PGOUT
INV3

OUT3_u

OUT3_d
LL3
TRIP3
PG_DELAY
FB3

LH3

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
CT 7 I/O External capacitor from CT to GND adjusts frequency of the triangle oscillator.
FB1 1 O Feedback output of SBRC-CH1 error amplifier
FB2 4 O Feedback output of SBRC-CH2 error amplifier
FB3 14 O Feedback output of SBRC-CH3 error amplifier
FLT 47 I/O Fault latch timer pin. An external capacitor connected between FLT and GND sets FLT enable time up.
GND 8 − Signal GND
INV1 48 I Inverting inputs of SBRC-CH1 error amplifier, skip comparator, OVP1/UVP1 comparator and PG comparator
INV2 3 I Inverting inputs of SBRC-CH2 error amplifier, skip comparator, OVP2/UVP2 comparator and PG comparator
INV3 15 I Inverting inputs of SBRC-CH3 error amplifier, skip comparator, OVP3/UVP3 comparator and PG comparator
INV_LDO 25 I Inverting inputs of LDO error amplifier, OVP/UVP comparators and PG comparator.
LDO_CUR 28 I Current sense input of LDO regulator.
LDO_GATE 27 O Gate control output of external MOSFET for LDO regulator
LDO_OUT 26 I/O LDO regulator’s output connection. If output voltage has an overshoot when output current changes high to
low quickly, it absorbs electrical charge from this pin.
LDO_IN 29 I Supply voltage input and current sense input of LDO regulator

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Terminal Functions (Continued)

TERMINAL
I/O DESCRIPTION
NAME NO.
LH1 46 I/O Bootstrap capacitor connection for SBRC-CH1 high-side gate driver.
LH2 34 I/O Bootstrap capacitor connection for SBRC-CH2 high-side gate driver.
LH3 20 I/O Bootstrap capacitor connection for SBRC-CH3 high-side gate driver.
LL1 44 I/O SBRC-CH1 high-side gate driving return. Connect this pin to the junction of the high-side and low-side
MOSFETs for floating drive configuration. This pin is also an input terminal for current comparator.
LL2 36 I/O SBRC-CH2 high-side gate driving return. Connect this pin to the junction of the high-side and low-side
MOSFETs for floating drive configuration. This pin is also an input terminal for current comparator.
LL3 22 I/O SBRC-CH3 high-side gate driving return. Connect this pin to the junction of the high-side and low-side
MOSFETs for floating drive configuration. This pin is also an input terminal for current comparator.
OUT1_d 43 O Gate drive output for SBRC-CH1 low-side MOSFETs
OUT2_d 37 O Gate drive output for SBRC-CH2 low-side MOSFETs
OUT3_d 23 O Gate drive output for SBRC-CH3 low-side MOSFETs
OUT1_u 45 O Gate drive output for SBRC-CH1 high-side MOSFETs.
OUT2_u 35 O Gate drive output for SBRC-CH2 high-side MOSFETs.
OUT3_u 21 O Gate drive output for SBRC-CH3 high-side MOSFETs.
OUTGND1 42 O Ground for SBRC-CH1 MOSFETs drivers. It is connected to the current limiting comparator’s negative input.
OUTGND2 38 O Ground for SBRC-CH2 MOSFETs drivers. It is connected to the current limiting comparator’s negative input.
OUTGND3 24 O Ground for SBRC-CH3 MOSFETs drivers. It is connected to the current limiting comparator’s negative input.
PGOUT 16 O Powergood open drain output. PG comparators monitor all SBRC’s and LDO’s over voltage and under
voltage. The threshold is ±7%. When one of the output is beyond this condition, powergood output goes low.
PG_DELAY 17 I/O Programmable delay for Powergood. Connect an external capacitor between this pin and GND to specify
time delay.
PWM_SEL 6 I PWM or auto PWM/SKIP mode select.
H : auto PWM/SKIP
L : PWM fixed
REF 9 O 0.85-V reference voltage output. This 0.85-V reference voltage is used to set the output voltage and the
reference for the over and undervoltage protections. This reference voltage is dropped down from the internal
5-V regulator.
REG5V_IN 30 I External 5-V input
SS_STBY1 2 I/O Soft start control and stand by control for SBRC-CH1. Connect an external capacitor between this pin and
GND to specify soft start time.
SS_STBY2 5 I/O Soft start control and stand by control for SBRC-CH2. Connect an external capacitor between this pin and
GND to specify soft start time.
SS_STBY3 13 I/O Soft start control and stand by control for SBRC-CH3. Connect an external capacitor between this pin and
GND to specify soft start time.
STBY_LDO 12 I Standby control input for LDO regulator. LDO regulator can be switched into standby mode by grounding the
STBY_LDO pin.
STBY_VREF3.3 11 I Standby control for 3.3-V linear regulator.
STBY_VREF5 10 I Standby control for 5-V linear regulator.
TRIP1 41 I External resistor connection for SBRC-CH1 output current protection control.
TRIP2 39 I External resistor connection for SBRC-CH2 output current protection control.
TRIP3 18 I External resistor connection for SBRC-CH3 output current protection control.
VIN 33 I Supply voltage input
VIN_SENSE12 40 I SBRC-CH1/2 supply voltage monitor for reference of current limit. Input range is 4.5 V to 28 V.
VIN_SENSE3 19 I SBRC-CH 3 supply voltage monitor for reference of current limit. Input range is 4.5 V to 28 V.
VREF3.3 32 O 3.3-V linear regulator output
VREF5 31 O 5-V linear regulator output.

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FUNCTIONAL BLOCK DIAGRAM

PWM_SEL SBRC−CH1

SOFTSTART
SS_STBY1 Duplicate for CH2 and CH3.
/STBY
SKIP Comp.
−
0.85 V
+
FB1

ERROR Amp. LH1

INV1 − PWM Comp. OUT1_u
+ + LL1
CT Oscillator + −
0.85 V OUT1_d
OUTGND1
Phase
Inverter Current Comp. 1
OVP Comp.
−
+
+
−
0.85 V + 12 % Current −(VIN_SENSE−TRIP)
Protection VIN_SENSE12
UVP Comp.
Trigger +
+
SS_STBY
− − TRIP1
Current Comp. 2
0.85 V − 35 %

LH2
SS_STBY2 SBRC−CH2
OUT2_u
FB2 LL2
INV2 OUT2_d
OUTGND2

TRIP2
SS_STBY3
FB 3
INV3
LH3
SBRC−CH3
+ OUT3_u
+ LL3
+ OUT3_d
+ OUTGND3
− VIN_SENSE3
TRIP3
−
−
TIMER
−

0.85 V + 7 % −
+

0.85 V − 7 %
Fault
Latch
PG_DELAY Timer
PGOUT
FLT
STBY_LDO
INV_LDO
UVLO STBY_LDO
VIN SS_STBY STBY_LDO
STBY_VREF5
VREF3.3 VIN_SENSE
ERROR Amp.
STBY_VREF3.3
−
LDO_GATE
3.3 V OVP Comp. +
REG. −
0.85 V
+
5V VREF
VREF5
REG. 0.85 V 0.85 V + 12 %

LDO_IN
+ Current Limit
REG5V_IN −
LDO_CUR
−
UVP Comp.
+
GND LDO Overshoot
0.85 V − 35 % LDO_OUT
4.5 V
Protection
LDO
REF

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DETAILED DESCRIPTION

PWM OPERATION
The SBRC block has a high-speed error amplifier to regulate the output voltage of the synchronous buck converter. The
output voltage of the SBRC is fed back to the inverting input (INVx (x=1,2,3)) of the error amplifier. The noninverting input
is internally connected to a 0.85-V precise band gap reference circuit. The unity gain bandwidth of the amplifier is 2.5 MHz.
This decreases the amplifier delay during fast load transients and contributes to a fast response. Loop gain and phase
compensation is programmable by an external C, R network between the FBx and INVx pins. The output signal of the error
amplifier is compared with a triangular wave to achieve the PWM control signal. The oscillation frequency of this triangular
wave sets the switching frequency of the SBRC and is determined by the capacitor connected between the CT and GND
pins. The PWM mode is used for the entire load range if the PWM_SEL pin is set LOW, or used in high output current
condition if auto PWM/SKIP mode is selected by setting the same pin to HIGH.

SKIP MODE OPERATION

The PWM_SEL pin selects either the auto PWM/SKIP mode or fixed PWM mode. If this pin is lower than 0.3-V, the SBRC
operates in the fixed PWM mode. If 2.5 V (min.) or higher is applied, it operates in auto PWM/SKIP mode. In the auto
PWM/SKIP mode, the operation changes from constant frequency PWM mode to an energy-saving SKIP mode
automatically in accordance with load conditions. Using a MOSFET with ultra-low rDS(on) when the auto SKIP function is
implemented is not recommended. The SBRC block has a hysteretic comparator to regulate the output voltage of the
synchronous buck converter during SKIP mode. The delay from the comparator input to the driver output is typically 1.2
µs. In the SKIP mode, the frequency varies with load current and input voltage.

HIGH-SIDE DRIVER
The high-side driver is designed to drive high current and low rDS(on) N-channel MOSFET(s). The current rating of the driver
is 1.2 A at source and sink. When configured as a floating driver, a 5-V bias voltage is delivered from VREF5 pin. The
instantaneous drive current is supplied by the flying capacitor between the LHx and LLx pins since a 5-V power supply does
not usually have low impedance. It is recommended to add a 5 Ω to 10 Ω resistor between the gate of the high-side
MOSFET(s) and the OUTx_u pin to suppress noise. The maximum voltage that can be applied between the LHx and
OUTGNDx pins is 33 V.
When selecting the high current rating MOSFET(s), it is important to pay attention to both gate drive power dissipation and
the rise/fall time against the dead-time between high-side and low-side drivers. The gate drive power is dissipated from
the controller IC and it is proportional to the gate charge at VGS = 5 V, PWM switching frequency, and the numbers of all
MOSFETs used for low-side and high-side switches. This gate drive loss should not exceed the maximum power dissipation
of the device.

LOW-SIDE DRIVER
The low-side driver is designed to drive high current and low rDS(on) N-channel MOSFET(s). The maximum drive voltage
is 5 V from the internal regulator or REG5V_IN pin. The current rating of the driver is typically 1.5 A at source and sink.
Gate resistance is not necessary for the low-side MOSFET for switching noise suppression since it turns on after the
parallel diode is turned on (ZVS). It needs the same dissipation consideration when using high current rating MOSFET(s).
Another issue that needs precaution is the gate threshold voltage. Even though the OUTx_d pin is shorted to the OUTGNDx
pin with low resistance when the low-side MOSFET(s) is OFF, high dv/dt of the LLx pin during turnon of the high-side arm
will generate a voltage peak at the OUTx_d pin through the drain to gate capacitance, Cdg, of the low-side MOSFET(s).
To prevent a short period shoot-through during this switching event, the application designer should select MOSFET(s) with
adequate threshold voltage.

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DEAD-TIME
The internally defined dead-time prevents shoot-through-current flowing through the main power MOSFETs during
switching transitions. Typical value of the dead-time is 100 ns.

STANDBY
The SBRC controller, the LDO controller, and the internal regulators can be switched into standby mode separately as
shown in Table 1. The standby mode current, when both controllers and regulators are off, can be as low as 1 nA.

Table 1. Standby Logic

INPUT FUNCTION
STBY_VREF5 SS_STBYx STBY_VREF3.3 STBY_LDO V(REG5V_IN) > 4.5V VREF5 VREF3.3 SBRCx LDO
L L L L False OFF OFF OFF OFF
L(1) L(1) L(1) L(1) True(1) ON(1) OFF(1) OFF(1) OFF(1)
H L L L x ON OFF OFF OFF
L H L L x OFF OFF OFF OFF
H H L L x ON OFF ON OFF
L L H L x ON ON OFF OFF
H L H L x ON ON OFF OFF
L H H L x ON ON OFF OFF
H H H L x ON ON ON OFF
L L L H x ON OFF OFF ON
H L L H x ON OFF OFF ON
L H L H x ON OFF OFF ON
H H L H x ON OFF ON ON
L L H H x ON ON OFF ON
H L H H x ON ON OFF ON
L H H H x ON ON OFF ON
H H H H x ON ON ON ON
(1) This functional mode is not recommended.
x = true or false

SOFT START
Soft start ramp up of the SBRC is controlled by the SS_STBYx pin voltage, which is controlled by an internal current source
and an external capacitor connected between the SS_STBYx and GND pins. When the STBY_VREF5 and/or SS_STBYx
pin voltages are forced to LOW, the SBRCx is disabled. When the STBY_VREF5 pin voltage is set to HIGH and the
SS_STBYx pin floats, the internal current source starts to charge the external capacitor. The output voltage ramps up as
the SS_STBYx pin voltage increases from 0 V to 0.85 V. The soft start time is easily calculated from the supply current and
the capacitance value (see application information). The soft start timing circuit for the LDO is integrated into the device.
The soft start time is fixed and can be as short as 600 µs. This is observed when the LDO is turned on separately from the
SBRC. Simultaneous start-up of one of the SBRC and the LDO, is also possible. Tie the LDO input to the SBRCx’s output,
let both the STBY_VREF5 and STBY_LDO voltages rise to the HIGH level, and invoke Soft start on the SS_STBYx pin;
then the LDO’s output follows the ramp of the SBRCx’s output.

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OVER CURRENT PROTECTION

Over current protection (OCP) is achieved by comparing the drain-to-source voltage of the high-side and low-side MOSFET
to a set-point voltage, which is defined by both the internal current source, I(TRIP), and the external resistor connected
between the VIN_SENSEx and the TRIPx pins. I(TRIP) has a typical value of 13 µA at 25°C. When the drain-to-source
voltage exceeds the set-point voltage during low-side conduction, the high-side current comparator becomes active, and
the low-side pulse is extended until this voltage comes back below the threshold. If the set-point voltage is exceeded during
high-side conduction in the following cycle, the current limit circuit terminates the high-side driver pulse. Together this action
has the effect of decreasing the output voltage until the under voltage protection circuit is activated to latch both the
high-side and low-side drivers OFF. In the TPS5130, trip current I(TRIP) has a temperature coefficient of 3400 ppm/°C in
order to compensate for temperature drift of the MOSFET on-resistance.

OCP FOR THE LDO

To achieve the LDO current limit, a sense resistor must be placed in series with the N-channel MOSFET drain, connected
between the LDO_IN and LDO_CUR pins (see reference schematic). If the voltage drop across this sense resistor exceeds
50 mV, the output voltage is reduced to approximately 22% of the nominal value, thus it activates the UVP to start the FLT
latch timer. When the time is up, the LDO_GATE pin is pulled LOW to makes the LDO regulator shut down. Note that all
of the SBRCs are latched OFF at the same time since the LDO and the SBRCs share the same FLT capacitor.

OVER VOLTAGE PROTECTION

For overvoltage protection (OVP), the TPS5130 monitors the INVx and INV_LDO pin voltages. When the INVx or INV_LDO
pin voltage is higher than 0.95 V (0.85 V +12%), the OVP comparator output goes low and the FLT timer starts to charge
an external capacitor connected to FLT pin. After a set time, the FLT circuit latches the high-side MOSFET driver, the
low-side MOSFET drivers, and the LDO. The latched state of each block is summarized in Table 2. The timer source current
for the OVP latch is 125 µA(typ.), and the time-up voltage is 1.185 V (typ.). The OVP timer is designed to be 50 times faster
than the under voltage protection timer described in Table 2.

Table 2. OVP Logic

OVP OCCURRED AT HIGH-SIDE MOSFET DRIVER LOW-SIDE MOSFET DRIVER LDO
SBRC OFF ON OFF
LDO OFF OFF OFF

UNDER VOLTAGE PROTECTION

For under voltage protection (UVP), the TPS5130 monitors the INVx and INV_LDO pin voltages. When the INVx or
INV_LDO pin voltage is lower than 0.55 V (0.85 V - 35 %), the UVP comparator output goes low, and the FLT timer starts
to charge the external capacitor connected to FLT pin. Also, when the current comparator triggers the OCP, the UVP
comparator detects the under voltage output and starts the FLT capacitor charge, too. After a set time, the FLT circuit latches
all of the MOSFET drivers to the OFF state. The timer latch source current for UVP is 2.3 µA (typ.), and the time-up voltage
is also 1.185 V (typ.). The UVP function of the LDO controller is disabled when voltage across the pass transistor is less
than 0.23 V (typ.).

FLT
When an OVP or UVP comparator output goes low, the FLT circuit starts to charge the FLT capacitor. If the FLT pin voltage
goes beyond a constant level, the TPS5130 latches the MOSFET drivers. At this time, the state of MOSFET is different
depending on the OVP alert and the UVP alert (see Table 2). The enable time used to latch the MOSFET drivers is decided
by the value of the FLT capacitor. The charging constant current value depends on whether it is an OVP alert or a UVP
alert as shown in the following equation:
FLT source current (OVP) = FLT source current (UVP) × 50

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UNDER VOLTAGE LOCK OUT (UVLO)

When the output voltage of the internal 5-V regulator or the REG5V_IN voltage decreases below about 4 V, the output
stages of all the SBRCs and the LDO are turned off. This state is not latched, and the operation recovers immediately after
the input voltage becomes higher than the turnon value again. The typical hysteresis voltage is 100 mV.

UVLO FOR LDO

The LDO_IN voltage is monitored with a hysteretic comparator. When this voltage is less than 1 V, the UVLO circuit disables
the UVP/OVP comparators that monitor the INV_LDO voltage. In case the SBRC overcurrent protection is activated prior
to that of the LDO’s, this protection function may also be observed.

LDO CONTROL
The LDO controller can drive an external N-channel MOSFET. This realizes a fast response as well as an ultralow dropout
voltage regulator. For example, it is easy to configure both a 1.8-V and a 1.5-V high current power supply for core and I/O
of modern digital processors, one from the SBRC and the other from the LDO. The LDO_IN voltage range is from 1.1 V
to 3.6 V, and the output voltage is adjustable from 0.9 V to 2.5 V by an external resistor divider. Gain and phase of the
high-speed error amplifier for this LDO control is internally compensated and is connected to the 0.85-V band gap reference
circuit. The gate driver buffer is supplied by VIN_SENSE voltage. In the relatively high output voltage applications, make
sure that output voltage plus threshold voltage of the pass transistor is less than the minimum VIN. More precisely,
VIN - 0.7 ≥ Vthn + V(LDO_OUT)
where Vthn is the threshold voltage of the Nch MOSFET.
The LDO controller is also equipped with OVP, UVP, overcurrent limit, and overshoot protection functions.

OVERSHOOT PROTECTION
In the event that load current changes from high to low very quickly, the LDO regulator output voltage may start to overshoot.
In order to resist this phenomenon, the LDO controller has an overshoot protection function. If the LDO regulator output
overshoots, the controller draws electrical charge out from the LDO_OUT pin to hold it stable.

POWERGOOD
A single powergood circuit monitors the SBRCx output voltages and the LDO output voltage. The powergood pin is an open
drain output. When the INV or INV_LDO voltage goes beyond ±7% of 0.85 V, the powergood pin is pulled down to the LOW
level. Powergood propagation delay is programmable by controlling rising time using an external capacitor connected to
the PG_DELAY pin. During the soft start period, powergood indicates LOW, in other words power bad.

Table 3. Powergood Logic

SS_STBY1 SS_STBY2 SS_STBY3 STBY_LDO POWERGOOD
L L L L L
H L L L H
L H L L H
H H L L H
L L H L H
H L H L H
L H H L H
H H H L H
H or L H or L H or L H H

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5-V REGULATOR
An internal linear voltage regulator is used for the high-side driver bootstrap. Since the input voltage ranges from 4.5 V to
28 V, this feature offers a fixed bootstrap voltage to simplify the drive design. It is active if the STBY_VREF5 is HIGH and
has a tolerance of 4%. The 5-V regulator is used for powering the low-side driver and the VREF. When this regulator is
disconnected from the MOSFET drivers, it is used only for the source of VREF.

3.3-V REGULATOR
The TPS5130 has a 3.3-V linear regulator. The output is made from the internal 5-V regulator or an external 5 V from the
REG5V_IN pin. The maximum output current of this regulator is limited to 30 mA by an output current limit control. A ceramic
capacitor of 4.7 µF should be connected between the VREF3.3 and GND pins to stabilize the output voltage.

EXTERNAL 5-V INPUT AND 5-V SWITCH

If the internal 5-V switch detects 5-V input from the REG5V_IN pin, the internal 5-V regulator is disconnected from the
MOSFET drivers. The external 5 V is used for both the high-side bootstrap and the low-side driver, thus increasing the
efficiency. When an excess voltage is applied to the REG5V_IN pin, the OVP timer starts to charge the FLT capacitor and
latches all the MOSFET drivers and the LDO at OFF state after a set time.

PHASE INVERTER
The SBRC3 of the TPS5130 operates in the same phase as the internal triangular oscillator output while the SBRC1 and
the SBRC2 operate 180 degrees out of phase. When the SBRC1 and the SBRC3 (or the SBRC2 and the SBRC3) share
the same input power supply, the TPS5130 realizes 180 degrees out of phase operation that reduces input current ripple
and enables the input capacitor value smaller.

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TYPICAL CHARACTERISTICS

SUPPLY CURRENT SUPPLY CURRENT (SHUTDOWN)

vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
3 250
V(LDO_IN) = V(LDO_CUR) = 3.6 V, V(LDO_IN) = V(LDO_CUR) = 3.6 V,

I CC − Supply Current (Shutdown) − nA

V(PWM_ESL) = V(FLT) = V(CT) = 0 V V(INX) = V(INV_LDO) = 0 V
V(SS_STBYx) = 0 V
I CC − Supply Current − mA

200
2.5 V(STBY_VREF 3.3/5) = 0 V
V(PWM_SEL) = 0 V
150
2

100

1.5
50

1 0
−50 0 50 100 150 −50 0 50 100 150
TJ − Junction Temperature − °C TJ − Junction Temperature − °C

Figure 1 Figure 2

SOURCE CURRENT FLT(OVP) SOURCE CURRENT FLT(UVP)

vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
−160 −3
I S − Source Current − FLT(OVP) − µ A

I S − Source Current − FLT(UVP) − µ A

−140
−2.5
−120
−2
−100

−80 −1.5

−60
−1
−40
V(LDO_IN) = V(LDO_CUR) = 3.3 V, −0.5 V(LDO_IN) = V(LDO_CUR) = 3.3 V,
−20
V(INV_LDO) = 1 V V(INV_LDO) = 5 V
0 0
−50 0 50 100 150 −50 0 50 100 150
TJ − Junction Temperature − °C TJ − Junction Temperature − °C

Figure 3 Figure 4

TRIP CURRENT SINK CURRENT (LDO_GATE)

vs vs
JUNCTION TEMPERATURE OUTPUT VOLTAGE
3
25
V(INV_LDO) = 2 V
V(Trip) = V(VIN_SENSE) − 0.1 V V(LDO_IN) = V(LDO_CUR) = 3.3 V
2.5
Sink Current (LDO_GATE) − mA

20
Trip Current − µ A

2
15
1.5

10
1

5
0.5

0 0
0 2 4 6 8 10
−50 0 50 100 150
TJ − Junction Temperature − °C VO − Output Voltage − V

Figure 5 Figure 6
V(VIN_SENSE) = 12 V, unless otherwise noted

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TYPICAL CHARACTERISTICS

SOURCE CURRENT (LDO_GATE) THRESHOLD VOLTAGE (OVP)

vs vs
OUTPUT VOLTAGE JUNCTION TEMPERATURE
−2 955
V(INV_LDO) = 0 V
V(LDO_IN) = V(LDO_CUR) = 3.3 V
Source Current (LDO_GATE) − mA

Threshold Voltage (OVP) − mV

−1.5 950

−1 945

−0.5 940

0 935
0 2 4 6 8 10 −50 0 50 100 150
VO − Output Voltage − V TJ − Junction Temperature − °C

Figure 7 Figure 8

OSCILLATOR FREQUENCY OUTPUT MAXIMUM DUTY CYCLE

vs vs
CAPACITANCE JUNCTION TEMPERATURE
1000 100
TJ = 25°C
Output Maximum Duty Cycle − %
95 CH2
Oscillator Frequency − kHz

90

100 85 CH1/3

80

V(LH) = 5 V, C(CT) = 45 pF,

75 V(PWM_SEL) = V(FLT) = V(LL) = V(INV)
=0V
10 70
0 50 100 150 200 250 300 350
−50 0 50 100 150
C − Capacitance − pF TJ − Junction Temperature − °C

Figure 9 Figure 10

DELAY TIME FLT(OVP) DELAY TIME FLT(UVP)

vs vs
CAPACITANCE CAPACITANCE
100000 100000
VINV = 0.85 to 1.05 V, VINV = 0.65 to 0.05 V,
TJ = 25°C TJ = 25°C
t d − Delay Time FLT (OVP) − µ s

t d − Delay Time FLT (UVP) − µ s

10000 10000

1000 1000

100 100

10 10

1 1

0.1 0.1
10 100 1000 10000 10 100 1000 10000
C − Capacitance − pF C − Capacitance − pF

Figure 11 Figure 12
VVIN_SENSE = 12 V, unless otherwise noted

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TYPICAL CHARACTERISTICS

CURRENT LIMIT THRESHOLD

SOFT START TIME VOLTAGE FOR LDO
vs vs
CAPACITANCE JUNCTION TEMPERATURE

Current Limit Threshold Voltage For LDO − mV

100000 60
TJ = 25°C
50
10000
Soft Start Time − µ s

40
1000
30

100
20

10 V(LDO_IN) = 3.3 V
10
V(INV_LDO) = 0.5 V

1 0
1 10 100 1000 10000 100000 −50 0 50 100 150
C − Capacitance − pF TJ − Junction Temperature − °C

Figure 13 Figure 14

LDO UVLO THRESHOLD VOLTAGE POWERGOOD DELAY TIME

vs vs
JUNCTION TEMPERATURE CAPACITANCE
1.2 10000
VIN = 12 V, TJ = 25°C
VTLH V(INV_LDO) = 1 V → 0.85 V
LDO UVLO Threshold Voltage − V

Powergood Delay Time − µ s

1
VTHL 1000
0.8

0.6 100

0.4
10
0.2
V(INV_LDO) = 1.2 V
0 1
−50 0 50 100 150 1 10 100 1000 10000
TJ − Junction Temperature − °C C − Capacitance − pF

Figure 15 Figure 16

VVIN_SENSE = 12 V, unless otherwise noted

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APPLICATION INFORMATION
The design shown is a reference design for a notebook PC application. An evaluation module (EVM) is available
for customer testing and evaluation.
The following key design procedures aid in the design of the notebook PC power supply using TPS5130.

Q01A Q01B C35

R25 5−8 5−8
4 1−3 4 1−3
C41 L01

VO1−1
Q02A Q02B C37 C38 C39 D07 C40
5−8 5−8 D02 VO1−2
4 1−3 4 1−3
D01
R09

R23 C43
R49

R03A C03 R01A C02

R24 C44
2SC4617
R03B R04 R01B R02 Q08 R26
R46 JP01 D03 C31 C32 C33 D08 C34
1 JP11 4 1−3 4 1−3
3 R28 R27
C42 5−8 5−8
2 Q04A Q04B L02
2SC4617
Q11 R05
VO2−1
Q09 R29
C16 C28
4 1−3 4 1−3 C29 JP08 VO2−2
48
47
46
45
44
43
42
41
40
39
38
37

U01 R31 R30 2

1 JP12 5−8 5−8
3
OUTGND1

OUTGND2
TRIP1

TRIP2
OUT1_u

OUT1_d

OUT2_d
LH1

LL1
INV1
FLT

VIN_SENSE12

3 Q03A Q03B
R47 1
2 D04
JP02 R22
C04 R06
1 36
C30 FB1 LL2 VREF3.3
Q12 C05
2 SS_STBY1 35
OUT2_u
R07 3 C26
INV2 LH2 34
C06 R08
4 33
C07
FB2 VIN VREF5
JP03 5 32 C27
1 SS_STBY2 VREF3.3
3 6
PWM_SEL VREF5 31
2 C08 7 CT
TPS5130PT REG5V_IN
30 VIN1−1
JP04 8 29
1 GND LDO_VIN R21A C01A C01B VIN1−2
3 C09 9 28 C45 2 LDO_IN
REF LDO_CUR
2 10 27 R20 5−8 R21B
STBY_VREF5 LDO_GATE GND−1
JP05 11 26 4 1−3 1 JP10
1 STBY_VREF3.3 LDO_OUT R21C
Q07A 3 Q07B
3 12 25 GND−2
STBY_LDO INV_LDO
VIN_SENSE3

2
PG_DELAY
SS_STBY3

OUTGND3

LDO_OUT−1
OUT3_u

OUT3_d

JP06
PGOUT

1
TRIP3

R18 C23 C24

INV3

3 C22
FB3

LH3

LL3

2 LDO_OUT−2
13

14
R12 15

19

20
21
22
23
24
16
17

18

R48
1 R19
JP13 2SC4617
3

VIN_SLIT
2
C10
C13

JP07 Q10 R32

D05
C11

C17 C18 C19 D09 C20

C36 R11 4 1−3 4 1−3
R14

Q13
R34 R33 5−8 5−8
R13

Q06A Q06B L03

C14

VO3−1
R14B
C12

R16
4 1−3 4 1−3 C15 VO3−2
C21

5−8 5−8
R17

Q05A Q05B
D06
R15

PWR_GD

Figure 17. EVM Schematic

An optional circuit composed of Q08, Q09, Q10, R26, R27, R28, R29, R30, R31, R32, R33, and R34 can be
used to increase temperature coefficient of the trip current.

OUTPUT VOLTAGE SETPOINT CALCULATION

In the following calculation, assume the output voltage of SBRC1 (VO1), SBRC2 (VO2), SBRC3 (VO3), and LDO
(VO4) are 3.3 V, 5 V, 1.8 V, and 1.5 V respectively. The reference voltage and the voltage divider set the output
voltage. In the TPS5130, the reference voltage is 0.85 V, and the divider is composed of three resistors in the
EVM design that are R01A, R01B, and R05 for the first SBRC output; R03A, R03B, and R07 for the second
SBRC output ; R14A, R14B, and R11 for the third SBRC output ; R18 and R19 for LDO regulator output.
R1 V ref R1 Vref
VO + ) V ref or R2 +
R2 V O * V ref
where R1 is the top resistor (kΩ) (R01A + R01B or R03A + R03B or R14A + R14B or R18); R2 is the bottom
resistor (kΩ) (R05 or R07 or R11 or R19); VO is the required output voltage (V); Vref is the reference voltage
(0.85 V in TPS5130). The value for R1 is set as a part of the compensation circuit and the value of R2 may be
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calculated to achieve the desired output voltage. In the EVM design, the value of R1 is determined as
R01A = 27 kΩ and R01B = 1.8 kΩ for VO1, R03A = 47 kΩ and R03B = 1.8 kΩ for VO2, R14A = 10 kΩ and
R14B = 1.2 kΩ for VO3, and R18 = 6.8 k + 820 Ω for VO4 considering stability. For VO1:
(27 k ) 1.8 k) 0.85
R05 + + 9.99 kW
3.3 * 0.85
Therefore, use 10 kΩ.
In a same manner, R07 = R11 = R19 = 10 kΩ as follows.
(47 k ) 1.8 k) 0.85
R07 + + 10.00 kW
5 * 0.85
(10 k ) 1.2 k) 0.85
R11 + + 10.02 kW
1.8 * 0.85
(6.8 k ) 820) 0.85
R19 + + 9.96 kW
1.5 * 0.85
The values of R01B, R03B, R14B and R19 are chosen so that the calculated values of R05, R07, R11, and R19
are standard value resistors and the VO setpoint maintains the highest precision. This is best accomplished by
combining two resistor values. If a standard value resistor can not be applied, use a value for R01A, R03A,
R14A, and R18 that is just slightly less than the desired total. A small resistor value in the range of tens or
hundreds of ohms for R01B, R03B, R14B and R18 can then be added to generate the desired final value.
OUTPUT INDUCTOR SELECTION
The required value for the output filter inductor can be calculated by using the equation below, assuming the
magnitude of the ripple current is 20 % of the maximum output current:
VIN * V O VO 1
L (out) +
0.2 I O VIN fS

Where L(out) is output filter inductor value (H), VIN is the input voltage (V), IO is the maximum output current
(A), fs is the switching frequency (Hz).
Example : VIN = 8 V; VO = 3.3 V; IO = 4 A; fs = 300 kHz.
Then, L(out) = 8.1 µH.
If faster output response is required for a sudden transition of the load, smaller inductance value is
recommended.
OUTPUT INDUCTOR RIPPLE CURRENT
The output inductor current can affect not only the efficiency, but also the output voltage ripple. The equation
is exhibited below:

VIN * V O * I O ǒr DS(on) ) RLǓ VO 1

I (ripple) +
L (out) VIN fS

where I(ripple) is the peak-to-peak ripple current (A) through the inductor; Io is the output current; rDS(on) is the
on-time resistance of MOSFET (Ω); RL is the inductor dc resistance (Ω). From the equation, it can be seen that
the current ripple can be adjusted by changing the output inductor value.
Example: VIN = 8 V; VO = 3.3 V; IO = 4 A; rDS(on) = 25 mΩ; RL = 10 mΩ; fs = 300 kHz; L(out) = 4 µH.
Then, the ripple current I(ripple) = 1.57 A

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OUTPUT CAPACITOR SELECTION

Selection of the output capacitor is basically dependent on the amount of peak-to-peak ripple voltage allowed
on the output and the ability of the capacitor to dissipate the RMS ripple current. Assuming that the ESR of the
output filter sees the entire inductor ripple current then:
V pp + I (ripple) R(esr)

And a suitable capacitor must be chosen so that the peak-to-peak output ripple is within the limits allowable
for the application.
OUTPUT CAPACITOR RMS CURRENT
Assuming the inductor ripple current totally goes through the output capacitor to ground, the RMS current in
the output capacitor can be calculated as:
I (ripple)
I O(rms) +
Ǹ12

where IO(rms) is maximum RMS current in the output capacitor (A); I(ripple) is the peak-to-peak inductor ripple
current (A).
Example: I(ripple) = 1.57 A, then, IO(rms) = 0.45 A

INPUT CAPACITOR RMS CURRENT

Since the SBRC3 of the TPS5130 operates 180 degree off phase against the SBRC1 and SBRC2, total RMS
current in the input capacitor is calculated as follows, assuming the input current totally goes into the input
capacitor to the power ground, and ignoring ripple current in the inductor.
When the duty cycle of the SBRC2 (D2) is over 50 %,

I I(rms) + Ǹ(D1 I O12) ) (D2 I O2 2) ) (D3 I O3 2) ) (2D1 I O1 I O2) ) (2D2 * 1) I O2 I O3 * I Ox 2

I Ox + (D1 I O1) ) (D2 I O2) ) (D3 I O3) D2 w 0.5 w D1 w D3

II(rms) is the input RMS current in the input capacitor; DX is duty cycles, defined as VO/VI in this case, of the
SBRCx.
When D2 is less than 50%,

I I(rms) + Ǹ(D1 I O1 2) ) (D2 I O22) ) (D3 I O32) ) (2D1 I O1 I O2) * I Ox 2

Example: VIN = 12 V, VO1 = 3.3 V, VO2 = 5 V (D2 = 0.42), VO3 = 1.8V, IO1 = IO2 = 4 A, IO3 = 6 A
Then, II(rms) = 3.44 A
On the contrary, if three SBRCs operate in a same phase the RMS current is calculated as follows.

I I(rms) + Ǹ(D1 I O12) ) (D2 I O2 2) ) (D3 I O3 2) ) (2D1 I O1 I O2) ) (2D3 I O3) ǒIO1 ) IO2Ǔ * I Ox2

Under the same operation condition, II(rms) = 5.13 A

Therefore, 180 degree out of phase operation is effective in reducing input RMS current, and it allows a smaller
input capacitance value. The input capacitors must be chosen so that together they can safely handle the input
ripple current. Depending on the input filtering and the dc input voltage source, not all the ripple current flows
through the input capacitors, but some may be present on the input leads to the EVM.

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SOFT START
The soft start timing can be adjusted by selecting the soft-start capacitor value. The equation is;
T(soft)
C(soft) + 2.3 10–6
0.85
where C(soft) is the soft-start capacitor (µF) (C05, C07 and C10 in EVM design):
T(soft) is the start-up time (s).
Example: T(soft) = 5 ms, therefore, C(soft) = 0.0135 µF.

CURRENT PROTECTION
The current limit in TPS5130 is set using an internal current source and an external resistor (R17, R23 and R24).
The current limit protection circuit compares the drain to source voltage of the high-side and low-side
MOSFET(s) with respect to the set-point voltage. If the voltage up exceeds the limit during high-side conduction,
the current limit circuit terminates the high-side driver pulse. If the set point voltage is exceeded during low-side
conduction, the low side pulse is extended through the next cycle. Together this action has the effect of
decreasing the output voltage until the under voltage protection circuit is activated and the fault latch is set and
both the high-side and low-side MOSFET drivers are shut off. The equation below should be used for calculating
the external resistor value for current protection set point:

r DS(on) ǒ I (trip) )
2
Ǔ
I (ripple)

R(cl) +
13 10 –6
where R(cl) is the external current limit resistor (R17, R23 and R24); rDS(on) is the low-side MOSFET(Q02, Q04
and Q06) on-time resistance. I(trip) is the required current limit.
Example: rDS(on) = 25 mΩ, I(trip) = 4 A, I(ripple) = 1.57 A, therefore, R(cl)= 9.2 kΩ.
It should be noted that rDS(on) of a FET is highly dependent on temperature, so to insure full output at maximum
operating temperature, the value of rDS(on) in the above equation should be adjusted. For maximum stability,
it is recommended that the high-side MOSFET(s) has the same, or slightly higher rDS(on)than the low-side
MOSFET(s). If the low-side MOSFET(s) has a higher rDS(on), in certain low duty cycle applications it may be
possible for the device to regulate at an output current higher than that set by the above equation by increasing
the high-side conduction time to compensate for the missed conduction cycle caused by the extension of the
previous low-side pulse.
TIMER-LATCH
The TPS5130 includes fault latch function with a user adjustable timer to latch the MOSFET drivers in case
of a fault condition. When either the OVP or UVP comparator detect a fault condition, the timer starts to charge
FLT capacitor (C42), which is connected with FLT pin. The circuit is designed so that for any value of FLT
capacitor, the undervoltage latch time t(uvplatch) is about 50 times larger than the overvoltage latch time t(ovplatch).
The equations needed to calculate the required value of the FLT capacitor for the desired over and undervoltage
latch delay times are:
t (uvplatch)
C (lat) + 2.3 10 *6 and
1.185
t (ovplatch)
C (lat) + 125 10 *6
1.185
where C(lat) is the external capacitor, t(uvplatch) is the time from UVP detection to latch. t(ovplatch) is the time from
OVP detection to latch.
For the EVM, t(uvplatch) = 5 ms and t(ovplatch) = 0.1 ms, so C(lat) = 0.01 µF. If the voltage on the FLT pin reaches
1.185 V, the fault latch is set, and the MOSFET drivers are set as follows:
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SLVS426 − MAY 2002

Undervoltage Protection
The undervoltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the
voltage at either pin falls below 65 % of the 0.85 V reference, the timer begins to charge the FLT capacitor. if
the fault condition persists beyond the time t(uvplatch), the fault latch is set and both the high-side and low-side
drivers, and LDO regulator drivers are forced OFF.
Short-Circuit Protection
The short-circuit protection circuitry uses the UVP circuit to latch the MOSFET drivers. When the current limit
circuit limits the output current, then the output voltage goes below the target output voltage and UVP
comparator detects a fault condition as described above.
Overvoltage Protection
The overvoltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage
at either pin rises above 112 % of the 0.85 V reference, the timer begins to charge the FLT capacitor. If the fault
condition persists beyond the time t(ovplatch), the fault latch is set and the high-side drivers are forced OFF, while
the low-side drivers are forced ON, and LDO regulator drivers are forced OFF.
CAUTION:
Do not set the FLT terminal to a lower voltage (or GND) while the device is timing out an OVP or UVP
event. If the FLT terminal is manually set to a lower voltage during this time, output overshoot may
occur. The TPS5130 must be reset by grounding SS_STBYx and STBY_LDO, or dropping down
REG5V_IN.
Disablement of the Protection Function
If it is necessary to inhibit the protection functions of the TPS5130 for troubleshooting or other purposes, the
OCP,OVP, and UVP circuits may be disabled.
D OCP(SBRC): Remove the current limit resistors R17, R23 and R24 to disable the current limit function.
D OCP(LDO): Short−circuit R21 to disable the current limit function.
D OVP, UVP: Grounding the FLT terminal can disable OVP and UVP.

LDO REGULATOR APPLICATION INFORMATION

Output Capacitor Selection
To keep stable operation of the LDO, capacitance of more than 33 µF and R(esr) of more than 30 mΩ are
recommended for the output capacitor.
Power MOSFET Selection
Also, to keep stable operation of LDO, lower input capacitance is recommended for the external power
MOSFET. However, input capacitance that is too small may lead the feedback loop into an unstable region.
In this case, the gate resistor of several hundreds ohms keeps the LDO operation in the stable state.
Current Protection
If excess output current flows through sense resistor (R21) and the voltage drop exceeds 50 mV, the output
voltage is reduced to approximately 22% of the nominal value, thus activates UVP to start the FLT latch timer.
When the set current is 3 A, the value of R21 is 16.7 mΩ.

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SLVS426 − MAY 2002

Layout Guidelines
Good power supply results only occur when care is given to proper design and layout. Layout affects noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens amps, good power supply layout is much more difficult than most general
PCB designs. The general design should proceed from the switching node to the output, then back to the driver
section and, finally, parallel the low-level components. Below are specific points to consider before the layout
of a TPS5130 design begins.
D A four-layer PCB design is recommended for design using the TPS5130. For the EVM design, the top layer
contains the interconnection to the TPS5130, plus some additional signal traces. Layer2 is fully devoted
to the ground plane. Layer3 has some signal traces. The bottom layer is almost devoted to ANAGND, and
the rest is to other signal trace.
D All sensitive analog components such as INV, REF, CT, GND, FLT, and SS_STBY should be referenced
to ANAGND.
D Ideally, all of the area directly under the TPS5130 chip should also be ANAGND.
D ANAGND and DRVGND should be isolated as much as possible, with a single point connection between
them.

CTRIP
TRIP
VIN_SENSE VIN
VREF5 CBS
LH CBP CIN
OUT_u

INV LL Vox
FB
SOFT_START COUT

OUT_d
CT
ANAGND
GND OUTGND VoxGND
DRVGND
REF LDO_IN

LDO_CUR

FLT
LDO_GATE
INV_LDO LDO_OUT Vo_LDO

Figure 18. PCB Diagram

Low-Side MOSFET(s)
D The source of low-side MOSFET(s) should be referenced to DRVGND, otherwise ANAGND is subject to
the noise of the outputs.
D DRVGND should be connected to the main ground plane close to the source of the low-side MOSFET.
D OUTGND should be placed close to the source of low side MOSFET(s).
D The Schottky diode anode, the returns for the high frequency bypass capacitor for the MOSFETs, and the
source of the low-side MOSFET(s) traces should be routed as close together as possible.
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SLVS426 − MAY 2002

Connections
D Connections from the drivers to the gate of the power MOSFETs should be as short and wide as possible
to reduce stray inductance. This becomes more critical if external gate resistors are not being used. In
addition, as for the current limit noise issue, use of a gate resistor on the high-side MOSFET(s) considerably
reduces the noise at the LL node, improving the performance of the current limit function.
D The connection from LL to the power MOSFETs should be as short and wide as possible.
Bypass Capacitor
D The bypass capacitor for VIN_SENSE should be placed close to the TPS5130.
D The bulk storage capacitors across VIN should be placed close to the power MOSFETs. High-frequency
bypass capacitors should be placed in parallel with the bulk capacitors and connected close to the drain
of the high-side MOSFET(s) and to the source of the low-side MOSFET(s).
D For aligning phase between the drain of high-side MOSFET(s) and the trip-pin, and for noise reduction, a
0.1 µF capacitor C(TRIP) should be placed in parallel with the trip resistor.
Bootstrap Capacitor
D The bootstrap capacitor C(BS) (connected from LH to LL) should be placed close to the TPS5130.
D LH and LL should be routed close to each other to minimize noise coupling to these traces.
D LH and LL should not be routed near the control pin area (ex. INV, FB, REF, etc.).
Output Voltage
D The output voltage sensing trace should be isolated by either ground plane.
D The output voltage sensing trace should not be placed under the inductors on same layer.
D The feedback components should be isolated from output components, such as, MOSFETs, inductors, and
output capacitors. Otherwise the feedback signal line is susceptible to output noise.
D The resistors for setup output voltage should be referenced to ANAGND.
D The INV trace should be as short as possible.
EFFICIENCY (PWM MODE) EFFICIENCY (PWM MODE) EFFICIENCY (PWM MODE)
vs vs vs
OUTPUT CURRENT OUTPUT CURRENT OUTPUT CURRENT
100 100 100
VIN = 8 V VIN = 8 V VIN = 8 V
Efficiency (PWM MODE) − %
Efficiency (PWM MODE) − %

80
Efficiency (PWM MODE) − %

80 80

VIN = 12 V
VIN = 12 V VIN = 12 V
60 60 60

VIN = 20 V
VIN = 20 V
VIN = 20 V 40 40
40

SBRC CH1 SBRC CH2 20 SBRC CH3

20 20
External 5 V External 5 V External 5 V
VO1 = 3.3 V VO2 = 5 V VO3 = 1.8 V
0 0 0
0.01 0.1 1 10 0.01 0.1 1 10 0.01 0.1 1 10
IO − Output Current − A IO − Output Current − A IO − Output Current − A

Figure 19 Figure 20 Figure 21

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SLVS426 − MAY 2002

EFFICIENCY (AUTO SKIP MODE) EFFICIENCY (AUTO SKIP MODE) EFFICIENCY (AUTO SKIP MODE)
vs vs vs
OUTPUT CURRENT OUTPUT CURRENT OUTPUT CURRENT
100 100 100

Efficiency (AUTO SKIP MODE) − %

Efficiency (AUTO SKIP MODE) − %

Efficiency (AUTO SKIP MODE) − %

80 VIN = 8 V 80
80 VIN = 8 V VIN = 8 V
VIN = 12 V
VIN = 12 V VIN = 12 V
VIN = 20 V
60 VIN = 20 V 60 60
VIN = 20 V

40 40 40

SBRC CH1 SBRC CH2

20 20 20 SBRC CH3
External 5 V External 5 V
External 5 V
VO1 = 3.3 V VO2 = 5 V
VO3 = 1.8 V
0 0 0
0.01 0.1 1 10 0.01 0.1 1 10 0.01 0.1 1 10
IO − Output Current − A IO − Output Current − A IO − Output Current − A

Figure 22 Figure 23 Figure 24

SBRC CH1 OUTPUT LINE REGULATION SBRC CH2 OUTPUT LINE REGULATION SBRC CH3 OUTPUT LINE REGULATION
1.766
3.270 5.004
IO = 4 A IO = 6 A
IO = 4 A
1.764
3.268 5.002

VO − Output Voltage − V
VO − Output Voltage − V
VO − Output Voltage − V

1.762
3.266 5

1.760
3.264 4.998

4.996 1.758
3.262

1.756
3.260 4.994
5 10 15 20 5 10 15 20
5 10 15 20
VI − Input Voltage − V VI − Input Voltage − V
VI − Input Voltage − V

Figure 25 Figure 26 Figure 27

LDO OUTPUT LINE REGULATION SBRC CH1 OUTPUT LOAD REGULATION SBRC CH2 OUTPUT LOAD REGULATION
1.464 3.290 5.030
V(LDO_IN = VO3 PWM Mode PWM Mode
IO = 3 A VIN = 12 V VIN = 12 V
3.285 5.025
1.462
VO − Output Voltage − V

VO − Output Voltage − V

VO − Output Voltage − V

3.280 5.020
1.460
3.275 5.015

1.458
3.270 5.010

1.456
3.265 5.005

1.454 3.260 5
5 10 15 20 0 1 2 3 4 0 1 2 3 4
VI − Input Voltage − V IO− Output Current − A IO− Output Current − A

Figure 28 Figure 29 Figure 30

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SLVS426 − MAY 2002

SBRC CH3 OUTPUT LOAD REGULATION LDO OUTPUT LOAD REGULATION

1.790 1.480
PWM Mode V(LDO_IN)= VO3
1.785 VIN = 12 V 1.475
VO − Output Voltage − V

VO − Output Voltage − V
1.780 1.470

1.775 1.465

1.770 1.460

1.765 1.455

1.760 1.450
0 1 2 3 4 5 6 0 1 2 3
IO− Output Current − A IO− Output Current − A

Figure 31 Figure 32
SBRC CH1 OUTPUT VOLTAGE RIPPLE SBRC CH2 OUTPUT VOLTAGE RIPPLE SBRC CH3 OUTPUT VOLTAGE RIPPLE
50 mV/div 50 mV/div 20 mV/div

IO1 = 0 A IO2 = 0 A IO2 = 0 A

2A 2A 4A

4A 4A 6A

VIN = 12 V, VO1 = 3.3 V VIN = 12 V, VO2 = 5 V VIN = 12 V, VO3 = 1.8 V 1 µs/div

1 µs/div 1 µs/div

Figure 33 Figure 34 Figure 35

LDO OUTPUT VOLTAGE RIPPLE SBRC CH1 LOAD TRANSIENT RESPONSE SBRC CH2 LOAD TRANSIENT RESPONSE
10 mV/div

VO1 VO2
20 mV/div 20 mV/div
IO= 0.3 A

1A
4A 4A

IO1 IO2
3A 0A 2 A/div 0A 2 A/div
VIN = 12 V, V(LDO_IN) = VO3 = 1.8 V,
IO3 = 0 A
1 µs/div VIN = 12 V, VO1 = 3.3 V 100 µs/div VIN = 12 V, VO2 = 5 V 100 µs/div

Figure 36 Figure 37 Figure 38

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SLVS426 − MAY 2002

SBRC CH3 LOAD TRANSIENT RESPONSE LDO LOAD TRANSIENT RESPONSE

VIN = 12 V, V(LDO_IN) = VO3 = 1.8 V,
V(LDO) = 1.5 V
VO3 VO
20 mV/div 50 mV/div

3A
6A

IO3 IO
30 mA 1 A/div
0A 2 A/div

VIN = 12 V, VO3 = 1.8 V 100 µs/div 100 µs/div

Figure 39 Figure 40

SBRC CH1 GAIN AND PHASE SBRC CH2 GAIN AND PHASE
80 240 80 240
Phase Margin = 59 Degrees
Phase Margin = 53 Degrees
60 180 60 180
Phase − Degrees

Phase − Degrees
40 120 40 120
Gain − dB

Gain − dB
Phase
Phase
20 60 20 60

0 0 0 0
VIN = 12 V, Gain VIN = 12 V, Gain
−20 VO1 = 3.3 V, −60 −20 VO2 = 5 V, −60
IO1 = 4 A IO2 = 4 A

−40 −120 −40 −120

100 1K 10K 100K 1M 100 1K 10K 100K 1M
f − Frequency − Hz f − Frequency − Hz

Figure 41 Figure 42

SBRC CH3 GAIN AND PHASE LDO GAIN AND PHASE

80 80 240
240
Phase Margin = 37 Degrees Phase Margin = 74 Degrees

60 60 180
180
Phase − Degrees
40 120
Phase − Degrees

40 120
Phase
Gain − dB
Gain − dB

Phase
60 20 60
20

Gain
0 0 0
0
VIN = 12 V, Gain
−20 VIN = 12 V, −60
−20 VO3 = 1.8 V, −60
V(LDO_IN) = VO3 =1.8 V,
IO3 = 6 A
I(LDO) = 3 A
−40 −120 −40 −120
100 1K 10K 100K 1M 100 1K 10K 100K 1M
f − Frequency − Hz f − Frequency − Hz

Figure 43 Figure 44

26
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SLVS426 − MAY 2002

MECHANICAL DATA
PT (S-PQFP-G48) PLASTIC QUAD FLATPACK

0,27
0,50 0,08 M
0,17

36 25

37 24

48 13

0,13 NOM
1 12

5,50 TYP
7,20
SQ
6,80 Gage Plane
9,20
SQ
8,80
0,25
1,45 0,05 MIN 0°−ā 7°
1,35

0,75
Seating Plane 0,45

1,60 MAX 0,10

4040052/ C 11/96

NOTES:A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

27
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS5130PT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PS5130

TPS5130PTG4 ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PS5130

TPS5130PTR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PS5130

TPS5130PTRG4 ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PS5130

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS5130 :

• Automotive: TPS5130-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW
Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
TPS5130PT PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TPS5130PTG4 PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25

Pack Materials-Page 1
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