19-0197; Rev 1; 1/95

CCFL Backlight and

LCD Contrast Controllers
_______________General Description ____________________________Features

MAX753/MAX754
The MAX753/MAX754 drive cold-cathode fluorescent ♦ Drives Backplane and Backlight
lamps (CCFLs) and provide the LCD backplane bias
(contrast) power for color or monochrome LCD panels. ♦ 4V to 30V Battery Voltage Range
These ICs are designed specifically for backlit note- ♦ Low 500µA Supply Current
book-computer applications.
♦ Digital or Potentiometer Control of CCFL
Both the backplane bias and the CCFL supply can be
shut down independently. When both sections are shut Brightness and LCD Bias Voltage
down, supply current drops to 25µA. The LCD contrast ♦ Negative LCD Contrast (MAX753)
and CCFL brightness can be adjusted by clocking sep-
♦ Positive LCD Contrast (MAX754)
arate digital inputs or using external potentiometers.
LCD contrast and backlight brightness settings are pre- ♦ Independent Shutdown of Backlight and
served in their respective counters while in shutdown. Backplane Sections
On power-up, the LCD contrast counter and CCFL
brightness counter are set to one-half scale. ♦ 25µA Shutdown Supply Current
The ICs are powered from a regulated 5V supply. The
magnetics are connected directly to the battery, for
maximum power efficiency. ______________Ordering Information
The CCFL driver uses a Royer-type resonant architec-
PART TEMP. RANGE PIN-PACKAGE
ture. It can provide from 100mW to 6W of power to one
or two tubes. The MAX753 provides a negative LCD MAX753CPE 0°C to +70°C 16 Plastic DIP
bias voltage; the MAX754 provides a positive LCD bias MAX753CSE 0°C to +70°C 16 Narrow SO
voltage. MAX753C/D 0°C to +70°C Dice*
MAX753EPE -40°C to +85°C 16 Plastic DIP
________________________Applications
MAX753ESE -40°C to +85°C 16 Narrow SO
Notebook Computers MAX754CPE 0°C to +70°C 16 Plastic DIP
Palmtop Computers MAX754CSE 0°C to +70°C 16 Narrow SO
Pen-Based Data Systems MAX754C/D 0°C to +70°C Dice*
MAX754EPE -40°C to +85°C 16 Plastic DIP
Personal Digital Assistants
MAX754ESE -40°C to +85°C 16 Narrow SO
Portable Data-Collection Terminals
* Contact factory for dice specifications.

__________________Pin Configuration
TOP VIEW

VDD 1 16 LFB
LADJ 2 15 BATT
LON 3 14 LX
CON 4 MAX753 13 LDRV
MAX754
CADJ 5 12 PGND
GND 6 11 CDRV
REF 7 10 CS
CFB 8 9 CC

DIP/SO
Block Diagram located at end of data sheet.

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
 CCFL Backlight and
LCD Contrast Controllers
ABSOLUTE MAXIMUM RATINGS
MAX753/MAX754

VDD to GND .................................................................-0.3V, +7V Operating Temperature Ranges

PGND to GND.....................................................................±0.3V MAX75_C_ _ ........................................................0°C to +70°C
BATT to GND.............................................................-0.3V, +36V MAX75_E_ _......................................................-40°C to +85°C
LX to GND............................................................................±50V Junction Temperature ......................................................+150°C
CS to GND.....................................................-0.6V, (VDD + 0.3V) Storage Temperature Range .............................-65°C to +160°C
Inputs/Outputs to GND (LADJ, CADJ, LON, Lead Temperature (soldering, 10sec) .............................+300°C
CON, REF, CFB, CC, CDRV, LDRV, LFB) .....-0.3V, (VDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ...........842mW
Narrow SO (derate 8.70mW/°C above +70°C) .............696mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(V DD = 5V, BATT = 15V, CON = LON = 5V, LX = GND = PGND = 0V, I REF = 0mA, all digital input levels are 0V or 5V,
TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
SUPPLY AND REFERENCE
BATT Input Range 4 30 V
VDD Supply Range 4.5 5.5 V
REF Output Voltage No external load 1.21 1.25 1.29 V
REF Line Regulation 4V < VDD < 6V 0.1 %/V
REF Load Regulation 0µA < IL < 100µA 5 15 mV
LON = CON = CS = LFB = CFB =
VDD Quiescent Current 0.5 2 mA
LADJ = CADJ = 5V
LON = CON = CS = LFB = CFB = LADJ
VDD Shutdown Current 25 40 µA
= CADJ = LX = BATT = 0V (Note 1)
DIGITAL INPUTS AND DRIVER OUTPUTS
Input Low Voltage LON, CON, CADJ, LADJ; VDD = 4.5V 0.8 V
Input High Voltage LON, CON, CADJ, LADJ; VDD = 5.5V 2.4 V
Input Leakage Current LON, CON, CADJ, LADJ; VIN = 0V or 5V ±1 µA
Driver Sink/Source Current LDRV = CDRV = 2V 0.5 A
LDRV, CDRV; Output high 10
Driver On-Resistance Ω
VDD = 4.5V Output low 7
CCFT CONTROLLER
Zero-Crossing-Comparator Threshold Voltage (CS) -10 20 mV
Overcurrent-Comparator Threshold Voltage (CS) 1.2 1.3 V
CS Input Bias Current VCS = 0V -5 µA
Minimum, CFB = 5V 32 47
VCO Frequency kHz
Maximum, CFB = 0V 85 115
DAC Resolution Guaranteed monotonic 5 Bits

2 _______________________________________________________________________________________
 CCFL Backlight and
LCD Contrast Controllers
ELECTRICAL CHARACTERISTICS (continued)

MAX753/MAX754
(V DD = 5V, BATT = 15V, CON = LON = 5V, LX = GND = PGND = 0V, I REF = 0mA, all digital input levels are 0V or 5V,
TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
At full scale (DAC code = 31) 1210 1250 1290
At preset DAC, CON = 0V, CADJ = 5V
Feedback Voltage (CFB) 745 782 820 mV
(code = 15)
At zero scale (code = 0) 320 343 365
Feedback-Amplifier Input Bias Current ±100 nA
Feedback-Amplifier Unity-Gain Bandwidth 1 MHz
Feedback-Amplifier Slew Rate 0.4 V/µs
Source current, CFB = 0V, CC = 2.5V 50
Feedback-Amplifier Output Current µA
Sink current, CFB = 5V, CC = 2.5V 200
LCD CONTROLLER
BATT = 4V 2 5
Switch On-Time µs
BATT = 16V 0.5 1.5
Switching Period BATT = 4V, LX = 0V 35 70 µs
DAC Resolution Guaranteed monotonic 6 Bits
At full scale (DAC code = 63) 1200 1240 1280
At preset DAC, LON = 0V, LADJ = 5V
MAX753 Feedback Voltage (REF-LFB) 893 928 963 mV
(code = 31)
At zero scale (code = 0) 595 625 655
At full scale (DAC code = 63) 1210 1250 1290
At preset DAC, LON = 0V, LADJ = 5V
MAX754 Feedback Voltage (LFB) 905 938 971 mV
(code = 31)
At zero scale (code = 0) 610 635 660
LFB Input Leakage Current ±150 nA
LON = CON = CS = LFB = CFB = LADJ =
BATT Input Current 12 20 µA
CADJ = LX = 0V
LON = CON = CS = LFB = CFB = LADJ =
LX Input Current 12 20 µA
CADJ = 0V, LX = BATT = 15V
TIMING (Note 2)
Reset Pulse Width (tR) 110 ns
Reset Setup Time (tRS) 0 ns
Reset Hold Time (tRH) 0 ns
CADJ, LADJ High Width (tSH) 100 ns
CADJ, LADJ Low Width (tSL) 100 ns
CADJ Low to CON Low or
50 ns
LADJ Low to LON Low (tSD)

Note 1: Maximum shutdown current occurs at BATT = LX = 0V.

Note 2: Timing specifications are guaranteed by design and not production tested.

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 CCFL Backlight and
LCD Contrast Controllers
______________________________________________________________Pin Description
MAX753/MAX754

PIN NAME FUNCTION

1 VDD 5V Power-Supply Input
2 LADJ Digital Input for LCD Backplane Bias Adjustment. See Table 1.
3 LON Digital Input to Control LCD Bias Section. See Table 1.
4 CON Digital Input to Control CCFT Section. See Table 1.
5 CADJ Digital Input for CCFT Brightness Adjustment. See Table 1.
6 GND Analog Ground
7 REF Reference Voltage Output, 1.25V
8 CFB Inverting Input for the CCFT Error Amplifier
9 CC Output of the CCFT Error Amplifier
10 CS Connect to VDD
11 CDRV Leave unconnected
12 PGND Power Ground Connection for LDRV
13 LDRV Gate-Driver Output. Drives LCD backplane N-channel MOSFET.
14 LX LCD Backplane Inductor Voltage-Sense Pin. Used to sense inductor voltage for on time determination.
15 BATT Battery Connection. Used to sense battery voltage for on time determination.
16 LFB Voltage Feedback for the LCD Backplane Section

_______________Theory of Operation D7B, and forms a voltage across resistor R8. The
MAX753’s error amplifier compares the average of this
CCFL Inverter voltage to the output of its internal DAC. Adjusting the
The MAX753/MAX754’s CCFL inverter is designed to DAC output from zero scale to full scale (digital control)
drive one or two cold-cathode fluorescent lamps causes the error amplifier to vary the tube current from
(CCFLs) with power levels from 100mW to 6W. These a minimum to a maximum. The DAC’s transfer function
lamps commonly provide backlighting for LCD panels is shown in Figure 2.
in portable computers. On power-up or after a reset, the counter sets the DAC
Drive Requirements for CCFL Tubes output to mid scale. Each rising edge of CADJ (with
CCFL backlights require a high-voltage, adjustable AC CON high) decrements the DAC output. When decre-
power source. The MAX753/MAX754 generate this AC mented beyond full scale, the counter rolls over and
waveform with a self-oscillating, current-fed, parallel sets the DAC to the maximum value. In this way, a sin-
resonant circuit, also known as a Royer-type oscillator. gle pulse applied to CADJ decreases the DAC set-
point by one step, and 31 pulses increase the set-point
Figure 1 shows one such circuit. The Royer oscillator is by one step.
comprised of T1, C9, the load at the secondary, Q4,
and Q5. The circuit self-oscillates at a frequency deter- The error amplifier’s output voltage controls the peak
mined by the effective primary inductance and capaci- current output of the MAX758A. The peak switch cur-
tance. Q4 and Q5 are self-driven by the extra winding. rent is therefore controlled by the output of the error
The current source feeding the Royer oscillator is com- amplifier. The lower the error amplifier’s output, the
prised of L1, D5, and the MAX758A. When current from lower the peak current. Since the current through the
the current source increases, so does the lamp current. current source is related to the current through the
tube, the lower the error amplifier’s output, the lower the
The lamp current is half-wave rectified by D7A and tube current.

4 _______________________________________________________________________________________
 CCFL Backlight and
LCD Contrast Controllers

MAX753/MAX754
+5V, ±5%
UNREGULATED INPUT VOLTAGE

10 15 1, 15, 16
CS BATT V+

1 2
VDD SHDN

D1B R16
C1 MAX754CSE D1A
3 10, 11
REF GND
4
CON C2 C3
5
CADJ +5V CMOS
LOGIC D5
3 CONTROL MAX758ACWE
LON
SIGNALS
2
LADJ R17
7 12, 13, 14
D2B SS LX
D2A
8
CC
R2
R1
Q2
11 Q1
CDRV L1

POSITIVE
CONTRAST
L2 VOLTAGE

14 D3
7 LX
REF D4
8 T1 12
C4
13 R5
LDRV 5 3,4 2 6 1
Q3
12 C10
PGND
R3 R10
CCFL

16
LFB R6 C9
Q5
R4 C6
C8
6 Q4 D7B
GND
D6A D7A
D6B
8 9
CFB CC

C7 R7
C5 R18 R8

Figure 1. CCFL and Positive LCD Power Supply

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 CCFL Backlight and
LCD Contrast Controllers
In Figure 1, the MAX758A, L1, and D5 form a voltage-
MAX753/MAX754

controlled switch-mode current source. The current out

1250 of L1 is proportional to the voltage applied to the SS
1221 pin. The MAX758A contains a current-mode pulse-
1191 width-modulating buck regulator that switches at
170kHz. The voltage on the SS pin sets the switch cur-
DAC OUTPUT VOLTAGE (mV)

811 rent limit and thus sets the current out of L1.
782
CCFL Current-Regulation Loop
753
Figure 3 shows a block diagram of the regulation loop,
which maintains a fixed CCFL average lamp current
despite changes in input voltage and lamp impedance.
This loop regulates the average value of the half-wave
402
rectified lamp current. The root mean square lamp cur-
372
rent is related to, but not equal to, the average lamp
343
current. Assuming a sinusoidal lamp current, select R8
as follows:
πVREF
0 1 2 3 14 15 16 29 30 31 R8 =
DAC CODE 2 ILAMP,RMS

where VREF = 1.25V and ILAMP,RMS is the desired full-

ZERO SCALE MID SCALE FULL SCALE scale root mean square lamp current.

Figure 2. CCFT DAC Transfer Function

CON CADJ

MAX754 LOGIC AND

5-BIT COUNTER MAX758A
SWITCH-MODE
FULL-SCALE = 1.250V SS VOLTAGE CONTROLLED
HALF-SCALE = 0.782V
CURRENT SOURCE
ZERO-SCALE = 0.343V
5-BIT VOLTAGE
OUTPUT DAC

IBUCK
ERROR CC
AMPLIFIER CENTER-TAP
ROYER
OSCILLATOR C10
CFB
CCFL

TRANSISTOR
EMITTERS
C5

R18
R8

Figure 3. CCFL Tube Current-Regulation Loop

6 _______________________________________________________________________________________
 CCFL Backlight and
LCD Contrast Controllers

MAX753/MAX754
VTAP(t)
C10

VTAP, PK
VSEC (t)

ILAMP(t) VLAMP(t) t

Figure 4. Simple Model of the CCFL Figure 5. Voltage at the Center Tap of T1

The minimum operating input voltage is determined by pulse-frequency-modulation (PFM) switching regulator.
the transformer turns ratio (n), the lamp operating volt- The MAX753 adds a simple diode-capacitor voltage
age (VLAMP), and the ballast capactor (C10). Using a inverter to the switching regulator.
simple model of the CCFL (see Figure 4) we can calcu-
late what the T1 center-tap voltage will be at maximum Constant-Current PFM Control Scheme
lamp current. The voltage on the CCFL is in phase with The LCD bias generators in these devices use a con-
the current through it. Let us define I LAMP (t) = stant-peak-current PFM control scheme. Figure 6, which
√2I LAMP,RMS cos(ωt) and V LAMP (t) = √2V LAMP,RMS shows the MAX754’s boost switching regulator, illus-
cos(ωt); then the peak voltage at the center tap will be trates this control method. When Q3 closes (Q3 “on”) a
as follows: voltage equal to BATT is applied to the inductor, caus-
ing current to flow from the battery, through the inductor
2 ILAMP,RMS
VTAP,PK = − and switch, and to ground. This current ramps up linear-
nωC10 sin(φ) ly, storing energy in the inductor’s magnetic field. When
where, Q3 opens, the inductor voltage reverses, and current
⎛ −ILAMP,RMS ⎞ flows from the battery, through the inductor and diode,
φ = tan −1⎜ ⎟ and into the output capacitor. The devices regulate the
⎝ ωC10VLAMP,RMS ⎠ , output voltage by varying how frequently the switch is
opened and closed.
n is the secondary-to-primary turns ratio of T1, and ω is
the frequency of Royer oscillation in radians per sec- The MAX753/MAX754 not only regulate the output volt-
ond. The voltage on the center tap of T1 is a full-wave age, but also maintain a constant peak inductor cur-
rectified sine wave (see Figure 5). The average voltage rent, regardless of the battery voltage. The ICs vary the
at VTAP must equal the average voltage at the LX node switch on-time to produce the constant peak current,
of the MAX758A, since there cannot be any DC voltage and vary its off-time to ensure that the inductor current
on inductor L1; thus the minimum operating voltage reaches zero at the end of each cycle.
must be greater than the average voltage at VTAP. The internal circuitry senses both the output voltage
and the voltage at the LX node, and turns on the MOS-
LCD Bias Generators FET only if: 1) The output voltage is out of regulation,
The MAX753/MAX754’s LCD bias generators provide and 2) the voltage at LX is less than the battery voltage.
adjustable output voltages for powering LCD displays. The first condition keeps the output in regulation, and
The MAX753’s LCD converter generates a negative the second ensures that the inductor current always
output, while the MAX754’s generates a positive output. resets to zero (i.e., the part always operates in discon-
The MAX753/MAX754 employ a constant-peak-current tinuous-conduction mode).

_______________________________________________________________________________________ 7
 CCFL Backlight and
LCD Contrast Controllers
MAX753/MAX754

BATTERY
INPUT
C2
10µF
+5V INPUT
L2
33µH
C1
0.22µF POSITIVE
D3 LCD-BIAS
2 3 1 15 14 1N5819 OUTPUT
LADJ LON VDD BATT LX

ON-TIME OFF-TIME LDRV 13 Q3 C6

LOGIC LOGIC 10µF
CONTROL ON/OFF R3 35V
PULSE-SKIP
COMPARATOR LFB 16
PRESET
6-BIT COUNTER
CLK R4
VDAC
MAX754 6-BIT DAC FULL-SCALE OUTPUT = 1.250V
HALF-SCALE OUTPUT = 0.938V
PGND GND ZERO-SCALE OUTPUT = 0.635V
12 6

Figure 6. MAX754 Positive LCD-Bias Generator

Table 1. CCFL Circuit Component Descriptions

ITEM DESCRIPTION

Integrating Capacitor. 1 / (C5 x R18) sets the dominant pole for the feedback loop, which regulates the lamp
current. Set the dominant pole at least two decades below the Royer frequency to eliminate the AC compo-
C5
nent of the voltage on R8. For example, if your Royer is oscillating at 50kHz = 314159rad/s, you should set
1 / (C5 x R18) ≤ 3142rad/s.

Integrating Resistor. The output source-current capability of the CC pin (50µA) limits how small R18 can be.
R18 Do not make R18 smaller than 70kΩ, otherwise CC will not be able to servo CFB to the DAC voltage (i.e., the
integrator will not be able to integrate) and the loop will not be able to regulate.

R8 converts the half-wave rectified lamp current into a voltage. The average voltage on R8 is not equal to the
R8 root mean square voltage on R8. The accuracy of R8 is important since it, along with the MAX754 reference,
sets the full-scale lamp current. Use a ±1%-accurate resistor.

D7A and D7B half-wave rectify the CCFL lamp current. Half-wave rectification of the lamp current and then
averaging is a simple way to perform AC-to-DC conversion. D7A and D7B’s forward voltage drop and speed
D7A, D7B
are unimportant; they do not need to pass currents larger than about 10mA, and their reverse breakdown
voltage can be as low as 10V.

The circuit of Figure 1, with the components shown in the bill of materials (Table 4), will drive a 500VRMS oper-
CCFL ating cold-cathode fluorescent lamp at 6W of power with a +12V input voltage. The lower the input voltage,
the less power the circuit can deliver.

8 _______________________________________________________________________________________
 CCFL Backlight and
LCD Contrast Controllers
Table 1. CCFL Circuit Component Descriptions (continued)

MAX753/MAX754
ITEM DESCRIPTION

The ballast capacitor linearizes the CCFL impedance and guarantees no DC current through the lamp. 15pF
will work with just about any lamp. Depending on the lamp, you can try higher values, but this may cause the
C10 regulation loop to become unstable. Larger values of C10 allow the circuit to operate with lower input volt-
ages. Don’t forget that C10 must be a high-voltage capacitor and cannot be polarized. A lamp with a
1500VRMS maximum strike voltage will require C10 to withstand 1500 x √2 = 2121V.

T1 must have high primary inductance (greater than 30µH), otherwise an inflated value of C9 will be required
T1 in order to keep the Royer frequency below 60kHz (the maximum allowed by most lamps). A higher T1 sec-
ondary-to-primary turns ratio allows lower-voltage operation, but increases the size of the transformer.

You must select a value for C9 high enough to keep the lamp current reasonably sinusoidal and yet low
enough that T1’s core does not saturate. For the Sumida EPS207 with a 171:1 turns ratio, choose a 0.22µF

LMAG
value for C9. The characteristic impedance of the resonant tank equals C9 , where LMAG is the mag-
C9 netizing inductance of T1. The characteristic impedance is defined as the ratio of the voltage across the par-
allel LC circuit divided by the current flowing between the inductor and capacitor. This circulating current is
not delivered to the load. If C9 has too large a value, it will cause excessive circulating currents, which will in
turn saturate the core of T1. It’s easy to tell when you have excess circulating current in the resonant tank,
because when you touch T1 you burn your finger. However, reducing the value of C9 decreases tank Q,
which increases the harmonic content of the lamp-current waveform. If the lamp-current waveform does not
look sinusoidal, then the circuit may not regulate to the right root mean square current.

R10 sets the base current for Q4 and Q5. If you choose too large a value for R10, Q4 and Q5 will overheat.
Too small a value will waste base current and slightly degrade efficiency. The optimal value will depend on
R10
how much power you are trying to deliver to the lamp. 510Ω is a good “always works but may not be the most
efficient” value for use with the FMMT619 transistors from ZETEX.
This resistive divider senses the voltage at the center tap of T1. When the CC pin on the MAX758A rises
R5, R6 above 1.25V, the internal switch turns off, interrupting power to the Royer oscillator and limiting the open-lamp
transformer center-tap voltage.
D6B, C7, and R7 form a soft-start clamp, which limits the rate-of-rise of the peak current in the MAX758A.
D6B, C7, R7
Make sure R7 is at least 100kΩ so it does not excessively load the CC pin.
D6A and R17 are also part of the soft-start clamp. The voltage on the SS pin controls the peak current in the
D6A, R17
MAX758A’s switch. Make sure R17 is at least 100kΩ so it does not excessively load the CC pin.
L1 Inductor for the Switching-Current Source. Use a 47µH to 150µH inductor with a 1A to 1.5A saturation current.
D5 Schottky Catch Diode. Use a 1A to 1.5A Schottky diode with low forward-voltage power.
C2 Supply Bypass Capacitor. Use low-ESR capacitor.

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 CCFL Backlight and
LCD Contrast Controllers
Table 2. CCFL Circuit Design Example (Note 1)
MAX753/MAX754

PARAMETER SYMBOL MIN TYP MAX UNITS

CCFL Specifications
Strike Voltage (VS) VS,RMS 1100 1500 VRMS
Discharging Tube Current (IL) ILAMP,RMS 0.001376 0.005 ARMS
Discharging Tube Voltage (VL) VLAMP,RMS 435 VRMS
LCD Contrast Voltage Specifications
Bias Voltage VLCD 16.3 32.6 V
Output Current ILCD 0.0245 A
Royer Specifications
T1 Turns Ratio (Sec/Pri) (Note 2) n 171
T1 Resonating Inductance (Note 2) LMAG 0.000045 H
C9 Value (Note 3) CRES 2.2E-07 F
C10 Value CBAL 1.5E-11 F
Royer Frequency w 317820.86 rad/s
MAX754 Specifications
Reference Voltage VREF 1.25 V
Second Volts Constant sV 0.000008 2.4E-05 sV
CCFL Circuit Calculations
R8 Current-Sensing Resistor R8 555.36037 Ω
Secondary Voltage Phase vs. Tube Voltage phi -1.1776341 Radian
T1 Center-Tap Peak Voltage VTAP,PK 9.3903817 VPEAK
Secondary Limit Voltage VLIM 1350 VRMS
T1 Center-Tap Limit Peak Voltage 11.164844 VPEAK
R5/R6 ROTP,RATIO 0.1341944 Ω/Ω
LCD Circuit Calculations
VIN(min) Full-Load Switching Period TFL 1.639E-06 s
L2 Inductance L2 1.96E-05 2.4E-05 H
L2 Peak Currrent 1.22704 A
R4/R3 RLCD,RATIO 0.0398724 Ω/Ω
Application Circuit Operating Range
Input Voltage VIN 5.978103 18 V
Note 1: To perform your own calculations for the parameters given in Table 2 (Design Example), use the equations given in Table
3 (Design Equations).
Note 2: T1 = Sumida’s EPS207
Note 3: C9 = Wima’s SMD 7.3 __/63

10 ______________________________________________________________________________________
 CCFL Backlight and
LCD Contrast Controllers
Table 3. Spreadsheet Design Equations

MAX753/MAX754
PARAMETER SYMBOL MIN TYP MAX
CCFL Specifications
Strike Voltage (VS) VS,RMS 1100 1500
= 0.28 *
Discharging Tube Current (IL) ILAMP,RMS 0.005
ILAMP,RMS(max)
Discharging Tube Voltage (VL) VLAMP,RMS 435
LCD Contrast Voltage Specifications
Bias Voltage VLCD = VLCD(max) / 2 32.6
Output Current ILCD 0.0245
Royer Specifications
T1 Turns Ratio (Sec/Pri) n 171
T1 Resonating Inductance LMAG 0.000045
C9 Value CRES 2.2E-07
C10 Value CBAL 1.5E-11
Royer Frequency w = SQRT [1 / (LMAG * CRES)]
MAX754 Specifications
Reference Voltage VREF 1.25
Second Volts Constant sV 0.000008 2.4E-05
CCFL Circuit Calculations
= PI() * VREF * SQRT(2) /
R8 Current-Sensing Resistor R8
(2 * ILAMP,RMS(max))
Secondary Voltage Phase vs. Tube = ATAN (-ILAMP,RMS(max) /
phi
Voltage (CBAL * w * + VLAMP,RMS)
= -SQRT(2) * ILAMP,RMS(max) /
T1 Center-Tap Peak Voltage VTAP,PK
(CBAL * w * SIN(phi)) / n
Secondary Limit Voltage VLIM = VS,RMS(max) * 0.9
T1 Center-Tap Limit Peak Voltage = SQRT(2) * VLIM / n
R5/R6 ROTP,RATIO = VREF / (D25 - 0.6 - VREF)
LCD Circuit Calculations
= sV(min) / VIN(min) + sV(min) /
VIN(min) Full-Load Switching Period TFL
(VLCD(max) - VIN(min))
= sV(min) ^ 2 / (2 * TFL *
L2 Inductance L2 = L2(max) * 0.8
VLCD(max) * ILCD(min))
L2 Peak Currrent = sV(max) / L2(min)
R4/R3 RLCD,RATIO = VREF / (VLCD(max) - VREF)
Application Circuit Operating Range
Input Voltage VIN = (2 / PI()) * VTAP,PK 18

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 CCFL Backlight and
LCD Contrast Controllers
Table 4. Bill of Materials
MAX753/MAX754

RESISTOR VALUE (Ω) TOLERANCE (%)

R1 100,000 ±10
R2 100,000 ±10
R3 1,000,000 ±1
R4 40,200 ±1
R5 100,000 ±1
R6 13,300 ±1
R7 100,000 ±10
R8 549 ±1
R10 680 ±5
R16 100,000 ±10
R17 100,000 ±10
R18 100,000 ±5

WORKING
CAPACITOR VALUE (µF) CHARACTERISTICS
VOLTAGE (V)
C1 0.1 6
C2 22 20 Low ESR
C3 0.1 20
C4 0.1 6
C5 0.01 6 Non-polarized
C6 10 50
C7 1 6
C8 1 30
C9 22 63
C10 1.5E-5 3000 High voltage

SURFACE-
OTHER BREAKDOWN GENERIC
MOUNT PART PACKAGE MANUFACTURER
COMPONENTS VOLTAGE (V) PART NO.
NUMBER
Q1 CMPTA06 SOT-23 80 MPSA06 Central Semi.
Q2 CMPT2907A SOT-23 60 2N2907 Central Semi.
Q3 MMFT3055ELT1 SOT-23 60 3055EL Motorola
Q4 FMMT619 SOT-23 50 Zetex
Q5 FMMT619 SOT-23 50 Zetex
D1A CMPD4150 SOT-23 75 1N4150 Central Semi.
D1B CMPD4150 SOT-23 75 1N4150 Central Semi.
D2A CMPD4150 SOT-23 75 1N4150 Central Semi.
D2B CMPD4150 SOT-23 75 1N4150 Central Semi.
D3 EC10QS05 D-64 50 1N5819 Nihon
D4 CMPD4150 SOT-23 75 1N4150 Central Semi.
D5 EC10QS02L D-64 20 1N5817 Nihon
D6A CMPD4150 SOT-23 75 1N4150 Central Semi.
D6B CMPD4150 SOT-23 75 1N4150 Central Semi.
D7A CMPD4150 SOT-23 75 1N4150 Central Semi.
D7B CMPD4150 SOT-23 75 1N4150 Central Semi.
Note: For T1, Use Sumida EPS207. Request No. USC-145, Special No. 6358-JP5-010.

12 ______________________________________________________________________________________
 CCFL Backlight and
LCD Contrast Controllers
Positive LCD Bias: MAX754

MAX753/MAX754
The voltage-regulation loop is comprised of resistors R3
and R4, the pulse-skip comparator, the internal DAC, 1250
the on-time and off-time logic, and the external power 1240
components. The comparator compares a fraction of 1230
the output voltage to the voltage generated by an on-

DAC OUTPUT VOLTAGE (mV)

chip 6-bit DAC. The part regulates by keeping the volt- 947
age at LFB equal to the DAC’s output voltage. Thus, 938
you can set the output to different voltages by varying 928
the DAC’s output.
Varying the DAC output voltage (digital control) adjusts
the external voltage from 50% to 100% of full scale. On
power-up or after a reset, the counter sets the DAC out- 655
put to mid scale. Each rising edge of LADJ (with LON 645
high) decrements the DAC output. When decremented 635
beyond zero scale, the counter rolls over and sets the
DAC to the maximum value. In this way, a single pulse
applied to LADJ decreases the DAC set point by one 0 1 2 30 31 32 61 62 63
step, and 63 pulses increase the set point by one step. DAC CODE

The MAX754’s DAC transfer function is shown in Figure 7.

The following equation relates the switching regulator’s ZERO SCALE MID SCALE FULL SCALE
regulated output voltage to the DAC’s voltage:
Figure 7. MAX754 LCD DAC Transfer Function
⎛ R3 ⎞
VOUT = VDAC ⎜1 + ⎟
⎝ R4 ⎠
hand side to -VHIGH. This voltage is more negative than
Table 5 is the logic table for the LADJ and LON inputs, the output, forcing D3 to conduct, and transferring
which control the internal DAC and counter. As long as the charge from the flying capacitor C15 to the output
timing specifications for LADJ and LON are observed, any capacitor C6. This charge transfer happens quickly,
sequence of operations can be implemented. resulting in a voltage spike at the output due to the
product of the output capacitor’s equivalent series
Negative LCD Bias: MAX753 resistance (ESR) and the current that flows from C15 to
The LCD bias generator of the MAX753 (Figure 8) gen- C6. To limit this drop, resistor R19 has been placed in
erates its negative output by combining the switching series with D3. R19 limits the rate of current flow. At the
regulator of the MAX754 with a simple diode-capacitor end of this cycle, the flying capacitor has been dis-
voltage inverter. To best understand the circuit, look at charged to 30V + Vd.
the part in a steady-state condition. Assume, for
If BATT(MAX) (i.e., either the fully charged battery volt-
instance, that the output is being regulated to -30V, and
age, or the wall-cube voltage) is greater than
that the battery voltage is +10V. When Q3 turns on, two
things occur: current ramps up in the inductor, just like
|VOUT(MIN)|, tie the cathode of D8 to BATT instead of
GND, as shown by the dashed lines in Figure 8.
with the boost converter; and the charge on C15 (trans-
Efficiency is lower with this method, so tie the cathode
ferred from the inductor on the previous cycle) is trans-
of D8 to GND whenever possible.
ferred to C6, boosting the negative output. At the end of
the cycle, the voltage on C15 is 30V + Vd, where Vd is The MAX753’s regulation loop is similar to that of the
the forward voltage drop of Schottky diode D3, and 30V MAX754. The MAX753, however, uses different power
is the magnitude of the output. components, and its feedback resistors are returned to
the reference (1.25V) rather than ground.
When the MOSFET turns off, the inductor’s energy is
transferred to capacitor C15, charging the capacitor to The MAX753’s PFM comparator compares a fraction of
a positive voltage (VHIGH) that is higher than |VOUT|. In the output voltage to the voltage generated by the on-
this instance, diode D8 allows current to flow from the chip 6-bit DAC. The part regulates by keeping the volt-
right-hand side of the flying capacitor (C15) to ground. age at LFB equal to the DAC’s output voltage. Thus,
you can set the LCD bias voltage to different voltages
When the MOSFET turns on, the left-hand side of
by varying the DAC’s output.
capacitor C15 is clamped to ground, forcing the right-

______________________________________________________________________________________ 13
 CCFL Backlight and
LCD Contrast Controllers
Table 5. Logic-Signal Truth Table
MAX753/MAX754

CCF CONTROL
LON LADJ CON CADJ CCFT STATUS CCFT DAC
X X 0 0 Off Hold
X X 0 1 On Reset
X X 1 0 On Hold
X X 1 0→1 On Dec
LCD BIAS CONTROL
LON LADJ CON CADJ LCD STATUS LCD DAC
0 0 X X Off Hold
0 1 X X On Reset
1 0 X X On Hold
1 0→1 X X On Dec

Hold = maintain last DAC value in counter

Reset = set DAC counter to half scale
Dec = decrement DAC counter one step
Off = section turned off, sleep state
On = section turned on
X = don’t care

Table 6. Component Suppliers

MANUFACTURER ADDRESS PHONE FAX
145 Adams Ave.
Central Semiconductor (516) 435-1110 (516) 435-1824
Hauppauge, NY 11788
6000 Park of Commerce Blvd.
Coiltronics (407) 241-7876 (407) 241-9339
Boca Raton, FL 33287
120 San Gabriel Dr.
Maxim (408) 737-7600 (408) 470-5841
Sunnyvale, CA 94025
c/o Quantum Marketing
Nihon (NIEC)* 12900 Rolling Oaks Rd. (805) 867-2555 (805) 867-2698
Twin Oaks, CA 93518
5999 New Wilke Rd., Suite 110
Sumida (708) 956-0666 (708) 956-0702
Rolling Meadows, IL 60008
2269 Saw Mill River Rd., Suite 400
Wima P.O. Box 217 (914) 347-2474 (914) 347-7230
Elmsford, NY 10523
87 Modular Ave.
Zetex (516) 543-7100 (516) 864-7630
Commack, NY 11725

* Contact John D. Deith, ask for “Maxim Discount” on orders less than 5k units.

14 ______________________________________________________________________________________
 CCFL Backlight and
LCD Contrast Controllers

MAX753/MAX754
BATTERY
INPUT ALTERNATE
D8 CONNECTION
C2 (SEE TEXT)
+5V INPUT 10µF
L2
33µH
C1
0.22µF NEGATIVE
C15 R19 D3
1µF LCD-BIAS
2 3 1 15 14 2.2Ω 1N5819 OUTPUT
LADJ LON VDD BATT LX
D8
ON-TIME OFF-TIME LDRV 13 1N5819
Q3 C6
LOGIC LOGIC 10µF
R3
CONTROL ON/OFF 35V
PULSE-SKIP
COMPARATOR LFB 16 VDD
PRESET
6-BIT COUNTER
R4
CLK
VDAC

MAX753 6-BIT DAC

7
REF
PGND GND
C4
12 6 0.22µF

Figure 8. MAX753 Negative LCD-Bias Generator

The MAX753’s DAC transfer function is shown in Figure 9.

The following equation relates the switching regulator’s
1240 regulated output voltage to the DAC’s voltage (REF - LFB):
⎛ R3 ⎞
( )
1230
1220 VOUT = REF − ⎜1 + ⎟ REF − LFB
⎝ R4 ⎠
DAC OUTPUT VOLTAGE (mV)*

937 The value REF - LFB (and not LFB) is specified in the
928 Electrical Characteristics. The most negative output
918 voltage occurs for the largest value of REF - LFB.
The MAX753’s combination boost converter and
charge-pump inverter was chosen over a conventional
buck-boost inverter because it allows the use of low-
645
cost N-channel MOSFETs instead of more expensive P-
635
channel ones. Additionally, its efficiency is 5% to 10%
625
better than a standard buck-boost inverter.

0 1 2 30 31 32 61 62 63
DAC CODE

ZERO SCALE MID SCALE FULL SCALE

* DAC OUTPUT VOLTAGE = REF - LFB

Figure 9. MAX753 LCD DAC Transfer Function

______________________________________________________________________________________ 15
 CCFL Backlight and
LCD Contrast Controllers
_____________________Block Diagram ___________________Chip Topography
MAX753/MAX754

V DD BATT
2 3 15 14 LFB LX
LADJ LON BATT LX
LADJ
LDRV 13
ON-TIME OFF-TIME
CONTROL
LOGIC LOGIC LON

CON
CLK PRESET LDRV
PULSE-SKIP CADJ
6-BIT LFB 16
COMPARATOR
COUNTER 0.112"
PGND (2.845mm)

CDRV
6-BIT 1
D/A CONVERTER VDD

MAX753/MAX754 7
REF GND
5-BIT
D/A CONVERTER ERROR 11
AMPLIFIER CDRV
REF CC
5-BIT CFB CS
CFB 8
COUNTER 0.076"
CLK PRESET CC 9
(1.930mm)
CS 10
LOGIC
TRANSISTOR COUNT: 321;
CONTROL
REF
SUBSTRATE CONNECTED TO VDD.

CON CADJ PGND GND

4 5 12 6

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600

© 1995 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products.