HX8394 F PDF

( DOC No.
HX8394-F-DS )
HX8394-F
720RGB x 1280 dots, 16.7M color
TFT Mobile Single Chip Driver
Preliminary Version 01 December, 2014
HX8394-F
720RGB x 1280 dots, 16.7M color,
Revision History December, 2014

Version Date Description of changes
01 2014/09/03 1. New setup.
01 2014/12/02 1. Modified B2h description typo.
Himax Confidential - P.2-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. December,
2014
HX8394-F
List of Contents December, 2014
1. GENERAL DESCRIPTION .......................................................................................11

2. FEATURES ...............................................................................................................12
2.1 Display ...........................................................................................................................................12
2.2 Display module...............................................................................................................................12
2.3 DC/DC booster...............................................................................................................................13
2.4 Display / Control interface..............................................................................................................13
2.5 Input power ....................................................................................................................................13
2.6 Miscellaneous ................................................................................................................................13
3. DEVICE OVERVIEW.................................................................................................14
3.1 Block diagram ................................................................................................................................14
3.2 Pin description................................................................................................................................15
4. INTERFACE ..............................................................................................................18
4.1 System interface ............................................................................................................................18
4.1.1Serial data transfer interface(MIPI DBI type C) .....................................................................18
4.1.2Serial data write mode ...........................................................................................................19
4.1.3Serial data read mode ...........................................................................................................20
4.2 DSI system interface......................................................................................................................21
4.2.1DSI layer definitions...............................................................................................................22
4.2.2Lane states ............................................................................................................................23
4.2.3Clock lane mode ....................................................................................................................24
4.2.4Data lane mode .....................................................................................................................26
4.2.5Escape mode.........................................................................................................................27
4.2.6High speed data transmission ...............................................................................................29
4.2.7Bi-directional data lane turnaround........................................................................................32
4.2.8DSI protocol ...........................................................................................................................33
4.2.9Processor to peripheral (forward direction) packets data types ............................................36
4.2.10Peripheral to processor (reverse direction) packet data type..............................................43
5. FUNCTION DESCRIPTION ......................................................................................45
5.1 Tearing effect output line ................................................................................................................45
5.1.1Tearing effect line timing ........................................................................................................47
5.2 Oscillator ........................................................................................................................................48
5.3 Source driver..................................................................................................................................49
5.3.1Zig-Zag inversion ...................................................................................................................50
5.4 LCD power generation scheme .....................................................................................................52
5.5 DC/DC converter circuit .................................................................................................................53
5.5.1Charge pump and step up circuit mode.................................................................................53
5.5.2Use external VSP,VSN,VGH,VGL circuit ...............................................................................54
5.5.3Use PFM DC/DC converter ...................................................................................................55
5.5.4Use HX5186-A/B/C................................................................................................................58
5.5.5Use external VSP,VSN circuit ................................................................................................59
5.6 8-color Idle display mode ...............................................................................................................60
5.7 1-bit GRAM Idle Display Mode.......................................................................................................61
5.8 Gamma characteristic correction function .....................................................................................62
5.8.1Gamma-characteristics adjustment register ..........................................................................64
5.8.2Gray voltage generator for digital gamma correction ............................................................80
5.9 Characteristics of I/O .....................................................................................................................82
5.9.1Output or bi-directional (I/O) pins ..........................................................................................82
5.9.2Input pins ...............................................................................................................................82
5.10 GIP control singal...........................................................................................................................83
in whole or in part without prior written permission of Himax. December, 2014
5.11 Sleep Out –command and self-diagnostic functions of the display module ..................................84
5.11.1Register loading detection ...................................................................................................84
5.11.2Functionality detection .........................................................................................................85
5.12 Power on/off sequence ..................................................................................................................86
5.12.1VDD1/VDD3 input power sequence (PCCS[1:0]=”01”, “10”)...............................................87
5.12.2VDD1/VSP/VSN input power sequence (PCCS[1:0]=”11”) .................................................88
5.13 Uncontrolled power off ...................................................................................................................89
5.14 Content adaptive brightness control (CABC) function ...................................................................90
5.14.1Module architectures ...........................................................................................................91
5.14.2CABC block .........................................................................................................................92
5.14.3Brightness control block ......................................................................................................93
5.14.4Minimum brightness setting of CABC function ....................................................................94
5.15 Temperature sensor .......................................................................................................................95
5.16 OTP programming..........................................................................................................................96
5.16.1OTP table.............................................................................................................................96
5.16.2OTP programming flow......................................................................................................108
5.16.3Programming sequence ....................................................................................................109
5.16.4OTP programming example of VCOM setting VCMC .......................................................110
5.16.5OTP programming example of ID1, ID2 and ID3 .............................................................. 111
5.16.6OTP read example of 0x00h (ID1).....................................................................................112
5.17 FRM (Free running mode) ...........................................................................................................113
5.18 Command list ...............................................................................................................................114
5.18.1Standard command............................................................................................................114
5.18.2User define command list table .........................................................................................116
5.18.3NOP (00h)..........................................................................................................................125
5.18.4Software reset (01h) ..........................................................................................................126
5.18.5Read Display Identification Information (04h) ...................................................................127
5.18.6RDNUMPE: Read number of the parity errors (05h).........................................................128
5.18.7Get_red_channel (06h)......................................................................................................129
5.18.8Get_green_channel (07h)..................................................................................................130
5.18.9Get_blue_channel (08h) ....................................................................................................131
5.18.10Read Display Status (09h) ...............................................................................................132
5.18.11Get_power_mode (0Ah)...................................................................................................136
5.18.12Read display MADCTL (0Bh) ..........................................................................................138
5.18.13Get_pixel_format (0Ch) ...................................................................................................140
5.18.14Get_display_mode (0Dh).................................................................................................142
5.18.15Get_signal_mode (0Eh)...................................................................................................144
5.18.16Get_diagnostic_result (0Fh) ............................................................................................145
5.18.17Enter_sleep_mode (10h) .................................................................................................146
5.18.18Exit_sleep_omde (11h) ....................................................................................................147
5.18.19Enter_normal_mode (13h)...............................................................................................148
5.18.20Exit_inversion_mode (20h)..............................................................................................149
5.18.21Enter_inversion_mode (21h) ...........................................................................................150
5.18.22All_Pixel_Off (22h)...........................................................................................................151
5.18.23All_Pixel_On (23h)...........................................................................................................152
5.18.24Set_gamma_curve (26h) .................................................................................................153
5.18.25Set_display_off (28h).......................................................................................................154
5.18.26Set_display_on (29h).......................................................................................................155
5.18.27Write_memory_start (2Ch) ..............................................................................................156
5.18.28Tearing effect line off (34h) ..............................................................................................157
5.18.29Set_tear_on (35h)............................................................................................................158
5.18.30Set_address_mode (36h) ................................................................................................159
5.18.31Idle mode off (38h)...........................................................................................................161
5.18.32Enter_Idle_mode (39h) ....................................................................................................162
5.18.33Set_pixel_format (3Ah) ....................................................................................................163
5.18.34Write_memory_contiune (3Ch)........................................................................................164
5.18.35Set tear scan lines (44h)..................................................................................................165
5.18.36Get the current scanline(45h) ..........................................................................................166
5.18.37Write display brightness (51h) .........................................................................................167
5.18.38Read display brightness value (52h) ...............................................................................168
5.18.39Write CTRL display (53h) ................................................................................................169
5.18.40Read CTRL value display (54h) ......................................................................................170
5.18.41Write content adaptive brightness control (55h) ..............................................................171
5.18.42Read content adaptive brightness control (56h)..............................................................172
5.18.43Write CABC minimum brightness (5Eh) ..........................................................................173
5.18.44Read CABC minimum brightness (5Fh) ..........................................................................174
5.18.45Read automatic brightness control self-diagnostic result (68h) ......................................175
5.18.46Write Idle Mode Color(80h) .............................................................................................176
5.18.47176
5.18.48Read Idle Mode Color(81h) .............................................................................................177
5.18.49Read_DDB_start (A1h)....................................................................................................178
5.18.50Read_DDB_continue (A8h) .............................................................................................180
5.18.51Read ID1 (DAh) ...............................................................................................................181
5.18.52Read ID2 (DBh) ...............................................................................................................182
5.18.53Read ID3 (DCh) ...............................................................................................................183
5.19 User define command description ...............................................................................................184
5.19.1SETSEQUENCE: Set sequence (B0h) .............................................................................184
5.19.2SETPOWER: Set power (B1h) ..........................................................................................186
5.19.3SETDISP: Set display related register (B2h).....................................................................196
5.19.4SETCYC: Set display waveform cycles (B4h)...................................................................199
5.19.5SETVCOM: Set VCOM voltage (B6h) ...............................................................................204
5.19.6SETTE: Set internal TE function (B7h)..............................................................................205
5.19.7SETSENSOR: Set temperature sensor (B8h) ...................................................................207
5.19.8SETEXTC: Set extension command (B9h) .......................................................................208
5.19.9SETMIPI: Set MIPI control (BAh) ......................................................................................209
5.19.10SETOTP: Set OTP (BBh) ................................................................................................211
5.19.11Set register bank (BDh) ...................................................................................................213
5.19.12SETDGCLUT: Set DGC LUT (C1h) .................................................................................214
5.19.13SETID: Set ID (C3h) ........................................................................................................218
5.19.14SETDDB: Set DDB (C4h) ................................................................................................219
5.19.15SETCABC: Set CABC control (C9h) ...............................................................................220
5.19.16SETCABCGAIN (CAh) ....................................................................................................222
5.19.17SETPANEL (CCh)............................................................................................................223
5.19.18SETOFFSET (D2h)..........................................................................................................224
5.19.19SETGIP0: Set GIP Option0 (D3h) ...................................................................................225
5.19.20Set GIP Option1 (D5h).....................................................................................................230
5.19.21Set GIP Option2 (D6h).....................................................................................................233
5.19.22SETGPO (D9h)................................................................................................................237
5.19.23SETSCALING (DDh) .......................................................................................................238
5.19.24SETIDLE (DFh)................................................................................................................239
5.19.25SETGAMMA: Set gamma curve related setting (E0h) ....................................................242
5.19.26SETCHEMODE_DYN (E4h)............................................................................................244
5.19.27SETCHE (E5h) ................................................................................................................245
5.19.28SETCESEL: Enable color enhance (E6h) .......................................................................247
5.19.29SET_SP_CMD (E9h) .......................................................................................................249
5.19.30SETREADINDEX: Set SPI Read Index (FEh) .................................................................250
5.19.31GETSPIREAD: SPI Read Command Data (FFh) ............................................................251
6. LAYOUT RECOMMENDATION ..............................................................................252
6.1 Maximum layout resistance .........................................................................................................252
6.2 External components connection.................................................................................................253
7. ELECTRICAL CHARACTERISTICS.......................................................................259
7.1 Absolute maximum ratings...........................................................................................................259
7.2 DC characteristics ........................................................................................................................260
7.3 AC characteristics ........................................................................................................................261
7.3.1DBI Type C interface characteristics ...................................................................................261
7.3.2DSI D-PHY electrical characteristics ...................................................................................262
7.3.3Timings for DSI video mode ................................................................................................270
8. ORDERING INFORMATION ...................................................................................272

HX8394-F
720RGB x 1280 dot, 16.7M color,
List of Figures December, 2014

Figure 4.1: Serial data stream, write mode .................................................................................... 19
Figure 4.2: Serial data stream, write mode .................................................................................... 19
Figure 4.3: Type C:Serial interface protocol 3-wire/4-wire read mode........................................... 20
Figure 4.4: Display module data transfer recovery ........................................................................ 20
Figure 4.5: DSI transmitter and receiver interface ......................................................................... 21
Figure 4.6: DSI transmitter and receiver interface ......................................................................... 22
Figure 4.7: Clock lane mode state diagram ................................................................................... 24
Figure 4.8: Data lane mode state diagram ..................................................................................... 26
Figure 4.9: Escape mode state machine........................................................................................ 27
Figure 4.10: Escape mode timing sequence.................................................................................. 28
Figure 4.11: High speed data transmission state machine ............................................................ 29
Figure 4.12: High speed data transmission timing sequence ........................................................ 29
Figure 4.13: Switching the Clock Lane between Clock Transmission and LP Mode..................... 30
Figure 4.14: Turnaround state machine ......................................................................................... 32
Figure 4.15: Turnaround timing sequence ..................................................................................... 32
Figure 4.16: Multiple packets transmission .................................................................................... 33
Figure 4.17: Structure of the short packet ...................................................................................... 33
Figure 4.18: Structure of the long packet ....................................................................................... 34
Figure 4.19: The format of data ID ................................................................................................. 34
Figure 4.20: Show short- / long-packet transmission command sequence ................................... 35
Figure 5.1: Tearing effect output signal mode 1 ............................................................................. 45
Figure 5.2: TE delay output ............................................................................................................ 45
Figure 5.3: Tearing Effect Output signal mode 2 ........................................................................... 46
Figure 5.4: TE Output for TELINE setting ...................................................................................... 46
Figure 5.5: Tearing Effect Output signal ........................................................................................ 46
Figure 5.6: Tearing effect output line –tearing effect line timing..................................................... 47
Figure 5.7: Tearing effect output line–definition of tf, tr .................................................................. 47
Figure 5.8: OSC architecture.......................................................................................................... 48
Figure 5.9: Zig-Zag inversion mode(ZZ_2PL=0)............................................................................ 50
Figure 5.10: Zig-Zag2 Inversion mode(ZZ_2PL=1)........................................................................ 51
Figure 5.11: LCD power generation scheme for HX5186 and PFM mode .................................... 52
Figure 5.12: LCD power generation scheme for external power mode ......................................... 52
Figure 5.17: DC/DC converter circuit of external VSP/VSN/VGH/VGL ......................................... 54
Figure 5.13: DC/DC converter circuit (PFM type D)....................................................................... 55
Figure 5.14: DC/DC converter circuit (PFM type A) ....................................................................... 56
Figure 5.15: DC/DC converter circuit (PFM type C)....................................................................... 57
Figure 5.16: DC/DC converter circuit of HX5186-A/B/C ................................................................ 58
Figure 5.17: DC/DC converter circuit of external VSP/VSN........................................................... 59
Figure 5.18: Idle mode grayscale control ....................................................................................... 60
Figure 5.19: Idle Mode On/Off Sequence ...................................................................................... 61
Figure 5.20: Gamma adjustments different of source driver with digital gamma correction .......... 62
Figure 5.21: Grayscale control ....................................................................................................... 63
Figure 5.22: Gamma resister stream and gamma reference voltage ............................................ 65
Figure 5.23: Block diagram of digital gamma correction................................................................ 80
Figure 5.24: Sleep out flow chart–command and self-diagnostic functions................................... 84
Figure 5.25: Sleep out flow chart internal function detection ......................................................... 85
Figure 5.26: Power on/off sequence .............................................................................................. 86
Figure 5.27: VDD1/VDD3 input power on sequence ..................................................................... 87
Figure 5.28: VDD1/VDD3 input power off sequence...................................................................... 87
Figure 5.29: VDD1/ VSP/VSN input power on sequence .............................................................. 88
Figure 5.30: VDD1/VSP/VSN input power off sequence ............................................................... 88
Figure 5.31: CABC block diagram.................................................................................................. 90
Figure 5.32: Module architecture ................................................................................................... 91
Figure 5.33: CABC gain / CABC duty generation .......................................................................... 92
Figure 5.34: CABC_PWM_OUT output duty.................................................................................. 93
Figure 5.35: Tempeture sensor diagram ........................................................................................ 95
Figure 5.36: OTP programming sequence................................................................................... 108
Figure 5.37: OTP programming sequence example 1 ..................................................................110
Figure 5.38: OTP programming sequence example 2 .................................................................. 111
Figure 5.39: OTP read sequence flow of index 0x00h ..................................................................112
Figure 5.40: FRM power on sequence..........................................................................................113
Figure 5.41: Display pattern sequence example in FRM ..............................................................113
Figure 7.1: DBI Type C interface characteristics.......................................................................... 261
Figure 7.2: Electrical functions of a fully D-PHY transceiver........................................................ 262
Figure 7.3: Shows both the HS and LP signal levels ................................................................... 262
Figure 7.4: Differential HS signals for HS receiver....................................................................... 264
Figure 7.5: Input glitch rejections of low-power receivers ............................................................ 265
Figure 7.6: DDR clock definition................................................................................................... 267
Figure 7.7: Data to clock timing definitions .................................................................................. 268
Figure 7.8: Skew window of transmittor and receiver .................................................................. 269
Figure 7.9: Vertical timings for DSI I/F ......................................................................................... 270
Figure 7.10: Horizontal timing for DSI video mode I/F ................................................................. 271

HX8394-F
List of Tables December, 2014

Table 4.1: Interface selection ......................................................................................................... 18
Table 4.2: Global Operation Timing Parameters for Data Lane ..................................................... 30
Table 4.3: Global Operation Timing Parameters for Clock Lane.................................................... 31
Table 4.4: Data types for processor-sourced packets .................................................................... 36
Table 4.5: Shows the error report bit definitions............................................................................. 44
Table 4.6: The complete set of peripheral-to-processor data types ............................................... 44
Table 5.1: AC characteristics of tearing effect signal ..................................................................... 47
Table 5.2: Source output for Panel resolution........................................................................... 49
Table 5.3: Power mode setting ....................................................................................................... 53
Table 5.4: Gamma-adjustment registers ........................................................................................ 64
Table 5.5: Edge adjustment 0~7, 21~28 ........................................................................................ 66
Table 5.6: Center adjustment 8~20 ................................................................................................ 66
Table 5.7: VinP0 ............................................................................................................................. 67
Table 5.8: VinP1 ............................................................................................................................. 67
Table 5.9: VinP3 ............................................................................................................................. 67
Table 5.10: VinP5 ........................................................................................................................... 68
Table 5.11: VinP7 ........................................................................................................................... 68
Table 5.12: VinP9 ........................................................................................................................... 68
Table 5.13: VinP12 ......................................................................................................................... 69
Table 5.14: VinP15 ......................................................................................................................... 69
Table 5.15: VinP20 ......................................................................................................................... 69
Table 5.16: VinP28 ......................................................................................................................... 70
Table 5.17: VinP40 ......................................................................................................................... 70
Table 5.18: VinP52 ......................................................................................................................... 70
Table 5.19: VinP76 ......................................................................................................................... 71
Table 5.20: VinP100 ....................................................................................................................... 71
Table 5.21: VinP128 ....................................................................................................................... 71
Table 5.22: VinP156 ....................................................................................................................... 72
Table 5.23: VinP180 ....................................................................................................................... 72
Table 5.24: VinP204 ....................................................................................................................... 72
Table 5.25: VinP216 ....................................................................................................................... 73
Table 5.26: VinP228 ....................................................................................................................... 73
Table 5.27: VinP236 ....................................................................................................................... 73
Table 5.28: VinP240 ....................................................................................................................... 74
Table 5.29: VinP243 ....................................................................................................................... 74
Table 5.30: VinP246 ....................................................................................................................... 74
Table 5.31: VinP248 ....................................................................................................................... 75
Table 5.32: VinP250 ....................................................................................................................... 75
Table 5.33: VinP252 ....................................................................................................................... 75
Table 5.34: VinP254 ....................................................................................................................... 76
Table 5.35: VinP255 ....................................................................................................................... 76
Table 5.36: Voltage calculation formula of 256-grayscale voltage (positive/negative polarity) ...... 79
Table 5.37: DGC Look-up table...................................................................................................... 81
Table 5.38: Characteristics of output or bi-directional (I/O) pins .................................................... 82
Table 5.39: Characteristics of input pins ........................................................................................ 82
Table 5.40: CABC timing table ....................................................................................................... 93
Table 5.41: OTP table................................................................................................................... 107
Table 5.42: OTP programming sequence .................................................................................... 109
Table 6.1: Maximum layout resistance ......................................................................................... 252
Table 6.2: HX5186-A/B/C mode external components ................................................................ 253
Table 6.3: PFM type A external components................................................................................ 254
Table 6.4: PFM type C external components ............................................................................... 255
Table 6.5: PFM type D external components ............................................................................... 256
Table 6.6: External VDD1 / VSP / VSN / VGH / VGL external components................................. 257
Table 6.7: External VDD1 / VSP / VSN external components...................................................... 258
Table 7.1: Absolute maximum rating ............................................................................................ 259
Table 7.2: DC characteristic ......................................................................................................... 260
Table 7.3: DBI Type C interface characteristics ........................................................................... 261
Table 7.4: LP transmitter DC specifications ................................................................................. 263
Table 7.5: LP transmitter AC specifications.................................................................................. 263
Table 7.6: HS receiver DC Specifications..................................................................................... 264
Table 7.7: HS receiver AC Specifications ..................................................................................... 264
Table 7.8: LP receiver DC specifications...................................................................................... 265
Table 7.9: LP receiver AC specifications ...................................................................................... 265
Table 7.10: Contention detector DC specifications ...................................................................... 266
Table 7.11: Reverse HS data transmission timing parameters .................................................... 268
Table 7.12: Data to clock timing specifications............................................................................. 269
Table 7.13: Vertical timings for DSI I/F ......................................................................................... 270
Table 7.14: Horizontal timings for DSI video mode I/F ................................................................. 271

HX8394-F
Preliminary Version 01 December, 2014
1. General Description
This document describes Himax’s HX8394-F supports WXGA resolution driving
controller. The HX8394-F is designed to provide a single-chip solution that combines
source driver control, gate driver control and power supply circuit to drive a TFT dot
matrix LCD with 720RGB x 1280 dots at maximum.
The HX8394-F can be operated in low-voltage condition for the interface and
integrated internal boosters that produce the liquid crystal voltage, breeder resistance
and the voltage follower circuit for liquid crystal driver. In addition, The HX8394-F also
supports various functions to reduce the power consumption of a LCD system via
software control.
The HX8394-F supports several interface modes, including MIPI DBI Type C
interface mode and MIPI DSI (Display Serial Interface) interface mode.
The HX8394-F is suitable for any small portable battery-driven and long-term driving
products, such as cellular phones, tablet and other mobile devices.

in whole or in part without prior written permission of Himax. December,
2014
HX8394-F
720RGBx1280dots, TFT Mobile Single Chip Driver
Preliminary DATA SHEET V01
2. Features
2.1 Display
Single chip solution for a WXGA type TFT LCD display

Resolution:
720RGB x (480 + (8 x NL))
640RGB x (480 + (8 x NL))
600RGB x (480 + (8 x NL))
Display color modes
Full color mode:
16.7M colours (24-bit 8(R):8(G):8(B))
Reduce color mode:
262k colours (18-bit 6(R):6(G):6(B))
65k colours (16-bit 5(R):6(G):5(B))
8 colors (Idle mode on): 8 colors (3-bit binary mode)
2.2 Display module
Support 2162 source channel outputs

Gate driver control signals for GIP
Support 1-dot / 2-dot / 4-dot / 8-dot / Zig-Zag / Zig-Zag2/Column inversion
Output voltage level
Positive source output voltage level: VSPR to VSSA
Negative source output voltage level: VSNR to VSSA
Positive gate driver output voltage level: VGH to VSSA
Negative gate driver output voltage level: VGL to VSSA
VCOM= -4V ~ -0.3V, each step=10mV

HX8394-F
2.3 DC/DC booster
External charge pump: support HX5186-C mode

PFM booster: support type A/C/D
External power mode:
1. VSP+VSN+VDD1
2. VSP+VSN+VGH+VGL+VDD1
2.4 Display / Control interface
Display interface types supported

MIPI-DSI (Display Serial Interface) interface
Support DSI Version 1.1
Support D-PHY version 1.1
2.5 Input power
Logic and interface power supply (VDD1): 1.65V to 3.6V

Analog power supply (VDD3): 2.5V to 3.6V
For PCCS[1:0]=10, VDD3 range is 2.5V ~ 3.6V
For PCCS[1:0]=00, 01 and 11, no VDD3 is needed
Positive source driver power (External input mode VSP): 4.3V to 6.5V
Negative source driver power (External input mode VSN): -4.3V to -6.5V
High speed interface power supply (HS_VCC): 1.65V to 3.6V
OTP programming voltage (VPP): 7.5V ± 0.2V
VGH,VGL: VGH-VGL<32V
2.6 Miscellaneous
Software programmable color depth mode

Oscillator for display clock generation
Low power consumption, suitable for battery operated systems
Smart source EQ for power saving
GAS function for preventing image sticking when abnormal power off
Optimized layout for COG assembly
Operation temperature range: -40 to +85 °C
Support DC COM driving
On-chip OTP program voltage generator
Support CABC (Content Adaptive Brightness Control) function
Support DGC (Digital Gamma Correction) function
Support CE (Color Enhancement) function
Support Scaling function
FWVGA(480RGBx854) to HD(720RGBx1280).
qHD(540RGBx960) to HD(720RGBx1280).
Support Temperature sensor function
Build in Free Funning Mode function(Internal BIST pattern generator)
Idle mode 1-bit GRAM
OTP memory to store initialization register settings
OTP memory to store 2 sets of Gamma and DGC setting
3 times MTP for VCOM setting, ID setting

HX8394-F
3. Device Overview
3.1 Block diagram
CABC_PWM_OUT S1 ~ S2160,SL1,SR1
VDD1
VPP OTP
BS[2:0]
3
RESX
Source driver
CSX
DCX Internal ABC function
SCL register
SDI
D/A Converter circuit
SDO Internal CABC function
Test
function
DGC function
Data Latch
V0~255
Color enhancement
function
Grayscale voltage
HS_CP / N 2 generator VSSAC
HS_D0P / N
2 Scaling/
HS_D1P / N one-bit GRAM
2
HS_D2P / N 24-bit display data FRM FRM
2 2
HS_D3P / N
2
DSI Gamma adjusting circuit VTESTOUTP /
Interface VTESTOUTN
2
TE / TE1
Timing
HS_VCC Control CGOUT_L 1/ R1
HS_VSS CGOUT_L2 / R2
Temperature CGOUT_L3 / R3
PCCS[1:0] sensor CGOUT_L4/ R4
Gate CGOUT_L5/ R5
TS[7:0] Control CGOUT_L6 / R6
Generator Unit CGOUT_L7 / R7
OSC RC OSC 44
Timing CGOUT_L8 / R8
CGOUT_L9 / R9
TEST[2:0]
CGOUT_L10 / R10
VDD3 CGOUT_L11 / R11
VCOM CGOUT_L12 / R12
DC / DC Converter Voltage reference
VSSA Cricuit CGOUT_L13 / R13
CGOUT_L14 / R14
VSSD CGOUT_L15 / R15
CGOUT_L16 / R16
CGOUT_L17 / R17
CGOUT_L18 / R18
VSNR
HS_LDO
VSN
C21P / C21N
C22P / C22N
VSPR
VSP
VCSW1
VCSW2
VCOM
V GH
C41P / C41N
VDDD
VREF
C31P / C31N
V GL
VCL
CGOUT_L19 / R19
CGOUT_L20 / R20
CGOUT_L21 / R21
CGOUT_L22 / R22

HX8394-F
3.2 Pin description
Host interface pins
Signals I/O Pin no. Connected Description
These pins must be connected to VDD1(logic=1) or VSSD(logic=0).
BS2 ~ BS0 are used for the combination of polarity swap and data lane
swap of DSI.
BS[2:0] HS_D0N HS_D0P HS_D1N HS_D1P HS_CN HS_CP HS_D2N HS_D2P HS_D3N HS_D3P
“000” D3N D3P D2N D2P CN CP D1N D1P D0N D0P
VSSD /
BS2 ~ BS0 I 6 “001” D3P D3N D2P D2N CP CN D1P D1N D0P D0N
VDD1 ”010” D0N D0P D1N D1P CN CP D2N D2P D3N D3P
”011” D0P D0N D1P D1N CP CN D2P D2N D3P D3N
”100” D2N D2P D1N D1P CN CP D0N D0P D3N D3P
Chip select signal. For test only.

Low: Chip can be accessed;
CSX I 2 MPU
High: Chip cannot be accessed.
If this pin is not used, connect it to VDD1 or VSSD .
Data / Command Selection pin. For test only.
DCX I 2 MPU
MPU or Reset pin. Setting either pin low initializes the LSI. It must be reset after
RESX I 4
reset circuit power is supplied.
Serial Clock. For test only.
SCL I 2 MPU
SDI I 2 MPU Serial data input pin. If not used, let it to open. For test only.
SDO O 2 MPU Serial data output pin. If not used, let it to open. For test only.
Line synchronizing signal. For test only.
HSYNC I 2 MPU
Data enable signal. For test only.
DE I 2 MPU
If this pin is not used, connect it to VDD1 or VSSD.
Frame synchronizing signal. For test only.
VSYNC I 2 MPU
Dot clock signal. For test only.
PCLK I 2 MPU
DB23~0 I 24 MPU Let unused pins open for each mode.
Source driver output pins
Output voltages applied to the liquid crystal.
Source channels
Panel
1 / 2 / 4 / 8 dot,
Resolution Zig-Zag inversion
Column inversion
S1 to S2160,
O 2162 LCD 720RGB S1~S2160 S1~S2160,SL1,SR1
SL1, SR1
S1~S960,
640RGB S1~S960, S1201~S2160
S1201~S2160,SL1,SR1
S1~S900,
600RGB S1~S900, S1261~S2160
S1261~S2160,SL1,SR1
TE O 6 MPU Tearing Effect pin.

TE1 O 6 MPU Tearing Effect pin of each scan line.
GIP control singal and bias voltage
Signals for left side GIP on panel view. (Left side in IC bump view)
CGOUT_L1~22 O 22 LCD
Unused pins should be left open.
Signals for right side GIP on panel view. (Right side in IC bump view)
CGOUT_R1~22 O 22 LCD
Unused pins should be left open.
Power supply pins
Power A power supply for the logic power and I/O circuit. VDD1 range is 1.65 to
VDD1 I 31
supply 3.6V. It must be connected to a stabilizing capacitor 2.2uF to VSSA.
A power supply for the analog power.
Power
VDD3 I 19 It must be connected to a stabilizing capacitor 2.2uF to VSSA.
supply
PCCS[1:0]=10, VDD3 range is 2.5V ~ 3.6V.
HX8394-F
PCCS[1:0]=00, 01 and 11, VDD3 range is 2.5V ~6.5V.
Power Analoge ground. VSSA=0V. When using the COG method, connect to
VSSA P 16
supply VSSD on the FPC to prevent noise.
Power
VSSAC P 4 Analoge ground. It must be connected to VSSA on the FPC.
supply
Power Ground for the internal logic. VSSD=0V. When using the COG method,
VSSD P 46
supply connect to VSSA on the FPC to prevent noise.
Power External high voltage pin used in OTP mode and operates at 7.5V.
VPP I 6
supply If not used, let it open.
Input voltage generated from HX5186-C, PFM or external power IC.
Stabilizing
VSP I 7 VSP range is 4.3V to 6.5V. It must be connected to a stabilizing capactor
capacitor
between VSP and VSSA.
Input voltage generated from HX5186-C, PFM or external power IC.
Stabilizing
VSN I 7 VSP range is -4.3V to -6.5V. It must be connected to a stabilizing capactor
capacitor
between VSN and VSSA.
Output pins of power and reference voltage
Select the VSP/VSN pumping method as listed below:
PCCS Power Input VGH/
VSP VSN
[1:0] mode Power VGL
External
00 VSP+VSN+ VDD1 External External External
VGH+VGL
PFM-D
Internal Internal
01 (External VDD1 External
PFM DC/DC
VSSD / VSP)
PCCS1 ~ PCCS0 I 4
VDD1 HX5186 or Internal Internal
VDD3 Internal
10 PFM-A or PFM or PFM or
VDD1 DC/DC
PFM-C HX5186 HX5186
External Internal
11 VDD1 External External
VSP+VSN DC/DC
PCCS[1:0] must be connected to VSSD (logic=0) or VDD1(logic=1).

Note: For External Power Mode(PCCS[1:0]=00,01 and 11), VDD3 is not
needed. Please let VDD3 open or connect it to VSP.
Output voltage from the set-up circuit. (-VDD3 or -2.5~-3.1V)
Stabilizing
VCL I 5 It is generated from VDD3.
capacitor
It must be connected a stabilizing capacitor 1.0uF to VSSA.
Stabilizing
VSPR O 3 Positive regulated voltage output for Gamma. (3.1V to VSP - 0.3)
capacitor
Stabilizing
VSNR O 3 Negative regulated voltage output for Gamma. (-3.1V to VSN + 0.3)
capacitor
Stabilizing Internal logic voltage output.
VDDD O 25
capacitor It must be connected a stabilizing capacitor 2.2uF to VSSA.
Stabilizing Output voltage from the step-up circuit, it is generated from VSP and VSN.
VGH O 6
capacitor Connect to a stabilizing capacitor 1uF between VSSA and VGH.
Output voltage from the step-up circuit, it is generated from VSP and VSN.
Stabilizing
VGL O 13 Connect to a stabilizing capacitor 1uF between VSSA and VGL. Place a
capacitor
schottkey barrier diode between VSSA and VGL.
The power supply of common voltage in DC com driving. The voltage
Stabilizing
VCOM O 6 range is -4V to -0.3V. It must be connected to a stabilizing capacitor 2.2uF
capacitor
to VSSA.
Stabilizing
VREF O 3 Internal reference voltage.
capacitor
DC/DC pumping
C21P, C21N 14 Step-up Connect to the step-up capacitors according to the DC/DC pumping factor
I/O
C22P, C22N 14 Capacitor for pumping VGH voltage.
Step-up Connect to the step-up capacitors according to the DC/DC pumping factor
C31P, C31N I/O 14
Capacitor for pumping tVGL voltage.
Step-up Connect to the step-up capacitors according to the DC/DC pumping factor
C41P, C41N I/O 14
Capacitor for pumping the VCL voltage.
VCSW1 and VCSW2 should be connected to HX5186-C for HX5186-C
VCSW1, VCSW2 I 16 -
mode.
CABC & ABC
CABC_PWM_OUT O 4 Led driver Backlight on/off control pin. If CABC function is used, the pin can be
HX8394-F
connected to external LED driver IC. The output voltage level is 0 or
VDD1.
High speed interface parts
HS_D0P, MIPI-DSI Data differential signal input pins. (Data lane 0)
I/O 6/6 DSI Host
HS_D0N if not used , Please connected to VSSD or open.
HS_CP, MIPI-DSI CLOCK differential signal input pins.
I 6/6 DSI Host
HS_CN If not used , Please connected to VSSD or open.
I 6/6 DSI Host
I 6/6 DSI Host
I 6/6 DSI Host
Power
HS_VCC P 12 Power supply for the MIPI DSI analog power. (1.65V to 3.6V)
Supply
MIPI DSI analogy ground. VSS=0V. When using the COG method,
HS_VSS P 17 Ground
connect to VSSA on the FPC to prevent noise.
DSI regulator output pin. (1.5V)
HS_LDO O 12 Capacitor Connect to a stabilizing capacitor 1uF between VSS and LDO.
If not used, please open these pins.
Test pins
Oscillator input for test purpose.
OSC I 2 Open
If not used, please let it open or connected to VDD1. (Weak pull high).
A test pin. This pin is for internal logic function test. It can be output on
TEST[2:0] I 6 Open
FPC. If not used, connect it to VSSD. (Weak pull low).
A test pin. This pin is for internal logic function test. It can be output on
TS0~7 O 8 Open
FPC.
VTESTOUTP O 2 Open A test pin. This pin will output Gamma voltage. It can be output on FPC.
VTESTOUTN O 2 Open A test pin. This pin will output Gamma voltage. It can be output on FPC.
A test pin. This pin for by internal logic function test. It can be output on
FPC. If not used, please open or connect it to VSSD. (Weak pull low).
This pin is used for Himax engineering mode.
FRM I 2 Open
FRM Free Running Mode
Low Disable
High Enable
DUMMYR1
DUMMYR2 Dummy pads. Available for measuring the COG contact resistance. They
- 16 Open
DUMMYR3 are short-circuited within the chip.
DUMMYR4
DUMMY - 397 Open Dummy pads(Not used). Let it open.

HX8394-F
4. Interface
4.1 System interface
The HX8394-F supports MIPI DSI (Display Serial Interface) interface. BS2~BS0 are
used for the combination of polarity swap and data lane swap of DSI.
BS[2:0] HS_D0N HS_D0P HS_D1N HS_D1P HS_CN HS_CP HS_D2N HS_D2P HS_D3N HS_D3P
“000” D3N D3P D2N D2P CN CP D1N D1P D0N D0P
“001” D3P D3N D2P D2N CP CN C1P C1N D0P D0N
Table 4.1: Interface selection
4.1.1 Serial data transfer interface(MIPI DBI type C)
The HX8394-F supports DBI Type C option 1, 3-wire serial bus to access command
set under DSI I/F. The 3-wire serial bus is use: chip select line (CSX), serial input data
(SDI),serial output data (SDO) and serial transfer clock line (SCL).

HX8394-F
4.1.2 Serial data write mode
The 3-wire serial data packet contains a control bit D/CX and a transmission byte. If
DCX is low, the transmission byte is command byte. If D/CX is high, the transmission
byte is stored in to command register. The MSB is transmitted first. The serial
interface is initialized when CSX is high. In this state, SCL clock pulse or serial
input/output data (SDI and SDO) have no effect. A falling edge on CSX enables the
serial interface and indicates the start of data transmission.
Figure 4.1: Serial data stream, write mode
Figure 4.2: Serial data stream, write mode

HX8394-F
4.1.3 Serial data read mode
The micro-controller first has to send a command and then the following byte is
transmitted in the opposite direction. The 3-wire serial read data format which just
needs 8-bit.
Figure 4.3: Type C:Serial interface protocol 3-wire/4-wire read mode
If there is a break on data transmission when transmit a command before a whole

byte has been completed, then the display module will have reset the interface such
that it will be ready to receive the same byte re-transmitted when the chip select line
(CSX) is next activated. See the following figure.
Figure 4.4: Display module data transfer recovery

HX8394-F
4.2 DSI system interface
The selection of interface is by BS[2:0]=”000”~”111“ the DSI specifies the interface

between a host processor and a peripheral such as a display module. Figure 4.5
shows a simplified DSI interface. From a conceptual viewpoint, a DSI-compliant
interface also sends pixels or commands to the peripheral, and can read back status
or pixel information from the peripheral. The main difference is that DSI serializes all
pixel data, commands, and events.
Figure 4.5: DSI transmitter and receiver interface
Please refer to “DRAFT MIPI Alliance Standard for DSI” for DSI detail
specifications.
The data lane number is selected by register RBAh.

HX8394-F
4.2.1 DSI layer definitions
According Figure 4.6 DSI transmitter and receiver interface to understand simple
interface block diagram. Then under diagram is internal block for DSI which include
four layers: PHY Layer, Lane Management Layer, Low level protocol and Application
Layer.
The PHY Layer specifies the characteristics of transmission medium and electrical
parameters for signaling the timing relationship between clock and Data Lanes.
The Lane Management Layer specifies DSI is Lane-scalable for increased

performance. The data signals maybe transmission through one or more channel
depending on the bandwidth requirements of the application.
The Protocol Layer specifies at the lowest level, DSI protocol specifies the sequence
and value of bits and bytes traversing the interface. It specifies how bytes are
organized into defined groups called packets.
The Application Layer describes higher-level encoding and interpretation of data

contained in the data stream. The DSI specification describes the mapping of pixel
values, commands and command’s parameters to bytes in the packet assembly.
Figure 4.6: DSI transmitter and receiver interface

HX8394-F
4.2.2 Lane states
The HX8394-F uses Data Lane and Clock Lane differential pairs for DSI. Both
differential lane pairs can be driven LP (Low Power) or HS (High Speed) mode.
LP mode means each line of the differential pairs are used in independently and
single-ended. In LP mode differential receiver is disable ( Termination resistor of the
receiver is disable). In LP mode there are four possible Low-Power Lane states (LP-00,
LP-01, LP-10, LP-11).
HS mode means the differential pairs are not used in single-end and termination
resistor of the receiver is enable. There are different modes and protocol in each
mode when transfer display data frim MCU to the display module.
The state code of HS and LP Lane pair are defined as below:
Line Voltage Levels High-Speed Low-Power

State Code
Dp-Line Dn-Line Burst Mode Control Mode Escape Mode
HS-0 HS Low HS High Differential-0 Note1 Note1
HS-1 HS High HS Low Differential-1 Note1 Note1
LP-00 LP Low LP Low N/A Bridge Space
LP-01 LP Low LP High N/A HS-Rqst Mark-0
LP-10 LP High LP Low N/A LP-Rqst Mark-1
LP-11 LP High LP High N/A Stop Note2
Note: (1) During High-Speed transmission the Low-Power Receivers observe LP-00 on the Lines.
(2) If LP-11 occurs during Escape mode the Lane returns to Stop state (Control Mode LP-11)

HX8394-F
4.2.3 Clock lane mode
Figure 4.7 shows the state diagram for Clock Lane Mode. The Clock Lane has three
different power modes: Low Power Stop State, Ultra Low Power State (ULPS) and
High Speed clock transmission.
Enter LP Stop State:

Init Master or Slave
Master or Slave
Enter ULPS:
Enter HS transmission mode:
ULPS
BRIDGE HS-REQ Stop BRIDGE
ENTER
LP-00 LP-01 LP-11 LP-00
LP-10
CLOCK ULPS
EXIT ULPS
HS-0 HS-1 TRAIL
LP-10 LP-00
HS-0
HS CLOCK
transmission
Figure 4.7: Clock lane mode state diagram
Clock Lane can be driven LP-11 to enter Low Power Stop State. There are three
ways to enter Lower Power Stop State:
(1) After Initial state. (HW reset, SW reset, Power on sequence)

(2) Leaving ULPS: ULPS LP-00 -> LP-10 -> Low Power Stop State LP-11.
(3) Leaving HS clock transmission mode: HS mode (HS-0 or HS-1) -> HS-0 -> Low
Power Stop State LP-11.

HX8394-F
Clock Lane can be driven LP-00 to enter Ultra Low Power State from Low Power
Stop State. The flow is Low Power Stop State LP-11 -> LP-10 -> ULPS LP-00.
Clock Lane can be High Speed Clock transmission State from Low Power Stop State.
The flow is Low Power Stop State LP-11 -> LP-01 -> LP-00 -> HS-0/1.
TLPX
TCLK-ZERO HS clock
transmission HS_CLKP
TCLK-TERMEN
HS-0 HS_CLKN
HS-0 or HS-1
LP Stop
LP-01 LP-00
LP-11

HX8394-F
4.2.4 Data lane mode
Figure 4.8 shows the operational flow diagram for Data Lane Mode. There are three
operating modes in Data Lane: Escape mode, High-Speed transmission mode and
Turnaround.
TX Trigger
Init Master Escape
ULP
LPDT Mode
LP-00>01>00
HS-Prpr HS-Rqst STOP LP-Rqst

LP-00 LP-01 LP-11 LP-10
Turnaround
SoT HST EoT
LP-00>10>00>10
RX Trigger
Init Master Escape
ULP
Wait Mode
LPDT
LP-00>01>00
HS-Prpr HS-Rqst STOP LP-Rqst

LP-00 LP-01 LP-11 LP-10
Turnaround
SoT HST EoT
LP-00>10>00>10
Figure 4.8: Data lane mode state diagram

HX8394-F
4.2.5 Escape mode
Data Lane0 is used in Escape Mode when data lane in LP mode. Data Lane shall
enter Escape mode via LP-11 -> LP-10 -> LP-00 -> LP-01 -> LP-00 and exit Escape
mode via LP-10 -> LP-11.
TX Stop RX Stop
TX LP-Rqst RX LP-Rqst
TX LP-Yield RX LP-Yield
TX Esc-Rqst RX Esc-Rqst
TX Esc-Go RX Esc-Go
TX Esc-Cmd RX Esc-Cmd
TX Triggers RX Triggers
TX Mark RX Wait
TX ULPS RX ULPS
TX LPDT RX LPDT
Figure 4.9: Escape mode state machine
Once Escape mode is entered, the transmitter shall send an 8-bit entry code to
indicate the requested action. The Entry Code as follows:
(1) Trigger (Reset-Trigger(46h), Tearing effect(BAh), Acknowledge(84h))

(2) Drive Data Lane to Ultra Low Power State (78h)
(3) Send Low Power Data Transmission (87h)

HX8394-F
Figure 4.10: Escape mode timing sequence

HX8394-F
4.2.6 High speed data transmission
The display module can enter High Speed Data Transimission when Clock Lane in
the High Speed Clock Mode. All Data Lane enter High Speed Data Tranmission
synchronously but may end at different time. Data Lane enter High Speed Data
Transmission flow: LP-11 -> LP-01 -> LP-00 -> SoT (0001_1101). And exit High Speed
Data Transmission flow: Toggles differential state immediately after last payload data
bit and keeps that state for a time THS-TRAIL.
Figure 4.11: High speed data transmission state machine
CLK
D(0~3)p/
TLPX THS- THS-ZERO THS-SYNC
D(0~3)n PREPARE
HS-00011101 Disconnect
Terminator
VIH(min)
VIL(max) HSDT HS-0 or HS-1
HS-0
Capture
LP-11 LP-01 LP-00 1st Data Bit
TEOT LP-11
THS-TRAIL THS-EXIT
Figure 4.12: High speed data transmission timing sequence

HX8394-F
Parameter Description Min. Typ. Max. Unit
Time that the transmitter drives the Data

Lane LP-00 Line state immediately
THS-PREPARE 40+4*UI - 85+6*UI ns
before the HS-0 Line state starting the
HS transmission.
THS-PREPARE + time that the
THS-PREPARE+ transmitter drives the HS-0 state prior to 145+10*UI - - ns
THS-ZERO transmitting the Sync sequence.
Transmitted time interval from the start of
TEOT THS-TRAIL or TCLK-TRAIL, to the start - - 105ns+12*UI ns
of the LP-11 state following a HS burst.
Time that the transmitter drives the
THS-TRAIL flipped differential state after last payload 60ns+4*UI - - ns
data bit of a HS transmission burst.
Time that the transmitter drives LP-11
THS-EXIT following a HS burst. 100 - - ns
Table 4.2: Global Operation Timing Parameters for Data Lane
Figure 4.13: Switching the Clock Lane between Clock Transmission and LP Mode
Parameter Description Min. Typ. Max. Unit
Time that the transmitter continues to

send HS clock after the last associated
TCLK-POST 60+52*UI - - ns
Data Lane has transitioned to LP Mode.
Time that the transmitter drives the

TCLK-TRAIL flipped differential state after last payload 60 - - ns
data bit of a HS transmission burst.
Time that the HS clock shall be driven by

the transmitter prior to any associated
TCLK-PREPARE 38 - 95 ns
Data Lane beginning the transition from
LP to HS mode.

HX8394-F
TCLK-PREPARE + time that the
TCLK-PREPARE+ transmitter drives the HS-0 state prior to 300 - - ns
TCLK-ZERO starting the Clock.
Time that the HS clock shall be driven by
the transmitter prior to any associated
TCLK-PRE 8*UI - - ns
Data Lane beginning the transition from
LP to HS mode.
Table 4.3: Global Operation Timing Parameters for Clock Lane

HX8394-F
4.2.7 Bi-directional data lane turnaround
The transmission direction od a bi-directional Data Lane can be swapped by means

of a Link Turnaround procedure. This procedure enables information transfer in the
opposite direction of the current direction. The procedure is the same for either a
change from Forward-to-Reverse direction or Reverse-to-Forward direction.
TX Stop RX Stop
TX LP-Rqst RX LP-Rqst
TX LP-Yield RX LP-Yield
TX TA-Rqst RX TA-Rqst
TX TA-Go RX TA-Wait
RX TA-Get
RX TA-Look
RX TA-Ack TX TA-Ack
RX StopT TX Stop
Figure 4.14: Turnaround state machine

HS_DP
Master Drive HS_DN
4TLPX
TLPX TLPX TLPX TTA-GO
Drive
overlap
2~3TLPX
LP-11 LP-10 LP-00 LP-10 LP-00 LP-00 LP-00 LP-10 LP-11

TTA-SURE TTA-GET TLPX TLPX
5TLPX
1~2TLPX Slave Drive
Note: TLPX(Master)/TLPX(Slave) between 2/3~3/2
Figure 4.15: Turnaround timing sequence

HX8394-F
4.2.8 DSI protocol
The protocol layer appends packet-protocol information and headers. The receiver
side of a DSI Link performs the converse of the transmitter side, decomposing the
packet into parallel data, signal events and commands. The DSI protocol permits
multiple packets which is useful for events such as peripheral initialization, where
many registers may be loaded separate write commands at system startup. Figure
4.15 illustrates multiple HS Transmission packets.
LPS：Low power state

SoT：Start of Transmission
SP：Short Packet
LgP：Long Packet
EoT：End of Transmission
Figure 4.16: Multiple packets transmission
The packet includes two types which are Long packet and Short packet. The first byte
of the packet, the Data Identifier (DI), includes information specifying the type of the
packet. Command Mode systems send commands and an associated set of
parameters, with the number of parameters depending on the command type.
Short packets are four bytes in length including the ECC. Short packet is used for
most Command Mode commands and associated parameters. Where Short packets
format include an 8-bit Data ID followed by two command or data and an 8-bit ECC.
Figure 4.16 shows the structure of the Short packet.
DI(Data ID)：
：Contain Virtual Channel Identifier and Data Type.
ECC(Error Correction Code)：：The Error Correction Code allows single-bit errors to
be corrected and 2-bit errors to be detected in the Short packet.
Figure 4.17: Structure of the short packet

HX8394-F
Long packets specify the payload length using a two-byte Word Count field and then
the payload maybe from 0 to 65,535 bytes in length. Long packets permit
transmission of large blocks of pixel or other data. Figure 4.17 shows the structure of
the Long packet. Long Packet Header composed of three elements: an 8-bit Data
Identifier, a 16-bit Word Count, and 8-bit ECC. An application-specific Data Payload
has Word Count * bytes following the Packet Header. The Packet Footer has one
element, a 16-bit checksum. Long packets can be from 6 to 65,541 bytes in length.
Where 65,541 bytes = 4 bytes PH + (216-1)bytes Payload + 2 bytes PF
DI (Data ID)：
：Contain Virtual Channel Identifier and Data Type.
WC (Word Count)：：The receiver use WC to determine the packet end.
ECC (Error Correction Code)：：The Error Correction Code allows single-bit errors to
be corrected and 2-bit errors to be detected in the Packet Header.
PF (Packet Footer)：：Mean 16-bit Checksum.
Figure 4.18: Structure of the long packet
According to packet form, basic elements include DI and ECC. Figure 4.18 the shows
format of Data ID.
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

VC (Virtual Channel) DT (Data Type)
DI[7:6] These two bits identify the data as directed to one of four virtual channels.
DI[5:0]: These six bits specify the Data Type.
Figure 4.19: The format of data ID

HX8394-F
Due to Data Type (DT) mean format of transmission type, Figure 4.19 show Short- /
Long-packet transmission command sequence.
Long packet write Command / Parameters / Pixel Datas
PH
LPS DCS WR CMD / CMD + PAs LPS
SOT DI WC ECC PF EOT
/ CMD+ Pixel DATA
DI ٛ Write suitable Data type.

WC ٛ Write number of Payload Data.
Ex: One CMD write, WC setting as 1.
CMD + PAs write, WC setting as number of (CMD+PAs).
CMD + DATA write, WC setting as number of (CMD + Pixel DATA).
Short packet write Command / Parameters
PH
LPS SOT DI DCS WR CMD / CMD + PAs ECC EOT LPS
DI ٛ Write suitable Data type.

Ex: One CMD write, DI + DCS WR CMD
CMD + PAs write, DI + DCS WR CMD + PAs
Figure 4.20: Show short- / long-packet transmission command sequence

HX8394-F
4.2.9 Processor to peripheral (forward direction) packets data types
The set of transaction types sent from the host processor to a peripheral, such as a
display module, are shown in Table 4.2 Data Types for Processor-sourced Packets.
Data type, hex Data type, binary Description packet Size

01h 00 0001 Sync Event, V Sync Start Short
11h 01 0001 Sync Event, V Sync End Short
21h 10 0001 Sync Event, H Sync Start Short
31h 11 0001 Sync Event, H Sync End Short
08h 00 1000 End of Transmission packet (EoTp) Short
05h 000101 DCS WRITE, no parameter Short
15h 010101 DCS WRITE, 1 parameter Short
06h 00 0110 DCS READ, no parameters Short
37h 11 0111 Set Maximum Return Packet Size Short
09h 00 1001 Null Packet, no data Long
19h 01 1001 Blanking Packet, no data Long
39h 11 1001 DCS Long Write/write_LUT Command Packet Long
0Eh 00 1110 Packed Pixel Stream, 16-bit RGB, 5-6-5 Format Long
Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6
2Eh 10 1110 Long
Format
xx 0000 DO NOT USE
X0h and XFh, unspecified -
xx 1111 All unspecified codes are reserved
Table 4.4: Data types for processor-sourced packets

HX8394-F
Under tables list all detail function of all data types
Sync event (H start, H end, V start, V end), data type=xx 0001 (x1h)
Data type, hex Function description Number of bytes
01h V Sync start, Start of VSA pulse. 4 bytes
11h V Sync End, End of VSA pulse. (DI+00h+00h+ECC)
21h H Sync Start, Start of I pulse.
31h H Sync End, End IHSA pulse.
Note: V Sync Start and V Sync End event represents the start and end of the VSA, respectively. Similarly H Sync Start
and H Sync End event represents the start and end oIhe I, respectively.
EoT Packet
08h End of Transmission Packet (EoTp) (08,0F,0F,01)
4 bytes
(DI+Data0+Data1+ECC)
Note: The main objective of the EoTp is to enhance overall robustness of the system during HS transmission mode.
Therefore, DSI transmitters should not generate an EoTp when transmitting in LP mode.
Color Mode Off /On Command

02h Color Mode Off Packet (02,00,00,0B) 4 bytes
12h Color Mode On Packet (12,00,00,18) (DI+Data0+Data1+ECC)
Note: Color Mode Off is a Short packet command that returns a Video Mode display module from low-color mode to normal
display operation. Color Mode On is a Short packet command that switches a Video Mode display module to a
low-color mode for power saving.
Display status (shutdown command, turn-on command )

22h Shutdown Peripheral command that turns off the display in a 4 bytes
Video Mode display for power saving. (DI+00h+00h +ECC)
32h Turn On Peripheral command that turns on the display in Video
Mode display for normal display.
Note: When use shutdown command, interface shall remain powered in order to receive the turn-on, or wake-up,
command.
DCS read/write function

06h DCS Read command, the returned data shall be Long packet 4 bytes
format. (DI+Data0+Data1+ECC)
05h and 15h DCS Short Write command, 0 or 1 parameter, Data Types = 00 4 bytes
0101(05h), 01 0101 (15h), Respectively. (DI+Data0+Data1+ECC)
39h DCS Long Write/ Write _ LUT Command is used to send larger Up to 65541 bytes
blocks of data to a display module that implements the Display ( DI + WC + ECC
Command Set. + DCS CMD.
+ Payload DATA + PF )
Note: (1) For write part, If DCS Short Write command, followed by BTA, the peripheral shall respond with ACK when
without error was detected in the transmission (Host Slave). Unless an error was detected, the peripheral
shall respond with Acknowledge with Error Report.
For example: 05h DCS WRITE for no parameter command set.
For example: 15h DCS WRITE for only one parameter command set.
(2) When use DCS Read Command, the Set Max Return Packet Size command will limit the size of returning

HX8394-F
packets.
(3) The peripheral shall respond to DCS Read Command Request in one of the following ways:
◆ If an error was detected by the peripheral, it shall send Acknowledge with Error Report. So the peripheral
◆
shall transmit the requested READ data packet with suitable ECC in the same transmission.
If no error was detected by the peripheral, it shall send the requested READ packet (Short or Long) with
appropriate ECC and Checksum, if either or both features are enabled.
16
(4) One byte <= Length of payload DATA <= 2 -1

HX8394-F
Maximum Return packet size setting

37h Set Maximum Return Packet Size that specifies the maximum 4 bytes
size of the payload in a Long packet transmitted from peripheral (DI + Maximum Return
back to the host processor. Packet Size + ECC)
Note: The two-byte value is transmitted with LS byte first. And during a power-on or Reset sequence, the Maximum Return
Packet Size shall be set by the peripheral to a default value of one.
Variable data packet

09h Null Packet is a mechanism for keeping the serial Data Lane(s) Up to 65541 bytes
in High-Speed mode while sending dummy data. ( DI + WC + ECC
19h Blanking packet is used to convey blanking timing information + DCS CMD.
in a Long packet. + Payload DATA + PF )
Note: (1) When Null Packet, the Payload Data belong “null” Data, actual data values sent are irrelevant because the
peripheral does not capture or store the data.
(2) When Blanking packet, the packet represents a period between active scan lines of a Video Mode display,
Data stream format

0Eh Packed Pixel Stream 16-Bit Format is used to transmit image Up to 65541 bytes
data formatted as 16-bit pixels to a Video Mode display ( DI + WC + ECC
module. Pixel format is “(5 bits) red, (6 bits) green and (5 bits) + DCS CMD.
blue”. + Payload DATA + PF )
1 byte 1 byte
D0 D7D0 D7
R0 R4 G0 G5 B0 B4
5b 6b 5b
Pixel 1
1 byte 2 bytes 1 byte 1 byte 1 byte 1 byte 1 byte 2 bytes

5b 6b 5b 5b 6b 5b
Virtual Channel
Data Type
Word Count ECC Checksum
Pixel 1 Pixel n
PH (Packet Header) Variable Payload data PF (Packet Footer)
Note: Within a color component, the “LSB is sent first, the MSB last “.

HX8394-F
Data stream format

module. Pixel format is “(6 bits) red, (6 bits) green and (6 bits) + DCS CMD.
blue”. + Payload DATA + PF )
1 byte 1 byte
D0 D7 D0 D7
R0 R5 G0 G5 B0 B5
6b 6b 6b
Pixel 1
1 byte 2 bytes 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte
Virtual Channel
6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b
Data Type
Word Count ECC
Pixel 1 Pixel 2 Pixel 3 Pixel 4
PH (Packet Header) Variable Payload Data (First 4 pixels packed at 9 bytes)
1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 bytes
6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b
Checksum
Pixel n-3 Pixel n-2 Pixel n-1 Pixel n

Variable Payload Data (First 4 pixels packed at 9 bytes) PF (Packet Footer)
Note: Within a color component, the LSB is sent first and the MSB last and pixel boundaries only line up with byte
boundaries every four pixels (nine bytes). Preferably, display modules employing this format have a horizontal
extent (width in pixels) evenly divisible by four, so no partial bytes remain at the end of the display line data. It is
possible to send pixel data that represent a line width that is not a multiple of four pixels, but display logic on the
receiver end shall dispose of the extra bits of the partial byte at the end of active display and ensure a “clean start” for
the next line.

HX8394-F
Data stream format

2Eh Packed Pixel Stream 18-Bit Format, each R, G, or B color Up to 65541 bytes
component is one byte form, but the valid pixel bits occupy bits ( DI + WC + ECC
[7:2] and bits [1:0] of are ignored. Pixel format is “(6 bits) red, (6 + DCS CMD.
bits) green and (6 bits) blue”. + Payload DATA + PF )
1 byte 1 byte 1 byte

D0 D7 D0 D7 D0 D7
R0 R5 G0 G5 B0 B5
6b 6b 6b
Pixel 1
1 byte 2 bytes 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 bytes
6b 6b 6b 6b 6b 6b
Virtual Channel
Data Type
Pixel 1 Pixel n
PH (Packet Header) Variable Payload Data PF (Packet Footer)
Note: Within a color component, the LSB is sent first, the MSB last and With this format, pixel boundaries line up with byte
boundaries every three bytes.

HX8394-F
Packed pixel stream, 24-bit format

module. Pixel format is (8 bits) red, (8 bits) green and (8 bits) + DCS CMD.
blue. + Payload DATA + PF )
1 byte 1 byte 1 byte

D0 D7D0 D7D0 D7
R0 R7G0 G7B0 B7
8b 8b 8b
Pixel 1
1 byte 2 bytes 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 bytes
8b 8b 8b 8b 8b 8b
Virtual Channel
Data Type
Pixel 1 Pixel n
PH (Packet Header) Variable Payload Data PF (Packet Footer)
Note: Within a color component, the LSB is sent first, the MSB last and With this format, pixel boundaries line up with byte
boundaries every three bytes.

HX8394-F
4.2.10 Peripheral to processor (reverse direction) packet data type
HX8394-F has the bidirectional capability for returning READ data, ACK or error
information to the host processor. The packet structure for peripheral-to-processor
transactions is the same as that for the processor-to-peripheral direction.
Peripheral-to-processor transactions are of four basic types:
A. Tearing Effect is a Trigger message sent to convey display timing information to

the host processor. Trigger messages are single byte packets sent by a
peripheral’s PHY layer in response to a signal form the DSI protocol layer.
B. Acknowledge is a Trigger Message sent when the current transmission, as well as
all preceding transmissions since the last peripheral to host communication is
received by the peripheral with no errors.
C. Acknowledge and Error Report is a Short packet sent if any errors were detected
in preceding transmission from the host processor. Once reported, accumulated
errors in the error register are cleared.
D. Response to Read Request may be Short or Long packet that returns data
requested by the preceding READ command from the processor.
In general, if the host processor completes a transmission to the peripheral with BTA
asserted, the peripheral shall respond with one or more appropriate packet(s), and
then return bus ownership to the host processor. If BTA is not asserted following a
transmission from the host processor, the peripheral shall not communicate an
Acknowledge or other error information back to the host processor.
The processor-to-peripheral transactions with BTA asserted, can contain under form.
A. Following a non-Read command in which no error was detected, the peripheral
shall respond with Acknowledge.
B. Following a Read request in which no error was detected, the peripheral shall
send the requested READ data.
C. Following a Read request in which the ECC error was detected and corrected, the
Peripheral shall send the requested READ data in a Long or Short packet,
followed by a 4-byte (Acknowledge with Error Report) packet in the same LP
transmission. The Error Report shall have the ECC Error flag set.
D. Following a non-Read command in which the ECC error was detected and
corrected, the peripheral shall proceed to execute the command, and shall
respond to BTA by sending a 4-byte (Acknowledge with Error Report) packet, the
Error Report shall have the ECC Error flag set.
E. Following any command in which SoT Error, SoT Sync Error, EoT Sync Error, LP
Transmit Sync Error, checksum error or DSI VC ID Invalid was detected, or the
DSI command was not recognized, the peripheral shall send a 4-byte
Acknowledge with Error Report response, with the appropriate error flags set in
the two-byte error field. Only the ACK/Error Report packet shall be transmitted; no
read or write accesses shall take place on the peripheral in response.

HX8394-F
Which,
A. “Acknowledge” is sent using a Trigger message which is one byte: 00100001

B. “Acknowledge with Error Report” include 4 bytes which are DI, 2 bytes Error
report and ECC.
C. “Response to Read Request” are Long packet format.
An error report is comprised of two bytes following the DI byte, with an ECC byte
following the error report bytes. Table 4.5 shows the Error Report Bit Definitions. And
Table 4.6 list complete set of peripheral-to-processor Data Types.
Bit Description
0 SoT Error
1 SoT Sync Error
2 Reserved
3 Escape Mode Entry Command Error
4 Low-Power Transmit Sync Error
5 Peripheral Timeout Error
6 Reserved
7 Reserved
8 ECC Error, single-bit (Detected and corrected)
9 ECC Error, multi-bit (Detected, not corrected)
10 Checksum Error (Long packet only)
11 DSI Data Type Not Recognized
12 DSI VC ID Invalid
13 Reserved
14 Reserved
15 Reserved
Table 4.5: Shows the error report bit definitions
Data type,
Data type, hex Description packet Size
binary
02h 00 0010 Acknowledge with Error Report Short
1Ch 01 1100 DCS Long READ Response Long
Others (00h
3Fh) Reserved -
Table 4.6: The complete set of peripheral-to-processor data types
Acknowledge types
02 Get Acknowledge with Error report when Error occurs 4 bytes
from processor transmission.
Note: When processor transmits complete Payload, following signal by BTA, peripheral must respond to processor.
With error Acknowledge with error report (Short packet), Without error request READ data or
Acknowledge (Trigger message).
DCS Read types

1Ch This is the Long-packet response to DCS Long Read Up to 65541 bytes
Request. ( DI + WC + ECC + DCS
CMD. + Payload DATA +
PF )
Note: (1)If the peripheral is Checksum capable, is shall return a calculated two-byte Checksum appended to the
N-byte payload data. If the peripheral does not support Checksum, it shall return 0000h.
If the DCS command itself is possibly corrupt, due to an uncorrectable ECC error, SoT or SoT Sync error, the
requested READ data packet shall not be sent after the Acknowledge with Error Report packet be sent.
(2)There is no dummy read byte in the read response packet.
HX8394-F
5. Function Description
5.1 Tearing effect output line
The Tearing Effect output line supplies a panel synchronization signal. This signal
can be enabled or disabled by the Tearing Effect Line Off & On commands. The
mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect
Line On command. The signal can be used by the MPU to synchronize frame
memory writing when displaying video images.
Tearing Effect Line Modes
Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:
Figure 5.1: Tearing effect output signal mode 1

tvdh= The LCD display is not updated from the Frame Memory
tvdl= The LCD display is updated from the Frame Memory (Except Invisible Line – see below)
Under Mode1, the TE output timing will be defined by TEP[10:0] setting.
Ex: 1. FB=BP=0x01h (3 line) .
TEP[10:0]=0, then TE signal will output after last line finished.
TEP[10:0]=7, then TE signal will output at second line start.
Figure 5.2: TE delay output
Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking
Information, there is one V-sync and N H-sync pulses per field.
N: 480+ 8xNL[7:0].

HX8394-F
Figure 5.3: Tearing Effect Output signal mode 2

thdh= The LCD display is not updated
thdl= The LCD display is updated
Under Mode2, the H-sync pulses output amount will be defined by TESL[15:0] setting.
Ex: 1. TESL[15:0]=0, then TE signal will like TE mode 1.
TESL[15:0]=1, then TE signal will output 1280 H-sync.
Figure 5.4: TE Output for TELINE setting
Figure 5.5: Tearing Effect Output signal

Note: During Sleep In Mode, the Tearing Output Pin is active Low

HX8394-F
5.1.1 Tearing effect line timing
The Tearing Effect signal is described below:
tvdl tvdh
Vertical Timing
Horizontal Timing
thdl thdh
Figure 5.6: Tearing effect output line –tearing effect line timing
Idle Mode Off (Resolution 720x1280 RGB, Frame Rate=60 Hz)

Symbol Parameter Min. Max. Unit
tvdl Vertical Timing Low Duration 15 - ms
tvdh Vertical Timing High Duration VFP+VHP+VBP - us
tr Rise time - 15 ns
tf Fall time - 15 ns
Note: The timings in Table 5.1 apply when MADCTL ML=0 and ML=1
Table 5.1: AC characteristics of tearing effect signal
The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
tr tf
0.8*VDD1 0.8*VDD1
0.2*VDD1 0.2*VDD1
Figure 5.7: Tearing effect output line–definition of tf, tr

HX8394-F
5.2 Oscillator
The HX8394-F can oscillate an internal R-C oscillator with an internal oscillation
resistor (Rf). The oscillation frequency is changed according to the internal register
UADJ[4:0] if needed. Please refer to OSC control register CBh. The default frequency
is 45MHz. The oscillation frequency tolerance is ±5%.
Display
Internal Display Mode Controller
45MHz
45MHz fosc Frequency
Oscillator Step up Circuit
UADJ[
UADJ[4:0] Divider 1
Clock FS0 ( for VSP)
VSP)
FS0[1:0]
Frequency
Divider 2 Step up Circuit
FS1
FS1[1:0] ( for VGH,
VGH,VGL)
VGL)
Frequency
Divider 3 Step up Circuit
FS3
FS3[1:0] ( for VCL)
VCL)
CABC_
CABC_PWM_
PWM_CLK
(for Backlight CABC)
CABC)
Figure 5.8: OSC architecture

HX8394-F
5.3 Source driver
The HX8394-F contains 2162 channels of source driver (Normal S1~S2160; Zig-zag
S1~S2160,SL1,SR1) which is used for driving the source line of TFT LCD panel. The
source driver converts the digital data into the analog voltage for 2160 channels and
generates corresponding gray scale voltage output, which can realize a 16.7M colors
display simultaneously. Since the output circuit of this source driver incorporates an
operational amplifier, a positive and a negative voltage can be alternately output from
each channel.
H_RES[2:0] Resolution Source channels

000 720RGBx(480+ (8xNL)) S1~S2160
001 640RGBx(480+(8xNL)) S1~S960, S1200~S2160
010 600RGBx(480+(8xNL)) S1~S900,S1260~S2160
Table 5.2: Source output for Panel resolution

HX8394-F
5.3.1 Zig-Zag inversion
The HX8394-F supports Zig-Zag inversion which can reduce power consumption.
This inversion uses the same polarity as column inversion for data line and has
almost the same display quality as 1-dot inversion.
Figure 5.9: Zig-Zag inversion mode(ZZ_2PL=0)

HX8394-F
ZZ_EO=0
ZZ_LR=0 ZZ_LR=1
G1 G1
- + + - + - + - + - + - + - + - +
G2 G2
- + + - + - + - + - + - + - + - +
G3 G3
+ - + - + - + - + - + - + + - + - + -
G4 G4
+ - + - + - + - + - + - + + - + - + -
G5 G5
- + + - + - + - + - + - + - + - +
G6 G6
- + + - + - + - + - + - + - + - +
G7 G7
+ - + - + - + - + - + - + + - + - + -
G1280 G1280
+ - + - + - + - + - + - + + - + - + -
S2160 S2159 S2158 S2160 S2158 S3 S2 S1

S3 S2 S1 SL1 SR1 S2159
IC Bumps down IC Bumps down
ZZ_EO=1
ZZ_LR=0 ZZ_LR=1
G1 G1
- + - + - + - + - + - + - - + - + - +
G2 G2
- + - + - + - + - + - + - - + - + - +
G3 G3
+ - - + - + - + - + - + - + - + -
G4 G4
+ - - + - + - + - + - + - + - + -
G5 G5
- + - + - + - + - + - + - - + - + - +
G6 G6
- + - + - + - + - + - + - - + - + - +
G7 G7
+ - - + - + - + - + - + - + - + -
G1280 G1280
+ - - + - + - + - + - + - + - + -
S2160 S2158 S3 S2 S1
S2160 S2159 S2158 S3 S2 S1 SL1 SR1 S2159
IC Bumps down IC Bumps down
Figure 5.10: Zig-Zag2 Inversion mode(ZZ_2PL=1)

HX8394-F
5.4 LCD power generation scheme
Figure 5.11: LCD power generation scheme for HX5186 and PFM mode
Figure 5.12: LCD power generation scheme for external power mode
HX8394-F
5.5 DC/DC converter circuit
5.5.1 Charge pump and step up circuit mode
HX8394-F supports various kinds of power generation mode, including PFM Type A,
PFM Type C, PFM Type D and external HX5186-A/B/C and external VSP & VSN
power mode. All power power mode can be set by hardware pins PCCS[1:0] as
below:
PCCS[1:0] Power mode Input Power VSP VSN VGH/VGL

External
00 VDD1 External External External
VSP+VSN+VGH+VGL
PFM-D Internal Internal
01 VDD1 External
(External VSP) PFM DC/DC
HX5186 or PFM-A or VDD3, Internal PFM Internal PFM Internal
10
PFM-C VDD1 or HX5186 or HX5186 DC/DC
Internal
11 External VSP+VSN VDD1 External External
DC/DC
Note: When use PCCS=[00,11] ,VDD3 is not needed.
Table 5.3: Power mode setting

HX8394-F
5.5.2 Use external VSP,VSN,VGH,VGL circuit
The input voltage range of VSP is from 4.3V ~ 6.5V. The input voltage range of VSN is
from -4.3V ~ -6.5V. The input voltage range of VGH is from 7.3V ~ 20V. The input
voltage range of VGL is from -5.3V ~ -18V. Please set VGH-VGL<32V, and VGL<VSN,
VSP<VGH.
Use external VSP,VSN,VGH,VGL circuit. (PCCS[1:0]=“00”)
C7
VDD3
C1
VSP
C2
VSN
VREF C13
C5
VSP VCOM C14
Voltage VSNR C15
Reference
C6 VSPR C16
VSN
VDDD C17
HS_LDO C18
C3
VDD1
C4
HS_VCC
HX8394-F
Figure 5.13: DC/DC converter circuit of external VSP/VSN/VGH/VGL

HX8394-F
5.5.3 Use PFM DC/DC converter
The PFM DC-DC converter generates the high voltage level VSP/VSN required for
source drivers. HX8394-F contains sub-circuits of the PFM boost converter, including
a precision 1.8V reference voltage, comparator, PFM controlling logic, and the output
buffer. The boost converter uses a external power transistor to provide maximum
efficiency and to minimize the number of external components. The output voltage of
the boost converter can be set from +4.3V to +6.5V (VSP) and -4.3V to -6.5V (VSN).
Use PFM DC/DC converter (PCCS[1:0]=“01”)
Figure 5.14: DC/DC converter circuit (PFM type D)

HX8394-F
Use PFM DC/DC converter (PCCS[1:0]=“10”) and (POWMOD[1:0]=“00”)
Figure 5.15: DC/DC converter circuit (PFM type A)

HX8394-F
Use PFM DC/DC converter (PCCS[1:0]=“10”) and (POWMOD[1:0]=“01”)
C41P
C41N C4
DC/DC
Pumping C5
VCL
C21P
C6
C21N
C22P
C7
C22N
C31P
DC/DC C8
Pumping C31N
C1
VDD3 D1
VGL C9
C2 VGH C10
VDD1
VREF C11
C3
HS_VCC
VCOM C12
Voltage VSNR C13

Reference
VSPR C14
VDDD C15
HS_LDO C16
VDD3
VCSW2
D3
VSN
C17
PFM VREF L1
Controller D2 C22
VSP C18
D4
VCSW1
SW1
HX8394-F
Figure 5.16: DC/DC converter circuit (PFM type C)

HX8394-F
5.5.4 Use HX5186-A/B/C
The HX5186-A/B/C is highly efficient switching voltage generator circuits that

generate the high voltage level VSP/VSN required for source drivers. HX8394-F
contains Charge Pump Controller for HX5186, including a comparator for VSP/VSN
feedback control. HX5186-A/B/C can provide maximum efficiency and use minimum
number of external components. The output voltage of the boost converter can be set
from 4.3V to 6.5V (VSP) and -4.3V to -6.5V (VSN).
(PCCS[1:0]=“10”) and (POWMOD[1:0]=“10” ,“11”)
Figure 5.17: DC/DC converter circuit of HX5186-A/B/C

HX8394-F
5.5.5 Use external VSP,VSN circuit
The input voltage range of VSP is from 4.3V ~ 6.5V. The input voltage range of VSN is
from -4.3V ~ -6.5V.
Use external VSP,VSN circuit. (PCCS[1:0]=“11”)
C5
VDD3
C1
VSP
DC/DC C21P
Pumping C8
C21N
C2 C22P
VSN
C9
C22N
C31P
DC/DC
Pumping C10
C31N
D1 VSN
VGL C11
VGH C12
C3
VDD1 VREF C13
VCOM C14
C4
Voltage VSNR C15
HS_VCC Reference
VSPR C16
VDDD C17
HS_LDO C18
HX8394-F
Figure 5.18: DC/DC converter circuit of external VSP/VSN

HX8394-F
5.6 8-color Idle display mode
The HX8394-F supports an 8-color idle display mode. The grayscale level to be used
is V0 and V255 with R7, G7, B7 decoding, and the other levels (V1-V254) are halted
to reduce power consumption. In idle display mode, the Gamma-micro-adjustment
registers are invalid and only the upper bits of RGB are used for display.
Graphics
(Input data)
R R R R R R R R G G G G G G GG B B B B B B B B
76543210 76543210 76 543210
1 1 1
Positive Polarity Register

VRP0[5:0]
V0P/V0N
8-bit Grayscale 8-bit Grayscale 8-bit Grayscale VRP5[5:0]
D/A Converter D/A Converter D/A Converter
Grayscale
<R> <G> Voltage
V255P/V255N Generator
Negative Polarity Register
Output Output Output
Driver Driver Driver VRN0[5:0]
VRN5[5:0]
R G B
LCD
Figure 5.19: Idle mode grayscale control

HX8394-F
5.7 1-bit GRAM Idle Display Mode
HX8394-F support display data from GRAM in Idle mode. User can use 2Ch/3Ch
command to write image data into GRAM. R/G/B MSB bit data stored in GRAM.
GRAM write direction not support MX/MY/MV function.
Figure 5.20: Idle Mode On/Off Sequence

HX8394-F
5.8 Gamma characteristic correction function
The HX8394-F offers two kinds of Gamma adjustment ways to come to accord with
LC characteristic, one kind is through Source Driver directly, another one is adjusted
by the digital gamma correction. The Gamma adjustment way is selected by internal
register DGC_EN bit.
Figure 5.21: Gamma adjustments different of source driver with digital gamma correction

HX8394-F
The HX8394-F incorporates gamma adjustment function for the 16,777,216-color

display (256 grayscale for each R, G, B color). Gamma adjustment operation is
implemented by deciding the 29 grayscale levels firstly in gamma adjustment control
registers to match the LCD panel. Then total 256 grayscale levels are generated in
grayscale voltage generator. These registers are available for both polarities.
Figure 5.22: Grayscale control

HX8394-F
5.8.1 Gamma-characteristics adjustment register
The HX8394-F has register groups for specifying a series grayscale voltage that meets
the Gamma-characteristics for the LCD panel used. These registers are divided into
two groups, which correspond to the gradient, amplitude, and macro adjustment of the
voltage for the grayscale characteristics. The polarity of each register can be specified
independently.
(1) Center adjustment registers
This gamma adjustment registers are used to adjust the reference gamma voltage for
center grayscale level. This function is implemented by controlling the 256-to-1 selector
in the gamma resister stream for reference gamma voltage generation. These registers
are available for both positive and negative polarities.
(2) Edge adjustment registers
This gamma adjustment registers are used to adjust the reference gamma voltage for
both edge grayscale level. This function is implemented by controlling the 128-to-1
selector in the gamma resister stream for reference gamma voltage generation. These
registers are available for both positive and negative polarities.
Register Positive Negative

Description
Groups Polarity Polarity
VHP0 6-0 VHN0 6-0 128-to-1 selector (voltage level of grayscale 0)
Up Edge VHP3 6-0 VHN3 6-0 128-to-1 selector (voltage level of grayscale 5)
adjustment VHP4 6-0 VHN4 6-0 128-to-1 selector (voltage level of grayscale 7)
VMP0 7-0 VMN0 7-0 255-to-1 selector (voltage level of grayscale 20)
Center
adjustment
VLP0 6-0 VLN0 6-0 128-to-1 selector (voltage level of grayscale 240)
Down Edge VLP3 6-0 VLN3 6-0 128-to-1 selector (voltage level of grayscale 248)
adjustment VLP4 6-0 VLN4 6-0 128-to-1 selector (voltage level of grayscale 250)
Table 5.4: Gamma-adjustment registers

HX8394-F
Gamma resister stream and 8 to 1 selector
Figure 5.23: Gamma resister stream and gamma reference voltage

HX8394-F
Variable resister
There are two types of variable resistors, one is for center adjustment and the other is for
edge adjustment. The resistances are decided by setting values in the center adjustment
and edge adjustment registers. Their relationships are shown below.
Value in Register Resistance Value in Register Resistance

VH(P/N)0~7 [6:0] VR(P/N) 0~7 VL(P/N)0~7 [6:0] VL(P/N) 0~7
000_0000 0R 000_0000 0R
000_0001 2R 000_0001 2R
000_0010 4R 000_0010 4R
000_0011 6R 000_0011 6R
• • • •
• • • •
011_1101 122R 011_1101 122R
011_1110 124R 011_1110 124R
011_1111 126R 011_1111 126R
100_0000 128R 100_0000 128R
100_0001 130R 100_0001 130R
100_0010 132R 100_0010 132R
• • • •
• • • •
111_1101 250R 111_1101 250R
111_1110 252R 111_1110 252R
111_1111 254R 111_1111 254R
Table 5.5: Edge adjustment 0~7, 21~28
Value in Register Resistance

VM(P/N)0~12 [7:0] VM(P/N)0~12
0000_0000 0R
0000_0001 1R
0000_0010 2R
• •
• •
0101_0101 85R
0101_0110 86R
0101_0111 87R
• •
• •
1101_0101 213R
1101_0110 214R
1101_0111 215R
• •
• •
1111_1101 253R
1111_1110 254R
1111_1111 255R
Table 5.6: Center adjustment 8~20

HX8394-F
The grayscale levels are determined by the following formulas:
Reference
Macro adjustment value VinP0 formula
voltage
VHP0 [6:0] = 000_0000 VSPR
VHP0 [6:0] = 000_0001 ((900R - 2R ) / 900R) * VSPR
VHP0 [6:0] = 000_0010 ((900R – 4R ) / 900R) * VSPR
VHP0 [6:0] = 000_0011 ((900R – 6R ) / 900R) * VSPR
VHP0 [6:0] = 000_0100 ((900R – 8R ) / 900R) * VSPR
VHP0 [6:0] = 000_0101 ((900R - 10R ) / 900R) * VSPR
•• ••
VHP0 [6:0] = 100_0001 ((900R - 130R ) / 900R) * VSPR
VHP0 [6:0] = 100_0010 ((900R - 132R ) / 900R) * VSPR
VinP0
VHP0 [6:0] = 100_0011 ((900R – 134R ) / 900R) * VSPR
VHP0 [6:0] = 100_0100 ((900R – 136R ) / 900R) * VSPR
VHP0 [6:0] = 100_0101 ((900R – 138R ) / 900R) * VSPR
•• ••
VHP0 [6:0] = 111_1011 ((900R – 246R ) / 900R) * VSPR
VHP0 [6:0] = 111_1100 ((900R – 248R ) / 900R) * VSPR
VHP0 [6:0] = 111_1101 ((900R – 250R ) / 900R) * VSPR
VHP0 [6:0] = 111_1110 ((900R - 252R ) / 900R) * VSPR
VHP0 [6:0] = 111_1111 ((900R - 254R ) / 900R) * VSPR
Table 5.7: VinP0
Reference
voltage
VHP1 [6:0] = 000_0000 VSPR
VHP1 [6:0] = 000_0001 ((900R - 2R ) / 900R) * VSPR
VHP1 [6:0] = 000_0010 ((900R – 4R ) / 900R) * VSPR
VHP1 [6:0] = 000_0011 ((900R – 6R ) / 900R) * VSPR
VHP1 [6:0] = 000_0100 ((900R – 8R ) / 900R) * VSPR
VHP1 [6:0] = 000_0101 ((900R - 10R ) / 900R) * VSPR
•• ••
VHP1 [6:0] = 100_0001 ((900R - 130R ) / 900R) * VSPR
VHP1 [6:0] = 100_0010 ((900R - 132R ) / 900R) * VSPR
VinP1
VHP1 [6:0] = 100_0011 ((900R – 134R ) / 900R) * VSPR
VHP1 [6:0] = 100_0100 ((900R – 136R ) / 900R) * VSPR
VHP1 [6:0] = 100_0101 ((900R – 138R ) / 900R) * VSPR
•• ••
VHP1 [6:0] = 111_1011 ((900R – 246R ) / 900R) * VSPR
VHP1 [6:0] = 111_1100 ((900R – 248R ) / 900R) * VSPR
VHP1 [6:0] = 111_1101 ((900R – 250R ) / 900R) * VSPR
VHP1 [6:0] = 111_1110 ((900R - 252R ) / 900R) * VSPR
VHP1 [6:0] = 111_1111 ((900R - 254R ) / 900R) * VSPR
Table 5.8: VinP1
Reference
voltage
VHP2 [6:0] = 000_0000 VSPR
VHP2 [6:0] = 000_0001 ((900R - 2R ) / 900R) * VSPR
VHP2 [6:0] = 000_0010 ((900R – 4R ) / 900R) * VSPR
VHP2 [6:0] = 000_0011 ((900R – 6R ) / 900R) * VSPR
VHP2 [6:0] = 000_0100 ((900R – 8R ) / 900R) * VSPR
VHP2 [6:0] = 000_0101 ((900R - 10R ) / 900R) * VSPR
•• ••
VHP2 [6:0] = 100_0001 ((900R - 130R ) / 900R) * VSPR
VHP2 [6:0] = 100_0010 ((900R - 132R ) / 900R) * VSPR
VinP3
VHP2 [6:0] = 100_0011 ((900R – 134R ) / 900R) * VSPR
VHP2 [6:0] = 100_0100 ((900R – 136R ) / 900R) * VSPR
VHP2 [6:0] = 100_0101 ((900R – 138R ) / 900R) * VSPR
•• ••
VHP2 [6:0] = 111_1011 ((900R – 246R ) / 900R) * VSPR
VHP2 [6:0] = 111_1100 ((900R – 248R ) / 900R) * VSPR
VHP2 [6:0] = 111_1101 ((900R – 250R ) / 900R) * VSPR
VHP2 [6:0] = 111_1110 ((900R - 252R ) / 900R) * VSPR
VHP2 [6:0] = 111_1111 ((900R - 254R ) / 900R) * VSPR
Table 5.9: VinP3

HX8394-F
Reference
voltage
VHP3 [6:0] = 000_0000 VSPR
VHP3 [6:0] = 000_0001 ((900R - 2R ) / 900R) * VSPR
VHP3 [6:0] = 000_0010 ((900R – 4R ) / 900R) * VSPR
VHP3 [6:0] = 000_0011 ((900R – 6R ) / 900R) * VSPR
VHP3 [6:0] = 000_0100 ((900R – 8R ) / 900R) * VSPR
VHP3 [6:0] = 000_0101 ((900R - 10R ) / 900R) * VSPR
•• ••
VHP3 [6:0] = 100_0001 ((900R - 130R ) / 900R) * VSPR
VHP3 [6:0] = 100_0010 ((900R - 132R ) / 900R) * VSPR
VinP5
VHP3 [6:0] = 100_0011 ((900R – 134R ) / 900R) * VSPR
VHP3 [6:0] = 100_0100 ((900R – 136R ) / 900R) * VSPR
VHP3 [6:0] = 100_0101 ((900R – 138R ) / 900R) * VSPR
•• ••
VHP3 [6:0] = 111_1011 ((900R – 246R ) / 900R) * VSPR
VHP3 [6:0] = 111_1100 ((900R – 248R ) / 900R) * VSPR
VHP3 [6:0] = 111_1101 ((900R – 250R ) / 900R) * VSPR
VHP3 [6:0] = 111_1110 ((900R - 252R ) / 900R) * VSPR
VHP3 [6:0] = 111_1111 ((900R - 254R ) / 900R) * VSPR
Table 5.10: VinP5
Reference
voltage
VHP4 [6:0] = 000_0000 VSPR
VHP4 [6:0] = 000_0001 ((900R - 2R ) / 900R) * VSPR
VHP4 [6:0] = 000_0010 ((900R – 4R ) / 900R) * VSPR
VHP4 [6:0] = 000_0011 ((900R – 6R ) / 900R) * VSPR
VHP4 [6:0] = 000_0100 ((900R – 8R ) / 900R) * VSPR
VHP4 [6:0] = 000_0101 ((900R - 10R ) / 900R) * VSPR
•• ••
VHP4 [6:0] = 100_0001 ((900R - 130R ) / 900R) * VSPR
VHP4 [6:0] = 100_0010 ((900R - 132R ) / 900R) * VSPR
VinP7
VHP4 [6:0] = 100_0011 ((900R – 134R ) / 900R) * VSPR
VHP4 [6:0] = 100_0100 ((900R – 136R ) / 900R) * VSPR
VHP4 [6:0] = 100_0101 ((900R – 138R ) / 900R) * VSPR
•• ••
VHP4 [6:0] = 111_1011 ((900R – 246R ) / 900R) * VSPR
VHP4 [6:0] = 111_1100 ((900R – 248R ) / 900R) * VSPR
VHP4 [6:0] = 111_1101 ((900R – 250R ) / 900R) * VSPR
VHP4 [6:0] = 111_1110 ((900R - 252R ) / 900R) * VSPR
VHP4 [6:0] = 111_1111 ((900R - 254R ) / 900R) * VSPR
Table 5.11: VinP7
Reference
voltage
VHP5 [6:0] = 000_0000 VSPR
VHP5 [6:0] = 000_0001 ((900R - 2R ) / 900R) * VSPR
VHP5 [6:0] = 000_0010 ((900R – 4R ) / 900R) * VSPR
VHP5 [6:0] = 000_0011 ((900R – 6R ) / 900R) * VSPR
VHP5 [6:0] = 000_0100 ((900R – 8R ) / 900R) * VSPR
VHP5 [6:0] = 000_0101 ((900R - 10R ) / 900R) * VSPR
•• ••
VHP5 [6:0] = 100_0001 ((900R - 130R ) / 900R) * VSPR
VHP5 [6:0] = 100_0010 ((900R - 132R ) / 900R) * VSPR
VinP9
VHP5 [6:0] = 100_0011 ((900R – 134R ) / 900R) * VSPR
VHP5 [6:0] = 100_0100 ((900R – 136R ) / 900R) * VSPR
VHP5 [6:0] = 100_0101 ((900R – 138R ) / 900R) * VSPR
•• ••
VHP5 [6:0] = 111_1011 ((900R – 246R ) / 900R) * VSPR
VHP5 [6:0] = 111_1100 ((900R – 248R ) / 900R) * VSPR
VHP5 [6:0] = 111_1101 ((900R – 250R ) / 900R) * VSPR
VHP5 [6:0] = 111_1110 ((900R - 252R ) / 900R) * VSPR
VHP5 [6:0] = 111_1111 ((900R - 254R ) / 900R) * VSPR
Table 5.12: VinP9

HX8394-F
Reference
voltage
VHP6 [6:0] = 000_0000 VSPR
VHP6 [6:0] = 000_0001 ((900R - 2R ) / 900R) * VSPR
VHP6 [6:0] = 000_0010 ((900R – 4R ) / 900R) * VSPR
VHP6 [6:0] = 000_0011 ((900R – 6R ) / 900R) * VSPR
VHP6 [6:0] = 000_0100 ((900R – 8R ) / 900R) * VSPR
VHP6 [6:0] = 000_0101 ((900R - 10R ) / 900R) * VSPR
•• ••
VHP6 [6:0] = 100_0001 ((900R - 130R ) / 900R) * VSPR
VHP6 [6:0] = 100_0010 ((900R - 132R ) / 900R) * VSPR
VinP12
VHP6 [6:0] = 100_0011 ((900R – 134R ) / 900R) * VSPR
VHP6 [6:0] = 100_0100 ((900R – 136R ) / 900R) * VSPR
VHP6 [6:0] = 100_0101 ((900R – 138R ) / 900R) * VSPR
•• ••
VHP6 [6:0] = 111_1011 ((900R – 246R ) / 900R) * VSPR
VHP6 [6:0] = 111_1100 ((900R – 248R ) / 900R) * VSPR
VHP6 [6:0] = 111_1101 ((900R – 250R ) / 900R) * VSPR
VHP6 [6:0] = 111_1110 ((900R - 252R ) / 900R) * VSPR
VHP6 [6:0] = 111_1111 ((900R - 254R ) / 900R) * VSPR
Table 5.13: VinP12
Reference
voltage
VHP7 [6:0] = 000_0000 ((900R - 27R ) / 900R) * VSPR
VHP7 [6:0] = 000_0001 ((900R – 29R ) / 900R) * VSPR
VHP7 [6:0] = 000_0010 ((900R – 31R ) / 900R) * VSPR
VHP7 [6:0] = 000_0011 ((900R – 33R ) / 900R) * VSPR
VHP7 [6:0] = 000_0100 ((900R – 35R ) / 900R) * VSPR
VHP7 [6:0] = 000_0101 ((900R - 37R ) / 900R) * VSPR
•• ••
VHP7 [6:0] = 100_0001 ((900R – 157R ) / 900R) * VSPR
VHP7 [6:0] = 100_0010 ((900R – 159R ) / 900R) * VSPR
VinP15
VHP7 [6:0] = 100_0011 ((900R – 161R ) / 900R) * VSPR
VHP7 [6:0] = 100_0100 ((900R – 163R ) / 900R) * VSPR
VHP7 [6:0] = 100_0101 ((900R – 165R ) / 900R) * VSPR
•• ••
VHP7 [6:0] = 111_1011 ((900R – 273R ) / 900R) * VSPR
VHP7 [6:0] = 111_1100 ((900R – 275R ) / 900R) * VSPR
VHP7 [6:0] = 111_1101 ((900R – 277R ) / 900R) * VSPR
VHP7 [6:0] = 111_1110 ((900R – 279R ) / 900R) * VSPR
VHP7 [6:0] = 111_1111 ((900R - 281R ) / 900R) * VSPR
Table 5.14: VinP15
Reference
voltage
VMP0 [7:0] = 0000_0000 ((900R – 82R ) / 900R) * VSPR
VMP0 [7:0] = 0000_0001 ((900R – 83R ) / 900R) * VSPR
VMP0 [7:0] = 0000_0010 ((900R – 84R ) / 900R) * VSPR
VMP0 [7:0] = 0000_0011 ((900R – 85R ) / 900R) * VSPR
VMP0 [7:0] = 0000_0100 ((900R – 86R ) / 900R) * VSPR
VMP0 [7:0] = 0000_0101 ((900R – 87R ) / 900R) * VSPR
•• ••
VMP0 [7:0] = 1000_0001 ((900R – 211R ) / 900R) * VSPR
VMP0 [7:0] = 1000_0010 ((900R – 212R ) / 900R) * VSPR
VinP20
VMP0 [7:0] = 1000_0011 ((900R – 213R ) / 900R) * VSPR
VMP0 [7:0] = 1000_0100 ((900R – 214R ) / 900R) * VSPR
VMP0 [7:0] = 1000_0101 ((900R – 215R ) / 900R) * VSPR
•• ••
VMP0 [7:0] = 1111_1011 ((900R – 333R ) / 900R) * VSPR
VMP0 [7:0] = 1111_1100 ((900R – 334R ) / 900R) * VSPR
VMP0 [7:0] = 1111_1101 ((900R – 335R ) / 900R) * VSPR
VMP0 [7:0] = 1111_1110 ((900R – 336R ) / 900R) * VSPR
VMP0 [7:0] = 1111_1111 ((900R – 337R ) / 900R) * VSPR
Table 5.15: VinP20

HX8394-F
Reference
voltage
VMP1 [7:0] = 0000_0000 ((900R – 118R ) / 900R) * VSPR
VMP1 [7:0] = 0000_0001 ((900R – 119R ) / 900R) * VSPR
VMP1 [7:0] = 0000_0010 ((900R – 120R ) / 900R) * VSPR
VMP1 [7:0] = 0000_0011 ((900R – 121R ) / 900R) * VSPR
VMP1 [7:0] = 0000_0100 ((900R – 122R ) / 900R) * VSPR
VMP1 [7:0] = 0000_0101 ((900R – 123R ) / 900R) * VSPR
•• ••
VMP1 [7:0] = 1000_0001 ((900R – 247R ) / 900R) * VSPR
VMP1 [7:0] = 1000_0010 ((900R – 248R ) / 900R) * VSPR
VinP28
VMP1 [7:0] = 1000_0011 ((900R – 249R ) / 900R) * VSPR
VMP1 [7:0] = 1000_0100 ((900R – 250R ) / 900R) * VSPR
VMP1 [7:0] = 1000_0101 ((900R – 251R ) / 900R) * VSPR
•• ••
VMP1 [7:0] = 1111_1011 ((900R – 369R ) / 900R) * VSPR
VMP1 [7:0] = 1111_1100 ((900R – 370R ) / 900R) * VSPR
VMP1 [7:0] = 1111_1101 ((900R – 371R ) / 900R) * VSPR
VMP1 [7:0] = 1111_1110 ((900R – 372R ) / 900R) * VSPR
VMP1 [7:0] = 1111_1111 ((900R – 373R ) / 900R) * VSPR
Table 5.16: VinP28
Reference
voltage
VMP2 [7:0] = 0000_0000 ((900R – 162R ) / 900R) * VSPR
VMP2 [7:0] = 0000_0001 ((900R – 163R ) / 900R) * VSPR
VMP2 [7:0] = 0000_0010 ((900R – 164R ) / 900R) * VSPR
VMP2 [7:0] = 0000_0011 ((900R – 165R ) / 900R) * VSPR
VMP2 [7:0] = 0000_0100 ((900R – 166R ) / 900R) * VSPR
VMP2 [7:0] = 0000_0101 ((900R – 167R ) / 900R) * VSPR
•• ••
VMP2 [7:0] = 1000_0001 ((900R – 291R ) / 900R) * VSPR
VMP2 [7:0] = 1000_0010 ((900R – 292R ) / 900R) * VSPR
VinP40
VMP2 [7:0] = 1000_0011 ((900R – 293R ) / 900R) * VSPR
VMP2 [7:0] = 1000_0100 ((900R – 294R ) / 900R) * VSPR
VMP2 [7:0] = 1000_0101 ((900R – 295R ) / 900R) * VSPR
•• ••
VMP2 [7:0] = 1111_1011 ((900R – 413R ) / 900R) * VSPR
VMP2 [7:0] = 1111_1100 ((900R – 414R ) / 900R) * VSPR
VMP2 [7:0] = 1111_1101 ((900R – 415R ) / 900R) * VSPR
VMP2 [7:0] = 1111_1110 ((900R – 416R ) / 900R) * VSPR
VMP2 [7:0] = 1111_1111 ((900R – 417R ) / 900R) * VSPR
Table 5.17: VinP40
Reference
voltage
VMP3 [7:0] = 0000_0000 ((900R – 198R ) / 900R) * VSPR
VMP3 [7:0] = 0000_0001 ((900R – 199R ) / 900R) * VSPR
VMP3 [7:0] = 0000_0010 ((900R – 200R ) / 900R) * VSPR
VMP3 [7:0] = 0000_0011 ((900R – 201R ) / 900R) * VSPR
VMP3 [7:0] = 0000_0100 ((900R – 202R ) / 900R) * VSPR
VMP3 [7:0] = 0000_0101 ((900R – 203R ) / 900R) * VSPR
•• ••
VMP3 [7:0] = 1000_0001 ((900R – 327R ) / 900R) * VSPR
VMP3 [7:0] = 1000_0010 ((900R – 328R ) / 900R) * VSPR
VinP52
VMP3 [7:0] = 1000_0011 ((900R – 329R ) / 900R) * VSPR
VMP3 [7:0] = 1000_0100 ((900R – 330R ) / 900R) * VSPR
VMP3 [7:0] = 1000_0101 ((900R – 331R ) / 900R) * VSPR
•• ••
VMP3 [7:0] = 1111_1011 ((900R – 449R ) / 900R) * VSPR
VMP3 [7:0] = 1111_1100 ((900R – 450R ) / 900R) * VSPR
VMP3 [7:0] = 1111_1101 ((900R – 451R ) / 900R) * VSPR
VMP3 [7:0] = 1111_1110 ((900R – 452R ) / 900R) * VSPR
VMP3 [7:0] = 1111_1111 ((900R – 453R ) / 900R) * VSPR
Table 5.18: VinP52

HX8394-F
Reference
voltage
VMP4 [7:0] = 0000_0000 ((900R – 258R ) / 900R) * VSPR
VMP4 [7:0] = 0000_0001 ((900R – 259R ) / 900R) * VSPR
VMP4 [7:0] = 0000_0010 ((900R – 260R ) / 900R) * VSPR
VMP4 [7:0] = 0000_0011 ((900R – 261R ) / 900R) * VSPR
VMP4 [7:0] = 0000_0100 ((900R – 262R ) / 900R) * VSPR
VMP4 [7:0] = 0000_0101 ((900R – 263R ) / 900R) * VSPR
•• ••
VMP4 [7:0] = 1000_0001 ((900R – 387R ) / 900R) * VSPR
VMP4 [7:0] = 1000_0010 ((900R – 388R ) / 900R) * VSPR
VinP76
VMP4 [7:0] = 1000_0011 ((900R – 389R ) / 900R) * VSPR
VMP4 [7:0] = 1000_0100 ((900R – 390R ) / 900R) * VSPR
VMP4 [7:0] = 1000_0101 ((900R – 391R ) / 900R) * VSPR
•• ••
VMP4 [7:0] = 1111_1011 ((900R – 509R ) / 900R) * VSPR
VMP4 [7:0] = 1111_1100 ((900R – 510R ) / 900R) * VSPR
VMP4 [7:0] = 1111_1101 ((900R – 511R ) / 900R) * VSPR
VMP4 [7:0] = 1111_1110 ((900R – 512R ) / 900R) * VSPR
VMP4 [7:0] = 1111_1111 ((900R – 513R ) / 900R) * VSPR
Table 5.19: VinP76
Reference
voltage
VMP5 [7:0] = 0000_0000 ((900R – 302R ) / 900R) * VSPR
VMP5 [7:0] = 0000_0001 ((900R – 303R ) / 900R) * VSPR
VMP5 [7:0] = 0000_0010 ((900R – 304R ) / 900R) * VSPR
VMP5 [7:0] = 0000_0011 ((900R – 305R ) / 900R) * VSPR
VMP5 [7:0] = 0000_0100 ((900R – 306R ) / 900R) * VSPR
VMP5 [7:0] = 0000_0101 ((900R – 307R ) / 900R) * VSPR
•• ••
VMP5 [7:0] = 1000_0001 ((900R – 431R ) / 900R) * VSPR
VMP5 [7:0] = 1000_0010 ((900R – 432R ) / 900R) * VSPR
VinP100
VMP5 [7:0] = 1000_0011 ((900R – 433R ) / 900R) * VSPR
VMP5 [7:0] = 1000_0100 ((900R – 434R ) / 900R) * VSPR
VMP5 [7:0] = 1000_0101 ((900R – 435R ) / 900R) * VSPR
•• ••
VMP5 [7:0] = 1111_1011 ((900R – 553R ) / 900R) * VSPR
VMP5 [7:0] = 1111_1100 ((900R – 554R ) / 900R) * VSPR
VMP5 [7:0] = 1111_1101 ((900R – 555R ) / 900R) * VSPR
VMP5 [7:0] = 1111_1110 ((900R – 556R ) / 900R) * VSPR
VMP5 [7:0] = 1111_1111 ((900R – 557R ) / 900R) * VSPR
Table 5.20: VinP100
Reference
voltage
VMP6 [7:0] = 0000_0000 ((900R – 356R ) / 900R) * VSPR
VMP6 [7:0] = 0000_0001 ((900R – 357R ) / 900R) * VSPR
VMP6 [7:0] = 0000_0010 ((900R – 358R ) / 900R) * VSPR
VMP6 [7:0] = 0000_0011 ((900R – 359R ) / 900R) * VSPR
VMP6 [7:0] = 0000_0100 ((900R – 360R ) / 900R) * VSPR
VMP6 [7:0] = 0000_0101 ((900R – 361R ) / 900R) * VSPR
•• ••
VMP6 [7:0] = 1000_0001 ((900R – 485R ) / 900R) * VSPR
VMP6 [7:0] = 1000_0010 ((900R – 486R ) / 900R) * VSPR
VinP128
VMP6 [7:0] = 1000_0011 ((900R – 487R ) / 900R) * VSPR
VMP6 [7:0] = 1000_0100 ((900R – 488R ) / 900R) * VSPR
VMP6 [7:0] = 1000_0101 ((900R – 489R ) / 900R) * VSPR
•• ••
VMP6 [7:0] = 1111_1011 ((900R – 607R ) / 900R) * VSPR
VMP6 [7:0] = 1111_1100 ((900R – 608R ) / 900R) * VSPR
VMP6 [7:0] = 1111_1101 ((900R – 609R ) / 900R) * VSPR
VMP6 [7:0] = 1111_1110 ((900R – 610R ) / 900R) * VSPR
VMP6 [7:0] = 1111_1111 ((900R – 611R ) / 900R) * VSPR
Table 5.21: VinP128
HX8394-F
Reference
voltage
VMP7 [7:0] = 0000_0000 ((900R – 390R ) / 900R) * VSPR
VMP7 [7:0] = 0000_0001 ((900R – 391R ) / 900R) * VSPR
VMP7 [7:0] = 0000_0010 ((900R – 392R ) / 900R) * VSPR
VMP7 [7:0] = 0000_0011 ((900R – 393R ) / 900R) * VSPR
VMP7 [7:0] = 0000_0100 ((900R – 394R ) / 900R) * VSPR
VMP7 [7:0] = 0000_0101 ((900R – 395R ) / 900R) * VSPR
•• ••
VMP7 [7:0] = 1000_0001 ((900R – 519R ) / 900R) * VSPR
VMP7 [7:0] = 1000_0010 ((900R – 520R ) / 900R) * VSPR
VinP156
VMP7 [7:0] = 1000_0011 ((900R – 521R ) / 900R) * VSPR
VMP7 [7:0] = 1000_0100 ((900R – 522R ) / 900R) * VSPR
VMP7 [7:0] = 1000_0101 ((900R – 523R ) / 900R) * VSPR
•• ••
VMP7 [7:0] = 1111_1011 ((900R – 641R ) / 900R) * VSPR
VMP7 [7:0] = 1111_1100 ((900R – 642R ) / 900R) * VSPR
VMP7 [7:0] = 1111_1101 ((900R – 643R ) / 900R) * VSPR
VMP7 [7:0] = 1111_1110 ((900R – 644R ) / 900R) * VSPR
VMP7 [7:0] = 1111_1111 ((900R – 645R ) / 900R) * VSPR
Table 5.22: VinP156
Reference
voltage
VMP8 [7:0] = 0000_0000 ((900R – 432R ) / 900R) * VSPR
VMP8 [7:0] = 0000_0001 ((900R – 433R ) / 900R) * VSPR
VMP8 [7:0] = 0000_0010 ((900R – 434R ) / 900R) * VSPR
VMP8 [7:0] = 0000_0011 ((900R – 435R ) / 900R) * VSPR
VMP8 [7:0] = 0000_0100 ((900R – 436R ) / 900R) * VSPR
VMP8 [7:0] = 0000_0101 ((900R – 437R ) / 900R) * VSPR
•• ••
VMP8 [7:0] = 1000_0001 ((900R – 561R ) / 900R) * VSPR
VMP8 [7:0] = 1000_0010 ((900R – 562R ) / 900R) * VSPR
VinP180
VMP8 [7:0] = 1000_0011 ((900R – 563R ) / 900R) * VSPR
VMP8 [7:0] = 1000_0100 ((900R – 564R ) / 900R) * VSPR
VMP8 [7:0] = 1000_0101 ((900R – 565R ) / 900R) * VSPR
•• ••
VMP8 [7:0] = 1111_1011 ((900R – 683R ) / 900R) * VSPR
VMP8 [7:0] = 1111_1100 ((900R – 684R ) / 900R) * VSPR
VMP8 [7:0] = 1111_1101 ((900R – 685R ) / 900R) * VSPR
VMP8 [7:0] = 1111_1110 ((900R – 686R ) / 900R) * VSPR
VMP8 [7:0] = 1111_1111 ((900R – 687R ) / 900R) * VSPR
Table 5.23: VinP180
Reference
voltage
VMP9 [7:0] = 0000_0000 ((900R – 478R ) / 900R) * VSPR
VMP9 [7:0] = 0000_0001 ((900R – 479R ) / 900R) * VSPR
VMP9 [7:0] = 0000_0010 ((900R – 480R ) / 900R) * VSPR
VMP9 [7:0] = 0000_0011 ((900R – 481R ) / 900R) * VSPR
VMP9 [7:0] = 0000_0100 ((900R – 482R ) / 900R) * VSPR
VMP9 [7:0] = 0000_0101 ((900R – 483R ) / 900R) * VSPR
•• ••
VMP9 [7:0] = 1000_0001 ((900R – 607R ) / 900R) * VSPR
VMP9 [7:0] = 1000_0010 ((900R – 608R ) / 900R) * VSPR
VinP204
VMP9 [7:0] = 1000_0011 ((900R – 609R ) / 900R) * VSPR
VMP9 [7:0] = 1000_0100 ((900R – 610R ) / 900R) * VSPR
VMP9 [7:0] = 1000_0101 ((900R – 611R ) / 900R) * VSPR
•• ••
VMP9 [7:0] = 1111_1011 ((900R – 729R ) / 900R) * VSPR
VMP9 [7:0] = 1111_1100 ((900R – 730R ) / 900R) * VSPR
VMP9 [7:0] = 1111_1101 ((900R – 731R ) / 900R) * VSPR
VMP9 [7:0] = 1111_1110 ((900R – 732R ) / 900R) * VSPR
VMP9 [7:0] = 1111_1111 ((900R – 733R ) / 900R) * VSPR
Table 5.24: VinP204

HX8394-F
Reference
voltage
VMP10 [7:0] = 0000_0000 ((900R – 506R ) / 900R) * VSPR
VMP10 [7:0] = 0000_0001 ((900R – 507R ) / 900R) * VSPR
VMP10 [7:0] = 0000_0010 ((900R – 508R ) / 900R) * VSPR
VMP10 [7:0] = 0000_0011 ((900R – 509R ) / 900R) * VSPR
VMP10 [7:0] = 0000_0100 ((900R – 510R ) / 900R) * VSPR
VMP10 [7:0] = 0000_0101 ((900R – 511R ) / 900R) * VSPR
•• ••
VMP10 [7:0] = 1000_0001 ((900R – 635R ) / 900R) * VSPR
VMP10 [7:0] = 1000_0010 ((900R – 636R ) / 900R) * VSPR
VinP216
VMP10 [7:0] = 1000_0011 ((900R – 637R ) / 900R) * VSPR
VMP10 [7:0] = 1000_0100 ((900R – 638R ) / 900R) * VSPR
VMP10 [7:0] = 1000_0101 ((900R – 639R ) / 900R) * VSPR
•• ••
VMP10 [7:0] = 1111_1011 ((900R – 757R ) / 900R) * VSPR
VMP10 [7:0] = 1111_1100 ((900R – 758R ) / 900R) * VSPR
VMP10 [7:0] = 1111_1101 ((900R – 759R ) / 900R) * VSPR
VMP10 [7:0] = 1111_1110 ((900R – 760R ) / 900R) * VSPR
VMP10 [7:0] = 1111_1111 ((900R – 761R ) / 900R) * VSPR
Table 5.25: VinP216
Reference
voltage
VMP11 [7:0] = 0000_0000 ((900R – 544R ) / 900R) * VSPR
VMP11 [7:0] = 0000_0001 ((900R – 545R ) / 900R) * VSPR
VMP11 [7:0] = 0000_0010 ((900R – 546R ) / 900R) * VSPR
VMP11 [7:0] = 0000_0011 ((900R – 547R ) / 900R) * VSPR
VMP11 [7:0] = 0000_0100 ((900R – 548R ) / 900R) * VSPR
VMP11 [7:0] = 0000_0101 ((900R – 549R ) / 900R) * VSPR
•• ••
VMP11 [7:0] = 1000_0001 ((900R – 673R ) / 900R) * VSPR
VMP11 [7:0] = 1000_0010 ((900R – 674R ) / 900R) * VSPR
VinP228
VMP11 [7:0] = 1000_0011 ((900R – 675R ) / 900R) * VSPR
VMP11 [7:0] = 1000_0100 ((900R – 676R ) / 900R) * VSPR
VMP11 [7:0] = 1000_0101 ((900R – 677R ) / 900R) * VSPR
•• ••
VMP11 [7:0] = 1111_1011 ((900R – 795R ) / 900R) * VSPR
VMP11 [7:0] = 1111_1100 ((900R – 796R ) / 900R) * VSPR
VMP11 [7:0] = 1111_1101 ((900R – 797R ) / 900R) * VSPR
VMP11 [7:0] = 1111_1110 ((900R – 798R ) / 900R) * VSPR
VMP11 [7:0] = 1111_1111 ((900R – 799R ) / 900R) * VSPR
Table 5.26: VinP228
Reference
voltage
VMP12 [7:0] = 0000_0000 ((900R – 572R ) / 900R) * VSPR
VMP12 [7:0] = 0000_0001 ((900R – 573R ) / 900R) * VSPR
VMP12 [7:0] = 0000_0010 ((900R – 574R ) / 900R) * VSPR
VMP12 [7:0] = 0000_0011 ((900R – 575R ) / 900R) * VSPR
VMP12 [7:0] = 0000_0100 ((900R – 576R ) / 900R) * VSPR
VMP12 [7:0] = 0000_0101 ((900R – 577R ) / 900R) * VSPR
•• ••
VMP12 [7:0] = 1000_0001 ((900R – 701R ) / 900R) * VSPR
VMP12 [7:0] = 1000_0010 ((900R – 702R ) / 900R) * VSPR
VinP236
VMP12 [7:0] = 1000_0011 ((900R – 703R ) / 900R) * VSPR
VMP12 [7:0] = 1000_0100 ((900R – 704R ) / 900R) * VSPR
VMP12 [7:0] = 1000_0101 ((900R – 705R ) / 900R) * VSPR
•• ••
VMP12 [7:0] = 1111_1011 ((900R – 823R ) / 900R) * VSPR
VMP12 [7:0] = 1111_1100 ((900R – 824R ) / 900R) * VSPR
VMP12 [7:0] = 1111_1101 ((900R – 825R ) / 900R) * VSPR
VMP12 [7:0] = 1111_1110 ((900R – 826R ) / 900R) * VSPR
VMP12 [7:0] = 1111_1111 ((900R – 827R ) / 900R) * VSPR
Table 5.27: VinP236

HX8394-F
Reference
voltage
VLP0 [6:0] = 000_0000 ((900R – 624R ) / 900R) * VSPR
VLP0 [6:0] = 000_0001 ((900R – 626R ) / 900R) * VSPR
VLP0 [6:0] = 000_0010 ((900R – 628R ) / 900R) * VSPR
VLP0 [6:0] = 000_0011 ((900R – 630R ) / 900R) * VSPR
VLP0 [6:0] = 000_0100 ((900R – 632R ) / 900R) * VSPR
VLP0 [6:0] = 000_0101 ((900R – 634R ) / 900R) * VSPR
•• ••
VLP0 [6:0] = 100_0001 ((900R – 754R ) / 900R) * VSPR
VLP0 [6:0] = 100_0010 ((900R – 756R ) / 900R) * VSPR
VinP240
VLP0 [6:0] = 100_0011 ((900R – 758R ) / 900R) * VSPR
VLP0 [6:0] = 100_0100 ((900R – 760R ) / 900R) * VSPR
VLP0 [6:0] = 100_0101 ((900R – 762R ) / 900R) * VSPR
•• ••
VLP0 [6:0] = 111_1011 ((900R – 870R ) / 900R) * VSPR
VLP0 [6:0] = 111_1100 ((900R – 872R ) / 900R) * VSPR
VLP0 [6:0] = 111_1101 ((900R – 874R ) / 900R) * VSPR
VLP0 [6:0] = 111_1110 ((900R – 876R ) / 900R) * VSPR
VLP0 [6:0] = 111_1111 ((900R – 878R ) / 900R) * VSPR
Table 5.28: VinP240
Reference
voltage
VLP1 [6:0] = 000_0000 ((900R – 624R ) / 900R) * VSPR
VLP1 [6:0] = 000_0001 ((900R – 626R ) / 900R) * VSPR
VLP1 [6:0] = 000_0010 ((900R – 628R ) / 900R) * VSPR
VLP1 [6:0] = 000_0011 ((900R – 630R ) / 900R) * VSPR
VLP1 [6:0] = 000_0100 ((900R – 632R ) / 900R) * VSPR
VLP1 [6:0] = 000_0101 ((900R – 634R ) / 900R) * VSPR
•• ••
VLP1 [6:0] = 100_0001 ((900R – 754R ) / 900R) * VSPR
VLP1 [6:0] = 100_0010 ((900R – 756R ) / 900R) * VSPR
VinP243
VLP1 [6:0] = 100_0011 ((900R – 758R ) / 900R) * VSPR
VLP1 [6:0] = 100_0100 ((900R – 760R ) / 900R) * VSPR
VLP1 [6:0] = 100_0101 ((900R – 762R ) / 900R) * VSPR
•• ••
VLP1 [6:0] = 111_1011 ((900R – 870R ) / 900R) * VSPR
VLP1 [6:0] = 111_1100 ((900R – 872R ) / 900R) * VSPR
VLP1 [6:0] = 111_1101 ((900R – 874R ) / 900R) * VSPR
VLP1 [6:0] = 111_1110 ((900R – 876R ) / 900R) * VSPR
VLP1 [6:0] = 111_1111 ((900R – 878R ) / 900R) * VSPR
Table 5.29: VinP243
Reference
voltage
VLP2 [6:0] = 000_0000 ((900R – 646R ) / 900R) * VSPR
VLP2 [6:0] = 000_0001 ((900R – 648R ) / 900R) * VSPR
VLP2 [6:0] = 000_0010 ((900R – 650R ) / 900R) * VSPR
VLP2 [6:0] = 000_0011 ((900R – 652R ) / 900R) * VSPR
VLP2 [6:0] = 000_0100 ((900R – 654R ) / 900R) * VSPR
VLP2 [6:0] = 000_0101 ((900R – 656R ) / 900R) * VSPR
•• ••
VLP2 [6:0] = 100_0001 ((900R – 776R ) / 900R) * VSPR
VLP2 [6:0] = 100_0010 ((900R – 778R ) / 900R) * VSPR
VinP246
VLP2 [6:0] = 100_0011 ((900R – 780R ) / 900R) * VSPR
VLP2 [6:0] = 100_0100 ((900R – 782R ) / 900R) * VSPR
VLP2 [6:0] = 100_0101 ((900R – 784R ) / 900R) * VSPR
•• ••
VLP2 [6:0] = 111_1011 ((900R – 892R ) / 900R) * VSPR
VLP2 [6:0] = 111_1100 ((900R – 894R ) / 900R) * VSPR
VLP2 [6:0] = 111_1101 ((900R – 896R ) / 900R) * VSPR
VLP2 [6:0] = 111_1110 ((900R – 898R ) / 900R) * VSPR
VLP2 [6:0] = 111_1111 ((900R –900R ) / 900R) * VSPR
Table 5.30: VinP246

HX8394-F
Reference
voltage
VLP3 [6:0] = 000_0000 ((900R – 646R ) / 900R) * VSPR
VLP3 [6:0] = 000_0001 ((900R – 648R ) / 900R) * VSPR
VLP3 [6:0] = 000_0010 ((900R – 650R ) / 900R) * VSPR
VLP3 [6:0] = 000_0011 ((900R – 652R ) / 900R) * VSPR
VLP3 [6:0] = 000_0100 ((900R – 654R ) / 900R) * VSPR
VLP3 [6:0] = 000_0101 ((900R – 656R ) / 900R) * VSPR
•• ••
VLP3 [6:0] = 100_0001 ((900R – 776R ) / 900R) * VSPR
VLP3 [6:0] = 100_0010 ((900R – 778R ) / 900R) * VSPR
VinP248
VLP3 [6:0] = 100_0011 ((900R – 780R ) / 900R) * VSPR
VLP3 [6:0] = 100_0100 ((900R – 782R ) / 900R) * VSPR
VLP3 [6:0] = 100_0101 ((900R – 784R ) / 900R) * VSPR
•• ••
VLP3 [6:0] = 111_1011 ((900R – 892R ) / 900R) * VSPR
VLP3 [6:0] = 111_1100 ((900R – 894R ) / 900R) * VSPR
VLP3 [6:0] = 111_1101 ((900R – 896R ) / 900R) * VSPR
VLP3 [6:0] = 111_1110 ((900R – 898R ) / 900R) * VSPR
VLP3 [6:0] = 111_1111 ((900R –900R ) / 900R) * VSPR
Table 5.31: VinP248
Reference
voltage
VLP4 [6:0] = 000_0000 ((900R – 646R ) / 900R) * VSPR
VLP4 [6:0] = 000_0001 ((900R – 648R ) / 900R) * VSPR
VLP4 [6:0] = 000_0010 ((900R – 650R ) / 900R) * VSPR
VLP4 [6:0] = 000_0011 ((900R – 652R ) / 900R) * VSPR
VLP4 [6:0] = 000_0100 ((900R – 654R ) / 900R) * VSPR
VLP4 [6:0] = 000_0101 ((900R – 656R ) / 900R) * VSPR
•• ••
VLP4 [6:0] = 100_0001 ((900R – 776R ) / 900R) * VSPR
VLP4 [6:0] = 100_0010 ((900R – 778R ) / 900R) * VSPR
VinP250
VLP4 [6:0] = 100_0011 ((900R – 780R ) / 900R) * VSPR
VLP4 [6:0] = 100_0100 ((900R – 782R ) / 900R) * VSPR
VLP4 [6:0] = 100_0101 ((900R – 784R ) / 900R) * VSPR
•• ••
VLP4 [6:0] = 111_1011 ((900R – 892R ) / 900R) * VSPR
VLP4 [6:0] = 111_1100 ((900R – 894R ) / 900R) * VSPR
VLP4 [6:0] = 111_1101 ((900R – 896R ) / 900R) * VSPR
VLP4 [6:0] = 111_1110 ((900R – 898R ) / 900R) * VSPR
VLP4 [6:0] = 111_1111 ((900R –900R ) / 900R) * VSPR
Table 5.32: VinP250
Reference
voltage
VLP5 [6:0] = 000_0000 ((900R – 646R ) / 900R) * VSPR
VLP5 [6:0] = 000_0001 ((900R – 648R ) / 900R) * VSPR
VLP5 [6:0] = 000_0010 ((900R – 650R ) / 900R) * VSPR
VLP5 [6:0] = 000_0011 ((900R – 652R ) / 900R) * VSPR
VLP5 [6:0] = 000_0100 ((900R – 654R ) / 900R) * VSPR
VLP5 [6:0] = 000_0101 ((900R – 656R ) / 900R) * VSPR
•• ••
VLP5 [6:0] = 100_0001 ((900R – 776R ) / 900R) * VSPR
VLP5 [6:0] = 100_0010 ((900R – 778R ) / 900R) * VSPR
VinP252
VLP5 [6:0] = 100_0011 ((900R – 780R ) / 900R) * VSPR
VLP5 [6:0] = 100_0100 ((900R – 782R ) / 900R) * VSPR
VLP5 [6:0] = 100_0101 ((900R – 784R ) / 900R) * VSPR
•• ••
VLP5 [6:0] = 111_1011 ((900R – 892R ) / 900R) * VSPR
VLP5 [6:0] = 111_1100 ((900R – 894R ) / 900R) * VSPR
VLP5 [6:0] = 111_1101 ((900R – 896R ) / 900R) * VSPR
VLP5 [6:0] = 111_1110 ((900R – 898R ) / 900R) * VSPR
VLP5 [6:0] = 111_1111 ((900R –900R ) / 900R) * VSPR
Table 5.33: VinP252

HX8394-F
Reference
voltage
VLP6 [6:0] = 000_0000 ((900R – 646R ) / 900R) * VSPR
VLP6 [6:0] = 000_0001 ((900R – 648R ) / 900R) * VSPR
VLP6 [6:0] = 000_0010 ((900R – 650R ) / 900R) * VSPR
VLP6 [6:0] = 000_0011 ((900R – 652R ) / 900R) * VSPR
VLP6 [6:0] = 000_0100 ((900R – 654R ) / 900R) * VSPR
VLP6 [6:0] = 000_0101 ((900R – 656R ) / 900R) * VSPR
•• ••
VLP6 [6:0] = 100_0001 ((900R – 776R ) / 900R) * VSPR
VLP6 [6:0] = 100_0010 ((900R – 778R ) / 900R) * VSPR
VinP254
VLP6 [6:0] = 100_0011 ((900R – 780R ) / 900R) * VSPR
VLP6 [6:0] = 100_0100 ((900R – 782R ) / 900R) * VSPR
VLP6 [6:0] = 100_0101 ((900R – 784R ) / 900R) * VSPR
•• ••
VLP6 [6:0] = 111_1011 ((900R – 892R ) / 900R) * VSPR
VLP6 [6:0] = 111_1100 ((900R – 894R ) / 900R) * VSPR
VLP6 [6:0] = 111_1101 ((900R – 896R ) / 900R) * VSPR
VLP6 [6:0] = 111_1110 ((900R – 898R ) / 900R) * VSPR
VLP6 [6:0] = 111_1111 ((900R –900R ) / 900R) * VSPR
Table 5.34: VinP254
Reference
voltage
VLP7 [6:0] = 000_0000 ((900R – 646R ) / 900R) * VSPR
VLP7 [6:0] = 000_0001 ((900R – 648R ) / 900R) * VSPR
VLP7 [6:0] = 000_0010 ((900R – 650R ) / 900R) * VSPR
VLP7 [6:0] = 000_0011 ((900R – 652R ) / 900R) * VSPR
VLP7 [6:0] = 000_0100 ((900R – 654R ) / 900R) * VSPR
VLP7 [6:0] = 000_0101 ((900R – 656R ) / 900R) * VSPR
•• ••
VLP7 [6:0] = 100_0001 ((900R – 776R ) / 900R) * VSPR
VLP7 [6:0] = 100_0010 ((900R – 778R ) / 900R) * VSPR
VinP255
VLP7 [6:0] = 100_0011 ((900R – 780R ) / 900R) * VSPR
VLP7 [6:0] = 100_0100 ((900R – 782R ) / 900R) * VSPR
VLP7 [6:0] = 100_0101 ((900R – 784R ) / 900R) * VSPR
•• ••
VLP7 [6:0] = 111_1011 ((900R – 892R ) / 900R) * VSPR
VLP7 [6:0] = 111_1100 ((900R – 894R ) / 900R) * VSPR
VLP7 [6:0] = 111_1101 ((900R – 896R ) / 900R) * VSPR
VLP7 [6:0] = 111_1110 ((900R – 898R ) / 900R) * VSPR
VLP7 [6:0] = 111_1111 ((900R –900R ) / 900R) * VSPR
Table 5.35: VinP255

HX8394-F
Grayscale Grayscale
Formula Formula
voltage voltage
V0 VinP/N0 V44 VinP/N40 - (VinP/N40 - VinP/N52)*(4R/12R)
V2 VinP/N0 - (VinP/N0 - VinP/N1)*(R/2R) V46 VinP/N40 - (VinP/N40 - VinP/N52)*(6R/12R)
V4 VinP/N3 - (VinP/N3 - VinP/N5)*(1R/2R) V48 VinP/N40 - (VinP/N40 - VinP/N52)*(8R/12R)
V8 VinP/N7 - (VinP/N7 - VinP/N9)*(1R/2R) V52 VinP/N52

HX8394-F
Grayscale Grayscale
Formula Formula
voltage voltage

HX8394-F
Grayscale Grayscale
Formula Formula
voltage voltage
Table 5.36: Voltage calculation formula of 256-grayscale voltage (positive/negative polarity)

HX8394-F
5.8.2 Gray voltage generator for digital gamma correction
The HX8394-F digital gamma correction can reach the independent GAMMA curve of
RGB. HX8394-F utilizes DGC_LUT (Digital Gamma Correction Look Up Table) to
change input data from 8-bit into 10-bit and sends 10-bit data to Dithering circuit, and
then drive Source Driver via Dithering circuit.
luminance of R
luminance of R
luminance of G
luminance of G
luminance of B
luminance of B
Figure 5.24: Block diagram of digital gamma correction
There are 126 bytes DGC LUT to set R, G, B gamma independently. When
DGC_EN=1, R, G, B gamma will mapping V0, V8, V16, ...., V240, V248, V255
voltage to the LUT register setting gray level voltage.
LUT D7 D6 D5 D4 D3 D2 D1 D0 Default
1st R009 R008 R007 R006 R005 R004 R003 R002 00h
2nd R019 R018 R017 R016 R015 R014 R013 R012 08h
3rd R029 R028 R027 R026 R025 R024 R023 R022 10h
: : : : : : : : : :
: : : : : : : : : :
32th R319 R318 R317 R316 R315 R314 R313 R312 F8h
33th R329 R328 R327 R326 R325 R324 R323 R322 FFh
34th R001 R000 R011 R010 R021 R020 R031 R030 00h
35th R041 R040 R051 R050 R061 R060 R071 R070 00h
: : : : : : : : : :
: : : : : : : : : :
41th R281 R280 R291 R290 R301 R300 R311 R310 00h
42th R321 R320 0 0 0 0 0 0 00h
43th G009 G008 G007 G006 G005 G004 G003 G002 00h
44th G019 G018 G017 G016 G015 G014 G013 G012 08h
45th G029 G028 G027 G026 G025 G024 G023 G022 10h
: : : : : : : : : :
: : : : : : : : : :
74th G319 G318 G317 G316 G315 G314 G313 G312 F8h
75th G329 G328 G327 G326 G325 G324 G323 G322 FFh
76th G001 G000 G011 G010 G021 G020 G031 G030 00h
77th G041 G040 G051 G050 G061 G060 G071 G070 00h
: : : : : : : : : :
: : : : : : : : : :
83th G281 G280 G291 G290 G301 G300 G311 G310 00h
84th G321 G320 0 0 0 0 0 0 00h
85th B009 B008 B007 B006 B005 B004 B003 B002 00h
86th B019 B018 B017 B016 B015 B014 B013 B012 08h
87th B029 B028 B027 B026 B025 B024 B023 B022 10h
: : : : : : : : : :
: : : : : : : : : :
116th B319 B318 B317 B316 B315 B314 B313 B312 F8h

HX8394-F
117th B329 B328 B327 B326 B325 B324 B323 B322 FFh
118th B001 B000 B011 B010 B021 B020 B031 B030 00h
119th B041 B040 B051 B050 B061 B060 B071 B070 00h
: : : : : : : : : :
: : : : : : : : : :
125th B281 B280 B291 B290 B301 B300 B311 B310 00h
126th B321 B320 0 0 0 0 0 0 00h
Table 5.37: DGC Look-up table

HX8394-F
5.9 Characteristics of I/O
5.9.1 Output or bi-directional (I/O) pins
Output or
After power on After hardware reset After software reset
bi-directional pins
TE Low Low Low
TE1 Low Low Low
SDO High-Z (Inactive) High-Z (Inactive) High-Z (Inactive)
CABC_PWM_OUT Low Low Low
Note: Please follow D9h GPO output setting.
Table 5.38: Characteristics of output or bi-directional (I/O) pins
5.9.2 Input pins
After After
During power After power During power
Input pins hardware software
on process on off process
reset reset
RESX Input invalid Input valid Input valid Input valid Input invalid
CSX Input invalid Input valid Input valid Input valid Input invalid
DCX Input invalid Input valid Input valid Input valid Input invalid
SCL Input invalid Input valid Input valid Input valid Input invalid
DB[23:0], SDI Input invalid Input valid Input valid Input valid Input invalid
HSYNC Input invalid Input valid Input valid Input valid Input invalid
VSYNC Input invalid Input valid Input valid Input valid Input invalid
PCLK Input invalid Input valid Input valid Input valid Input invalid
DE Input invalid Input valid Input valid Input valid Input invalid
OSC Input invalid Input valid Input valid Input valid Input invalid
TEST[2:0] Low Low Low Low Low
FRM Low Low Low Low Low
PCCS[1:0] Input invalid Input valid Input valid Input valid Input invalid
Table 5.39: Characteristics of input pins

HX8394-F
5.10 GIP control singal
HX8394-F is a single chip solution for a WXGA GIP (Gate In Panel) type TFT LCD
display. There are many GIP/ASG type TFT panels that correspond to different GIP
timing. Therefore, the GIP setting must be setup to the correct GIP/ASG timing for the
normal display. The GIP timing adjustment is related to register 0xD5h SETGIP.
The GIP control signals (CGOUT1_L/R ~ CGOUT22_L/R) are for panel used. The
assignment of each panel type is specified on the application note. Regarding the
GIP/ASG timing, please refer to HX8394-F application note.

HX8394-F
5.11Sleep Out –command and self-diagnostic functions of the display module
5.11.1 Register loading detection
Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the
display module, which indicates, if the display module loading function of factory
default values from OTP (or similar device) to registers of the display controller is
working properly. There are compared factory values of the OTP and register values
of the display controller by the display controller. If those both values (OTP and
register values) are same, there is inverted (=increased by 1) a bit, which is defined in
command “Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR) (The used bit of
this command is D7). If those both values are not same, this bit (D7) is not inverted
(=increased by 1).
The flow chart for this internal function is following:
Figure 5.25: Sleep out flow chart–command and self-diagnostic functions

HX8394-F
5.11.2 Functionality detection
Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the
display module, which indicates, if the display module is still running and meets
functionality requirements.
The internal function (=the display controller) is comparing, if the display module still
meets functionality requirements (e.g. booster voltage levels, timings, etc.). If
functionality requirement is met, 1 bit will be inverted (=increased by 1), which is
defined in command “Read Display Self- Diagnostic Result (0Fh)” (=RDDSDR) (The
used bit of this command is D6). If functionality requirement is not the same, this bit
(D6) is not inverted (=increased by 1). The flow chart for this internal function is
shown as below.
Power on sequence
Sleep In (10h) HW reset
SW reset
Sleep Out Sleep In

RDDSDR`s D6=0
Mode Mode
Sleep Out (11h)
Checks timings, voltage levels and other

functionalities
NO
Is functionality
requirement meet ?
YES
D6 inverted
Note: There is needed 120m sec. after Sleep Out –command, when there is changing from Sleep
In–mode toSleep Out –mode, before there is possible to check if Customer’s functionality
requirements are met and a value of RDDSDR’s D6 is valid. Otherwise, there is 5msec delay for
D6’s value, when Sleep Out –command is sent in Sleep Out –mode.
Figure 5.26: Sleep out flow chart internal function detection
HX8394-F
5.12 Power on/off sequence
The Power supply On/Off, Sleep In/Out and Display On/Off sequence is illustrated
below.
Figure 5.27: Power on/off sequence

HX8394-F
5.12.1 VDD1/VDD3 input power sequence (PCCS[1:0]=”01”, “10”)
VDD1 VDD1 on before VDD3 on

HS_VCC
VDD3 >1ms
≥10us
RESX
>1ms
Note: MIPI Data Lane and

CLK Lane must set LP11
before HW reset go high
MIPI Data & CLK lane
>50ms >120ms +/- no limit
MIPI Video Packet
Host Command
Initial SLPOUT Initial+DISPON
Note: SLPOUT CMD can before or after Initial code, but after SLPOUT CMD must wait at least 120ms
Figure 5.28: VDD1/VDD3 input power on sequence
VDD1
HS_VCC
+- no limit
VDD3
RESX ≥0us
MIPI Video Packet
≥0 frame
≥2 frame
Host Command
SLPIN
Figure 5.29: VDD1/VDD3 input power off sequence

HX8394-F
5.12.2 VDD1/VSP/VSN input power sequence (PCCS[1:0]=”11”)
VDD1
VSP
>1ms
VSP / VSN Hi-Z or GND
VSN >1ms
>10us
RESX
MIPI >1ms
Note : MIPI Data/CLK lane should be LP-11 state before RESX rising edge
Data/CLK
>50ms >0ms >120ms
Host CMD
Initial code SLPOUT DISPON
Video +- no limit
Packet
Figure 5.30: VDD1/ VSP/VSN input power on sequence
VDD1
HS_ VCC
≥0ms
VSP
Hi-Z or GND
≥0ms
Hi-Z or GND
VSN
RESX
≥0 us
MIPI Video Packet
≥ 0 frame
≥ 2 frame
Host Command
SLPIN
Figure 5.31: VDD1/VSP/VSN input power off sequence

HX8394-F
5.13 Uncontrolled power off
The uncontrolled power off means a situation when e.g. there is removed a battery
without the controlled power off sequence. There will not be any damages for the
display module or the display module will not cause any damages for the host or lines
of the interface. At an uncontrolled power off the display will go blank and there will
not be any visible effects within 1 second on the display (blank display) and remains
blank until “Power On Sequence” powers it up.
Note: HX8394-F is support the noise reject filter (20ns) to reject spike or noise.

HX8394-F
5.14Content adaptive brightness control (CABC) function
The general block diagram of the CABC and the brightness control is illustrated
below:
Figure 5.32: CABC block diagram

HX8394-F
5.14.1 Module architectures
HX8394-F can support two module architectures for CABC operation. The BL bit
setting of R53h can be used to select used display module architecture. White LED
driver circuit for display backlight is located on the main PWB, not in the display
module both in architecture I and II.
• Architecture I
• Architecture II
Figure 5.33: Module architecture

HX8394-F
5.14.2 CABC block
There are DBG0~8[6:0] register bits in CABC block to define the “CABC gain”/
“CABC duty” table. Every DBGx[6:0] has 33 gain/duty value setting.
After one-frame display data content analysis, LSI will generate one CABC gain /
CABC duty value calculated from DBG0~8[6:0] register bits setting (by using
interpolated method) for display data generating and for backlight PWM pulse
generating.
Please note that the CABC gain / CABC duty value calculated by the LSI is one of the
33 gain/duty value setting in DBGxx[6:0].
Please note that : Duty ( valid level period (LED on) / one complete period)=1/ gain.
DBG0
Gain curve
DBG1
DBG2
DBG3
DBG4
Gain
DBG5
SAVEPOWER DBG6
DBG7
DBG8
0 32 64 96 128 160 192 224 256
One frame display data

content analysis
Figure 5.34: CABC gain / CABC duty generation
For power saving of backlight module, there are SAVEPOWER[6:0] bits to define the
“minimum gain”/ “maximum duty” of CABC block output. If the CABC gain / duty after
one-frame display data contents analysis is smaller (gain) / larger (duty) than
SAVEPOWER[6:0] bits setting, the CABC block will output CABC gain / duty equal to
SAVEPOWER[6:0] and ignore the result of display data contents analysis.

HX8394-F
5.14.3 Brightness control block
There is an external output signal from brightness block, CABC_PWM_OUT, to

control the LED driver IC in order to control display brightness.
There are resister bits, DBV[7:0] of R51h, for display brightness of manual brightness
setting. The CABC_PWM_OUT duty is calculated as (DBV[7:0]) / 255 x CABC duty
(generated after one-frame display data content analysis).
For ex: CABC_PWM_OUT period=2.95 ms, and DBV[7:0] (R51h)=‘228DEC’ and

CABC duty is 74%. Then CABC_PWM_OUT duty=(228) / 255 x 74.42%≡66.54%.
Correspond to the CABC_PWM_OUT period=2.95 ms, the high-level of
CABC_PWM_OUT (high effective)=1.96ms, and the low-level of CABC_PWM_OUT
=0.99ms.
Figure 5.35: CABC_PWM_OUT output duty
Symbol Parameter Min. Max. Unit Description

tpw Pulse width 0.0333 8.33 ms -
Table 5.40: CABC timing table
Note: (1) The signal rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
(2) The pulse width range by setting CABC related registers is locate between 0.0333ms to 8.33ms.
When Architecture II module is used (BL=’0’) with the example below, the
CABC_PWM_OUT is always output low and the DBV[7:0] (R51h) will be read a value
as 169DEC ((169) / 255≡66.27%).

HX8394-F
5.14.4 Minimum brightness setting of CABC function
CABC function is automatically reduced backlight brightness based on image

contents. In the case of the combination with the CABC or manual brightness setting,
display brightness is too dark. It must affect to image quality degradation. CABC
minimum brightness setting (CMB[7:0] bits of R5Eh) is to avoid too much brightness
reduction.
When CABC is active, CABC can not reduce the display brightness to less than
CABC minimum brightness setting. Image processing function is worked as normal,
even if the brightness can not be changed.
This function does not affect to the other function, manual brightness setting. Manual
brightness can be set the display brightness to less than CABC minimum brightness.
Smooth transition and dimming function can be worked as normal.
When display brightness is turned off (BCTRL=’0’ of R53h), CABC minimum

brightness setting is ignored. “CMB[7:0], Read CABC minimum brightness
(R5Fh)“ always read the setting value of “CMB[7:0], Write CABC minimum brightness
(R5Eh)”

HX8394-F
5.15Temperature sensor
HX8394-F supports temperature sensor function that changes to H_Temp or L_Temp

mode in different environment temperature and it also achieves low power
consumption to save power dissipation. Besides, this function can cover panel GIP
timing deviation when environment in high or low temperature.
At HX8394-F temperature sensor setting, user can set the temperature upper
(H_Temp) and lower boundary (L_Temp). Following those setting, voltage and
source output will automatically change to suitable value when environment
temperature reaches upper or lower boundary setting.
H_Temp
L_Temp
H_Stage
N_Stage
L_Stage H_Stage
N_Stage
L_Stage
Figure 5.36: Tempeture sensor diagram

HX8394-F
5.16OTP programming
5.16.1 OTP table
OTP_INDEX
B7 B6 B5 B4 B3 B2 B1 B0
(HEX)
0 ID1_1[7:0]
1 ID2_1[7:0]
2 ID3_1[7:0]
3 ID4_1[7:0]
4 ID1_2[7:0]
5 ID2_2[7:0]
6 ID3_2[7:0]
7 ID4_2[7:0]
8 ID1_3[7:0]
9 ID2_3[7:0]
A ID3_3[7:0]
B ID4_3[7:0]
C NVALID_ID1 NVALID_ID2 NVALID_ID3 - - - - -
D VCMC_F1[7:0]
E VCMC_B1[7:0]
F VCMC_F2[7:0]
10 VCMC_B2[7:0]
11 VCMC_F3[7:0]
12 VCMC_B3[7:0]
13 - - VCMC_B38 VCMC_B38 VCMC_B28 VCMC_B28 VCMC_B18 VCMC_B18
NVALID_VC NVALID_VC NVALID_VC
14 - - - - -
MC1 MC2 MC3
NVALID_PA BGR_PANE
15 - - - SS_PANEL GS_PANEL REV_PANE
NEL L
NVALID_GA
45 VHP_0[6:0]
MMA
46 - VHP_1[6:0]
47 - VHP_2[6:0]
48 - VHP_3[6:0]
49 - VHP_4[6:0]
4A - VHP_5[6:0]
4B - VHP_6[6:0]
4C - VHP_7[6:0]
4D VMP_0[7:0]
4E VMP_1[7:0]
4F VMP_2[7:0]
50 VMP_3[7:0]
51 VMP_4[7:0]
52 VMP_5[7:0]
53 VMP_6[7:0]
54 VMP_7[7:0]
55 VMP_8[7:0]
56 VMP_9[7:0]
57 VMP_10[7:0]
58 VMP_11[7:0]
59 VMP_12[7:0]
5A - VLP_0[6:0]
5B - VLP_1[6:0]
5C - VLP_2[6:0]
5D - VLP_3[6:0]
5E - VLP_4[6:0]
5F - VLP_5[6:0]
60 - VLP_6[6:0]
61 - VLP_7[6:0]
62 - VHN_0[6:0]
63 - VHN_1[6:0]
64 - VHN_2[6:0]
65 - VHN_3[6:0]
HX8394-F
66 - VHN_4[6:0]
67 - VHN_5[6:0]
68 - VHN_6[6:0]
69 - VHN_7[6:0]
6A VMN_0[7:0]
6B VMN_1[7:0]
6C VMN_21[7:0]
6D VMN_3[7:0]
6E VMN_4[7:0]
6F VMN_5[7:0]
70 VMN_6[7:0]
71 VMN_7[7:0]
72 VMN_8[7:0]
73 VMN_9[7:0]
74 VMN_10[7:0]
75 VMN_11[7:0]
76 VMN_12[7:0]
77 - VLN_0[6:0]
78 - VLN_1[6:0]
79 - VLN_2[6:0]
7A - VLN_3[6:0]
7B - VLN_4[6:0]
7C - VLN_5[6:0]
7D - VLN_6[6:0]
7E - VLN_7[6:0]
NVALID_DG
7F - - - - - - DGC_EN
C
80 R_GAMMA0[9:2]
81 R_GAMMA1[9:2]
82 R_GAMMA2[9:2]
83 R_GAMMA3[9:2]
84 R_GAMMA4[9:2]
85 R_GAMMA5[9:2]
86 R_GAMMA6[9:2]
87 R_GAMMA7[9:2]
88 R_GAMMA8[9:2]
89 R_GAMMA9[9:2]
8A R_GAMMA10[9:2]
8B R_GAMMA11[9:2]
8C R_GAMMA12[9:2]
8D R_GAMMA13[9:2]
8E R_GAMMA14[9:2]
8F R_GAMMA15[9:2]
90 R_GAMMA16[9:2]
91 R_GAMMA17[9:2]
92 R_GAMMA18[9:2]
93 R_GAMMA19[9:2]
94 R_GAMMA20[9:2]
95 R_GAMMA21[9:2]
96 R_GAMMA22[9:2]
97 R_GAMMA23[9:2]
98 R_GAMMA24[9:2]
99 R_GAMMA25[9:2]
9A R_GAMMA26[9:2]
9B R_GAMMA27[9:2]
9C R_GAMMA28[9:2]
9D R_GAMMA29[9:2]
9E R_GAMMA30[9:2]
9F R_GAMMA31[9:2]
A0 R_GAMMA32[9:2]
A1 R_GAMMA0[1:0] R_GAMMA1[1:0] R_GAMMA2[1:0] R_GAMMA3[1:0]
HX8394-F
R_GAMMAF R_GAMMA_
A9 R_GAMMA32[1:0] - - - -
F_OPT 256
AA G_GAMMA0[9:2]
AB G_GAMMA1[9:2]
AC G_GAMMA2[9:2]
AD G_GAMMA3[9:2]
AE G_GAMMA4[9:2]
AF G_GAMMA5[9:2]
B0 G_GAMMA6[9:2]
B1 G_GAMMA7[9:2]
B2 G_GAMMA8[9:2]
B3 G_GAMMA9[9:2]
B4 G_GAMMA10[9:2]
B5 G_GAMMA11[9:2]
B6 G_GAMMA12[9:2]
B7 G_GAMMA13[9:2]
B8 G_GAMMA14[9:2]
B9 G_GAMMA15[9:2]
BA G_GAMMA16[9:2]
BB G_GAMMA17[9:2]
BC G_GAMMA18[9:2]
BD G_GAMMA19[9:2]
BE G_GAMMA20[9:2]
BF G_GAMMA21[9:2]
C0 G_GAMMA22[9:2]
C1 G_GAMMA23[9:2]
C2 G_GAMMA24[9:2]
C3 G_GAMMA25[9:2]
C4 G_GAMMA26[9:2]
C5 G_GAMMA27[9:2]
C6 G_GAMMA28[9:2]
C7 G_GAMMA29[9:2]
C8 G_GAMMA30[9:2]
C9 G_GAMMA31[9:2]
CA G_GAMMA32[9:2]
CB G_GAMMA0[1:0] G_GAMMA1[1:0] G_GAMMA2[1:0] G_GAMMA3[1:0]
CC G_GAMMA4[1:0] G_GAMMA5[1:0] G_GAMMA6[1:0] G_GAMMA7[1:0]
CD G_GAMMA8[1:0] G_GAMMA9[1:0] G_GAMMA10[1:0] G_GAMMA11[1:0]
CE G_GAMMA12[1:0] G_GAMMA13[1:0] G_GAMMA14[1:0] G_GAMMA15[1:0]
CF G_GAMMA16[1:0] G_GAMMA17[1:0] G_GAMMA18[1:0] G_GAMMA19[1:0]
D0 G_GAMMA20[1:0] G_GAMMA21[1:0] G_GAMMA22[1:0] G_GAMMA23[1:0]
G_GAMMA G_GAMMA_
D3 G_GAMMA32[1:0] - - - -
FF_OPT 256
D4 B_GAMMA0[9:2]
D5 B_GAMMA1[9:2]
D6 B_GAMMA2[9:2]
D7 B_GAMMA3[9:2]
D8 B_GAMMA4[9:2]
D9 B_GAMMA5[9:2]
DA B_GAMMA6[9:2]
DB B_GAMMA7[9:2]
DC B_GAMMA8[9:2]
DD B_GAMMA9[9:2]
DE B_GAMMA10[9:2]
DF B_GAMMA11[9:2]
E0 B_GAMMA12[9:2]
E1 B_GAMMA13[9:2]
E2 B_GAMMA14[9:2]
E3 B_GAMMA15[9:2]
E4 B_GAMMA16[9:2]
HX8394-F
E5 B_GAMMA17[9:2]
E6 B_GAMMA18[9:2]
E7 B_GAMMA19[9:2]
E8 B_GAMMA20[9:2]
E9 B_GAMMA21[9:2]
EA B_GAMMA22[9:2]
EB B_GAMMA23[9:2]
EC B_GAMMA24[9:2]
ED B_GAMMA25[9:2]
EE B_GAMMA26[9:2]
EF B_GAMMA27[9:2]
F0 B_GAMMA28[9:2]
F1 B_GAMMA29[9:2]
F2 B_GAMMA30[9:2]
F3 B_GAMMA31[9:2]
F4 B_GAMMA32[9:2]
F5 B_GAMMA0[1:0] B_GAMMA1[1:0] B_GAMMA2[1:0] B_GAMMA3[1:0]
FA B_GAMMA20[1:0] B_GAMMA21[1:0] B_GAMMA22[1:0] B_GAMMA23[1:0]
FB B_GAMMA24[1:0] B_GAMMA25[1:0] B_GAMMA26[1:0] B_GAMMA27[1:0]
FC B_GAMMA28[1:0] B_GAMMA29[1:0] B_GAMMA30[1:0] B_GAMMA31[1:0]
B_GAMMAF B_GAMMA_
FD B_GAMMA32[1:0] - - - -
F_OPT 256
FE
VALID_DGC
FF
_USEFUL
NVALID_GA
100 VHP_0[6:0]
MMA
101 - VHP_1[6:0]
102 - VHP_2[6:0]
103 - VHP_3[6:0]
104 - VHP_4[6:0]
105 - VHP_5[6:0]
106 - VHP_6[6:0]
107 - VHP_7[6:0]
108 VMP_0[7:0]
109 VMP_1[7:0]
10A VMP_2[7:0]
10B VMP_3[7:0]
10C VMP_4[7:0]
10D VMP_5[7:0]
10E VMP_6[7:0]
10F VMP_7[7:0]
110 VMP_8[7:0]
111 VMP_9[7:0]
112 VMP_10[7:0]
113 VMP_11[7:0]
114 VMP_12[7:0]
115 - VLP_0[6:0]
116 - VLP_1[6:0]
117 - VLP_2[6:0]
118 - VLP_3[6:0]
119 - VLP_4[6:0]
11A - VLP_5[6:0]
11B - VLP_6[6:0]
11C - VLP_7[6:0]
11D - VHN_0[6:0]
11E - VHN_1[6:0]
11F - VHN_2[6:0]
120 - VHN_3[6:0]
121 - VHN_4[6:0]
122 - VHN_5[6:0]
HX8394-F
123 - VHN_6[6:0]
124 - VHN_7[6:0]
125 VMN_0[7:0]
126 VMN_1[7:0]
127 VMN_21[7:0]
128 VMN_3[7:0]
129 VMN_4[7:0]
12A VMN_5[7:0]
12B VMN_6[7:0]
12C VMN_7[7:0]
12D VMN_8[7:0]
12E VMN_9[7:0]
12F VMN_10[7:0]
130 VMN_11[7:0]
131 VMN_12[7:0]
132 - VLN_0[6:0]
133 - VLN_1[6:0]
134 - VLN_2[6:0]
135 - VLN_3[6:0]
136 - VLN_4[6:0]
137 - VLN_5[6:0]
138 - VLN_6[6:0]
139 - VLN_7[6:0]
NVALID_DG
13A - - - - - - DGC_EN
C
13B R_GAMMA0[9:2]
13C R_GAMMA1[9:2]
13D R_GAMMA2[9:2]
13E R_GAMMA3[9:2]
13F R_GAMMA4[9:2]
140 R_GAMMA5[9:2]
141 R_GAMMA6[9:2]
142 R_GAMMA7[9:2]
143 R_GAMMA8[9:2]
144 R_GAMMA9[9:2]
145 R_GAMMA10[9:2]
146 R_GAMMA11[9:2]
147 R_GAMMA12[9:2]
148 R_GAMMA13[9:2]
149 R_GAMMA14[9:2]
14A R_GAMMA15[9:2]
14B R_GAMMA16[9:2]
14C R_GAMMA17[9:2]
14D R_GAMMA18[9:2]
14E R_GAMMA19[9:2]
14F R_GAMMA20[9:2]
150 R_GAMMA21[9:2]
151 R_GAMMA22[9:2]
152 R_GAMMA23[9:2]
153 R_GAMMA24[9:2]
154 R_GAMMA25[9:2]
155 R_GAMMA26[9:2]
156 R_GAMMA27[9:2]
157 R_GAMMA28[9:2]
158 R_GAMMA29[9:2]
159 R_GAMMA30[9:2]
15A R_GAMMA31[9:2]
15B R_GAMMA32[9:2]
15C R_GAMMA0[1:0] R_GAMMA1[1:0] R_GAMMA2[1:0] R_GAMMA3[1:0]
15D R_GAMMA4[1:0] R_GAMMA5[1:0] R_GAMMA6[1:0] R_GAMMA7[1:0]
15E R_GAMMA8[1:0] R_GAMMA9[1:0] R_GAMMA10[1:0] R_GAMMA11[1:0]
15F R_GAMMA12[1:0] R_GAMMA13[1:0] R_GAMMA14[1:0] R_GAMMA15[1:0]
160 R_GAMMA16[1:0] R_GAMMA17[1:0] R_GAMMA18[1:0] R_GAMMA19[1:0]
HX8394-F
R_GAMMAF R_GAMMA_
164 R_GAMMA32[1:0] - - - -
F_OPT 256
165 G_GAMMA0[9:2]
166 G_GAMMA1[9:2]
167 G_GAMMA2[9:2]
168 G_GAMMA3[9:2]
169 G_GAMMA4[9:2]
16A G_GAMMA5[9:2]
16B G_GAMMA6[9:2]
16C G_GAMMA7[9:2]
16D G_GAMMA8[9:2]
16E G_GAMMA9[9:2]
16F G_GAMMA10[9:2]
170 G_GAMMA11[9:2]
171 G_GAMMA12[9:2]
172 G_GAMMA13[9:2]
173 G_GAMMA14[9:2]
174 G_GAMMA15[9:2]
175 G_GAMMA16[9:2]
176 G_GAMMA17[9:2]
177 G_GAMMA18[9:2]
178 G_GAMMA19[9:2]
179 G_GAMMA20[9:2]
17A G_GAMMA21[9:2]
17B G_GAMMA22[9:2]
17C G_GAMMA23[9:2]
17D G_GAMMA24[9:2]
17E G_GAMMA25[9:2]
17F G_GAMMA26[9:2]
180 G_GAMMA27[9:2]
181 G_GAMMA28[9:2]
182 G_GAMMA29[9:2]
183 G_GAMMA30[9:2]
184 G_GAMMA31[9:2]
185 G_GAMMA32[9:2]
186 G_GAMMA0[1:0] G_GAMMA1[1:0] G_GAMMA2[1:0] G_GAMMA3[1:0]
18A G_GAMMA16[1:0] G_GAMMA17[1:0] G_GAMMA18[1:0] G_GAMMA19[1:0]
18B G_GAMMA20[1:0] G_GAMMA21[1:0] G_GAMMA22[1:0] G_GAMMA23[1:0]
18C G_GAMMA24[1:0] G_GAMMA25[1:0] G_GAMMA26[1:0] G_GAMMA27[1:0]
18D G_GAMMA28[1:0] G_GAMMA29[1:0] G_GAMMA30[1:0] G_GAMMA31[1:0]
G_GAMMA G_GAMMA_
18E G_GAMMA32[1:0] - - - -
FF_OPT 256
18F B_GAMMA0[9:2]
190 B_GAMMA1[9:2]
191 B_GAMMA2[9:2]
192 B_GAMMA3[9:2]
193 B_GAMMA4[9:2]
194 B_GAMMA5[9:2]
195 B_GAMMA6[9:2]
196 B_GAMMA7[9:2]
197 B_GAMMA8[9:2]
198 B_GAMMA9[9:2]
199 B_GAMMA10[9:2]
19A B_GAMMA11[9:2]
19B B_GAMMA12[9:2]
19C B_GAMMA13[9:2]
19D B_GAMMA14[9:2]
19E B_GAMMA15[9:2]
19F B_GAMMA16[9:2]
1A0 B_GAMMA17[9:2]
1A1 B_GAMMA18[9:2]
HX8394-F
1A2 B_GAMMA19[9:2]
1A3 B_GAMMA20[9:2]
1A4 B_GAMMA21[9:2]
1A5 B_GAMMA22[9:2]
1A6 B_GAMMA23[9:2]
1A7 B_GAMMA24[9:2]
1A8 B_GAMMA25[9:2]
1A9 B_GAMMA26[9:2]
1AA B_GAMMA27[9:2]
1AB B_GAMMA28[9:2]
1AC B_GAMMA29[9:2]
1AD B_GAMMA30[9:2]
1AE B_GAMMA31[9:2]
1AF B_GAMMA32[9:2]
1B0 B_GAMMA0[1:0] B_GAMMA1[1:0] B_GAMMA2[1:0] B_GAMMA3[1:0]
B_GAMMAF B_GAMMA_
1B8 B_GAMMA32[1:0] - - - -
F_OPT 256
NVALID_GI
1B9 - GIP_EQ_OPT[1:0] - - EQ_DELAY_HSYNC[1:0]
P_D3
1BA - - - - - EQ_VSEL EQ_DISC[1:0]
1BB EQ_DELAY_ON1[7:0]
1BC EQ_DELAY_OFF1[7:0]
1BD GTO[7:0]
1BE GNO[7:0]
1BF USER_GIP_GATE[7:0]
1C0 USER_GIP_GATE1[7:0]
1C1 SHR0_3[3:0] SHR0_2[3:0]
1C2 SHR0_1[3:0] SHR0[11:8]
1C3 SHR0[7:0]
1C4 - - - - SHR0_GS[11:8]
1C5 SHR0_GS[7:0]
1C6 SHR1_3[3:0] SHR1_2[3:0]
1C7 SHR1_1[3:0] SHR1[11:8]
1C8 SHR1[7:0]
1C9 - - - - SHR1_GS[11:8]
1CA SHR1_GS[7:0]
1CB SHR2_3[3:0] SHR2_2[3:0]
1CC SHR2_1[3:0] SHR2[11:8]
1CD SHR2[7:0]
1CE - - - - SHR2_GS[11:8]
1CF SHR2_GS[7:0]
1D0 SHP0[3:0] SCP[3:0]
1D1 SHP2[3:0] SHP1[3:0]
1D2 CHR0[7:0]
1D3 CHR0_GS[7:0]
1D4 CHP0[3:0] CCP0[3:0]
1D5 CHR1[7:0]
1D6 CHR1_GS[7:0]
1D7 CHP1[3:0] CCP1[3:0]
NVALID_CA PWM_PERI BC_CTRL_ SEL_BLDUT
1EE SEL_PWMCLK[2:0] INVPULS
BC OD[16] EN Y
1EF PWM_PERIOD[15:8]
1F0 PWM_PERIOD[7:0]
CABC_FSY
1F1 DIM_FRAME[6:0]
NC
CABC_DD_I EN_DIM_MI ABC_CHEC
1F2 CABC_DD CABC_FLM[3:0]
DLE X KSUM_EN
1F7 NVALID_SE - - - - - - -
HX8394-F
TDPHY
1F8 DPHYCMD0[7:0]
1F9 DPHYCMD1[7:0]
NVALID_GI CGTS_L_INV
249 COS1_L[5:0] (CGOUT1_L)
P_D5 [1]
CGTS_R_IN
24A - COS1_R[5:0] (CGOUT1_R)
V[1]
CGTS_L_INV
24B - COS2_L[5:0] (CGOUT2_L)
[2]
CGTS_R_IN
24C - COS2_R[5:0] (CGOUT2_R)
V[2]
CGTS_L_INV
24D - COS3_L[5:0] (CGOUT3_L)
[3]
CGTS_R_IN
24E - COS3_R[5:0] (CGOUT3_R)
V[3]
CGTS_L_INV
24F - COS4_L[5:0] (CGOUT4_L)
[4]
CGTS_R_IN
250 - COS4_R[5:0] (CGOUT4_R)
V[4]
CGTS_L_INV
251 - COS5_L[5:0] (CGOUT5_L)
[5]
CGTS_R_IN
252 - COS5_R[5:0] (CGOUT5_R)
V[5]
CGTS_L_INV
253 - COS6_L[5:0] (CGOUT6_L)
[6]
CGTS_R_IN
254 - COS6_R[5:0] (CGOUT6_R)
V[6]
CGTS_L_INV
255 - COS7_L[5:0] (CGOUT7_L)
[7]
CGTS_R_IN
256 - COS7_R[5:0] (CGOUT7_R)
V[7]
CGTS_L_INV
257 - COS8_L[5:0] (CGOUT8_L)
[8]
CGTS_R_IN
258 - COS8_R[5:0] (CGOUT8_R)
V[8]
CGTS_L_INV
259 - COS9_L[5:0] (CGOUT9_L)
[9]
CGTS_R_IN
25A - COS9_R[5:0] (CGOUT9_R)
V[9]
CGTS_L_INV
25B - COS10_L[5:0] (CGOUT10_L)
[10]
CGTS_R_IN
25C - COS10_R[5:0] (CGOUT10_R)
V[10]
CGTS_L_INV
25D - COS11_L[5:0] (CGOUT11_L)
[11]
CGTS_R_IN
25E - COS11_R[5:0] (CGOUT11_R)
V[11]
CGTS_L_INV
25F - COS12_L[5:0] (CGOUT12_L)
[12]
CGTS_R_IN
260 - COS12_R[5:0] (CGOUT12_R)
V[12]
CGTS_L_INV
261 - COS13_L[5:0] (CGOUT13_L)
[13]
CGTS_R_IN
262 - COS13_R[5:0] (CGOUT13_R)
V[13]
CGTS_L_INV
263 - COS14_L[5:0] (CGOUT14_L)
[14]
CGTS_R_IN
264 - COS14_R[5:0] (CGOUT14_R)
V[14]
CGTS_L_INV
265 - COS15_L[5:0] (CGOUT15_L)
[15]
CGTS_R_IN
266 - COS15_R[5:0] (CGOUT15_R)
V[15]
CGTS_L_INV
267 - COS16_L[5:0] (CGOUT16_L)
[16]
268 - CGTS_R_IN COS16_R[5:0] (CGOUT16_R)

HX8394-F
V[16]
CGTS_L_INV
269 - COS17_L[5:0] (CGOUT17_L)
[17]
CGTS_R_IN
26A - COS17_R[5:0] (CGOUT17_R)
V[17]
CGTS_L_INV
26B - COS18_L[5:0] (CGOUT18_L)
[18]
CGTS_R_IN
26C - COS18_R[5:0] (CGOUT18_R)
V[18]
CGTS_L_INV
26D COS19_L[5:0] (CGOUT19_L)
[19]
CGTS_R_IN
26E COS19_R[5:0] (CGOUT19_R)
V[19]
CGTS_L_INV
26F COS20_L[5:0] (CGOUT20_L)
[20]
CGTS_R_IN
270 COS20_R[5:0] (CGOUT20_R)
V[20]
CGTS_L_INV
271 - COS21_L[5:0] (CGOUT21_L)
[21]
CGTS_R_IN
272 - COS21_R[5:0] (CGOUT21_R)
V[21]
CGTS_L_INV
273 - COS22_L[5:0] (CGOUT22_L)
[22]
CGTS_R_IN
274 - COS22_R[5:0] (CGOUT22_R)
V[22]
NVALID_GI CGOUT_L_H
275 COS1_L_GS[5:0] (CGOUT1_L)
P_D6 IZ_IN[1]
CGOUT_R_
276 - COS1_R_GS[5:0] (CGOUT1_R)
HIZ_IN[1]
CGOUT_L_H
277 - COS2_L_GS[5:0] (CGOUT2_L)
IZ_IN[2]
CGOUT_R_
278 - COS2_R_GS[5:0] (CGOUT2_R)
HIZ_IN[2]
CGOUT_L_H
279 - COS3_L_GS[5:0] (CGOUT3_L)
IZ_IN[3]
CGOUT_R_
27A - COS3_R_GS[5:0] (CGOUT3_R)
HIZ_IN[3]
CGOUT_L_H
27B - COS4_L_GS[5:0] (CGOUT4_L)
IZ_IN[4]
CGOUT_R_
27C - COS4_R_GS[5:0] (CGOUT4_R)
HIZ_IN[4]
CGOUT_L_H
27D - COS5_L_GS[5:0] (CGOUT5_L)
IZ_IN[5]
CGOUT_R_
27E - COS5_R_GS[5:0] (CGOUT5_R)
HIZ_IN[5]
CGOUT_L_H
27F - COS6_L_GS[5:0] (CGOUT6_L)
IZ_IN[6]
CGOUT_R_
280 - COS6_R_GS[5:0] (CGOUT6_R)
HIZ_IN[6]
CGOUT_L_H
281 - COS7_L_GS[5:0] (CGOUT7_L)
IZ_IN[7]
CGOUT_R_
282 - COS7_R_GS[5:0] (CGOUT7_R)
HIZ_IN[7]
CGOUT_L_H
283 - COS8_L_GS[5:0] (CGOUT8_L)
IZ_IN[8]
CGOUT_R_
284 - COS8_R_GS[5:0] (CGOUT8_R)
HIZ_IN[8]
CGOUT_L_H
285 - COS9_L_GS[5:0] (CGOUT9_L)
IZ_IN[9]
CGOUT_R_
286 - COS9_R_GS[5:0] (CGOUT9_R)
HIZ_IN[9]
CGOUT_L_H
287 - COS10_L_GS[5:0] (CGOUT10_L)
IZ_IN[10]
CGOUT_R_
288 - COS10_R_GS[5:0] (CGOUT10_R)
HIZ_IN[10]
289 - CGOUT_L_H COS11_L_GS[5:0] (CGOUT11_L)

HX8394-F
IZ_IN[11]
CGOUT_R_
28A - COS11_R_GS[5:0] (CGOUT11_R)
HIZ_IN[11]
CGOUT_L_H
28B - COS12_L_GS[5:0] (CGOUT12_L)
IZ_IN[12]
CGOUT_R_
28C - COS12_R_GS[5:0] (CGOUT12_R)
HIZ_IN[12]
CGOUT_L_H
28D - COS13_L_GS[5:0] (CGOUT13_L)
IZ_IN[13]
CGOUT_R_
28E - COS13_R_GS[5:0] (CGOUT13_R)
HIZ_IN[13]
CGOUT_L_H
28F - COS14_L_GS[5:0] (CGOUT14_L)
IZ_IN[14]
CGOUT_R_
290 - COS14_R_GS[5:0] (CGOUT14_R)
HIZ_IN[14]
CGOUT_L_H
291 - COS15_L_GS[5:0] (CGOUT15_L)
IZ_IN[15]
CGOUT_R_
292 - COS15_R_GS[5:0] (CGOUT15_R)
HIZ_IN[15]
CGOUT_L_H
293 - COS16_L_GS[5:0] (CGOUT16_L)
IZ_IN[16]
CGOUT_R_
294 - COS16_R_GS[5:0] (CGOUT16_R)
HIZ_IN[16]
CGOUT_L_H
295 COS17_L_GS[5:0] (CGOUT17_L)
IZ_IN[17]
CGOUT_R_
296 COS17_R_GS[5:0] (CGOUT17_R)
HIZ_IN[17]
CGOUT_L_H
297 COS18_L_GS[5:0] (CGOUT18_L)
IZ_IN[18]
CGOUT_R_
298 COS18_R_GS[5:0] (CGOUT18_R)
HIZ_IN[18]
CGOUT_L_H
299 - COS19_L_GS[5:0] (CGOUT19_L)
IZ_IN[19]
CGOUT_R_
29A - COS19_R_GS[5:0] (CGOUT19_R)
HIZ_IN[19]
CGOUT_L_H
29B - COS20_L_GS[5:0] (CGOUT20_L)
IZ_IN[20]
CGOUT_R_
29C - COS20_R_GS[5:0] (CGOUT20_R)
HIZ_IN[20]
CGOUT_L_H
29D - COS21_L_GS[5:0] (CGOUT21_L)
IZ_IN[21]
CGOUT_R_
29E - COS21_R_GS[5:0] (CGOUT21_R)
HIZ_IN[21]
CGOUT_L_H
29F - COS22_L_GS[5:0] (CGOUT22_L)
IZ_IN[22]
CGOUT_R_
2A0 - COS22_R_GS[5:0] (CGOUT22_R)
HIZ_IN[22]
NVALID_1B
2ED - - - - NW_PE[2:0]
PP
2EE BP_PE[7:0]
2EF FP_PE[7:0]
2F0 RTN_PE[7:0]
2F1 VCMC_F_IDLE[7:0]
2F2 VCMC_B_IDLE[7:0]
VCMC_B_I VCMC_F_ID
2F3 AP_PE[2:0] - - -
DLE[8] LE[8]
NVALID_CE DYN_CEH_E
2F8 - - - - - -
MODE N
2F9 HUE_MODE[1:0] SE_MODE[1:0] BE_MODE[1:0] CE_MODE[1:0]
NVALID_PO DSTBY_OP
300 POWMOD[1:0] AP[2:0] DSTB
WER T
301 VCLS[2:0] VRHP[4:0]
302 VPPS[2:0] VRHN[4:0]
VSP_FBOF
303 EQ_VCLEN - - - XDK[2:0]
F (1 no FB)
304 - - CLK_OPT2 CLK_OPT1( FS0[3:0](VSP_pmping)
HX8394-F
(VGL) VGH)
305 FS1[3:0](VGH_pmping) FS2[3:0](VGL_pmping)
306 VGH_RATIO[2:0] BTP[4:0]
307 VGL_RATIO[2:0] BTN[4:0]
308 - VGHS[6:0]
309 - VGLS[6:0]
30A DT1[1:0] DT2[1:0] DCDIV[3:0]
30B - DCS[2:0] - DC[2:0]
30C - DTPS[2:0] - DTP[2:0]
30D - DTNS[2:0] - DTN[2:0]
NVALID_GA
30E APF_EN GASIOVCC_OPT[1:0] - GASVCI_OPT[2:0]
S
GAS_CP_V
30F GASVSN_OPT[2:0] - GASVSP_OPT[2:0]
SPVSN
NVALID_DI
312 ZZ_LR ZZ_EO ZZ_2PL - NW[2:0]
SP
313 MESSI_ENB H_RES[2:0] - - - -
314 NL[7:0]
315 BP [7:0]
316 FP [7:0]
317 RTN[7:0]
DISP_BIST_
31C FRM_PATTERN_CYCLE[3:0] FRM_SCAN_CYCLE[2:0]
EN
SAP_PURE
NVALID_CY SAP_PURE SAP_XTALK SAP_XTALK
320 - - - COLOR_S
C COLOR_EN _EN _SW
W
321 SPON[7:0]
322 SPOFF[7:0]
323 CON[7:0]
324 COFF[7:0]
325 CON1[7:0]
326 COFF1[7:0]
327 EQON1[7:0]
328 SON[7:0]
329 SOFF[7:0]
32A SAP1_P[3:0] - SAP2[2:0]
32B - DX2_EN EQ_ON EQ_MIX - - - -
32C DX2OFF[7:0]
32D SPON_MPU[7:0]
32E SPOFF_MPU[7:0]
32F CON_MPU[7:0]
330 COFF_MPU[7:0]
331 CON1_MPU[7:0]
332 COFF1_MPU[7:0]
333 EQON1_MPU[7:0]
334 SON_MPU[7:0]
335 SOFF_MPU[7:0]
336 DX2OFF_MPU[7:0]
NVALID_CA
33F DBG0[6:0]
BCDBG
340 - DBG1[6:0]
341 - DBG2[6:0]
342 - DBG3[6:0]
343 - DBG4[6:0]
344 - DBG5[6:0]
345 - DBG6[6:0]
346 - DBG7[6:0]
347 - DBG8[6:0]
NVALID_SE
348 DSISETUP0[6:0]
TDSI
349 DSISETUP1[7:0]
NVALID_SE TSENSOR_E
354 LT_EN HT_EN - TEMP_GAP[2:0]
NSOR N
NVALID_OF
367 - - - - - - -
FSET3

HX8394-F
368 VN_REFS[3:0] VP_REFS[3:0]
NVALID_SC SCALING_T SCALING_E
36A - - - - -
L YPE N
Table 5.41: OTP table

HX8394-F
5.16.2 OTP programming flow
OTP_KEY0[7:0]
Description Note
OTP Program Flow OTP_KEY1[7:0]
OTP_KEY0[7:0] = 0xAAh
Enter OTP program mode
OTP_KEY1[7:0] = 0x55h
H/W Reset
<Step1> + OTP_KEY0[7:0] = 0x00h
SLPOUT Leave OTP program mode
OTP_KEY1[7:0] = 0x00h
Delay 120ms
1. If HX8394-F operate on OTP
program mode, then keep on OTP
Set 0xB9h=0xFFh, 0x83h, 0x94h to
<Step2> program mode.
access extension commands Other value Invalid
2. If HX8394-F operate on non-OTP
program mode, then keep on
non-OTP program mode.
Write optimized OTP value in
<Step3> related register
(need to programmed value)
<Step4>
OTP_KEY1[7:0] = 0x55h
Using External power 7.5V to VPP

<Step5> Or
Set INTVPP_EN=1
<Step6> Set OTP index
<Step7> OTP_PROG=1
<Step8> Delay 10ms/byte
Yes
<Step9> Program another OTP index
No
<Step10> OTP_KEY0[7:0] = 0x00h

OTP_KEY1[7:0] = 0x00h
END
Figure 5.37: OTP programming sequence

HX8394-F
5.16.3 Programming sequence
Step Operation
1 Power on and reset the module.
2 SLPOUT and set 0xB9h = 0xFFh, 0x83h, 0x94h to access the extension commands.
3 Write optimized values to related registers.
4 Set OTP_KEY0[7:0]=0xAAh and OTP_KEY1[7:0]=0x55h to enter OTP program mode.
Set INTVPP_EN=1 for OTP programming state for using internal power mode.
5
Or using the external power 7.5V to VPP.
6 Specify OTP_index, please refer to the OTP table.
7 Set OTP_Mask=0x00h, programming the entire bit of one parameter.
8 Set OTP_PROG=1, Internal register begin write to OTP according to OTP_index.
9 Wait 10ms/byte (Note 1)
10 Set OTP_PROG=0, OTP_index programming action done.
Complete programming one parameter to OTP. If continue to programming other parameter,
11 return to step (5). Otherwise, set OTP_KEY1[7:0]=0x00h and OTP_KEY1[7:0]=0x00h to leave
OTP program mode and power off the module and remove the external power on VPP pin.
Note: (1) When do the OTP programming process, it must be added 5ms delay time after setting OTP_PROG=1.
Table 5.42: OTP programming sequence

HX8394-F
5.16.4 OTP programming example of VCOM setting VCMC
OTP Program Flow
H/W Reset + SLPOUT
Set extension commands

Set CMD 0xB9h
1st parameter 0xFFh
2nd parameter 0x83h
3rd parameter 0x94h
Write optimized VCOM value of

Register
Set CMD 0xB6h
1st parameter 0x##h(VCMC)
Set OTP_KEY0[7:0] = 0xAAh

OTP_KEY1[7:0] = 0x55h
Set CMD 0xBBh
6th parameter 0xAAh
7th parameter0x55h

Or
Set INTVPP_EN=1
OTP programming action done

OTP_KEY0[7:0] = 0x00h
Set OTP index 0x0Dh for VCMC_F1[8:0] OTP_KEY1[7:0] = 0x00h
Set CMD 0xBBh Set CMD 0xBBh
1st parameter 0x00h(internal VPP set 0x80h) 1st parameter 0x00h
2nd parameter 0x0Dh 2nd parameter0x00h
Reset IC for OTP relaod

Set OTP_PROG=1 for programming action
Set CMD 0xBBh
1st parameter 0x00h(internal VPP set 0x80h)
2nd parameter 0x0Dh
3rd parameter 0x00h END
4th parameter 0x01h
Delay 40ms
Figure 5.38: OTP programming sequence example 1

HX8394-F
5.16.5 OTP programming example of ID1, ID2 and ID3
OTP Program Flow
H/W Reset + SLPOUT (command 0x11h) OTP_KEY0[7:0] = 0x00h

OTP_KEY1[7:0] = 0x00h
Set CMD 0xBBh
6th parameter 0x00h
7th parameter0x00h
Set CMD 0xB9h
1st parameter 0xFFh
2nd parameter 0x83h
3rd parameter 0x94h
Reset IC for OTP relaod
Set ID1, ID2 and ID3 values

Set CMD 0xC3h
1st parameter 0x##h (ID1)
END
2nd parameter0x##h (ID2)
3rd parameter0x##h (ID3)
4th parameter0x##h (ID4)
Set OTP_KEY0[7:0] = 0xAAh

OTP_KEY1[7:0] = 0x55h
Set CMD 0xBBh
6th parameter 0xAAh
7th parameter0x55h

Or
Set INTVPP_EN=1
Set OTP index 0x00h for ID1[7:0]~ID4[7:0]

Set CMD 0xBBh
2nd parameter 0x00h
Set OTP_PROG=1 for programming action

Set CMD 0xBBh
2nd parameter 0x00h
3rd parameter 0x00h
3rd parameter 0x01h
Delay 50ms
Figure 5.39: OTP programming sequence example 2

HX8394-F
5.16.6 OTP read example of 0x00h (ID1)
OTP Read Flow
H/W Reset + SLPOUT (command 0x11h)
Clear OTP_POR
Set CMD 0xBBh
1st parameter 0x00h
Delay 120 ms for OTP relaod
2nd parameter 0x00h
3rd parameter 0x00h
4th parameter 0x00h

Set CMD 0xB9h
1st parameter 0xFFh
2nd parameter 0x83h
3rd parameter 0x94h
Read OTP_DATA from BBh
Read CMD 0xBBh
1st parameter 0x00h
2nd parameter 0x00h
Set OTP_INDEX(0x00) for ID1 setting
3rd parameter 0x00h
Set CMD 0xBBh
4th parameter 0x00h
1st parameter 0x00h
5th parameter 0x##h (OTP data)
2nd parameter 0x00h
Set OTP_POR
Set CMD 0xBBh Read OTP_DATA YES
1st parameter 0x00h Comparing the related register
2nd parameter 0x00h If 0x##=0xFF
3rd parameter 0x00h
4th parameter 0x80h
No
OTP Programmed OTP not Program
Figure 5.40: OTP read sequence flow of index 0x00h

HX8394-F
5.17FRM (Free running mode)
Burn-in of TFT displays consists of driving each module for 10hr at a temperature of
60oC. In order to drive the modules, it requires extra electronics. To reduce the
burn-in cost, it is requested that the driver IC will generate the required display image
without requiring extra electronics. We term this a free running mode (FRM). For
burn-in, it is sufficient that the display is powered up with a plane saturated black or
white pattern. The Display pattern sequence and power on sequence is as below
Figure. Free-running mode pattern number and pattern delay time can be further set
in register B2h FRM_PATTERN_CYCLE[3:0] and FRM_SCAN_CYCLE[2:0].
Figure 5.41: FRM power on sequence
Figure 5.42: Display pattern sequence example in FRM

(FRM_PATTERN_CYCLE[3:0] =4h, FRM_SCAN_CYCLE[2:0]=1h)

HX8394-F
5.18Command list
5.18.1 Standard command
Default
(Hex) Operation code DCX D7 D6 D5 D4 D3 D2 D1 D0 Function
(Hex)
00 NOP 0 0 0 0 0 0 0 0 0 No Operation -
01 SWRESET 0 0 0 0 0 0 0 0 1 Software Reset -
Read Display Identification
0 0 0 0 0 0 1 0 0 -
Information
04 RDDIDIF 1 ID1[7:0] -
1 ID2[7:0] -
1 ID3[7:0] -
Read Number of DSI
0 0 0 0 0 0 1 0 1 -
05 RDNUMPE Parity Error
1 P[7:0] -
0 0 0 0 0 0 1 1 0 Read Red Colour -
06 RDRED
1 R7 R6 R5 R4 R3 R2 R1 R0 xx -
0 0 0 0 0 0 1 1 1 Read Green Colour -
07 RDGREEN
1 G7 G6 G5 G4 G3 G2 G1 G0 xx -
0 0 0 0 0 1 0 0 0 Read Blue Colour -
08 RDBLUE
1 B7 B6 B5 B4 B3 B2 B1 B0 xx -
0 0 0 0 0 1 0 0 1 Read display status -
1 D31 D30 D29 0 0 D26 D25 D24 -
09 RDDST 1 D23 D22 D21 D20 D19 0 D17 D16 -
1 0 0 D13 D12 D11 D10 D9 D8 -
1 D7 D6 D5 D4 D3 D2 D1 D0 -
0 0 0 0 0 1 0 1 0 Read display power mode -
0A RDDPM
1 D7 D6 0 D4 D3 D2 0 0 -
0 0 0 0 0 1 0 1 1 Read display MADCTL -
0B RDDMADCTL
1 D7 D6 0 0 D3 D2 D1 D0 -
0 0 0 0 0 1 1 0 0 Read display pixel format -
0C RDDCOLMOD
1 0 D6 D5 D4 0 0 0 0 -
0 0 0 0 0 1 1 0 1 Read display image mode -
0D RDDIM
1 0 0 D5 D4 D3 D2 D1 D0 -
0 0 0 0 0 1 1 1 0 Read display signal mode -
0E RDDSM
1 D7 D6 D5 D4 D3 D2 0 D0 -
Read display
0 0 0 0 0 1 1 1 1 -
0F RDDSDR self-diagnostic result
1 D7 D6 D5 D4 0 0 0 0 -
10 SLPIN 0 0 0 0 1 0 0 0 0 Sleep In -
11 SLPOUT 0 0 0 0 1 0 0 0 1 Sleep Out -
13 NORON 0 0 0 0 1 0 0 1 1 Normal display mode on -
20 INVOFF 0 0 0 1 0 0 0 0 0 Display inversion off -
21 INVON 0 0 0 1 0 0 0 0 1 Display inversion on -
22 ALLPOFF 0 0 0 1 0 0 0 1 0 All pixel off (black) -
23 ALLPON 0 0 0 1 0 0 0 1 1 All pixel on (white) -
0 0 0 1 0 0 1 1 0 Gamma set -
26 GAMSET GC
1 GC7 GC6 GC5 GC4 GC3 GC2 GC1 -
0
28 DISPOFF 0 0 0 1 0 1 0 0 0 Display off -
29 DISPON 0 0 0 1 0 1 0 0 1 Display on -
0 0 0 1 0 1 1 0 0 Memory Write -
1 D17 D16 D15 D14 D13 D12 D11 D10 Write data -
2C RAMWR
1 Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 Write data -
1 Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 Write data -
34 TEOFF 0 0 0 1 1 0 1 0 0 Tearing Effect Line OFF -
0 0 0 1 1 0 1 0 1 Tearing Effect Line ON -
35 TEON
1 X X X X X X X M -
0 0 0 1 1 0 1 1 0 Memory Access Control -
36 MADCTL
1 D7 D6 X X D3 D2 D1 D0 -
38 IDMOFF 0 0 0 1 1 1 0 0 0 Idle mode off -
39 IDMON 0 0 0 1 1 1 0 0 1 Idle mode on -
0 0 0 1 1 1 0 1 0 0 -
3A COLMOD
1 X D6 D5 D4 X D2 D1 D0 -
0 0 0 1 1 1 1 0 0 Memory write -
1 D17 D16 D15 D14 D13 D12 D11 D10 -
3C RAMWRCON
1 Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 -
1 Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 -
44 TESL 0 0 1 0 0 0 1 0 0 TESL -
1 TELINE[15:8](8’b0) -
HX8394-F
1 TELINE[7:0](8’b0) -
Reture the current scanline -
0 0 1 0 0 0 1 0 1
SLN[15:0]
45 GETSCAN
1 SLN[15:8] -
1 SLN[7:0] -
0 0 1 0 1 0 0 0 1 Write Display Brightness -
51 WRDISBV
1 DBV[7:0] -
Read Display Brightness
0 0 1 0 1 0 0 1 0 -
52 RDDISBV Value
1 DBV[7:0] -
0 0 1 0 1 0 0 1 1 -
53 WRCTRLD BCT Write CTRL Display
1 xx xx xx DD BL xx xx -
RL
Read Control Value
0 0 1 0 1 0 0 1 1 -
Display
54 RDCTRLD
BCT
1 0 0 0 DD BL 0 0 -
RL
Write Adaptive Brightness
0 0 1 0 1 0 1 0 1 -
55 WRCABC Control
1 xx xx xx xx xx xx CABC[1:0] -
Read Adaptive Brightness
0 0 1 0 1 0 1 1 0 -
56 RDCABC Control Content
1 0 0 0 0 0 0 C1 C0 -
Write CABC minimum
0 0 1 0 1 1 1 1 0 -
5E WRCABCMB brightness
1 CMB[7:0] -
Read CABC minimum
0 0 1 0 1 1 1 1 1 -
5F RDCABCMB brightness
1 CMB[7:0] -
Read Automatic
0 0 1 1 0 1 0 0 0 Brightness Control -
68 RDABCSDR
Self-Diagnostic Result
1 D[7:6] 0 0 0 0 0 0 -
0 1 0 0 0 0 0 0 0 Write Idle Mode Color -
80 WRIMCOL
1 XX XX XX XX XX R G B -
0 1 0 0 0 0 0 0 0 Read Idle Mode Color -
81 RDIMCOL
1 0 0 0 0 0 R G B -
Read the DDB from the
0 1 0 1 0 0 0 0 1 -
provided location.
A1 Read_DDB_start 1 x x x x x x x x -
1 x x x x x x x x -
1 x x x x x x x x -
Continue reading the DDB
0 1 0 1 0 1 0 0 0 -
from the last read location.
A8 Read_DDB_continue 1 x x x x x x x x -
1 x x x x x x x x -
1 x x x x x x x x -
0 1 1 0 1 1 0 1 0 Read ID1 -
DA RDID1
1 module’s manufacturer[7:0] -
0 1 1 0 1 1 0 1 1 Read ID2 -
DB RDID2
1 LCD module/driver version [7:0] -
0 1 1 0 1 1 1 0 0 Read ID3 -
DC RDID3
1 LCD module/driver ID[7:0] -
Note: (1) Undefined commands are treated as NOP (00h) command.

(2) B0h to D8h and E0h to FFh are for factory use of display supplier.

HX8394-F
5.18.2 User define command list table
User define command list is available only set “SETEXC” command.

Note: *=Read only
Operation Parameter Default

(Hex) D7 D6 D5 D4 D3 D2 D1 D0
Code index (Hex)
NO_OTP 1 0 1 1 0 0 0 0
1 - - - - - - - - 00
B0 SETAUTO 2 - - - - - - OSC_EN 10
3 - VSN_EN VSP_EN VGL_EN VGH_EN VCL_EN - STB 7D
4 - - - - GON DTE D[1:0] 0C
1 0 1 1 0 0 0 0
DSTBY_O
Bank_0_1 - POWMOD[1:0] AP[2:0] DSTB 10
PT
Bank_0_2 VCLS[2:0] VRHP[4:0] 10
Bank_0_3 VPPS[2:0] VRHN[4:0] 70
EQ_VCLE VSP_FBOF
Bank_0_4 - - - XDK[2:0] 81
N F
Bank_0_5 - - CLK_OPT2 CLK_OPT1 FS0[3:0] 32
Bank_0_6 FS1[3:0] FS2[3:0] 33
Bank_0_7 VGH_RATIO[2:0] BTP[4:0] 71
B1 SETPOWER Bank_0_8 VGL_RATIO[2:0] BTN[4:0] 71
Bank_0_9 - VGHS[6:0] 34
Bank_0_10 - VGLS[6:0] 48
Bank_0_11 DT1[1:0] DT2[1:0] DCDIV[3:0] 56
Bank_0_12 - DCS[2:0] - DC[2:0] 73
Bank_0_13 - DTPS[2:0] - DTP[2:0] 02
Bank_0_14 - DTNS[2:0] - DTN[2:0] 02
Bank_1_1 - APF_EN GASIOVCC_OPT[1:0] - GASVCI_OPT[2:0] 64
GAS_CP_
Bank_1_2 GASVSN_OPT[2:0] - GASVSP_OPT[2:0] 44
VSPVSN
Bank_1_3 - - GASVGL_OPT[1:0] - GASVGH_OPT[1:0] 11
1 0 1 1 0 0 1 0
Bank_0_1 - ZZ_LR ZZ_EO ZZ_2PL - NW[2:0] 40
MESSI_EN
Bank_0_2 H_RES[2:0] - - - - 80
B
Bank_0_3 NL[7:0] 64
Bank_0_4 BP [7:0] 08
Bank_0_5 FP [7:0] 08
Bank_0_6 RTN[7:0] 2F
Bank_0_7 - - - - 00
Bank_0_8 - - - - - - - 00
Bank_0_9 - - - - - - - 00
Bank_0_10 - - - - - - - - 00
DISP_BIST
Bank_0_11 FRM_PATTERN_CYCLE[3:0] FRM_SCAN_CYCLE[2:0] C0
_EN
1 SPON[7:0] 03
2 SPOFF[7:0] 3F
3 CON[7:0] 05
4 COFF[7:0] 3F
B2 SETDISP
5 CON1[7:0] 05
6 COFF1[7:0] 3F
7 EQON1[7:0] 05
8 SON[7:0] 10
9 SOFF[7:0] 7E
10 SAP1_P[3:0] - SAP2[2:0] 73
11 - DX2_EN EQ_ON EQ_MIX - - - - 20
12 DX2OFF[7:0] 3F
13 SPON_MPU[7:0] 03
14 SPOFF_MPU[7:0] 3F
15 CON_MPU[7:0] 05
16 COFF_MPU[7:0] 3F
17 CON1_MPU[7:0] 05
18 COFF1_MPU[7:0] 3F
19 EQON1_MPU[7:0] 05
20 SON_MPU[7:0] 10
21 SOFF_MPU[7:0] 7E
22 DX2OFF_MPU[7:0] 3F
B6 SETVCOM 1 0 1 1 0 1 1 0
(OTPx3) 1 VCMC_F[7:0] 46
HX8394-F
2 VCMC_B[7:0] 46
VCMC_B[8
3 VCOM_TIMES[2:0] - - - VCMC_F[8] E0
]
1 0 1 1 0 1 1 1
1 - TEI[3:0] TEP[10:8] 00
B7 SETTE
2 TEP[7:0] 00
3 TE_SEL[3:0] TE1_SEL[3:0] 00
1 1 0 1 0 0 0 1
B8 SETSENSOR TSENSOR
bank_0_1 - LT_EN HT_EN - - 01
_EN
NO_OTP 1 0 1 1 1 0 0 1
1 EXTC1[7:0] 00/FF
B9 SETEXTC
2 EXTC2[7:0] 00/83
3 EXTC3[7:0] 00/94
1 0 1 1 1 0 1 0
1 - DSISETUP0[6:0] 63
BA SETMIPI 2 DSISETUP1[7:0] 03
3 DPHYCMD0[7:0] 68
4 DPHYCMD1[7:0] 63
NO_OTP 1 0 1 1 1 0 1 1
INTVPP_E OTP_PROG
1 - - - - OTP_INDEX[9:8] 00
N _ALL
2 OTP_INDEX[7:0] 00
3 OTP_DATA[7:0] 00
BB SETOTP OTP_PWR_ OTP_PRO
4 OTP_POR OTP_PWE OTP_PTM[2:0] OTP_TEST 00
SEL G
5 OTP_DATA_READ[7:0] FF
6 OTP_KEY0[7:0] 00
7 OTP_KEY1[7:0] 00
8 OTP_MASK[7:0] 00
NO_OTP 1 1 1 1 0 0 0 1
BD SET_BANK
1 - - - - - - BANK_INDEX[1:0] 00
C1 SETDGCLUT 1 1 0 0 0 0 0 1
Bank_0_1 - - - - - - DGC_INV DGC_EN 00
Bank_0_2 R_GAMMA0[9:2] -
Bank_0_12 R_GAMMA10[9:2] -
Bank_0_13 R_GAMMA11[9:2] -
Bank_0_14 R_GAMMA12[9:2] -
Bank_0_15 R_GAMMA13[9:2] -
Bank_0_16 R_GAMMA14[9:2] -
Bank_0_17 R_GAMMA15[9:2] -
Bank_0_18 R_GAMMA16[9:2] -
Bank_0_19 R_GAMMA17[9:2] -
Bank_0_20 R_GAMMA18[9:2] -
Bank_0_21 R_GAMMA19[9:2] -
Bank_0_22 R_GAMMA20[9:2] -
Bank_0_23 R_GAMMA21[9:2] -
Bank_0_24 R_GAMMA22[9:2] -
Bank_0_25 R_GAMMA23[9:2] -
Bank_0_26 R_GAMMA24[9:2] -
Bank_0_27 R_GAMMA25[9:2] -
Bank_0_28 R_GAMMA26[9:2] -
Bank_0_29 R_GAMMA27[9:2] -
Bank_0_30 R_GAMMA28[9:2] -
Bank_0_31 R_GAMMA29[9:2] -
Bank_0_32 R_GAMMA30[9:2] -
Bank_0_33 R_GAMMA31[9:2] -
Bank_0_34 R_GAMMA32[9:2] -
Bank_0_35 R_GAMMA0[1:0] R_GAMMA1[1:0] R_GAMMA2[1:0] R_GAMMA3[1:0] -
HX8394-F
Bank_0_43 R_GAMMA32[1:0] - - - - - - 01
Bank_1_1 G_GAMMA0[9:2] -
Bank_1_11 G_GAMMA10[9:2] -
Bank_1_12 G_GAMMA11[9:2] -
Bank_1_13 G_GAMMA12[9:2] -
Bank_1_14 G_GAMMA13[9:2] -
Bank_1_15 G_GAMMA14[9:2] -
Bank_1_16 G_GAMMA15[9:2] -
Bank_1_17 G_GAMMA16[9:2] -
Bank_1_18 G_GAMMA17[9:2] -
Bank_1_19 G_GAMMA18[9:2] -
Bank_1_20 G_GAMMA19[9:2] -
Bank_1_21 G_GAMMA20[9:2] -
Bank_1_22 G_GAMMA21[9:2] -
Bank_1_23 G_GAMMA22[9:2] -
Bank_1_24 G_GAMMA23[9:2] -
Bank_1_25 G_GAMMA24[9:2] -
Bank_1_26 G_GAMMA25[9:2] -
Bank_1_27 G_GAMMA26[9:2] -
Bank_1_28 G_GAMMA27[9:2] -
Bank_1_29 G_GAMMA28[9:2] -
Bank_1_30 G_GAMMA29[9:2] -
Bank_1_31 G_GAMMA30[9:2] -
Bank_1_32 G_GAMMA31[9:2] -
Bank_1_33 G_GAMMA32[9:2] -
Bank_1_34 G_GAMMA0[1:0] G_GAMMA1[1:0] G_GAMMA2[1:0] G_GAMMA3[1:0] -
Bank_1_42 G_GAMMA32[1:0] - - - - - - 01
Bank_2_1 B_GAMMA0[9:2] -
Bank_2_11 B_GAMMA10[9:2] -
Bank_2_12 B_GAMMA11[9:2] -
Bank_2_13 B_GAMMA12[9:2] -
Bank_2_14 B_GAMMA13[9:2] -
Bank_2_15 B_GAMMA14[9:2] -
Bank_2_16 B_GAMMA15[9:2] -
Bank_2_17 B_GAMMA16[9:2] -
Bank_2_18 B_GAMMA17[9:2] -
Bank_2_19 B_GAMMA18[9:2] -
Bank_2_20 B_GAMMA19[9:2] -
Bank_2_21 B_GAMMA20[9:2] -
Bank_2_22 B_GAMMA21[9:2] -
Bank_2_23 B_GAMMA22[9:2] -
Bank_2_24 B_GAMMA23[9:2] -
Bank_2_25 B_GAMMA24[9:2] -
Bank_2_26 B_GAMMA25[9:2] -
Bank_2_27 B_GAMMA26[9:2] -
Bank_2_28 B_GAMMA27[9:2] -
HX8394-F
Bank_2_29 B_GAMMA28[9:2] -
Bank_2_30 B_GAMMA29[9:2] -
Bank_2_31 B_GAMMA30[9:2] -
Bank_2_32 B_GAMMA31[9:2] -
Bank_2_33 B_GAMMA32[9:2] -
Bank_2_34 B_GAMMA0[1:0] B_GAMMA1[1:0] B_GAMMA2[1:0] B_GAMMA3[1:0] -
Bank_2_42 B_GAMMA32[1:0] - - - - - - 01
1 1 0 0 0 0 1 1
1 ID1[7:0] 83
SETID 2 ID2[7:0] 94
C3
(OTPx3) 3 ID3[7:0] 0F
4 ID4[7:0] 00
5 ID_TIMES[2:0]* - - - - - E0
1 1 0 0 0 1 0 0
1 DDB1[7:0] 00
2 DDB2[7:0] 00
C4 SETDDB 3 DDB3[7:0] 00
4 DDB4[7:0] 00
5 DDB5[7:0] 00
6 DDB6[7:0] 00
1 1 0 0 1 0 0 1
PWM_PERI BC_CTRL_ SEL_BLDU
1 - SEL_PWMCLK[2:0] INVPULS 13
OD[16] EN TY
2 PWM_PERIOD[15:8] 00
C9 SETCABC 3 PWM_PERIOD[7:0] 2E
CABC_FS
4 DIM_FRAME[6:0] 1E
YNC
CABC_DD
5 CABC_DD - - CABC_FLM[3:0] B1
_IDLE
1 1 0 0 1 0 1 0
1 - DBG0[6:0] 40
2 - DBG1[6:0] 3C
3 - DBG2[6:0] 38
SETCABCGAI 4 - DBG3[6:0] 34
CA
N 5 - DBG4[6:0] 33
6 - DBG5[6:0] 32
7 - DBG6[6:0] 2B
8 - DBG7[6:0] 24
9 - DBG8[6:0] 22
1 1 0 0 1 1 0 0
CC SETPANEL REV_PAN BGR_PANE
1 - - - - SS_PANEL GS_PANEL 00
EL L
1 1 0 1 0 0 1 0
D2 SETOFFSET
1 VN_REFS[3:0] VP_REFS[3:0] 55
D3 SETGIP_0 1 1 0 1 0 0 1 1
EQ_DELAY_HSYNC[1:0
bank_0_1 - - GIP_EQ_OPT[1:0] - - 00
]
bank_0_2 - - - - - EQ_VSEL EQ_DISC[1:0] 00
bank_0_3 EQ_DELAY_ON1[7:0] 00
bank_0_4 EQ_DELAY_OFF1[7:0] 00
bank_0_5 GTO[7:0] 00
bank_0_6 GNO[7:0] 00
bank_0_7 USER_GIP_GATE[7:0] 08
bank_0_8 USER_GIP_GATE1[7:0] 08
bank_0_9 SHR0_3[3:0] SHR0_2[3:0] 32
bank_0_10 SHR0_1[3:0] SHR0[11:8] 10
bank_0_11 SHR0[7:0] 02
bank_0_12 - - - - SHR0_GS[11:8] 00
bank_0_13 SHR0_GS[7:0] 02
bank_0_14 SHR1_3[3:0] SHR1_2[3:0] 32
bank_0_15 SHR1_1[3:0] SHR1[11:8] 13
bank_0_16 SHR1[7:0] C0
bank_0_17 - - - - SHR1_GS[11:8] 00
bank_0_18 SHR1_GS[7:0] 00
bank_0_19 SHR2_3[3:0] SHR2_2[3:0] 32
bank_0_20 SHR2_1[3:0] SHR2[11:8] 10
HX8394-F
bank_0_21 SHR2[7:0] 08
bank_0_22 - - - - SHR2_GS[11:8] 00
bank_0_23 SHR2_GS[7:0] 00
bank_0_24 SHP0[3:0] SCP[3:0] 4B
bank_0_25 SHP2[3:0] SHP1[3:0] 00
bank_0_26 CHR0[7:0] 06
bank_0_27 CHR0_GS[7:0] 06
bank_0_28 CHP0[3:0] CCP0[3:0] 47
bank_0_29 CHR1[7:0] 04
bank_0_30 CHR1_GS[7:0] 00
bank_0_31 CHP1[3:0] CCP1[3:0] 27
D5 SETGIP_1 1 1 0 1 0 1 0 1
CGTS_L_I
1 - COS1_L[5:0] (CGOUT1_L) 18
NV[1]
CGTS_R_I
2 - COS1_R[5:0] (CGOUT1_R) 18
NV[1]
CGTS_L_I
3 - COS2_L[5:0] (CGOUT2_L) 18
NV[2]
CGTS_R_I
4 - COS2_R[5:0] (CGOUT2_R) 18
NV[2]
CGTS_L_I
5 - COS3_L[5:0] (CGOUT3_L) 18
NV[3]
CGTS_R_I
6 - COS3_R[5:0] (CGOUT3_R) 18
NV[3]
CGTS_L_I
7 - COS4_L[5:0] (CGOUT4_L) 18
NV[4]
CGTS_R_I
8 - COS4_R[5:0] (CGOUT4_R) 18
NV[4]
CGTS_L_I
9 - COS5_L[5:0] (CGOUT5_L) 18
NV[5]
CGTS_R_I
10 - COS5_R[5:0] (CGOUT5_R) 18
NV[5]
CGTS_L_I
11 - COS6_L[5:0] (CGOUT6_L) 18
NV[6]
CGTS_R_I
12 - COS6_R[5:0] (CGOUT6_R) 18
NV[6]
CGTS_L_I
13 - COS7_L[5:0] (CGOUT7_L) 18
NV[7]
CGTS_R_I
14 - COS7_R[5:0] (CGOUT7_R) 18
NV[7]
CGTS_L_I
15 - COS8_L[5:0] (CGOUT8_L) 18
NV[8]
CGTS_R_I
16 - COS8_R[5:0] (CGOUT8_R) 18
NV[8]
CGTS_L_I
17 - COS9_L[5:0] (CGOUT9_L) 18
NV[9]
CGTS_R_I
18 - COS9_R[5:0] (CGOUT9_R) 18
NV[9]
CGTS_L_I
19 - COS10_L[5:0] (CGOUT10_L) 18
NV[10]
CGTS_R_I
20 - COS10_R[5:0] (CGOUT10_R) 18
NV[10]
CGTS_L_I
21 - COS11_L[5:0] (CGOUT11_L) 18
NV[11]
CGTS_R_I
22 - COS11_R[5:0] (CGOUT11_R) 18
NV[11]
CGTS_L_I
23 - COS12_L[5:0] (CGOUT12_L) 18
NV[12]
CGTS_R_I
24 - COS12_R[5:0] (CGOUT12_R) 18
NV[12]
CGTS_L_I
25 - COS13_L[5:0] (CGOUT13_L) 18
NV[13]
CGTS_R_I
26 - COS13_R[5:0] (CGOUT13_R) 18
NV[13]
CGTS_L_I
27 - COS14_L[5:0] (CGOUT14_L) 18
NV[14]
CGTS_R_I
28 - COS14_R[5:0] (CGOUT14_R) 18
NV[14]
CGTS_L_I
29 - COS15_L[5:0] (CGOUT15_L) 18
NV[15]
CGTS_R_I
30 - COS15_R[5:0] (CGOUT15_R) 18
NV[15]
CGTS_L_I
31 - COS16_L[5:0] (CGOUT16_L) 18
NV[16]

HX8394-F
CGTS_R_I
32 - COS16_R[5:0] (CGOUT16_R) 18
NV[16]
CGTS_L_I
33 - COS17_L[5:0] (CGOUT17_L) 18
NV[17]
CGTS_R_I
34 - COS17_R[5:0] (CGOUT17_R) 18
NV[17]
CGTS_L_I
35 - COS18_L[5:0] (CGOUT18_L) 18
NV[18]
CGTS_R_I
36 - COS18_R[5:0] (CGOUT18_R) 18
NV[18]
CGTS_L_I
37 - COS19_L[5:0] (CGOUT19_L) 18
NV[19]
CGTS_R_I
38 - COS19_R[5:0] (CGOUT19_R) 18
NV[19]
CGTS_L_I
39 - COS20_L[5:0] (CGOUT20_L) 18
NV[20]
CGTS_R_I
40 - COS20_R[5:0] (CGOUT20_R) 18
NV[20]
CGTS_L_I
41 - COS21_L[5:0] (CGOUT21_L) 18
NV[21]
CGTS_R_I
42 - COS21_R[5:0] (CGOUT21_R) 18
NV[21]
CGTS_L_I
43 - COS22_L[5:0] (CGOUT22_L) 18
NV[22]
CGTS_R_I
44 - COS22_R[5:0] (CGOUT22_R) 18
NV[22]
D6 SETGIP_2 1 1 0 1 0 1 1 0
CGOUT_L
1 - COS1_L_GS[5:0] (CGOUT1_L) 18
_HIZ_IN[1]
CGOUT_R
2 - COS1_R_GS[5:0] (CGOUT1_R) 18
_HIZ_IN[1]
CGOUT_L
3 - COS2_L_GS[5:0] (CGOUT2_L) 18
_HIZ_IN[2]
CGOUT_R
4 - COS2_R_GS[5:0] (CGOUT2_R) 18
_HIZ_IN[2]
CGOUT_L
5 - COS3_L_GS[5:0] (CGOUT3_L) 18
_HIZ_IN[3]
CGOUT_R
6 - COS3_R_GS[5:0] (CGOUT3_R) 18
_HIZ_IN[3]
CGOUT_L
7 - COS4_L_GS[5:0] (CGOUT4_L) 18
_HIZ_IN[4]
CGOUT_R
8 - COS4_R_GS[5:0] (CGOUT4_R) 18
_HIZ_IN[4]
CGOUT_L
9 - COS5_L_GS[5:0] (CGOUT5_L) 18
_HIZ_IN[5]
CGOUT_R
10 - COS5_R_GS[5:0] (CGOUT5_R) 18
_HIZ_IN[5]
CGOUT_L
11 - COS6_L_GS[5:0] (CGOUT6_L) 18
_HIZ_IN[6]
CGOUT_R
12 - COS6_R_GS[5:0] (CGOUT6_R) 18
_HIZ_IN[6]
CGOUT_L
13 - COS7_L_GS[5:0] (CGOUT7_L) 18
_HIZ_IN[7]
CGOUT_R
14 - COS7_R_GS[5:0] (CGOUT7_R) 18
_HIZ_IN[7]
CGOUT_L
15 - COS8_L_GS[5:0] (CGOUT8_L) 18
_HIZ_IN[8]
CGOUT_R
16 - COS8_R_GS[5:0] (CGOUT8_R) 18
_HIZ_IN[8]
CGOUT_L
17 - COS9_L_GS[5:0] (CGOUT9_L) 18
_HIZ_IN[9]
CGOUT_R
18 - COS9_R_GS[5:0] (CGOUT9_R) 18
_HIZ_IN[9]
CGOUT_L
19 - _HIZ_IN[10 COS10_L_GS[5:0] (CGOUT10_L) 18
]
CGOUT_R
20 - _HIZ_IN[10 COS10_R_GS[5:0] (CGOUT10_R) 18
]
CGOUT_L
]
CGOUT_R
]
HX8394-F
CGOUT_L
]
CGOUT_R
]
CGOUT_L
]
CGOUT_R
]
CGOUT_L
]
CGOUT_R
]
CGOUT_L
]
CGOUT_R
]
CGOUT_L
]
CGOUT_R
]
CGOUT_L
]
CGOUT_R
]
CGOUT_L
]
CGOUT_R
]
CGOUT_L
]
CGOUT_R
]
CGOUT_L
]
CGOUT_R
]
CGOUT_L
]
CGOUT_R
]
CGOUT_L
]
CGOUT_R
]
1 1 0 1 1 0 1 0
1 ESD_DET - TE_GPO[3:0] 00
D9 SETGPO 2 - - TE1_GPO[3:0] 01
3 - - CABC_GPO[3:0] 82
4 - SDO_GPO[3:0] 07
1 1 0 1 1 1 0 1
DD SETSCL SCALING_ SCALING_
2 - - - - - - 00
TYPE EN
DF SET1BPP 1 1 0 1 1 1 1 1
HX8394-F
1 - - - - - NW_PE[2:0] 00
2 BP_PE[7:0] 08
3 FP_PE[7:0] 08
4 RTN_PE[7:0] 2F
5 VCMC_F_IDLE[7:0] FE
6 VCMC_B_IDLE[7:0] FE
VCMC_B_I VCMC_F_I
7 AP_PE[2:0] - - - 83
DLE[8] DLE[8]
1 1 1 0 0 0 0 0
1 - VHP_0[6:0] 00
2 - VHP_1[6:0] 04
3 - VHP_2[6:0] 08
4 - VHP_3[6:0] 0C
5 - VHP_4[6:0] 10
6 - VHP_5[6:0] 14
7 - VHP_6[6:0] 18
8 - VHP_7[6:0] 1C
9 VMP_0[7:0] 20
10 VMP_1[7:0] 24
11 VMP_2[7:0] 28
12 VMP_3[7:0] 2C
13 VMP_4[7:0] 30
14 VMP_5[7:0] 34
15 VMP_6[7:0] 38
16 VMP_7[7:0] 3C
17 VMP_8[7:0] 40
18 VMP_9[7:0] 44
19 VMP_10[7:0] 48
20 VMP_11[7:0] 4C
21 VMP_12[7:0] 50
22 - VLP_0[6:0] 54
23 - VLP_1[6:0] 58
24 - VLP_2[6:0] 5C
25 - VLP_3[6:0] 60
26 - VLP_4[6:0] 64
27 - VLP_5[6:0] 68
28 - VLP_6[6:0] 6C
E0 SETGAMMA 29 - VLP_7[6:0] 7F
30 - VHN_0[6:0] 00
31 - VHN_1[6:0] 04
32 - VHN_2[6:0] 08
33 - VHN_3[6:0] 0C
34 - VHN_4[6:0] 10
35 - VHN_5[6:0] 14
36 - VHN_6[6:0] 18
37 - VHN_7[6:0] 1C
38 VMN_0[7:0] 20
39 VMN_1[7:0] 24
40 VMN_2[7:0] 28
41 VMN_3[7:0] 2C
42 VMN_4[7:0] 30
43 VMN_5[7:0] 34
44 VMN_6[7:0] 38
45 VMN_7[7:0] 3C
46 VMN_8[7:0] 40
47 VMN_9[7:0] 44
48 VMN_10[7:0] 48
49 VMN_11[7:0] 4C
50 VMN_12[7:0] 50
51 - VLN_0[6:0] 54
52 - VLN_1[6:0] 58
53 - VLN_2[6:0] 5C
54 - VLN_3[6:0] 60
55 - VLN_4[6:0] 64
56 - VLN_5[6:0] 68
57 - VLN_6[6:0] 6C
58 - VLN_7[6:0] 7F
1 1 1 0 0 1 0 0
SETCHEMOD DYN_CEH_
E4 1 - - - - - - - 01
E EN
2 HUE_MODE[1:0] SE_MODE[1:0] BE_MODE[1:0] CE_MODE[1:0] 00
E5 SETCHE 1 1 1 0 0 1 0 1
1 - - - - - - - - -
HX8394-F
2 - - - SG0_F[4:0] -
3 - - - SG64_F[4:0] -
4 - - - SG128_F[4:0] -
5 - - - SG192_F[4:0] -
6 - - - SG255_F[4:0] -
7 TH_SAT[7:0] -
8 TH_WHITE[7:0] -
9 TH_COLOR[7:0] -
10 TH_GREY[7:0] -
11 - - - - - - - - -
12 - - - CG0_F[4:0] -
13 - - - CG64_F[4:0] -
14 - - - CG128_F[4:0] -
15 - - - CG192_F[4:0] -
16 - - - CG255_F[4:0] -
17 THC[7:0] -
18 - - - - EG2_F[1:0] EG1_F[1:0] -
19 TH_RFL[7:0] -
20 - - - SG16_F[4:0] -
21 - - - SG32_F[4:0] -
22 - - - SG48_F[4:0] -
23 - - - SG80_F[4:0] -
24 - - - SG96_F[4:0] -
25 - - - SG112_F[4:0] -
26 - - - SG144_F[4:0] -
27 - - - SG160_F[4:0] -
28 - - - SG176_F[4:0] -
29 - - - SG208_F[4:0] -
30 - - - SG224_F[4:0] -
31 - - - SG240_F[4:0] -
32 - - - CG16_F[4:0] -
33 - - - CG32_F[4:0] -
34 - - - CG48_F[4:0] -
35 - - - CG80_F[4:0] -
36 - - - CG96_F[4:0] -
37 - - - CG112_F[4:0] -
38 - - - CG144_F[4:0] -
39 - - - CG160_F[4:0] -
40 - - - CG176_F[4:0] -
41 - - - CG208_F[4:0] -
42 - - - CG224_F[4:0] -
43 - - - CG240_F[4:0] -
1 1 1 0 0 1 1 0
ENCH00_S
1 ENCH00_SEL[6:0] AMPLE_SE 00
L
ENCH01_S ENCH01_B ENCH01_C
2 ENCH01_SW[4:0] -
E_OFF E_OFF E_OFF
ENCH02_S ENCH02_B ENCH02_C
3 ENCH02_DS[4:0] -
E_DS E_DS E_DS
4 ENCH03_reg[7:0] 05
5 ENCH04_reg[7:0] 05
6 ENCH05_reg[7:0] -
E6 SETCHESEL
7 ENCH06_reg[7:0] -
8 ENCH07_reg[7:0] -
9 ENCH08_reg[7:0] -
10 ENCH09_reg[7:0] -
11 ENCH10_reg[7:0] -
12 ENCH11_reg[7:0] -
13 ENCH12_reg[7:0] -
14 ENCH13_reg[7:0] -
15 ENCH14_reg[7:0] -
16 ENCH15_reg[7:0] -
17 ENCH16_reg[7:0] -
NO_OTP 1 1 1 0 1 0 0 1
RAND_WR
FORCE_O
E9 SET_SP_CMD _SERIAL_ RAND_WR_CNT[5:0] 3F
PT
EN
1 WR_CMD_CN[7:0] -
SET READ 1 1 1 1 1 1 1 0
FE
INDEX 1 CMD_ADD[7:0] 00

HX8394-F
5.18.3 NOP (00h)
NOP (No Operation)

00H
DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 0 0 0 0 0 0 00
Parameter NO PARAMETER
This command is an empty command; it does not have any effect on the display
Description
module.
Restriction -
Status Availability
Register Normal Mode On, Idle Mode Off, Sleep Out Yes
Availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default N/A
Flow Chart -

HX8394-F
5.18.4 Software reset (01h)
SWRESET (Software Reset)

01H
Command 0 0 0 0 0 0 0 0 1 01
When the Software Reset command is written, it causes a software reset. It resets
Description the commands and parameters to their S/W Reset default values. (See default
tables in each command description.)
It will be necessary to wait 5msec before sending new command following
software reset.
The display module loads all display supplier’s factory default values to the
registers during this 5msec. If Software Reset is applied during Sleep Out mode, it
Restriction
will be necessary to wait 120msec before sending Sleep out command. Software
Reset Command cannot be sent during Sleep Out sequence.
The host processor needs continuing to send PCLK, HSYNC, VSYNC and DE
signals to HX8394-F for two frames after this command is sent.
Status Availability
Default N/A
Legend
SWRESET
Red and Blue
Parameter
Display whole
blank screen
Display
Flow Chart
Action
Set Commands
to S/W Default
Value
Mode
Sequential
transfer
Sleep In Mode

HX8394-F
5.18.5 Read Display Identification Information (04h)
RDDIDIF (Read Display Identification Information)

04H
Command 0 0 0 0 0 0 1 0 0 04
st
1 parameter 1 ID1[7:0] xx
nd
rd
st
This read byte returns 24-bit display identification information. The 1 Parameter
identifies the LCD module’s manufacturer. It is specified by display supplier and for
nd
xx is defined as xxHEX. The 2 Parameter has 2 purposes. Bit7 (MSB) defines the
type of panel. 0=Driver (STN B/W), 1=Module (Colour). Bits 6..0 are used to track
the LCD module/driver version. It is defined by display supplier and it changes
each time a revision is made to the display, material or construction specifications.
See Table:
ID Byte Value V[7:0] Version Changes
Description 80h - -
81h - -
82h - -
83h - -
84h - -
85h - -
rd
The 3 parameter identifies the LCD module/driver. It is specified by display
supplier and for this LCD project module is defined as xxHEX.
Restriction -
Status Availability
Status Default Value
Power On Sequence OTP Value
Default
S/W Reset OTP Value
H/W Reset OTP Value
Flow Chart

HX8394-F
5.18.6 RDNUMPE: Read number of the parity errors (05h)
RDNUMPE (Read Number of the Parity Errors)

05H
Command 0 0 0 0 0 0 1 0 1 05
st
1 parameter 1 P7 P6 P5 P4 P3 P2 P1 P0 xx
The first parameter is telling a number of the errors on DSI. The more detailed
description of the bits is below.
P[6..0] bits are telling a number of the errors.
Description P[7] is set to ‘1’ if there is overflow with P[6..0] bits.
P[7..0] bits are set to ‘0’s (as well as RDDSM(0Eh)’s D0 is set ‘0’ at the same time)
after there is sent the second parameter information. (The read function is
completed)
Restriction SETEXTC turn on to enable this command
Status Availability

Power On Sequence 00h
Default
S/W Reset 00h
H/W Reset 00h
DSI I/F Mode Legend
Command
RDNUMPE
(R05h)
Host
Parameter
Driver
Send 1st parameter
Display
Flow Chart
Action
RDDSM (R0Eh) 's D0 = '0'
P[7:0] = "00"h
Mode
Sequential
transfer

HX8394-F
5.18.7 Get_red_channel (06h)
RDRED (Read Red Colour)

06H
Command 0 0 0 0 0 0 1 1 0 06
st
1 parameter 1 R7 R6 R5 R4 R3 R2 R1 R0 xx
The first parameter is telling red colour value of the first pixel of the frame when
there is used DPI I/F.
Description 16 bit format: R5 is MSB and R1 is LSB. R7, R6 and R0 are set to ‘0’.
18 bit format: R5 is MSB and R0 is LSB. R7 and R6 are set to ‘0’.
24 bit format: R7 is MSB and R0 is LSB.
Restriction -
Status Availability
Default
S/W Reset 00h
H/W Reset 00h
Flow Chart

HX8394-F
5.18.8 Get_green_channel (07h)
RDGREEN (Read Green Colour)

07H
Command 0 0 0 0 0 0 1 1 1 07
st
1 parameter 1 G7 G6 G5 G4 G3 G2 G1 G0 xx
The first parameter is telling green colour value of the first pixel of the frame when
there is used DPI I/F.
Description
16 and 18 bit formats: G5 is MSB and G0 is LSB. G7 and G6 are set to ‘0’.
24 bit format: G7 is MSB and G0 is LSB.
Restriction -
Status Availability

Default
S/W Reset 00h
H/W Reset 00h
Flow Chart

HX8394-F
5.18.9 Get_blue_channel (08h)
RDBLUE (Read Blue Colour)

08H
Command 0 0 0 0 0 1 0 0 0 08
st
1 parameter 1 B7 B6 B5 B4 B3 B2 B1 B0 xx
The first parameter is telling blue colour value of the first pixel of the frame
when there is used DPI I/F.
Description 16 bit format: B5 is MSB and B1 is LSB. B7, B6 and B0 are set to ‘0’.
18 bit format: B5 is MSB and B0 is LSB. B7 and B6 are set to ‘0’.
24 bit format: B7 is MSB and B0 is LSB.
Restriction -
Status Availability
Default
S/W Reset 00h
H/W Reset 00h
Flow Chart

HX8394-F
5.18.10 Read Display Status (09h)
RDDST (Read Display Status)

09H
Command 0 0 0 0 0 1 0 0 1 09
st
1 parameter 1 D[31:24] xx
nd
rd
th
This command indicates the current status of the display as described in the table
below:
Bit Description Comment
D31 Booster Voltage Status -
D30 Page Address Order Set to ‘0’
D29 Column Address Order Set to ‘0’
D28 Page/Column Order Set to ‘0’
D27 Vertical Order Set to ‘0’
D26 RGB/BGR Order -
D25 Horizontal Order Set to ‘0’
D24 Source scan sequence -
D23 Gate scan sequence -
D22
D21 Interface Colour Pixel Format Definition -
D20
D19 Idle Mode On/Off -
D18 Partial Mode On/Off Set to ‘0’
D17 Sleep In/Out -
D16 Display Normal Mode On/Off -
D15 Vertical Scrolling Status Set to ‘0’
D14 Horizontal Scrolling Status Set to ‘0’
D13 Inversion Status -
D12 All Pixels On -
D11 All Pixels Off -
Description D10 Display On/Off -
D9 Tearing Effect Line On/Off -
D8
D7 Gamma Curve Selection -
D6
D5 Tearing Effect Output Line Mode -
D4 Horizontal Sync. (HSYNC, DPI I/F) -
D3 Vertical Sync. (VSYNC, DPI I/F) -
D2 Pixel Clock (DCK, DPI I/F) -
D1 Data Enable (ENABLE, DPI I/F) -
D0 For Future Use Set to ‘0’
Bit Values are explained overleaf.
Bit D31 – Booster Voltage Status
‘0’=Booster Off.
‘1’=Booster On.
Bit D30 – Page Address Order
‘0’=Top to Bottom (When MADCTL B7=’0’).
‘1’=Bottom to Top (When MADCTL B7=’1’).
This bit is not applicable for this project, so it is set to ‘0’
Bit D29 – Column Address Order
‘0’=Left to Right (When MADCTL B6=’0’).
‘1’=Right to Left (When MADCTL B6=’1’).
Bit D28 – Page/Column Order
‘0’=Normal (When MADCTL B5=’0’).

HX8394-F
‘1’=Rotation (When MADCTL B5=’1’).
Bit D27 – Line Address Order
‘0’=LCD Refresh Top to Bottom (When MADCTL B4=’0’).
‘1’=LCD Refresh Bottom to Top (When MADCTL B4=’1’).
Bit D26 – RGB/BGR Order
‘0’=RGB (When MADCTL B3=’0’).
‘1’=BGR (When MADCTL B3=’1’).
Bit D24 – Source scan sequence
‘1’=Flipped (When MADCTL B1=’1’).
Bit D23 – Gate scan sequence
Bits D22, D21, D20 – Interface Colour Pixel Format Definition
Interface Format D22 D21 D20
Not Defined 0 0 0
Not Defined 0 0 1
Not Defined 0 1 0
Not Defined 0 1 1
Not Defined 1 0 0
16 Bit/Pixel 1 0 1
18 Bit/Pixel 1 1 0
24 Bit/Pixel 1 1 1
Bit D19 – Idle Mode On/Off
‘0’=Idle Mode Off.
‘1’=Idle Mode On.
Bit D18 – Partial Mode On/Off
‘0’=Partial Mode Off.
‘1’=Partial Mode On.
Bit D17 – Sleep In/Out
‘0’=Sleep In Mode.
‘1’=Sleep Out Mode.
Bit D16 – Display Normal Mode On/Off
‘0’=Partial or Scrolling Mode.
‘1’=Normal Mode.
Bit D15 – Vertical Scrolling On/Off
‘0’=Vertical Scrolling is Off.
‘1’=Vertical Scrolling is On.
Bit D14 – Horizontal Scrolling Status
Bit D13 – Inversion On/Off
‘0’=Inversion is Off.
‘1’=Inversion is On.
Bit D12 – All Pixels On.
‘0’=Nornal mode.
‘1’=All Pixels On.
Bit D11 – All Pixels Off.
0’=Nornal mode.
‘1’=All Pixels Off.
Bit D10 – Display On/Off
‘0’=Display is Off.
‘1’=Display is On.
Bit D9 – Tearing Effect Line On/Off
‘0’=Tearing Effect Line Off.
‘1’=Tearing Effect On.
Bits D8, D7, D6 – Gamma Curve Selection
HX8394-F
Gamma Curve Gamma Set (26h)
B8 B7 B6
Selected Parameter
Gamma Curve 1 0 0 0 GC0
Gamma Curve 2 0 0 1 GC1
Gamma Curve 3 0 1 0 Reload disable
Gamma Curve 4 0 1 1 Setting Inhibit
Not Defined 1 0 0 Not Defined
Bit D5 – Tearing Effect Line Output Mode.
‘0’=Mode 1, V-Blanking only.
‘1’=Mode 2, both H-Blanking and V-Blanking.
Bit D4 – Horizontal Sync. (HSYNC) On/Off, Note
‘0’=Horizontal Sync. Line is Off (“Low”).
‘1’=Horizontal Sync. Line is On (“High”).
Bit D3 – Vertical Sync. (VSYNC) On/Off, Note
‘0’=Vertical Sync. Line is Off (“Low”).
‘1’=Vertical Sync. Line is On (“High”).
Bit D2 – Pixel Clock (PCLK) On/Off, Note
‘0’=Pixel Clock line is Off (“Low”).
‘1’=Pixel Clock line is On (“High”).
Bit D1 – Data Enable (DE) On/Off, Note
‘0’=Data Enable line is Off (“Low”).
‘1’=Data Enable line is On (“High”).
Bit D0 – Parity Error check
Note: This bit indicates current status of the line when this command has
been sent.
Restriction
Status Availability

Power On Sequence Refer to Description
Default
S/W Reset Refer to Description
H/W Reset Refer to Description

HX8394-F
Flow Chart

HX8394-F
5.18.11 Get_power_mode (0Ah)
RDDPM (Read Display Power Mode)

0AH
Command 0 0 0 0 0 1 0 1 0 0A
st
1 parameter 1 0 D6 0 D4 D3 D2 0 0 xx
below:
D7 Not Defined Set to ‘0’
D6 Idle Mode On/Off -
D5 Partial Mode On/Off Set to ‘0’
D4 Sleep In/Out -
D3 Display Normal Mode On/Off -
D2 Display On/Off -

Bit D7 is for future use and set to ‘0’.
Bit D6 – Idle Mode On/Off
Description ‘0’=Idle Mode Off.
‘1’=Idle Mode On.
Bit D5 – Partial Mode On/Off
‘0’=Partial Mode Off.
‘1’=Partial Mode On.
Bit D4 – Sleep In/Out
‘0’=Sleep In Mode.
‘1’=Sleep Out Mode.
Bit D3 – Display Normal Mode On/Off
‘0’=Display Normal Mode Off.
‘1’=Display Normal Mode On.
Bit D2 – Display On/Off
‘0’=Display is Off.
‘1’=Display is On.
Restrictions -
Status Availability
Default
S/W Reset 08h
H/W Reset 08h

HX8394-F
Flow Chart

HX8394-F
5.18.12 Read display MADCTL (0Bh)
RDDMADCTL (Read Display MADCTL)

0BH
Command 0 0 0 0 0 1 0 1 1 0B
st
1 parameter 1 0 0 0 0 D3 0 D1 D0 xx
below:
D7 Page Address Order Set to ‘0’
D6 Column Address Order Set to ‘0’
D5 Page/Column Order Set to ‘0’
D4 Line Address Order Set to ‘0’
D3 RGB/BGR Order -
D2 Display Data Latch Order Set to ‘0’
D1 Source scan sequence -
D0 Gate scan sequence -
Bit D7 – Page Address Order

This bit is not applicable for this project, so it is set to “0”.
Bit D6 – Column Address Order
Description This bit is not applicable for this project, so it is set to “0”.
Bit D5 – Page/Column Order
Bit D4 – Line Address Order
Bit D3 – RGB/BGR Order
‘0’=RGB (When MADCTL B3=’0’).
‘1’=BGR (When MADCTL B3=’1’).
Bit D2 – Display Data Latch Data Order
Bit D1 – Source scan sequence
Bit D0 – Gate scan sequence
Restrictions -
Status Availability

Default
S/W Reset Keep
H/W Reset 00h

HX8394-F
Flow Chart

HX8394-F
5.18.13 Get_pixel_format (0Ch)
RDDCOLMOD (Read Display COLMOD)

0CH
Command 0 0 0 0 0 1 1 0 0 0C
st
1 parameter 1 0 D6 D5 D4 0 0 0 0 xx
below:
D7 Reserved Set to ‘0’
D6 -
D5 DPI Interface Pixel format -
D4 -
Bits D6, D5, D4 – DPI Interface Colour Pixel Format Definition

Description Bits D2, D1, D0 – DBI Interface Colour Pixel Format Definition.
This bit is not applicable for this project, and it is set to “1”.
Interface Colour Format D6 D5 D4

Not Defined 0 0 0
Not Defined 0 0 1
Not Defined 0 1 0
Not Defined 0 1 1
Not Defined 1 0 0
16-bit/pixel 1 0 1
18-bit/pixel 1 1 0
24-bit/pixel 1 1 1
If the setting is not used then the corresponding bits in the parameter returned from
Restrictions -
Status Availability

Default
S/W Reset 07h
H/W Reset 07h

HX8394-F
Flow Chart

HX8394-F
5.18.14 Get_display_mode (0Dh)
RDDIM (Read Display Image Mode)

0DH
Command 0 0 0 0 0 1 1 0 1 0D
st
1 parameter 1 0 0 D5 D4 D3 D2 D1 D0 xx
below:
Bit D7 – Vertical Scrolling On/Off
Bit D6 – Horizontal Scrolling Status
Bit D5 – Inversion On/Off
‘0’=Inversion is Off.
‘1’=Inversion is On.
Bit D4 – All Pixels On
‘0’=Normal Display
‘1’=White Display
Bit D3 – All Pixels Of
Description ‘0’=Normal Display
‘1’=Black Display
Bits D2, D1, D0 – Gamma Curve Selection
Gamma Curve Gamma Set (26h)
D2 D1 D0
Selected Parameter
Gamma Curve1 0 0 0 GC0
Gamma Curve2 0 0 1 GC1
Gamma Curve3 0 1 0 Reload disable
Gamma Curve4 0 1 1 Setting Inhibit
Restrictions -
Status Availability
Default
S/W Reset 00h
H/W Reset 00h

HX8394-F
Flow Chart

HX8394-F
5.18.15 Get_signal_mode (0Eh)
RDDSM (Read Display Signal Mode)

0EH
Command 0 0 0 0 0 1 1 1 0 0E
st
1 parameter 1 D7 D6 D5 D4 D3 D2 0 0 xx
This command indicates the current status of the display described in the table as
below:
Bit D7 – Tearing Effect Line On/Off
‘0’=Tearing Effect Line Off.
‘1’=Tearing Effect On.
Bit D6 – Tearing Effect Line Output Mode, see section 5.1 for mode definitions.
‘0’=Mode 1.
‘1’=Mode 2.
Bit D5 – Horizontal Sync. (DPI I/F) On/Off.
‘0’=Horizontal Sync. Line is Off (“Low”).
Description ‘1’=Horizontal Sync. Line is On (“High”).
Bit D4 – Vertical Sync. (DPI I/F) On/Off.
‘0’=Vertical Sync. Line is Off (“Low”).
‘1’=Vertical Sync. Line is On (“High”).
Bit D3 – Pixel Clock (PCLK, DPI I/F) On/Off.
‘0’=PCLK line is Off (“Low”).
‘1’=PCLK line is On (“High”).
Bit D2 – Data Enable (DE, DPI I/F) On/Off.
‘0’=DE line is Off (“Low”).
‘1’=DE line is On (“High”).
Bits D[1:0] – Reserved.
Restrictions -
Status Availability
Default
S/W Reset 00h
H/W Reset 00h
Flow Chart

HX8394-F
5.18.16 Get_diagnostic_result (0Fh)
RDDSDR (Read Display Self-Diagnostic Result)

0FH
Command 0 0 0 0 0 1 1 1 1 0F
st
1 parameter 1 D7 D6 D5 D4 0 0 0 0 xx
The display module returns the self-diagnostic results following a Sleep Out
command. See section 5.10 for a description of the status results.
Bit D7 – Register Loading Detection
Bit D6 – Functionality Detection
Description Bit D5 – Chip Attachment Detection
Set to ‘0’ if feature unimplemented.
Bit D4 – Display Glass Break Detection
Set to ‘0’ if feature unimplemented.
Bits D[3:0] – Reserved.
Restrictions -
Status Availability
Default
S/W Reset 00h
H/W Reset 00h
Flow Chart

HX8394-F
5.18.17 Enter_sleep_mode (10h)
SLPIN (Sleep In)

10H
Command 0 0 0 0 1 0 0 0 0 10
This command causes the LCD module to enter the minimum power consumption
mode.
In this mode the DC/DC converter is stopped, Internal oscillator is stopped, and
panel scanning is stopped.
Description
This command has no effect when module is already in sleep in mode.Sleep In

Mode can only be left by the Sleep Out Command (11h). It will be necessary to wait
5msec before sending next command, this is to allow time for the supply voltages
Restriction and clock circuits to stabilize. It will be necessary to wait 120msec after sending
Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent.
The host processor continues to send PCLK, HSYNC, and VSYNC and DE signals
to HX8394-F for two frames after this command is sent.
Status Availability
Default N/A
It takes 120msec to get into Sleep In mode after SLPIN command issued.
Flow Chart

HX8394-F
5.18.18 Exit_sleep_omde (11h)
SLPOUT (Sleep Out)

11H
Command 0 0 0 0 1 0 0 0 1 11
This command turns off sleep mode. In this mode the DC/DC converter is enabled,
Internal oscillator is started, and panel scanning is started.
Description
This command has no effect when module is already in sleep out mode. Sleep Out
Mode can only be left by the Sleep In Command (10h). It will be necessary to wait
5msec before sending next command, this is to allow time for the supply voltages
and clock circuits to stabilize. The display module loads all display supplier’s factory
default values to the registers during this 5msec and there cannot be any abnormal
visual effect on the display image if factory default and register values are same
Restriction
when this load is done and when the display module is already Sleep Out –mode.
The display module is doing self-diagnostic functions during this 5msec. It will be
necessary to alit 120msec after sending Sleep In command (when in Sleep Out
mode) before Sleep Out command can be sent.
The host processor continues to send PCLK, HSYNC, and VSYNC and DE signals
to HX8394-F for two frames after this command is sent.
Status Availability
Default N/A
It takes 120msec to become Sleep Out mode after SLPOUT command issued.
Flow Chart

HX8394-F
5.18.19 Enter_normal_mode (13h)
NORON (Normal Display Mode On)

13H
Command 0 0 0 0 1 0 0 1 1 13
Description This command returns the display to normal mode.
Restriction This command has no effect when Normal Display mode is active.
Status Availability

Power On Sequence Normal display mode
Default
S/W Reset Normal display mode
H/W Reset Normal display mode
Flow Chart -

HX8394-F
5.18.20 Exit_inversion_mode (20h)
INVOFF (Display Inversion Off)

20H
Command 0 0 0 1 0 0 0 0 0 20
This command is used to recover from display inversion mode.
This command does not change any other status.
Description
Restriction This command has no effect when module is already in inversion off mode.
Status Availability
Default
Flow Chart

HX8394-F
5.18.21 Enter_inversion_mode (21h)
INVON (Display Inversion On)

21H
Command 0 0 0 1 0 0 0 0 1 21
This command is used to enter into display inversion mode.
Description
Restriction This command has no effect when module is already in inversion on mode.
Status Availability
Default
Flow Chart

HX8394-F
5.18.22 All_Pixel_Off (22h)
ALLPOFF (All Pixel Off)

22H
Command 0 0 0 1 0 0 0 1 0 22
This command turns the display panel black in ‘Sleep Out’ –mode and a status of
the ‘Display On/Off’ –register can be ‘on’ or ‘off’.
Description
‘All Pixels On’ or ’Normal Display Mode On’ – commands are used to leave this
mode. The display is showing the content of the frame memory after ‘Normal
Display Mode On’ command.
Status Availability
Default
Flow Chart

HX8394-F
5.18.23 All_Pixel_On (23h)
ALLPON(All Pixel On)

23H
Command 0 0 0 1 0 0 0 1 1 23
This command turns the display panel white in ‘Sleep out ‘ –mode and a status of
the ‘Display On/Off’ –register can be ‘on’ or ‘off’.
Description
‘All Pixels Off’ or ’Normal Display Mode On’ – commands are used to leave this
mode. The display is showing the content of the frame memory after ‘Normal
Display Mode On’ command.
Status Availability
Default
Flow Chart

HX8394-F
5.18.24 Set_gamma_curve (26h)
GAMSET (Gamma Set)

26H
Command 0 0 0 1 0 0 1 1 0 26
Parameter 1 GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0 1..08
This command is used to select the desired Gamma curve for the current display.
A maximum of 4 fixed gamma curves can be selected. The curves are defined in
Curve Correction Power Supply Circuit. The curve is selected by setting the
appropriate bit in the parameter as described in the Table:
GC[7:0] Parameter Curve selected OTP index
Gamma Curve 1 (reload from OTP
Description 01h GC0 45h~FDh
gamma set1)
Gamma Curve 2 (reload from OTP
02h GC1 100h~1B8h
gamma set2)
04h GC2 Reload disable -
08h GC3 Setting Inhibit -
Note: All other values are undefined.

Values of GC[7:0] not shown in table above are invalid and will not change the
Restriction
current selected Gamma curve until valid value is received.
Status Availability

Default
S/W Reset 01h
H/W Reset 01h
Legend
GAMSET Command
Parameter
GC [7:0] Display
Flow Chart Action
New Gamma Mode

Curve Loaded
Sequential
transfer

HX8394-F
5.18.25 Set_display_off (28h)
DISPOFF (Display Off)

28H
Command 0 0 0 1 0 1 0 0 0 28
This command is used to enter into DISPLAY OFF mode. In this mode, the output
from DPI I/F is disabled and blank page inserted.
There will be no abnormal visible effect on the display.
Description
Restriction This command has no effect when module is already in display off mode.
Status Availability
Power On Sequence Display off
Default
S/W Reset Display off
H/W Reset Display off
Legend
Display On Command
Mode
Parameter
Display
Flow Chart DISPOFF
Action
Mode
Display Off
Mode Sequential
transfer

HX8394-F
5.18.26 Set_display_on (29h)
DISPON (Display On)

29H
Command 0 0 0 1 0 1 0 0 1 29
This command is used to recover from DISPLAY OFF mode. Output from DPI I/F is
enabled.
Description
Restriction This command has no effect when module is already in display on mode.
Status Availability
Power On Sequence Display on
Default
S/W Reset Display on
H/W Reset Display on
Flow Chart

HX8394-F
5.18.27 Write_memory_start (2Ch))
RAMWR (Memory Write)

2CH
Command 0 0 0 1 0 1 1 0 0 2C
st
1 parameter 1 D17 D16 D15 D14 D13 D12 D11 D10 00..FF
: 1 Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 00..FF
th
N parameter 1 Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 00..FF
This command transfers image data from the host processor to the display module’s frame
Description memory. The start pointer is (0,0).Frame memory pointer will auto increment when data is
written.
Restriction The transferred data must be line based.
Status Availability
Default Contents of memory is set randomly and not cleared.

Legend
RAMWR Command
Parameter
Image Data
D1[7:0],D2[7:0], Display
...,Dn[7:0]
Flow Chart Action
Any Command Mode
Sequential
transfer

HX8394-F
5.18.28 Tearing effect line off (34h)
TEOFF (Tearing Effect Line OFF)

34H
Command 0 0 0 1 1 0 1 0 0 34
This command is used to turn OFF (Active Low) the Tearing Effect output signal from the
Description TE signal line.
Restriction This command has no effect when Tearing Effect output is already OFF.
Status Availability

Power On Sequence Off
Default
S/W Reset Off
H/W Reset Off
Flow Chart

HX8394-F
5.18.29 Set_tear_on (35h)
TEON (Tearing Effect Line ON)

35H
Command 0 0 0 1 1 0 1 0 1 35
Parameter 1 X X X X X X X M xx
This command is used to turn ON the Tearing Effect output signal from the TE
signal line.
The Tearing Effect Line On has one parameter which describes the mode of the
Tearing Effect Output Line. (X=Don’t Care).
When M=0:
The Tearing Effect Output line consists of V-Blanking information only:
tvdl tvdh
Vertical Time
Scale
Description
When M=1:
The Tearing Effect Output Line consists of both V-Blanking and H-Blanking
information:
tvdl tvdh
Vertical Time
Scale
Note: M=1 is not applicable for this project, so it is set to “0”.

Restriction This command has no effect when Tearing Effect output is already ON.
Status Availability

Default
S/W Reset Off
H/W Reset Off
Legend
TE Line Output OFF Command
Parameter
TEON
Display
Flow Chart
M Action
Mode
TE Line Output ON
Sequential
transfer

HX8394-F
5.18.30 Set_address_mode (36h)
MADCTL (Memory Access Control)

36H
Command 0 0 0 1 1 0 1 1 0 36
st
1 parameter 1 X X X X B3 X B1 B0 xx
This command defines the display scanning direction of LCD.
This command makes no change on the other driver status.
Bit Assignment
Bit Name Description
Page Address Order This bit is not applicable for this project,
B7
so it is set to “0”.
Column Address Order This bit is not applicable for this project,
B6
Page/Column Selection This bit is not applicable for this project,
B5
Display Device Line This bit is not applicable for this project,
B4
Refresh Order so it is set to “0”.
Colour selector switch control
B3 RGB-BGR Order (BGR) (0=RGB colour filter panel, 1=BGR colour
filter panel)
Display Data Latch Data This bit is not applicable for this project,
B2
Order so it is set to “0”.
Flip Horizontal Select the Source driver scan direction
B1
(Source scan sequence) on panel module
Description Flip Vertical Select the Gate driver scan direction on
B0
(Gate scan sequence) panel module

HX8394-F
st
Restriction D7, D6, D5, D4, and D2 of the 1 parameter are set to ‘0’ internally.
Status Availability

Default
S/W Reset No Change
H/W Reset 00h
Flow Chart

HX8394-F
5.18.31 Idle mode off (38h)
IDMOFF (Idle mode off)

38H
Command 0 0 0 1 1 1 0 0 0 38
This command is used to recover from Idle mode on. In the idle off mode, LCD
Description
can display maximum 16.7M colours.
Restriction This command has no effect when module is already in idle off mode.
Status Availability
Default
S/W Reset Off
H/W Reset Off
Flow Chart

HX8394-F
5.18.32 Enter_Idle_mode (39h)
IDMON (Idle mode on)

39H
Command 0 0 0 1 1 1 0 0 1 39
This command is used to enter into Idle mode on. In the idle on mode, colour
expression is reduced. The primary and the secondary colours using MSB of
each R, G and B, 8 colour depth data is displayed.
(Example)
Memory Display
Description Display Colour

R7 – R0 G7 – G0 B7 – B0
Black 0XXXXX 0XXXXX 0XXXXX
Blue 0XXXXX 0XXXXX 1XXXXX
Red 1XXXXX 0XXXXX 0XXXXX
Magent 1XXXXX 0XXXXX 1XXXXX
Green 0XXXXX 1XXXXX 0XXXXX
Cyan 0XXXXX 1XXXXX 1XXXXX
Yellow 1XXXXX 1XXXXX 0XXXXX
White 1XXXXX 1XXXXX 1XXXXX
X=don’t care
Restriction This command has no effect when module is already in idle on mode.
Status Availability
Default
S/W Reset Off
H/W Reset Off
Flow Chart

HX8394-F
5.18.33 Set_pixel_format (3Ah)
COLMOD (Interface Pixel Format)

3A H
Command 0 0 0 1 1 1 0 1 0 3A
st
1 parameter 1 X D6 D5 D4 X X X X XX
This command is used to define the format of RGB picture data.
D6~D4: DPI Pixel format Definition.
Bits D7, D[3:0]: Reserved.
The formats are shown in the table:
Pixel Format D6 D5 D4
Not Defined 0 0 0
Not Defined 0 0 1
Description Not Defined 0 1 0
Not Defined 0 1 1
Not Defined 1 0 0
16 Bit/Pixel 1 0 1
18 Bit/Pixel 1 1 0
24 Bit/Pixel 1 1 1
If the setting is not used then the corresponding bits in the parameter returned
Restriction There is no visible effect until the image data is written.

Status Availability

Default
S/W Reset 70h
H/W Reset 70h
Flow Chart

HX8394-F
5.18.34 Write_memory_contiune (3Ch)
Write_memory_contiune
3CH
D/CX D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 0 0 1 1 1 1 0 0 3C
st
1
1 D17 D16 D15 D14 D13 D12 D11 D10 00..FF
parameter
: 1 Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 00..FF
th
N
1 Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 00..FF
parameter
This command transfers image data from the host processor to the display module’s
frame memory continuing from the pixel location following the previous
Description
write_memory_continue or write_memory_start command. Sending any other command
can stop frame Write.
Restriction The transferred data must be line based.
Status Availability
Status Default value

Default Power On Sequence Contents of memory is set randomly
S/W Reset Contents of memory is set randomly
Legend
RAMWR Command
Parameter
Image Data
D1[7:0],D2[7:0], Display
...,Dn[7:0]
Flow Chart Action
Any Command Mode
Sequential
transfer

HX8394-F
5.18.35 Set tear scan lines (44h)
TESL (Tear Effect Scan Lines)

44H
Command 0 0 1 0 0 0 1 0 0 44
st
1 parameter 1 TELINE[15:8] (8’b0) 00..FF
nd
2 parameter 1 TELINE[7:0] (8’b0) 00..FF
This command is turns on the display module’s Tearing Effect output signal on the
TE signal
Line when the display module reacfes line TELINE. The TE signal is not affected
by changing MADCTL bit B4.
The Tearing Effect Line On has one parameter which describes the mode of the
Tearing Effect Output Line.
The Tearing Effect Output line consists of V-Blanking information only:
Description
tvdl tvdh
Vertical Time
Scale
Note: That TELINE=0 is equivalent to TEMODE=0. The Tearing Effect Output Line shall
be active low when the display module is in Sleep mode.
Restriction The command has no effect when Tearing Effect output is already ON.
Status Availability
Default
S/W Reset 0000h
H/W Reset 0000h
Flow Chart

HX8394-F
5.18.36 Get the current scanline(45h)
GETSCAN (Get the current scanline)

45H
Command 0 0 1 0 0 0 1 0 1 45
st
1 parameter 1 SLN[15:8] (8’b0) 00..FF
nd
2 parameter 1 SLN[7:0] (8’b0) 00..FF
The display module returns the current scanline, N, used to update the display
device. The total number of scanlines on a display device is defined as VSYNC +
Description VBP + VACT + VFP. The first scanline is defined as the first line of V Sync and is
denoted as Line 0.
When in Sleep Mode, the value returned by get_scanline is undefined.
Restriction -
Status Availability
Default
S/W Reset 0000h
H/W Reset 0000h
Flow Chart

HX8394-F
5.18.37 Write display brightness (51h)
WRDISBV (Write Display Brightness)

51H
Command 0 0 1 0 1 0 0 0 1 51
st
1 parameter 1 DBV[7:0] 00..FF
This command is used to adjust the brightness value of the display.
It should be checked what the relationship between this written value and output
brightness of the display is. This relationship is defined on the display module
Description specification.
In principle relationship is that 00h value means the lowest brightness and FFh
value means the highest brightness.
See chapter “5.13.3 Brightness Control Block”.
Restriction -
Status Availability
Default
S/W Reset 00h
H/W Reset 00h
Flow Chart

HX8394-F
5.18.38 Read display brightness value (52h)
RDDISBV (Read Display Brightness Value)

52H
Command 0 0 1 0 1 0 0 1 0 52
st
1 parameter 1 DBV[7:0] xx
This command returns the brightness value of the display.
It should be checked what the relationship between this returned value and output
brightness of the display. This relationship is defined on the display
modulespecification is.
In principle the relationship is that 00h value means the lowest brightness and
FFh value means the highest brightness.
See chapters: “5.13.3 Brightness Control Block”, and “6.2.33 Write Display
Brightness (51h)”
Description DBV[7:0] is reset when display is in sleep-in mode.
DBV[7:0] is ‘00h’ when bit BCTRL of “6.2.35 Write CTRL Display (53h)” command
is ‘0’.
DBV[7:0] is manual set brightness specified with “6.2.35 Write CTRL Display
(53h)” command when bit BCTRL is ‘1’.
When bit BCTRL of “6.2.35 Write CTRL Display (53h)” command is ‘1’ and bit
C1/C0 of “6.2.37 Write Content Adaptive Brightness Control (55h)” are ‘0’,
DBV[7:0] output is the brightness value specified with “6.2.33 Write Display
Brightness (51h)” command.
Restriction -
Status Availability
Default
S/W Reset 00h
H/W Reset 00h
Flow Chart

HX8394-F
5.18.39 Write CTRL display (53h)
WRCTRLD (Write Control Display)

53H
Command 0 0 1 0 1 0 0 1 1 53
st
1 parameter 1 X X BCTRL X DD BL X X 00..FF
This command is used to control display brightness.
BCTRL: Brightness Control Block On/Off, This bit is always used to switch
brightness for display.
0=Off (Brightness registers are 00h, DBV[7..0])
1=On (Brightness registers are active, according to the other parameters.)
Display Dimming (DD): (Only for manual brightness setting)
DD=0: Display Dimming is off
Description DD=1: Display Dimming is on
BL: Backlight Control On/Off
0=Off (Completely turn off backlight circuit. Control lines must be low. )
1=On
Dimming function is adapted to the brightness registers for display when bit
BCTRL is changed at DD=1, e.g. BCTRL: 0 -> 1 or 1-> 0.
When BL bit change from “On” to “Off”, backlight is turned off without gradual
dimming, even if dimming-on (DD=1) are selected.
X=Don’t care.
Restriction -
Status Availability
Default
S/W Reset 00h
H/W Reset 00h
Flow Chart

HX8394-F
5.18.40 Read CTRL value display (54h)
RDCTRLD (Read Control Value Display)

54H
Command 0 0 1 0 1 0 1 0 0 54
st
1 parameter 1 X X BCTRL X DD BL X X xx
This command returns ambient light and brightness control values, see chapter:
“6.2.35 Write CTRL Display (53h)”.
BCTRL: Brightness Control Block On/Off, This bit is always used to switch
brightness for display.
0=Off
Description 1=On
Display Dimming (DD):
DD=0: Display Dimming is off
DD=1: Display Dimming is on
BL: Backlight Control On/Off
0=Off (Completely turn off backlight circuit)
1=On
Restriction -
Status Availability

Default
S/W Reset 00h
H/W Reset 00h
Legend
Command
Serial I/F Mode
Parameter
Read RDCTRLD Displa
Host y
Flow Chart Display
Parameter Action
Mode
Sequential
transfer

HX8394-F
5.18.41 Write content adaptive brightness control (55h)
WRCABC (Write Content Adaptive Brightness Control)

55 H
Command 0 0 1 0 1 0 1 0 1 55
st
1 parameter 1 X X X X X X CABC[1:0] xx
This command is used to set parameters for image content based adaptive
brightness control functionality.
There is possible to use 4 different modes for content adaptive image functionality,
which are defined on a table below. See chapter “5.13 Content Adaptive
Brightness Control (CABC)”.
Description CABC[1] CABC[0] Function
0 0 Off
0 1 User Interface Image
1 0 Still Picture
1 1 Moving Image
Restriction -
Status Availability

Default
S/W Reset 00h
H/W Reset 00h
Flow Chart

HX8394-F
5.18.42 Read content adaptive brightness control (56h)
RDCABC (Read Content Adaptive Brightness Control)

56H
Command 0 0 1 0 1 0 1 1 0 56
st
1 parameter 1 0 0 0 X 0 0 CABC[1:0] xx
This command is used to set parameters for image content based adaptive
brightness control functionality.
There is possible to use 4 different modes for content adaptive image functionality,
which are defined on a table below. See chapter “5.13 Content Adaptive
Brightness Control (CABC)”.
Description
CABC[1] CABC[0] Function
0 0 Off
0 1 User Interface Image
1 0 Still Picture
1 1 Moving Image
Restriction
Status Availability
Default
S/W Reset 00h
H/W Reset 00h
Flow Chart

HX8394-F
5.18.43 Write CABC minimum brightness (5Eh)
WRCABCMB (Write CABC minimum brightness)

5E H
Command 0 0 1 0 1 1 1 1 0 5E
st
1 parameter 1 CMB[7:0] 00..FF
This command is used to set the minimum brightness value of the display for
CABC function.
Description In principle relationship is that 00h value means the lowest brightness for CABC
and FFh value means the highest brightness for CABC.
See chapter “5.13.4 Minimum brightness setting of CABC function”.
Restriction -
Status Availability

Default
S/W Reset 00h
H/W Reset 00h
Flow Chart

HX8394-F
5.18.44 Read CABC minimum brightness (5Fh)
RDCABCMB (Read CABC minimum brightness)

5FH
Command 0 0 1 0 1 1 1 1 1 5F
st
1 parameter 1 CMB[7:0] XX
This command returns the minimum brightness value of CABC function.
In principle the relationship is that 00h value means the lowest brightness and FFh
value means the highest brightness.
Description
See chapter “5.13.4 Minimum brightness setting of CABC function”.
CMB[7:0] is CABC minimum brightness specified with “6.2.39 Write CABC
minimum brightness (5Eh)” command.
Restriction -
Status Availability

Default
S/W Reset 00h
H/W Reset 00h
Flow Chart

HX8394-F
5.18.45 Read automatic brightness control self-diagnostic result (68h)
RDABCSDR (Read Automatic Brightness Control Self-Diagnostic Result)

68H
Command 0 0 1 1 0 1 0 0 0 68
st
1 parameter 1 D[7:6] 0 0 0 0 0 0 xx
This command indicates the status of the display self-diagnostic results for
automatic brightness control after Sleep Out –command as described in the table
below:
Bit D7 – Register Loading Detection.
Description
See section “5.10.1 Register loading Detection”.
Bit D6 – Functionality Detection.
See section “5.10.2 Functionality Detection “.
Bits D[5:0] are for future use and are set to ‘0’.
Restriction -
Status Availability
Default
S/W Reset 00h
H/W Reset 00h
Legend
Command
Serial I/F Mode
Parameter
Read RDABCSDR
Host Display
Flow Chart Display
Parameter Action
Mode
Sequential
transfer

HX8394-F
5.18.46 Write Idle Mode Color(80h)
WRIMCOL (Write Idle Mode Color)
80 H
Command 0 1 0 0 0 0 0 0 0 80
st
1 parameter 1 X X X X X R G B 07
This command can be used to select color 1bbp Idle Mode. Color selection is
configured with bits [2:0], where:
D2: R Component
D1: G Component
D0: B Component
Color selection is defined in the following table:

1bpp Idle Mode
R G B
Color Selection
Black 0 0 0
Blue 0 0 1
Description Green 0 1 0
Cyan 0 1 1
Red 1 0 0
Magenta 1 0 1
Yellow 1 1 0
White 1 1 1
Default setting for 1bpp color selection for “Normal Black” panel is ‘White’;
R=G=B=’1’
X=Reserved
Restriction -
Status Availability

Default
S/W Reset 07h
H/W Reset 07h
Flow Chart
5.18.47

HX8394-F
5.18.48 Read Idle Mode Color(81h)
RDIMCOL (Read Idle Mode Color)

81 H
Command 0 1 0 0 0 0 0 0 1 81
st
1 parameter 1 0 0 0 0 0 R G B 07
This command returns the current color selection of 1bbp Idle Mode. Bits [2:0] are
defined as:
D2: R Component
D1: G Component
D0: B Component
Color selection is defined in the following table:

1bpp Idle Mode
R G B
Color Selection
Black 0 0 0
Description Blue 0 0 1
Green 0 1 0
Cyan 0 1 1
Red 1 0 0
Magenta 1 0 1
Yellow 1 1 0
White 1 1 1
Default setting for 1bpp color selection for “Normal Black” panel is ‘White’;
R=G=B=’1’
Restriction -
Status Availability

Default
S/W Reset 07h
H/W Reset 07h
Flow Chart

HX8394-F
5.18.49 Read_DDB_start (A1h)
Read_DDB_start
A1H
Command 0 1 0 1 0 0 0 0 1 A1
st
1 parameter 1 xx xx xx xx xx xx xx xx xx
nd
: 1 xx xx xx xx xx xx xx xx xx
th
N parameter 1 xx xx xx xx xx xx xx xx xx
This command reads identifying and descriptive information from the peripheral.
This information is organized in the Device Descriptor Block (DDB) stored on the
peripheral. The response to this command returns a sequence of bytes that may
be any length up to 64K bytes. Note that the returned sequence of bytes does not
necessarily correspond to the entire DDB; it may be a portion of a larger block of
data.
The format of returned data is as follows:
Parameter 1: LS (least significant) byte of Supplier ID. Supplier ID is a unique value
assigned to each peripheral supplier by the MIPI organization.
Parameter 2: MS (most significant) byte of Supplier ID.
Parameter 3: LS (least significant) byte of Supplier Elective Data. This is a byte of
information that is determined by the supplier. It could include model number or
revision information, for example.
Parameter 4: MS (most significant) byte of Supplier Elective Data
Parameter 5: single-byte Escape or Exit Code (EEC). The code is interpreted as
follows:
- FFh – Exit code – there is no more data in the Descriptor Block
- 00h – Escape code – there is supplier-proprietary data in the Descriptor Block
(does not conform to any MIPI standard)
- Any other value – there is DDB data in the Descriptor Block. The format and
Description
interpretation of this data is documented in MIPI Alliance Standard for Device
Descriptor Block (DDB).
DDBs may contain many more data fields providing information about the
peripheral.
In a DSI system, read activity takes the form of two separate transactions across
the bus: first the read command read_DDB_start from host processor to peripheral,
which includes the bus turn-around token.
The peripheral then takes control of the bus and returns the requested data. The
peripheral response to read_DDB_start is a Long Packet type, so its length may be
up to 64K bytes unless limited by a previous set_max_return_size command.
The response to a read_DDB_start command always starts at the beginning of the
Device Descriptor Block. After receiving the first packet and processing the
returned DDB data, the host processor may initiate a read_DDB_continue
command to access the next portion of the DDB. A read_DDB_continue command
begins the next read at the location following the last byte of the previous data read
from the DDB.
Subsequent read_DDB_continue commands can be used to read a DDB or
supplier-proprietary block of arbitrary size. There is, however, no obligation to read
the entire block. The host processor may choose to stop reading after completion
of any read_DDB_xxx command.
Restrictions -
Status Availability
th
Power On Sequence PA1st~4 is OTP value, PA5th is FFh
Default th
S/W Reset PA1st~4 is OTP value, PA5th is FFh
th
H/W Reset PA1st~4 is OTP value, PA5th is FFh

HX8394-F
Flow Chart

HX8394-F
5.18.50 Read_DDB_continue (A8h)
Read_DDB_continue
A8H
Command 0 1 0 1 0 1 0 0 0 A8
st
nd
: 1 xx xx xx xx xx xx xx xx xx
th
N parameter 1 xx xx xx xx xx xx xx xx xx
A read_DDB_start command should be executed at least once before a
Description read_DDB_continue command to define the read location. Otherwise, data read
with a read_DDB_continue command is undefined.
Restrictions -
Status Availability
st th
Without A1h read, 1 ~4 read is the
st th th
Power On Sequence same as A8h 1 ~4 OTP value, after 5
read is FFh.
st th
Default st th th
S/W Reset same as A8h 1 ~4 OTP value, after 5
read is FFh.
st th
st th th
H/W Reset same as A8h 1 ~4 OTP value, after 5
read is FFh.
Flow Chart

HX8394-F
5.18.51 Read ID1 (DAh)
RDID1 (Read ID1)

DAH
Command 0 1 1 0 1 1 0 1 0 DA
st
1 parameter 1 module’s manufacturer[7:0] xx
This read byte identifies the LCD module’s manufacturer. It is specified by display
Description
supplier and for xx is defined as xxHEX.
Restriction -
Status Availability

Power On Sequence OTP value
Default
S/W Reset OTP value
H/W Reset OTP value
Legend
Command
Serial I/F Mode
Parameter
Display
Read ID1
Flow Chart Host
Action
Display
Parameter Mode
Sequential
transfer

HX8394-F
5.18.52 Read ID2 (DBh)
RDID2 (Read ID2)

DBH
Command 0 1 1 0 1 1 0 1 1 DB
st
1 parameter 1 1 LCD module/driver version [6:0] xx
This read byte is used to track the LCD module/driver version. It is defined by
display supplier and changes each time a revision is made to the display, material
or construction specifications. See Table:
ID Byte Value V[7:0] Version Changes
80h
Description 81h
82h
83h
84h
85h
X= Don’t care
Restrictions -
Status Availability

Default
S/W Reset OTP value
H/W Reset OTP value
Flow Chart

HX8394-F
5.18.53 Read ID3 (DCh)
RDID3 (Read ID3)

DCH
Command 0 1 1 0 1 1 1 0 0 DC
st
1 parameter 1 LCD module/driver ID[7:0] xx
This read byte identifies the LCD module/driver. It is specified by display supplier
Description
and for this LCD project module is defined as xxHEX.
Restrictions -
Status Availability

Default
S/W Reset OTP value
H/W Reset OTP value
Flow Chart

HX8394-F
5.19User define command description
5.19.1 SETSEQUENCE: Set sequence (B0h)
SETSEQUENCE( Set Sequence)

B0H
Command 0 1 0 1 1 0 0 0 0 B0
st
1 parameter 1 - - - - - - - -
nd OSC_
2 parameter 1 - - - - - - -
EN
rd VSN_ VSP_ VGL_ VGH_ VCL_
3 parameter 1 -
EN EN EN EN EN
- STB
th
4 parameter 1 - - - - GON DTE D[1:0]
This command is used for DCS command auto sequence and manual mode debug use,
please don't access this command in initial code.
OSC_EN: Enable internal oscillator. “1”: Enable; “0”: Disable.
STB: When STB = “1”, the HX8394-F enters the standby mode, where all display operation
stops, suspend all the internal operations. But the internal R-C oscillator stop or not is
determined by OSC_EN bit. To minimize the standby power, OSC_EN is set to 0. During
the standby mode, only the following process can be executed.
a. Exit the Standby mode (STB = “0”)
b. Enable or disable the oscillator
c. Software reset
VCL_EN : ON/OFF the operation of VCL charge bump circuit in manual power on mode.
Using state machine SLPOUT CMD to power on this bit must set “1”.
VCL_EN Operation of VCL charge bump circuit
0 OFF
1 ON
VGH_EN: ON/OFF the operation of VGH charge bump circuit in manual power on mode.
VGH_EN Operation of VGH charge bump circuit
Description 0 OFF
1 ON
VGL_EN : ON/OFF the operation of VGL charge bump circuit in manual power on mode.
VGL_EN Operation of VGL charge bump circuit
0 OFF
1 ON
VSP_EN: ON/OFF the operation of VSP circuit in manual power on mode. Using state
machine SLPOUT CMD to power on this bit must set “1”.
VSP_EN Operation of VSP DC/DC circuit
0 OFF
1 ON
VSN_EN: ON/OFF the operation of VSN circuit in manual power on mode. Using state
machine SLPOUT CMD to power on this bit must set “1”.
VSN_EN Operation of VSN DC/DC circuit

0 OFF
1 ON
GON: GIP control signal enable selection

HX8394-F
GON GIP Enable
0 GIP Off
1 GIP On
DTE: Source output enable selection

DTE Source Output
0 Source output off
1 Source output on
D[1:0]: Setting Source driver output

D1 D0 Source Output HX8394-F Internal Operations
0 0 Halt Halt
0 1 Blanking or GND GIP initial sequence
1 0 V255 or V0 Blanking
1 1 Normal Operate
Restrictions SETEXTC turn on to enable this command.

Status Availability

HX8394-F
5.19.2 SETPOWER: Set power (B1h)
SETPOWER( Set power related setting)

B1H
Command 0 1 0 1 1 0 0 0 1 B1
Bank0 DSTBY
st 1 - POWMOD[1:0] AP[2:0] DSTB
1 parameter _OPT
nd
2 parameter 1 VCLS[2:0] VRHP[4:0]
rd
3 parameter 1 VPPS[2:0] VRHN[4:0]
th EQ_V VSP_F
4 parameter 1 - - - XDK[2:0]
CLEN BOFF
th
5 parameter 1 - - CLK_OPT[2:1] FS0[3:0]
th
6 parameter FS1[3:0] FS2[3:0]
th
7 parameter 1 VGH_RATIO[2:0] BTP[4:0]
th
8 parameter 1 VGL_RATIO[2:0] BTN[4:0]
th
9 parameter 1 - VGHS[7:0]
th
10 parameter 1 - VGLS[7:0]
st
11 parameter 1 DT1[1:0] DT2[1:0] DCDIV[3:0]
nd
12 parameter 1 - DCS[2:0] - DC[2:0]
rd
13 parameter 1 - DTPS[2:0] - DTP[2:0]
th
14 parameter 1 - DTNS[2:0] - DTN[2:0]
Bank1 APF_E GASIOVCC_OPT
st 1 - - GASVCI_OPT[2:0]
1 parameter N [1:0]
GAS_
nd
2 parameter 1 CP_VS GASVSN_OPT[2:0] - GASVSP_OPT[2:0]
PVSN
rd GASVGL_OPT[1: GASVGH_OPT[1:
3 parameter 1 - -
0]
- -
0]
This command is used to set related setting of power.
POWMOD[1:0]: Power mode selection

POWMOD[1] POWMOD[0] Power Mode
0 0 PFM Type A
0 1 PFM Type C
1 0 HX5186
1 1 inhibited
DSTBY_OPT: DSTB mode option. When DSTBY_OPT=0, logic power will be off and must
HWRESET to leave deep standy mode.
DSTB: Set ‘1’ to enter deep standby mode for saving power in SLPIN mode. User must
enter SLPIN mode before enter deep standby mode.
Description
When DSTBY_OPT=0:
Enter DSTB Mode Leave DSTB Mode
Sleep in mode
Deep standby mode
Set DSTB=1
RESX pin low pulse at least
3ms
Deep standby mode

Sleep in mode
When DSTBY_OPT=1:

HX8394-F
AP[2:0]: Adjust the amount of fixed current from the fixed current source for the operational
amplifier in the power supply circuit. When the amount of fixed current is increased, the LCD
driving capacity and the display quality are high, but the current consumption is increased.
This is a tradeoff, Adjust the fixed current by considering both the display quality and the
current consumption. During no display operation, when AP[2:0] = 000, the current
consumption can be reduced by stopping the operations of operational amplifier and
step-up circuit.
AP2 AP1 AP0 Constant Current of Operational Amplifier
0 0 0 Stop
0 0 1 0.5µA
0 1 0 1.0µA
0 1 1 1.5µA
1 0 0 2.0µA
1 0 1 2.5µA
1 1 0 3.0µA
1 1 1 3.5µA
VCLS[2:0]: Set VCL voltage

VCLS2 VCLS1 VCLS0 VCL voltage
0 0 0 -2.5V
0 0 1 -2.6V
0 1 0 -2.7V
0 1 1 -2.8V
1 0 0 -2.9V
1 0 1 -3.0V
1 1 0 -3.1V
1 1 1 -VDD3
VRHP[4:0]: VSPR regulator output control setting for source data output driving.
VRHP[4:0] VSPR Voltage
0 0 0 0 0 VP_REF
0 0 0 0 1 3.1V
0 0 0 1 0 3.2V
0 0 0 1 1 3.3V
0 0 1 0 0 3.4V
0 0 1 0 1 3.5V
0 0 1 1 0 3.6V
0 0 1 1 1 3.7V
0 1 0 0 0 3.8V
0 1 0 0 1 3.9V
0 1 0 1 0 4.0V
0 1 0 1 1 4.1V
0 1 1 0 0 4.2V
0 1 1 0 1 4.3V
0 1 1 1 0 4.4V
0 1 1 1 1 4.5V
HX8394-F
1 0 0 0 0 4.6V
1 0 0 0 1 4.7V
1 0 0 1 0 4.8V
1 0 0 1 1 4.9V
1 0 1 0 0 5.0V
1 0 1 0 1 5.1V
1 0 1 1 0 5.2V
1 0 1 1 1 5.3V
1 1 0 0 0 5.4V
1 1 0 0 1 5.5V
1 1 0 1 0 5.6V
1 1 0 1 1 5.7V
1 1 1 0 0 5.8V
1 1 1 0 1 5.9V
1 1 1 1 0 6.0V
1 1 1 1 1 6.1V
VRHN[4:0]: VSNR regulator output control setting for source data output driving
VRHN[4:0] VSNR Voltage
0 0 0 0 0 VN_REF
0 0 0 0 1 -3.1V
0 0 0 1 0 -3.2V
0 0 0 1 1 -3.3V
0 0 1 0 0 -3.4V
0 0 1 0 1 -3.5V
0 0 1 1 0 -3.6V
0 0 1 1 1 -3.7V
0 1 0 0 0 -3.8V
0 1 0 0 1 -3.9V
0 1 0 1 0 -4.0V
0 1 0 1 1 -4.1V
0 1 1 0 0 -4.2V
0 1 1 0 1 -4.3V
0 1 1 1 0 -4.4V
0 1 1 1 1 -4.5V
1 0 0 0 0 -4.6V
1 0 0 0 1 -4.7V
1 0 0 1 0 -4.8V
1 0 0 1 1 -4.9V
1 0 1 0 0 -5.0V
1 0 1 0 1 -5.1V
1 0 1 1 0 -5.2V
1 0 1 1 1 -5.3V
1 1 0 0 0 -5.4V
1 1 0 0 1 -5.5V
1 1 0 1 0 -5.6V
1 1 0 1 1 -5.7V
1 1 1 0 0 -5.8V
1 1 1 0 1 -5.9V
1 1 1 1 0 -6.0V
1 1 1 1 1 -6.1V
VPPS[2:0]: Set VPP output voltage for OTP.

VPPS[2:0] VPP voltage
0 0 0 8.0V
0 0 1 8.1V
0 1 0 8.2V
0 1 1 8.25V
HX8394-F
1 0 0 8.3V
1 0 1 8.4V
1 1 0 8.5V
1 1 1 External from VGH
CLK_OPT1: The pumping clock of VGH will reset with Hsync when CLK_OPT1 = 1.
CLK_OPT2: The pumping clock of VGL will reset with Hsync when CLK_OPT2 = 1.
EQ_VCLEN: VCL enable bit. 0: Disable(sharing mode), 1: Enable(VCL level). Set to 0 for
external VSP mode.
VSP_FBOFF: VSP voltage feedback to control VSP pumping clock operation. “1” no
feecdback. It is effective only for HX5186 mode, not for PFM circuit.
XDK[2:0]: Setting VSP Voltage pumping ratio in HX5186 mode.

XDK2 XDK1 XDK0 VSP
0 0 0 inhibit
0 0 1 X2
0 1 0 X1.5
0 1 1 inhibit
1 0 0 inhibit
1 0 1 inhibit
1 1 0 X3
1 1 1 X3
FS0[3:0]:Set the operating frequency of the step-up circuit for VSP/VSN voltage
generation. (Fosc_pump=5MHz)
FS0[3:0] Operation Frequency of Step-up Circuit
0 0 0 0 Fosc_pump/2
0 0 0 1 Fosc_pump/4
0 0 1 0 Fosc_pump/8
0 0 1 1 Fosc_pump/16
1 0 0 1 Fosc_pump/112
1 0 1 0 Fosc_pump/128
1 0 1 1 Fosc_pump/144
1 1 0 0 Fosc_pump/160
1 1 0 1 Fosc_pump/176
1 1 1 0 Fosc_pump/192
1 1 1 1 Fosc_pump/208
FS1[3:0]: Set the operating frequency of the step-up circuit for VGH voltage generation.
(Fosc_pump=5MHz)
0 0 1 0 Fosc_pump/128
0 0 1 1 Fosc_pump/160
0 1 0 0 Fosc_pump/192
0 1 0 1 Fosc_pump/224
0 1 1 0 Fosc_pump/256
0 1 1 1 Fosc_pump/336
1 0 0 0 Hsync*4

HX8394-F
1 0 0 1 Hsync*2
1 0 1 0 Hsync
1 0 1 1 Hsync/2
1 1 0 0 Hsync/4
1 1 0 1 Hsync/8
1 1 1 0 Hsync/16
1 1 1 1 Inhibited
FS2[3:0]: Adjust the charge pump frequency of internal VGL. (Fosc_pump=5MHz)

0 0 1 0 Fosc_pump/128
0 0 1 1 Fosc_pump/160
0 1 0 0 Fosc_pump/192
0 1 0 1 Fosc_pump/224
0 1 1 0 Fosc_pump/256
0 1 1 1 Fosc_pump/336
1 0 0 0 Hsync*4
1 0 0 1 Hsync*2
1 0 1 0 Hsync
1 0 1 1 Hsync/2
1 1 0 0 Hsync/4
1 1 0 1 Hsync/8
1 1 1 0 Hsync/16
1 1 1 1 Inhibited
BTP[4:0]: Switch the output factor for DC/DC circuit for VSP voltage generation. The LCD
drive voltage level VSP can be selected according to the characteristic of liquid crystal
which panel used.
BTP4 BTP3 BTP2 BTP1 BTP0 VSP Voltage
0 0 0 0 0 3.00V
0 0 0 0 1 3.15V
0 0 0 1 0 3.30V
0 0 0 1 1 3.45V
0 0 1 0 0 3.60V
: :
1 0 0 0 0 5.40V
1 0 0 0 1 5.55V
1 0 0 1 0 5.70V
1 0 0 1 1 5.85V
1 0 1 0 0 6.00V
1 0 1 0 1 6.15V
1 0 1 1 0 6.30V
1 0 1 1 1 6.45V
1 1 0 0 0 6.60V
Others Inhibited
BTN[4:0]: Switch the output factor of DC/DC circuit for VSN voltage generation. The LCD
drive voltage level VSN can be selected according to the characteristic of liquid crystal
which panel used.
BTN4 BTN3 BTN2 BTN1 BTN0 VSN Voltage
0 0 0 0 0 -3.00V
0 0 0 0 1 -3.15V
0 0 0 1 0 -3.30V
0 0 0 1 1 -3.45V
0 0 1 0 0 -3.60V
: :
1 0 0 0 0 -5.40V
HX8394-F
1 0 0 0 1 -5.55V
1 0 0 1 0 -5.70V
1 0 0 1 1 -5.85V
1 0 1 0 0 -6.00V
1 0 1 0 1 -6.15V
1 0 1 1 0 -6.30V
1 0 1 1 1 -6.45V
1 1 0 0 0 -6.60V
Others Inhibited
VGH_RATIO[2:0]: Specify the VGH voltage source.

VGH_RATIO[2] VGH_RATIO[1] VGH_RATIO[0] VGH Voltage pumping ratio
0 0 0 VDD3-VSN
0 0 1 VSP-VSN
0 1 0 VSP-VSN+VDD3
0 1 1 2*VSP-VSN
1 0 0 VDD3+VSP-2*VSN
1 0 1 2*VSP-2*VSN
1 1 0 VDD3+2*VSP-2*VSN
1 1 1 3*VSP-2*VSN
VGHS[6:0]: VGH regulator output voltage setting. The LCD drive voltage level VGH can be
selected according to the characteristic of liquid crystal which panel used.
VGHS[6:0] VGH Voltage
0 0 0 0 0 0 0 7.3V
0 0 0 0 0 0 1 7.4V
0 0 0 0 0 1 0 7.5V
0 0 0 0 0 1 1 7.6V
: :
0 1 1 0 0 1 1 12.4V
0 1 1 0 1 0 0 12.5V
0 1 1 0 1 0 1 12.6V
0 1 1 0 1 1 0 12.7V
: :
1 1 1 1 1 0 1 19.8V
1 1 1 1 1 1 0 19.9V
1 1 1 1 1 1 1 20.0V
VGL_RATIO[2:0]: Specify the VGL voltage source.

VGL_RATIO[2] VGL_RATIO[1] VGL_RATIO[0] VGL Voltage pumping ratio
0 0 0 VSN-VDD3
0 0 1 VSN-VSP
0 1 0 2*VSN-VDD3
0 1 1 2*VSN-VSP
1 0 0 2*VSN-VSP
1 0 1 2*VSN-VSP
1 1 0 2*VSN-VSP
1 1 1 2*VSN-VSP
VGLS[6:0]: VGL regulator output voltage setting. The LCD drive voltage level VGL can be
selected according to the characteristic of liquid crystal which panel used.
VGLS[6:0] VGL Voltage
0 0 0 0 0 0 0 -5.3V
0 0 0 0 0 0 1 -5.4V
0 0 0 0 0 1 0 -5.5V
0 0 0 0 0 1 1 -5.6V
: :
1 0 0 0 1 1 1 -12.4V
1 0 0 1 0 0 0 -12.5V
HX8394-F
1 0 0 1 0 0 1 -12.6V
1 0 0 1 0 1 0 -12.7V
: :
1 1 1 1 1 0 1 -17.8V
1 1 1 1 1 1 0 -17.9V
1 1 1 1 1 1 1 -18.0V
DT1[1:0]:Delay time of power on and power off sequence.

DT1[1:0] Delay time of power on and power off sequence
0 0 0ms
0 1 2.5ms
1 0 5ms
1 1 7.5ms
DT2[1:0]:Delay time of power on and power off sequence.

DT2[1:0] Delay time of power on and power off sequence
0 0 0ms
0 1 2.5ms
1 0 5ms
1 1 7.5ms
DCDIV[3:0]: Set the normal operate frequency FoscD of DC/DC converter circuit during
normal mode. (Fosc=45MHz)
Normal operate frequency of
DCDIV[3:0]
DC/DC converter(foscD)
0 0 0 0 Fosc/1
0 0 0 1 Fosc/2
0 0 1 0 Fosc/3
0 0 1 1 Fosc/4
0 1 0 0 Fosc/5
0 1 0 1 Fosc/6
0 1 1 0 Fosc/7
0 1 1 1 Fosc/8
1 0 0 0 Fosc/9
1 0 0 1 Fosc/10
1 0 1 0 Fosc/11
1 0 1 1 Fosc/12
1 1 0 0 Fosc/13
1 1 0 1 Fosc/14
1 1 1 0 Fosc/15
1 1 1 1 Fosc/16
DCS[2:0]: Soft start VSP/VSN frequency of DC/DC clock.

DCS[2:0] Operation Frequency of DC/DC Clock
0 0 0 foscD/4
0 0 1 foscD/5
0 1 0 foscD/6
0 1 1 foscD/7
1 0 0 foscD/8
1 0 1 foscD/10
1 1 0 foscD/11
1 1 1 foscD/12
DC[2:0]: Operation VSP/VSN frequency of DC/DC clock.

DC[2:0] Operation Frequency of DC/DC Clock
0 0 0 foscD/4
0 0 1 foscD/5
0 1 0 foscD/6
0 1 1 foscD/7
HX8394-F
1 0 0 foscD/8
1 0 1 foscD/10
1 1 0 foscD/11
1 1 1 foscD/12
DTPS[2:0]: For PFM circuit. Set the soft start operating duty cycle of VSP.
DTPS[2:0] Soft start operation duty of VSP
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8
DTP[2:0]: For PFM circuit:Set the operating duty cycle of VSP.

DTP[2:0] Operation duty of VSP
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8
DTNS[2:0]: For PFM circuit. Set the soft start operating duty cycle of VSN.
DTNS[2:0] Soft start operation duty of VSN
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8
DTN[2:0]: For PFM circuit:Set the operating duty cycle of VSN.

DTN[2:0] Operation duty of VSN
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8

HX8394-F
APF_EN: Abnormal power-off detection enable (GAS function). “1”: Enable.
GASIOVCC_OPT[1:0]: Set VDD1 threshold voltage of GAS function.

GASIOVCC_OPT[1:0] GAS threshold VDD1 voltage
0 0 1.2V
0 1 1.3V
1 0 1.4V
1 1 1.5V
GASVCI_OPT[2:0]: Set VDD3 threshold voltage of GAS function.

GASVCI_OPT[2:0] GAS threshold VDD3 voltage
0 0 0 1.9V
0 0 1 2.0V
0 1 0 2.1V
0 1 1 2.2V
1 0 0 2.3V
1 0 1 2.4V
1 1 0 2.5V
1 1 1 2.6V
GASVSN_OPT[2:0]: Set VSN threshold voltage of GAS function.

GASVSN_OPT[2:0] GAS threshold VSN voltage
0 0 0 -2.8V
0 0 1 -3.0V
0 1 0 -3.2V
0 1 1 -3.4V
1 0 0 -3.6V
1 0 1 -3.8V
1 1 0 -4.0V
1 1 1 -4.2V
GASVSP_OPT[2:0]: Set VSP threshold voltage of GAS function.

GASVSP_OPT[2:0] GAS threshold VSP voltage
0 0 0 2.8V
0 0 1 3.0V
0 1 0 3.2V
0 1 1 3.4V
1 0 0 3.6V
1 0 1 3.8V
1 1 0 4.0V
1 1 1 4.2V
GASVGL_OPT[1:0]: Set VGL threshold voltage of GAS function.

HX8394-F
GASVGL_OPT[1:0] GAS threshold VGL voltage
0 0 -6V
0 1 -7V
1 0 -8V
1 1 -9V
GASVGH_OPT[1:0]: Set VGH threshold voltage of GAS function.

GASVGH_OPT[1:0] GAS threshold VGH voltage
0 0 6V
0 1 7V
1 0 8V
1 1 9V

Status Availability

HX8394-F
5.19.3 SETDISP: Set display related register (B2h)
SETDISP( Set display related register)

B2H
Command 0 1 0 1 1 0 0 1 0 B2
Bank 0
nd 1 - ZZ_LR ZZ_EO ZZ_2PL - NW[2:0] -
1 parameter
rd MESSI
2 parameter _ENB
H_RES[2:0] - - - -
th
3 parameter 1 NL[7:0] -
th
4 parameter 1 BP [7:0] -
th
5 parameter 1 FP [7:0] -
th
6 parameter 1 RTN[7:0] -
th
7 parameter 1 - - - - - - - -
th
8 parameter 1 - - - - - - - - -
th
9 parameter 1 - - - - - - - - -
th
10 parameter 1 - - - - - - - - -
DISP_
st
11 parameter 1 FRM_PATTERN_CYCLE[3:0] BIST_E FRM_SCAN_CYCLE[2:0] -
N
This command is used to set display related register.
ZZ_LR: Zig-zag Left / Right mode selection.
ZZ_LR Zig-zag Left / Right mode selection
0 S1~SR1
1 SL1~S2160
ZZ_EO: Zig-zag Odd / Even mode selection.

ZZ_EO Zig-zag Odd / Even mode selection
0 Odd-line shift
1 Even-line shift
ZZ_2PL: Zig-zag 1H/2H selection when NW[2:0]=101

ZZ_2PL Zig-zag 1H/2H selection
0 1H Zig-zag
1 2H Zig-zag
Description

HX8394-F
MESSI_ENB : Support Nokia DCS enable bit. “0” Enable.
0: support Nokia,don’t support 44h CMD
1: support 44h CMD to adjust the position of TE(horizontal)
NW[2:0]: Inversion type setting.

NW2 NW1 NW0 Inversion type
0 0 0 Column inversion
0 0 1 1-dot inversion
1 0 1 Zig-zag
Others Inhibited
1
H_RES[2:0]: Resolution selection.
H_RES[2:0] Resolution Source channels

000 720RGBx(480+ (8xNL)) S1~S2160
001 640RGBx(480+(8xNL)) S1~S960, S1201~S2160
010 600RGBx(480+(8xNL)) S1~S900,S1261~S2160
Others inhibited inhibited
NL[7:0]: Setting the number of lines to drive the LCD at an interval of 8 lines. The number of
lines must be the same or more than the number of lines necessary for the size of the liquid
crystal panel.
NL[7:0] Line
0 0 0 0 0 0 0 0 480
0 0 0 0 0 0 0 1 488
0 0 0 0 0 0 1 0 496
0 0 0 0 0 0 1 1 504
‧‧‧ ‧‧‧
‧‧‧ ‧‧‧
0 1 0 1 0 0 1 0 1136
‧‧‧ ‧‧‧
0 1 1 0 0 1 0 0 1280
‧‧‧ ‧‧‧
1 0 1 1 0 1 0 0 1920
Others Inhibited
BP[7:0] : Specify the amount of scan line for back porch(BP) in blanking.
FP[7:0]: Specify the amount of scan line for front porch (FP) in blanking.
FP[7:0] / BP[7:0] Number of front porch/ back porch Lines

8h’00 2 lines
8h’01 3 lines
8h’02 4 lines
8h’03 5 lines
8h’04 6 lines
8h’05 7 lines
: :
8h’FB 253 lines
8h’FC 254 lines
8h’FD 255 lines
8h’FE 256 lines
8h’FF 257 lines
Note: Set BP[7:0] = VS + VBP – 2, and FP[7:0] = VFP – 2.
HX8394-F
RTN[7:0]: A cycle time of line width in blanking.
(1 TCON clock period= 4/45MHz)
RTN[7:0] Clock per Line
8h’00 97 TCON CLK
8h’01 98 TCON CLK
8h’02 99 TCON CLK
: :
8’hFD 350 TCON CLK
8’hFE 351 TCON CLK
8’hFF 352 TCON CLK
DISP_BIST_EN: Set “1” enable SW free running mode.
FRM_PATTERN_CYCLE[3:0]: Number of Free-running mode pattern.

FRM_PATTERN_CYCLE[3:0] Free-running mode pattern number
0000 White
0001 White, Black
0010 White, Black, Red
0011 White, Black, Red, Blue
0100 White, Black, Red, Blue, Green
0101 White, Black, Red, Blue, Green, Gray127
0110 White, Black, Red, Blue, Green, Gray127,
H-Grayscale
H-Grayscale, V-Grayscale
H-Grayscale, V-Grayscale, White pattern with black
outline
outline
outline, Checker 1x1
outline, Checker 1x1, Gray128
outline, Checker 1x1, Gray128, Black
Others Inhibited
FRM_SCAN_CYCLE[2:0]: Free-running each pattern keeps time.

FRM_ SCAN_CYCLE[2:0] Free-running mode pattern keep time
000 1s
001 2s
010 4s
011 8s
Others Inhibited
Restrictions SETEXTC turn on to enable this command
Status Availability

HX8394-F
5.19.4 SETCYC: Set display waveform cycles (B4h)
SETCYC(Set panel driving timing)

B4H
Command 0 1 0 1 1 0 1 0 0 B4
st
1 parameter 1 SPON[7:0]
nd
2 parameter 1 SPOFF[7:0]
rd
3 parameter 1 CON[7:0]
th
4 parameter 1 COFF[7:0]
th
5 parameter 1 CON1[7:0]
th
6 parameter 1 COFF1[7:0]
th
7 parameter 1 EQON1[7:0]
th
8 parameter 1 SON[7:0]
th
9 parameter 1 SOFF[7:0]
th
10 parameter 1 SAP1_P[3:0] - SAP2[2:0]
st DX2_E EQ_O EQ_MI
11 parameter 1 -
N N X
- - - -
nd
12 parameter 1 DX2OFF[7:0]
rd
13 parameter 1 SPON_MPU[7:0]
th
14 parameter 1 SPOFF_MPU[7:0]
th
15 parameter 1 CON_MPU[7:0]
th
16 parameter 1 COFF_MPU[7:0]
th
17 parameter 1 CON1_MPU[7:0]
th
18 parameter 1 COFF1_MPU[7:0]
th
19 parameter 1 EQON1_MPU[7:0]
th
20 parameter 1 SON_MPU[7:0]
st
21 parameter 1 SOFF_MPU[7:0]
nd
22 parameter 1 DX2OFF_MPU[7:0]
This command is used to set display waveform cycles.
SPON[7:0]: Fine tune the Start and End signal delay from original starting point.
SPON_MPU[7:0]: Fine tune the Start and End signal delay from original starting point for
blanking frame.
(1 TCON CLK period = 4/45MHz)
SPON[7:0]/ SPON_MPU[7:0] Start / END signal output start delay
0x00h 0 TCON CLK
0x01h 1TCON CLK
0x02h 2 TCON CLK
0x03h 3 TCON CLK
:
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK
Description
SPOFF[7:0]: Fine tune the Start and End signal ending point.
SPOFF_MPU[7:0]: Fine tune the Start and End signal ending point for blanking frame.
SPOFF[7:0]/ SPOFF_MPU[7:0] Start / END signal output end delay
0x00h 0 TCON CLK
0x01h 1 TCON CLK
0x02h 2 TCON CLK
0x03h 3 TCON CLK
:
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK
Note: When output Start / End signal width is 1- Hsync only, set SPON[7:0] < SPOFF[7:0]
CON[7:0]/CON1[7:0]: Fine tune the Clock signal delay from original starting point.
CON_MPU[7:0]/CON1_MPU[7:0]: Fine tune the Clock signal delay from original starting
point for blanking frame.
HX8394-F
CON[7:0]/ CON_MPU[7:0] Clock signal output start delay
CON1[7:0]/ CON1_MPU[7:0]
0x00h 0 TCON CLK
0x01h 1 TCON CLK
0x02h 2 TCON CLK
0x03h 3 TCON CLK
:
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK
COFF[7:0]/COFF1[7:0]: Fine tune the Clock signal ending point.

COFF_MPU[7:0]/COFF1_MPU[7:0]: Fine tune the Clock signal ending point for blanking
frame.
COFF[7:0]/ COFF_MPU[7:0] Clock signal output end delay
COFF1[7:0]/ COFF1_MPU[7:0]
0x00h 0 TCON CLK
0x01h 1 TCON CLK
0x02h 2 TCON CLK
0x03h 3 TCON CLK
:
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK
Note: When output Clock signal width is 1- Hsync only, set COFF[7:0] ≧ CON[7:0] + 2
SON[7:0]: Source OP turn on time.

SOFF[7:0]: Source OP turn off time.
SON_MPU[7:0]: Source OP turn on time for blanking frame.
SOFF_MPU[7:0]: Source OP turn off time for blanking frame.
SON[7:0]/SON_MPU[7:0] Source OP turn on/off time

SOFF[7:0]/ SOFF_MPU[7:0]
0x00h 0 TCON CLK
0x01h 1 TCON CLK
0x02h 2 TCON CLK
:
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK
VSYNC
HSYNC
SPOFF[7:0]
SPON[7:0]
SHR0[11:0]
Start1
SHP[3:0] define the width of high pulse
End1 SHR1[11:0]
COFF[7:0]
CON[7:0]
CHR[7:0]
Clock1
CHP[3:0] define the width of high pulse
Clock2

HX8394-F
1 frame
1280 lines VBLK
Start
Normal scan
UD=High
CK1 1 3 5 1 3
1279 1281
CK2 0 2 4 0 2
1280 1282
Reverse scan
UD=Low
CK1 0 2
0 2 4
1280 1282
CK2 1
1 3 5 3
1279 1281
1H
HS
COFF[7:0]
CON[7:0]
CK1(2)
CK2(1)
EQON1[7:0]: Specify the source EQ period.

EQON1_MPU[7:0]: Specify the source EQ period for blanking frame.
EQON1[7:0]/ EQON1_MPU[7:0]] Source EQ time
0x00h 0 TCON CLK
0x01h 1 TCON CLK
0x02h 2 TCON CLK
0x03h 3 TCON CLK
:
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK
DX2OFF[7:0]: Source driving enhancement period setting.

DX2OFF_MPU[7:0]: Source driving enhancement period setting for blanking frame.
DX2OFF[7:0]/DX2OFF_MPU[7:0] Set source enhancement time
0x00h 0 TCON CLK
0x01h 1 TCON CLK
0x02h 2 TCON CLK
0x03h 3 TCON CLK
:
0xFEh 254 TCON CLK
0xFFh 255 TCON CLK
DX2_EN: DX2 on period selection

“1”: SON ~ DX2OFF

HX8394-F
1-Line Period 1-Line Period
SOFF SOFF
DX2OFF DX2OFF
S(N)
SON
SON
DX2 on EQON1
EQON1
Charge
sharing
VSSA VSSA
DX2 on VSSA
Charge
sharing
“0”: SON ~ SOFF

1-Line Period 1-Line Period
SOFF SOFF
S(N)
SON
SON
DX2 on EQON1
EQON1
Charge
sharing
VSSA VSSA
DX2 on VSSA
Charge
sharing
st
SAP1_P[3:0]: 1 stage OP bias current adjust
nd
SAP2[2:0]: class-AB (2 ) stage OP bias current adjust:
st
SAP2[2:0] 1 stage OP Class AB OP
Total
(SAP1_P[3:0] =0011)
0 0 0 0.757 uA 0.224uA 0.981 uA
0 0 1 0.778 uA 0.245uA 1.023 uA
0 1 0 0.815 uA 0.271uA 1.086 uA
0 1 1 0.857 uA 0.306uA 1.163 uA
1 0 0 0.906 uA 0.346uA 1.252 uA
1 0 1 0.954 uA 0.383uA 1.337uA
1 1 0 1.008 uA 0.423uA 1.431 uA
1 1 1 1.059 uA 0.463uA 1.522 uA
st
Total OP biase current = 1 OP current + class-AB biase current
Different SAP1_P[3:0] will have map to diffent class-AB current setting

HX8394-F
st
SAP1_P[3:0] 1 stage OP Class AB OP
Total
(SAP2[2:0]=011)
0 0 0 0 0.222 uA 0.076 uA 0.298 uA
0 0 0 1 0.431 uA 0.149 uA 0.58 uA
0 0 1 0 0.657 uA 0.23 uA 0.887uA
0 0 1 1 0.857 uA 0.307 uA 1.164 uA
0 1 0 0 1.075 uA 0.392 uA 1.467 uA
0 1 0 1 1.269 uA 0.477 uA 1.746uA
0 1 1 0 1.484 uA 0.563 uA 2.047 uA
0 1 1 1 1.677 uA 0.644 uA 2.321 uA
1 0 0 0 1.888 uA 0.738 uA 2.626 uA
1 0 0 1 2.079 uA 0.823uA 2.902 uA
1 0 1 0 2.289 uA 0.916 uA 3.205 uA
1 0 1 1 2.476 uA 0.999 uA 3.475 uA
1 1 0 0 2.683 uA 1.096 uA 3.779 uA
1 1 0 1 2.874 uA 1.182 uA 4.056 uA
1 1 1 0 3.074 uA 1.277 uA 4.351 uA
1 1 1 1 3.258 uA 1.359 uA 4.617 uA
EQ_ON/ EQ_MIX:
EQ_ON 0 0 1 1
EQ_MIX 0 1 0 1
EQ to
Sharing mode Frist line EQ All line EQ All line EQ
VCI/VCL
Restrictions -
Status Availability

HX8394-F
5.19.5 SETVCOM: Set VCOM voltage (B6h)
SETVCOM ( Set VCOM Voltage)

B6 H
Command 0 1 0 1 1 0 1 1 0 B6
st
1 parameter 1 VCMC_F[7:0]
nd
2 parameter 1 VCMC_B[7:0]
rd
3 parameter 1 VCOM_TIMES[2:0] - - - VCMC_B[8] VCMC_F[8] -
This command is used to set VCOM Voltage.
VCMC_F[8:0]: Forward scan VCOM voltage control.
VCMC_B[8:0]: Backward scan VCOM voltage control.
VCMC_F[8:0]/VCMC_B[8:0] VCOM
0 0 0 0 0 0 0 0 0 -0.30V
0 0 0 0 0 0 0 0 1 -0.31V
0 0 0 0 0 0 0 1 0 -0.32V
0 0 0 0 0 0 0 1 1 -0.33V
: :
1 0 1 1 1 0 0 0 0 -3.98V
Description 1 0 1 1 1 0 0 0 1 -3.99V
1 0 1 1 1 0 0 1 0 -4.00V
Others Inhibited
1 1 1 1 1 1 1 1 0 VSSA
1 1 1 1 1 1 1 1 1 HZ
VCOM_TIMES[2:0]: Read the VCOM OTP programmed times.

VCOM_TIMES[2:0] VCOM OTP programmed times
111 No programmed
011 VCOM has been programmed 1 time
001 VCOM has been programmed 2 times
000 VCOM has been programmed 3 times

Status Availability

HX8394-F
5.19.6 SETTE: Set internal TE function (B7h)
SETTE ( Set internal TE function)

B7H
Command 0 1 0 1 1 0 1 1 1 B7
st
1 parameter 1 TEI[3:0] - TEP[10:8] 00
nd
2 parameter 1 TEP[7:0] 00
rd
3 parameter 1 TE_SEL[3:0] TE1_SEL[3:0] 00
TEI[3:0]: Set the output interval of TE signal according to the display data rewrite cycle and
data transfer rate.
TEI3 TEI2 TEI1 TEI0 Output Interval
0 0 0 0 1 frame
0 0 0 1 2 frames
0 0 1 0 3 frames
: :
1 1 1 0 15 frames
1 1 1 1 16 frames
Description TEP[10:0]: Set the output position of frame cycle signal. TE can be used as the trigger
signal for frame synchronous write operation.
Make sure the setting restriction 11’h000 ≤ TEP[10:0] ≤ Numbers of Line-1.
TEP[10:0] Output position
000h 0th line
001h 1st line
002h 2nd line
003h 3rd line
‧‧‧ ‧‧‧
4FEh 1278th line
4FFh 1279th line
500h 1280th line
TE_SEL[3:0]: TE pin output signal select

TE_SEL[3:0] TE pin Output signal
0000 Original TE
0001 V-blanking
0010 H-blanking
0011 Source driving period
Others Inhibited
TE1_SEL[3:0]: TE1 pin output signal select

TE1_SEL[3:0] TE1 pin Output signal
0000 Original TE
0001 V-blanking
HX8394-F
0010 H-blanking
0011 Source driving period
Others Inhibited

Status Availability

HX8394-F
5.19.7 SETSENSOR: Set temperature sensor (B8h)
SETSENSOR ( Set temperature sensor)

B8H
Command 0 1 0 1 1 1 0 0 0 B8
TSENS
Bank0
st 1 - OR_E LT_EN HT_EN - - - - -
1 parameter N
TSENSOR_EN: Set “1” Enable Temperature sensor function.
LT_EN: Set “1” Enable Low Temperature.

Description
HT_EN: Set “1” Enable High Temperature.

Status Availability

HX8394-F
5.19.8 SETEXTC: Set extension command (B9h)
SETEXTC ( Set extended command set)

B9H
Command 0 1 0 1 1 1 0 0 1 B9
st
1 parameter 1 EXTC1[7:0] -
nd
rd
This command is used to set extended command set access enable.
Extend cmd Command description
After command (B9h), write 3 parameters
Description Enable
(FFh, 83h, 94h) by order
Disable After command (B9h), write 3 parameters (xxh,xxh,xxh)
(default) any value except (FFh, 83h, 94h)
Restrictions -
Status Availability

HX8394-F
5.19.9 SETMIPI: Set MIPI control (BAh)
SETMIPI( Set MIPI control)

BAH
Command 0 1 0 1 1 1 0 1 0 BA
st
1 parameter 1 - DSISETUP0[6:0]
nd
2 parameter 1 DSISETUP1[7:0]
rd
3 parameter 1 DPHYCMD0[7:0]
th
4 parameter 1 DPHYCMD1[7:0]
This command is used to set MIPI DSI Related Setting.
Tx Type: Define the LP-TX BTA behavior when there are error.
DSISETUP0[6] 0: only BTA Error
1: BTA Read + Error
CD_disable: Define the contention detection (LP-CD) function.
DSISETUP0[5] 0 : LP-CD function enable
1: LP-CD function disable
Tx_OscDiv: LP-TX clock (TLPX) selection.
DSISETUP0[4] 0 : 50ns (10MHz)(osc_clk)
1 :100ns (5MHz)(osc_clk/2)
DSISETUP0[3:2] Internal option
LAN_NUM: Define the DSI lane number
00 : 1-lane
DSISETUP0[1:0] 01 : 2-lane
10 : 3-lane
11 : 4-lane
DSISETUP1[7] RxCRC_enable: Enable RX CRC Check.

ECC_ignore: Define the RX behavior when error occurring.
DSISETUP1[6] 0 : the transmission will be broken when there are ECC or CRC error
1 : the transmission will keep when there are ECC or CRC error
DSISETUP1[5] Internal option
DSISETUP1[4] conti_w_en: 29h continuous write function 0:disable,1:enable
Description Txe_Wait: BTA from Tx into Rx overlap waiting time counter(TTA-GO)
00: TA-go = 2 Tlpx
DSISETUP1[3:2] 01: TA-go = 4 Tlpx
10: TA-go = 6 Tlpx
11: TA-go = 8 Tlpx
Txs_Wait: BTA from Rx into Tx overlap waiting time counter(TTA-GET)
00: Disable, no wait time
DSISETUP1[1:0] 01: TA-get = 2 Tlpx
10: TA-get = 4 Tlpx
11: TA-get = 6 Tlpx
LP-RX LPF delay capacitance setting, for clock path: 00=4ns,

DPHYCMD0[7:6]
01=8ns(default), 10=13ns, 11=2ns
LP-RX VHYS trimming: 00=92mV, 01=37mV, 10=66mV (default),
DPHYCMD0[5:4]
11=3mV (w/o hysteresis)
DPHYCMD0[3] LP-TX Slew Rate trimming: 0=w/i S/R (default), 1=relief SR limit
DPHYCMD0[2] LP-TX Slew Rate trimming: 0=fast S/R, 1=slow S/R(default)
DPHYCMD0[1] TXTEN:Enable LP-TX: 0=disable (default), floating output, 1=enable
Force: Force LP-TX output logic ‘1’ or ‘0’: 0=output ‘0’ (default),
DPHYCMD0[0]
1=output ‘1’. To enable this function, TXTEN must be set to 1
LDOHB: HS_LDO output voltage trimming for DSI: 000=1.25V,

DPHYCMD1[7:5] 001=1.45V, 010=1.50V, 011=1.55V (dsi default), 100=1.65V,
101=1.70V, 110=1.75V, 111=1.80V
DPHYCMD1[4:3] IHSRB[1:0]:HS-RX current trimming: 00=8x, 01=7x, 10=6x (default),

HX8394-F
11=5x
RTB: HS-RX Rterm terminator resistance value trimming for DSI:
DPHYCMD1[2:1]
00=123ohm, 01=100ohm, 1x=84ohm
DPHYCMD1[0] ILPCB: LP-CD current trimming: 0=4x, 1=2x (default)

Status Availability

HX8394-F
5.19.10 SETOTP: Set OTP (BBh)
SETOTP( Set OTP Related Setting)

BBH
Command 0 1 0 1 1 1 0 1 1 BB
OTP_P
st INTVP
1 parameter 1
P_EN
- ROG_ - - - OTP_INDEX[9:8]
ALL
nd
2 parameter 1 OTP_INDEX[7:0]
rd
3 parameter 1 OTP_DATA[7:0]
OTP_P
th OTP_P OTP_P OTP_T OTP_P
4 parameter 1
OR WE
WR_S OTP_PTM[2:0]
EST ROG
EL
th
5 parameter 1 OTP_DATA_READ[7:0]
th
6 parameter 1 OTP_KEY0[7:0]
th
7 parameter 1 OTP_KEY1[7:0]
th
8 parameter 1 OTP_MASK[7:0]
This command is used to set OTP related setting.
OTP_KEY0[7:0],
Description Note
OTP_KEY1[7:0]
Enter OTP program mode
OTP_KEY1[7:0] = 0x55h
OTP_KEY0[7:0] = 0x00h
Leave OTP program mode
OTP_KEY1[7:0] = 0x00h
If HX8394-F operate on OTP
program mode, Then keep on OTP
program mode.
Other value Invalid
If HX8394-F operate on non-OTP
program mode, Then keep on
non-OTP program mode.
INTVPP_EN: OTP_PWR power selected.

“0” : External OTP_PWR is selected when programmed.
“1” : Internal OTP_PWR is selected when programmed.
OTP_PROG_ALL: When set to “1’, all OTP index is programmed, except for CAh, E5h, E6h.
Description
OTP_INDEX[9:0]: Set index of OTP table for programming.
OTP_PROG: When set to “1’, the register content of OTP index is programmed.
OTP_PWR_SEL: When written to “1”, OTP power voltage is fed to OTP circuit.
OTP_PTM[2:0]: For test mode using. Not open.
OTP_PWE: OTP program write enable, “1” means OTP is able to be programmed.
OTP_POR: Pulse for OTP data read operation.
OTP_TEST: “0”, setting OTP_PROG high will trigger internal state machine.
“1”, setting OTP_PROG high will not trigger internal state machine.
OTP_DATA[7:0]: Write data of OTP index.
OTP_DATA_READ[7:0]: Read back the OTP index data.
OTP_MASK[7:0]: Bit programming mask, “1” means this bit can’t be programmed.

HX8394-F
Status Availability

HX8394-F
5.19.11 Set register bank (BDh)
SET_BANK(Set register bank)

BDH
Command 0 1 0 1 1 1 1 0 1 BD
st BANK_INDEX
1 parameter 1 - - - - - -
[1:0]
00
Set the register bank for some Commands.
This command is active only for RB1h/RB2h/RB8h/RC1h/RD3h/RD8h.

For example:
Write RC1h Bank1
Step1: write RBDh = 01h
Description
Step2: write RC1h, PA1~42
Read RC1h Bank2

Step1: write RBDh = 02h
Step2: read RC1h, PA1~42

Status Availability

HX8394-F
5.19.12 SETDGCLUT: Set DGC LUT (C1h)
SETDGCLUT ( Set DGC LUT)

C1H
Command 0 1 1 0 0 0 0 0 1 C1
Bank0 DGC_I DGC_
st 1 - - - - - - 00
1 parameter NV EN
nd
2 parameter 1 R_GAMMA0[9:2] -
rd
th
th
th
th
th
th
th
st
nd
rd
th
th
th
th
th
th
th
st
nd
rd
th
th
th
th
th
th
th
st
nd
rd
th
th
35 parameter 1 R_GAMMA0[1:0] R_GAMMA1[1:0] R_GAMMA2[1:0] R_GAMMA3[1:0] -
th
36 parameter 1 R_GAMMA4[1:0] R_GAMMA5[1:0] R_GAMMA6[1:0] R_GAMMA7[1:0] -
th R_GAMMA10[1:0 R_GAMMA11[1:0
37 parameter 1 R_GAMMA8[1:0] R_GAMMA9[1:0]
] ]
-
th R_GAMMA12[1:0 R_GAMMA13[1:0 R_GAMMA14[1:0 R_GAMMA15[1:0
38 parameter 1 -
] ] ] ]
39 parameter 1
] ] ] ]
-
40 parameter 1
] ] ] ]
-
st R_GAMMA24[1:0 R_GAMMA25[1:0 R_GAMMA26[1:0 R_GAMMA27[1:0
41 parameter 1 -
] ] ] ]
nd R_GAMMA28[1:0 R_GAMMA29[1:0 R_GAMMA30[1:0 R_GAMMA31[1:0
42 parameter 1
] ] ] ]
-

HX8394-F
rd R_GAMMA32[1:0
43 parameter 1
]
- - - - - - -
Bank1
st 1 G_GAMMA0[9:2] -
1 parameter
nd
2 parameter 1 G_GAMMA1[9:2] -
rd
th
th
th
th
th
th
th
st
nd
rd
th
th
th
th
th
th
th
st
nd
rd
th
th
th
th
th
th
th
st
nd
rd
th
34 parameter 1 G_GAMMA0[1:0] G_GAMMA1[1:0] G_GAMMA2[1:0] G_GAMMA3[1:0] -
th
th G_GAMMA10[1:0 G_GAMMA11[1:0
36 parameter 1 G_GAMMA8[1:0] G_GAMMA9[1:0]
] ]
-
th G_GAMMA12[1:0 G_GAMMA13[1:0 G_GAMMA14[1:0 G_GAMMA15[1:0
37 parameter 1 -
] ] ] ]
38 parameter 1
] ] ] ]
-
39 parameter 1
] ] ] ]
-
40 parameter 1 -
] ] ] ]
st G_GAMMA28[1:0 G_GAMMA29[1:0 G_GAMMA30[1:0 G_GAMMA31[1:0
41 parameter 1
] ] ] ]
-
nd G_GAMMA32[1:0
42 parameter 1
]
- - - - - - -
Bank2
st 1 G_GAMMA0[9:2] -
1 parameter
nd
HX8394-F
rd
th
th
th
th
th
th
th
st
nd
rd
th
th
th
th
th
th
th
st
nd
rd
th
th
th
th
th
th
th
st
nd
rd
th
th
th G_GAMMA10[1:0 G_GAMMA11[1:0
36 parameter 1 G_GAMMA8[1:0] G_GAMMA9[1:0]
] ]
-
37 parameter 1
] ] ] ]
-
38 parameter 1
] ] ] ]
-
39 parameter 1
] ] ] ]
-
40 parameter 1
] ] ] ]
-
st G_GAMMA28[1:0 G_GAMMA29[1:0 G_GAMMA30[1:0 G_GAMMA31[1:0
41 parameter 1
] ] ] ]
-
nd G_GAMMA32[1:0
42 parameter 1
]
- - - - - - -

HX8394-F
This command is used to set Digital Gamma Curve Look-Up Table.
DGC_EN: Enable the DGC function. “1”: Enable; “0”: Disable.
DGC_INV: DGC mapping inversion.
R/G/B_GAMMA0[9:0] ~ R/G/B_GAMMA32[9:0]: MSB 8-bit is setting to mapping related

gary level to which gray level voltage of real gamma. LSB 2-bit is for dithering.
LUT Mapping Gray level
R_GAMMA0[9:0] R0
R_GAMMA1[9:0] R8
R_GAMMA2[9:0] R16
: :
R_GAMMA31[9:0] R240
R_GAMMA32[9:0] R255
Description
G_GAMMA0[9:0] G0
G_GAMMA1[9:0] G8
G_GAMMA2[9:0] G16
: :
G_GAMMA31[9:0] G240
G_GAMMA32[9:0] G255
B_GAMMA0[9:0] B0
B_GAMMA1[9:0] B8
B_GAMMA2[9:0] B16
: :
B_GAMMA31[9:0] B240
B_GAMMA32[9:0] B255

Status Availability

HX8394-F
5.19.13 SETID: Set ID (C3h)
SETID ( Set ID)

C3H
Command 0 1 1 0 0 0 0 1 1 C3
st
1 parameter 1 ID1[7:0] 83
nd
rd
3 parameter 1 ID3[7:0] 0A
th
th
5 parameter 1 ID_TIMES[2:0] - - - - - E0
ID1[7:0] is used to set ID RDAh value.
ID2[7:0] is used to set ID RDBh value.
ID3[7:0] is used to set ID RDCh value.
ID4[7:0] is used to set the fourth ID.

Description
ID_TIMES[2:0]: Read the ID OTP programmed times.
ID_TIMES[2:0] ID OTP Programmed Times
111 No programmed
011 ID has been programmed 1 time
001 ID has been programmed 2 times
000 ID has been programmed 3 times

Status Availability

HX8394-F
5.19.14 SETDDB: Set DDB (C4h)
SETDDB ( Set DDB)

C4H
Command 0 1 1 0 0 0 1 0 0 C4
st
1 parameter 1 DDB1[7:0] 00
nd
rd
th
th
th
Description This command is used to set CMD RA1h DDB1~6 value.
Status Availability

HX8394-F
5.19.15 SETCABC: Set CABC control (C9h)
SETCABC (Set CABC Control)

C9H
Command 0 1 1 0 0
1 0 0 1 C9
st PWM_PE BC_CTR SEL_BLD
1 Parameter 1 - SEL_PWMCLK[2:0] INVPULS
RIOD[16] L_EN UTY
nd
2 Parameter 1 PWM_PERIOD[15:8]
rd
3 Parameter 1 PWM_PERIOD[7:0]
th CABC_F
4 Parameter 1 DIM_FRAME[6:0]
SYNC
th CABC_D CABC_D
5 Parameter 1
D D_I
- - CABC_FLM[3:0]
This command is used to set CABC parameter.
SEL_BLDUTY: Backligh pwm output duty on/off control when CABC operation.
‘0’, The Backligh pwm output duty is 100%.
‘1’, The Backligh pwm output duty is calculate from CABC operation..
INVPULS: The backlight PWM output polarity select.

‘0’, The backlight PWM output is low level active.
‘1’, The backlight PWM output is high level active.
BC_CTRL_EN: Enable Backlight EN signal output
SEL_PWMCLK[2:0] : Internal PWM_CLK divider for CABC clock.

SEL_PWMCLK[2:0] Brightness Control Clock frequency
0 0 0 PWM_CLK / 1
0 0 1 PWM_CLK / 2
0 1 0 PWM_CLK / 4
0 1 1 PWM_CLK / 6
1 0 0 PWM_CLK / 8
1 0 1 PWM_CLK / 10
1 1 0 PWM_CLK / 12
1 1 1 PWM_CLK / 14
Description PWM_PERIOD[16:0]: The backlight PWM output period setting.
When PWM_PERIOD[16]=0, PWM_PERIOD[15:6] setting inhibited.

If PWM_PERIOD[16]=0 and SEL_PWMCLK[2:0]=3’b001.The PWM_CLK frequency
mapping table is as bellows:
PWM_PERIOD[5:0] PWM_CLK
00h 40KHz
01h 39KHz
02h 38KHz
03h 37KHz
04h 36KHz
05h 35KHz
06h 34KHz
07h 33KHz
08h 32KHz
09h 31KHz
0Ah 30KHz
0Bh 29KHz
0Ch 28KHz
0Dh 27KHz
0Eh 26KHz
0Fh 25KHz
HX8394-F
10h 24KHz
11h 23KHz
12h 22KHz
13h 21KHz
14h 20KHz
15h 19KHz
16h 18KHz
17h 17KHz
18h 16KHz
19h 15KHz
1Ah 14KHz
1Bh 13KHz
1Ch 12KHz
1Dh 11KHz
1Eh 10KHz
1Fh 9KHz
20h 8KHz
21h 7KHz
22h 6KHz
23h 5KHz
24h 4KHz
25h 3KHz
26h 2KHz
27h 1KHz
28h 900Hz
29h 800Hz
2Ah 700Hz
2Bh 600Hz
2Ch 500Hz
2Dh 400Hz
2Eh 300Hz
2Fh 200Hz
30h 100Hz
When PWM_PERIOD[16]=1:
CABC_PWM_OUT frequency= (Fosc/4) / (SEL_PWMCLK[2:0]+1) / (PWM_PERIOD[15:0])
Note: PWM_PERIOD[15:0]=0000h is inhibited.
CABC_FSYNC: Reset CABC_PWM_OUT signal by each VSYNC.
DIM_FRAME[6:0] : Manual brightness setting dimming period.
CABC_DD: CABC dimming function enable bit.

‘0’, Disable CABC dimming.
‘1’, Enable CABC dimming.
CABC_DD_I: CABC dimming function enable bit in idle mode.
CABC_FLM[3:0]: CABC dimming frame number for each step.
Restriction SETEXTC turn on to enable this command.

Status Availability

HX8394-F
5.19.16 SETCABCGAIN (CAh)
SETCABCGAIN
CAH
Command 0 1 1 0 0 1 0 1 0 CA
st
1 Parameter 1 - DBG0[6:0] 40
nd
2 parameter 1 - DBG1[6:0] 3C
rd
3 parameter 1 - DBG2[6:0] 38
th
th
th
th
7 parameter 1 - DBG6[6:0] 2B
th
th
DBG0~8[6:0] : Gain select register 0~8.
DBG0~8[6:0] CABC Gain CABC Duty
0 0 x x x x x Reserve
0 1 0 0 0 0 0 1+0/32 100%
0 1 0 0 0 0 1 1+1/32 96.97%
0 1 0 0 0 1 0 1+2/32 94.12%
0 1 0 0 0 1 1 1+3/32 91.43%
0 1 0 0 1 0 0 1+4/32 88.89%
0 1 0 0 1 0 1 1+5/32 86.49%
0 1 0 0 1 1 0 1+6/32 84.21%
0 1 0 0 1 1 1 1+7/32 82.05%
0 1 0 1 0 0 0 1+8/32 80%
0 1 0 1 0 0 1 1+9/32 78.05%
0 1 0 1 0 1 0 1+10/32 76.19%
0 1 0 1 0 1 1 1+11/32 74.42%
0 1 0 1 1 0 0 1+12/32 72.73%
0 1 0 1 1 0 1 1+13/32 71.11%
0 1 0 1 1 1 0 1+14/32 69.57%
Description
0 1 0 1 1 1 1 1+15/32 68.09%
0 1 1 0 0 0 0 1+16/32 66.67%
0 1 1 0 0 0 1 1+17/32 65.31%
0 1 1 0 0 1 0 1+18/32 64%
0 1 1 0 0 1 1 1+19/32 62.75%
0 1 1 0 1 0 0 1+20/32 61.54%
0 1 1 0 1 0 1 1+21/32 60.38%
0 1 1 0 1 1 0 1+22/32 59.26%
0 1 1 0 1 1 1 1+23/32 58.18%
0 1 1 1 0 0 0 1+24/32 57.14%
0 1 1 1 0 0 1 1+25/32 56.14%
0 1 1 1 0 1 0 1+26/32 55.17%
0 1 1 1 0 1 1 1+27/32 54.24%
0 1 1 1 1 0 0 1+28/32 53.33%
0 1 1 1 1 0 1 1+29/32 52.46%
0 1 1 1 1 1 0 1+30/32 51.61%
0 1 1 1 1 1 1 1+31/32 50.79%
1 0 0 0 0 0 0 1+32/32 50%
Status Availability

HX8394-F
5.19.17 SETPANEL (CCh)
SETPANEL( Set panel related register)

CCH
Command 0 1 1 0 0 1 1 0 0 CC
st SS_PAN GS_PAN REV_PA BGR_PA
1 parameter 1 - - - -
EL EL NEL NEL
00
This command is used to set setting of panel related register and make panel module meets
below spec from viewpoint of user
BGR_PANEL: The order of <R><G> dot color for module supplier, default value is stored
in OTP. If color filter of panel is <G><R> type, setting BGR_PANEL = 1, if color filter of
panel is <R><G> type, setting BGR_PANEL = 0. This bit is to make panel module look
like a <R><G> type panel form the user viewpoint.
REV_PANEL: The REV_PANEL setting is used to select the inversion of the display of all
Description0 characters and graphics. This setting allows the display of the same data on both normally
white and normally black panels.
GS_PANEL: Specify the shift direction of gate driver output.

When GS_PANEL = 0, the panel control signal is normal scan.
When GS_PANEL = 1, the panel control signal is reverse scan.
SS_PANEL: Specify the shift direction of source driver output. When SS_PANEL = 0, the
shift direction from S1 to S3240 When SS_PANEL = 1, the shift direction from S3240 to S1.

Status Availability

HX8394-F
5.19.18 SETOFFSET (D2h)
SETOFFSET
D2H
Command 0 1 1 0 1 0 0 1 0 D2
st
1 parameter 1 VN_REFS[3:0] VP_REFS[3:0]
This command is used to set VP_REF and VN_REF voltage.
Please set VSPR ≦
P_REFS ≦
VSP-0.3V, |VSNR| VN_REFS| ≦ ≦ |VSN|-0.3V
VP_REFS[3:0]: Positive reference voltage VP_REF setting.
VP_REFS[3:0] VP_REF Voltage
0 0 0 0 4.0V
0 0 0 1 4.3V
0 0 1 0 4.5V
0 0 1 1 4.6V
0 1 0 0 4.7V
0 1 0 1 4.8V
0 1 1 0 4.9V
0 1 1 1 5.0V
1 0 0 0 5.1V
1 0 0 1 5.2V
1 0 1 0 5.3V
1 0 1 1 5.4V
1 1 0 0 5.5V
1 1 0 1 5.6V
1 1 1 0 5.8V
Description 1 1 1 1 6.1V
VN_REFS[3:0]: Negative reference voltage VN_REF setting.

VN_REFS[3:0] VN_REF Voltage
0 0 0 0 -4.0V
0 0 0 1 -4.3V
0 0 1 0 -4.5V
0 0 1 1 -4.6V
0 1 0 0 -4.7V
0 1 0 1 -4.8V
0 1 1 0 -4.9V
0 1 1 1 -5.0V
1 0 0 0 -5.1V
1 0 0 1 -5.2V
1 0 1 0 -5.3V
1 0 1 1 -5.4V
1 1 0 0 -5.5V
1 1 0 1 -5.6V
1 1 1 0 -5.8V
1 1 1 1 -6.1V
Status Availability

HX8394-F
5.19.19 SETGIP0: Set GIP Option0 (D3h)
SETGIP0(Set GIP Option0)

D3H
Command 0 1 1 0 1 0 0 1 1 D3
Bank0 EQ_DELAY_HSYN
st 1 - - GIP_EQ_OPT[1:0] - - 00
1 parameter C[1:0]
nd EQ_VSE
2 parameter 1 - - - - - EQ_DISC[1:0] 00
L
rd
3 parameter 1 EQ_DELAY_ON1[7:0] 00
th
4 parameter 1 EQ_DELAY_OFF1[7:0] 00
th
5 parameter 1 GTO[7:0] 00
th
6 parameter 1 GNO[7:0] 00
th
7 parameter 1 USER_GIP_GATE[7:0] 08
th
8 parameter 1 USER_GIP_GATE1[7:0] 08
th
9 parameter SHR0_3[3:0] SHR0_2[3:0] 32
th
10 parameter 1 SHR0_1[3:0] SHR0[11:8] 10
st
11 parameter 1 SHR0[7:0] 02
nd
12 parameter 1 - - - - SHR0_GS[11:8] 00
rd
13 parameter 1 SHR0_GS[7:0] 02
th
14 parameter 1 SHR1_3[3:0] SHR1_2[3:0] 32
th
th
16 parameter 1 SHR1[7:0] C0
th
17 parameter 1 - - - - SHR1_GS[11:8] 00
th
th
19 parameter 1 SHR2_3[3:0] SHR2_2[3:0] 32
th
st
21 parameter 1 SHR2[7:0] 08
nd
22 parameter 1 - - - - SHR2_GS[11:8] 00
rd
th
24 parameter 1 SHP[3:0] SCP[3:0] 4B
th
25 parameter 1 SHP2[3:0] SHP1[3:0] 00
th
26 parameter 1 CHR0[7:0] 06
th
27 parameter 1 CHR0_GS[7:0] 06
th
28 parameter 1 CHP0[3:0] CCP0[3:0] 47
th
29 parameter 1 CHR1[7:0] 04
th
30 parameter 1 CHR1_GS[7:0] 00
st
31 parameter 1 CHP1[3:0] CCP1[3:0] 27
This command is used for GIP signal setting.
GIP_EQ_OPT[1:0]: GIP EQ (pre-charge) type selection

GIP_EQ_OPT 1 GIP_EQ_OPT 0 GIP EQ Type
0 0 Both rising / falling EQ
0 1 Only rising edge EQ
1 0 Only falling edge EQ
1 1 EQ Off
EQ_DELAY_ON1[7:0] / EQ_DELAY_OFF1[7:0]: Set GIP control signal EQ period

Description (1 TCON CLK period = 4/45MHz)
EQ_DELAY_ON1[7:0] / EQ_DELAY_OFF1[7:0] GIP EQ Period
0 0 0 0 0 0 0 0 Inhibited
0 0 0 0 0 0 0 1 1 TCON clock cycle
: :
1 1 1 1 1 1 0 1 253 TCON clock cycle
1 1 1 1 1 1 1 0 254 TCON clock cycle
1 1 1 1 1 1 1 1 255 TCON clock cycle
HX8394-F
EQ_DELAY_HSYNC[1:0]: Set the EQ period in HSYNC width.

EQ_DELAY_HSYNC[1:0] EQ Period in HSYNC width
0 0 Normal Driving
0 1 1 x Hsync
1 0 2 x Hsync
1 1 3 x Hsync
EQ_VSEL: Select GIP falling EQ voltage level. 0: VSSA; 1: VSP.
GTO[7:0]: GPWR signal toggle frequency.

GTO[7:0] GPWR toggle frequency
6’h00 256 x Frame
6’h01 1 x Frame
6’h02 2 x Frame
HX8394-F
6’h03 3 x Frame
: :
6’h3D 253 x Frame
6’h3E 254 x Frame
6’h3F 255 x Frame
GNO[7:0]: GPWR signal non-overlap timing.

GNO[7:0] GPWR non-overlap timing
8’h00 0
8’h01 1 TCON clock cycle
: :
8’hFD 253 TCON clock cycle
8’hFE 254 TCON clock cycle
8’hFF 255 TCON clock cycle
GPWR1/2 non-overlap signal are as below:
GPWR1/2 overlap signal are as below:
USER_GIP_Gate[7:0]: Set the GIP dummy clock numbers for first CKV.
USER_GIP_Gate1[7:0]: Set the GIP dummy clock numbers for second CKV.

HX8394-F
Group0:
st
SHR0[11:0]: Set the 1 Start/End signal delay from VSYNC falling edge when GS=0.
st
SHR0_GS[11:0]: Set the 1 Start/End signal delay from VSYNC falling edge when GS=1.
nd rd th st
SHR0_1 / SHR0_2 / SHR0_3[3:0]:Set the 2 /3 /4 Start / End signal delay from the 1
Start/End signal.
Group1:
st
SHR1[11:0]: Set the 1 Start/End siganl delay from VSYNC falling edge when GS=0.
st
SHR1_GS[11:0]: Set the 1 Start/End siganl delay from VSYNC falling edge when GS=1.
nd rd th st
SHR1_1 / SHR1_2 / SHR1_3[3:0]: Set the 2 /3 /4 Start / End signal delay from the 1
Start/End signal.
Group2:
st
SHR2[11:0]: Set the 1 Start/End signal delay from VSYNC falling edge when GS=0.
st
SHR2_GS[11:0]: Set the 1 Start/End signal delay from VSYNC falling edge when GS=1.
nd rd th st
SHR2_1 / SHR2_2 / SHR2_3[3:0]: Set the 2 /3 /4 Start / End signal delay from the 1
Start/End signal.
SHR0/SHR1/SHR2[11:0]
Start signal output delay
SHR0_GS/SHR1_GS/SHR2_GS[11:0]
0x000h 2 x Hsync
0x001h 3 x Hsync
0x002h 4 x Hsync
: :
0xFFEh 4096 x Hsync
0xFFFh 4097 x Hsync
SHR0_1 / SHR1_1 / SHR2_1[3:0] 2nd Start / End signal output delay

SHR0_2 / SHR1_2 / SHR2_2[3:0] 3th Start / End signal output delay
SHR0_3 / SHR1_3 / SHR2_3[3:0] 4th Start / End signal output delay
0000 0 x Hsync
0001 1 x Hsync
0010 2 x Hsync
: :
1110 14 x Hsync
1111 15 x Hsync
SCP[3:0]: Numbers of output Start and End signal.

SCP3 SCP2 SCP1 SCP0 Start and End numbers
0 0 0 0 1
0 0 0 1 2
HX8394-F
0 0 1 0 3
: :
1 1 0 1 14
1 1 1 0 15
1 1 1 1 16
SHP0/1/2[3:0]: Width of Start and End signal high pulse.

SHP3 SHP2 SHP1 SHP0 Start Pulse Width
0 0 0 0 1 x Hsync
0 0 0 1 2 x Hsync
0 0 1 0 3 x Hsync
: :
1 1 1 0 15 x Hsync
1 1 1 1 16 x Hsync
CHR0[7:0]/CHR1[7:0]: Set the Clock signal delay from VSYNC falling edge when GS=0.
CHR0_GS[7:0]/CHR1_GS[7:0]: Set the Clock signal delay from VSYNC falling edge when
GS=1.
CHR0[7:0]/CHR0_GS[7:0] Clock signal output delay
CHR1[7:0]/CHR1_GS[7:0]
0x00h 2 x HSYNC
0x01h 3 x HSYNC
0x02h 4 x HSYNC
: :
0xFEh 256 x HSYNC
0xFFh 257 x HSYNC
CCP0[3:0]/CCP1[3:0]: Numbers of Output Clock signal.

CCP0[3:0]/CCP1[3:0] Clock nunbers
0 0 0 0 1
0 0 0 1 2
0 0 1 0 3
: :
1 1 1 0 15
1 1 1 1 16
CHP0[3:0]/CHP1[3:0]: Width of Clock signal high pulse.

CHP0[3:0]/CHP1[3:0] Clock signal width
0 0 0 0 1 x Hsync
0 0 0 1 2 x Hsync
0 0 1 0 3 x Hsync
: :
1 1 1 0 15 x Hsync
1 1 1 1 16 x Hsync

Status Availability

HX8394-F
5.19.20 Set GIP Option1 (D5h)

D5H
Command 0 1 1 0 1 0 1 0 1 D5
st CGTS_L_
1 parameter 1 -
INV[1]
COS1_L[5:0] 18
nd CGTS_R
2 parameter 1 -
_INV[1]
COS1_R[5:0] 18
rd CGTS_L_
3 parameter 1 -
INV[2]
COS2_L[5:0] 18
th CGTS_R
4 parameter 1 - COS2_R[5:0] 18
_INV[2]
th CGTS_L_
5 parameter 1 -
INV[3]
COS3_L[5:0] 18
th CGTS_R
6 parameter 1 -
_INV[3]
COS3_R[5:0] 18
th CGTS_L_
7 parameter 1 - COS4_L[5:0] 18
INV[4]
th CGTS_R
8 parameter 1 -
_INV[4]
COS4_R[5:0] 18
th CGTS_L_
9 parameter 1 -
INV[5]
COS5_L[5:0] 18
th CGTS_R
_INV[5]
st CGTS_L_
11 parameter 1 -
INV[6]
COS6_L[5:0] 18
nd CGTS_R
12 parameter 1 -
_INV[6]
COS6_R[5:0] 18
rd CGTS_L_
INV[7]
th CGTS_R
14 parameter 1 -
_INV[7]
COS7_R[5:0 18
th CGTS_L_
15 parameter 1 -
INV[8]
COS8_L[5:0] 18
th CGTS_R
_INV[8]
th
17 parameter CGTS_L_
1 - COS9_L[5:0] 18
INV[9]
th CGTS_R
18 parameter 1 -
_INV[9]
COS9_R[5:0] 18
th CGTS_L_
INV[10]
th
20 parameter CGTS_R
1 - COS10_R[5:0] 18
_INV[10]
st CGTS_L_
21 parameter 1 -
INV[11]
COS11_L[5:0] 18
nd CGTS_R
22 parameter 1 -
_INV[11]
COS11_R[5:0] 18
rd CGTS_L_
23 parameter 1 -
INV[12]
COS12_L[5:0] 18
th CGTS_R
24 parameter 1 -
_INV[12]
COS12_R[5:0] 18
th
1 - COS13_L[5:0] 18
INV[13]
th CGTS_R
26 parameter 1 -
_INV[13]
COS13_R[5:0] 18
th
1 - COS14_L[5:0] 18
INV[14]
th CGTS_R
28 parameter 1 -
_INV[14]
COS14_R[5:0] 18
th CGTS_L_
29 parameter 1 -
INV[15]
COS15_L[5:0] 18
th
30 parameter CGTS_R
1 - COS15_R[5:0] 18
_INV[15]
HX8394-F
st CGTS_L_
31 parameter 1 -
INV[16]
COS16_L[5:0] 18
nd CGTS_R
32 parameter 1 -
_INV[16]
COS16_R[5:0] 18
rd CGTS_L_
33 parameter 1 -
INV[17]
COS17_L[5:0] 18
th CGTS_R
34 parameter 1 -
_INV[17]
COS17_R[5:0] 18
th
1 - COS18_L[5:0] 18
INV[18]
th CGTS_R
36 parameter 1 -
_INV[18]
COS18_R[5:0] 18
th
1 - COS19_L[5:0] 18
INV[19]
th CGTS_R
_INV[19]
th CGTS_L_
39 parameter 1 -
INV[20]
COS20_L[5:0] 18
th
40 parameter CGTS_R
1 - COS20_R[5:0] 18
_INV[20]
st CGTS_L_
INV[21]
nd CGTS_R
42 parameter 1 -
_INV[21]
COS21_R[5:0] 18
rd CGTS_L_
43 parameter 1 -
INV[22]
COS22_L[5:0] 18
th CGTS_R
44 parameter 1 -
_INV[22]
COS22_R[5:0] 18
CGTS_L_INV[20:1]: Set the corresponding signal CGOUTL_n output polarity,n=1~20
CGTS_R_INV[20:1]: Set the corresponding signal CGOUTR_n output polarity,n=1~20
0: Normal output
1: Invert output signal
COSn_L_GS[3:0]: When GS_Panel=1, select CGOUTL_n output, n=1~20

COSn_R_GS[3:0]: When GS_Panel=1, select CGOUTR_n output, n=1~20
COSn_L[5:0]~
COSn_R[5:0]~ Output Signal Description
n=1~22
00_0000 CK[0] GROUP0:Gate CLK
00_0001 CK[1] Gate CLK
Description 00_0101 CK[5] Gate CLK
00_1010 CK[10] Gate CLK
00_1011 CK[11] Gate CLK
00_1100 CK[12] Gate CLK
00_1101 CK[13] Gate CLK
00_1110 CK[14] Gate CLK
00_1111 CK[15] Gate CLK
01_0000 CK_1[0] GROUP1:Gate CLK
01_0001 CK_1 [1] Gate CLK
01_0010 CK_1 [2] Gate CLK
01_0011 CK_1 [3] Gate CLK

HX8394-F
01_0101 CK_1 [5] Gate CLK
01_0110 CK_1 [6] Gate CLK
01_0111 CK_1 [7] Gate CLK
01_1000 1'b0 VGL
01_1001 1'b1 VGH
Frame or Line toggle signal
01_1010 GPWR1
(Non-overlap)
01_1011 GPWR2
(Non-overlap)
01_1100 GPWR1
(overlap)
01_1101 GPWR2
(overlap)
01_1110 - -
01_1111 - -
10_0000 STV[0] GROUP 0 SHR0[11:0]
10_0001 STV[1] SHR0[11:0]+SHR0_1[3:0]
10_0010 STV[2] SHR0[11:0]+SHR0_2[3:0]
10_0011 STV[3] SHR0[11:0]+SHR0_3[3:0]
10_0100 STV[4] GROUP 1 SHR1[11:0]
10_0101 STV[5] SHR1[11:0]+SHR1_1[3:0]
10_0110 STV[6] SHR1[11:0]+SHR1_2[3:0]
10_0111 STV[7] SHR1[11:0]+SHR1_3[3:0]
10_1000 STV[8] GROUP-2 SHR2[11:0]
10_1001 STV[9] SHR2[11:0]+SHR2_1[3:0]
10_1010 STV[10] SHR2[11:0]+SHR2_2[3:0]
10_1011 STV[11] SHR2[11:0]+SHR2_3[3:0]
Others inhibited -

Status Availability

HX8394-F
5.19.21 Set GIP Option2 (D6h)

D6H
Command 0 1 1 0 1 0 1 1 0 D6
CGOUT
st
1 parameter 1 - _L_HIZ_ COS1_L_GS[5:0] 18
IN[1]
CGOUT
nd
2 parameter 1 - _R_HIZ COS1_R_GS[5:0] 18
_IN[1]
CGOUT
rd
IN[2]
CGOUT
th
_IN[2]
CGOUT
th
IN[3]
CGOUT
th
_IN[3]
CGOUT
th
IN[4]
CGOUT
th
_IN[4]
CGOUT
th
IN[5]
CGOUT
th
_IN[5]
CGOUT
st
IN[6]
CGOUT
nd
_IN[6]
CGOUT
rd
IN[7]
CGOUT
th
_IN[7]
CGOUT
th
IN[8]
CGOUT
th
_IN[8]
th CGOUT
17 parameter
1 - _L_HIZ_ COS9_L_GS[5:0] 18
IN[9]
CGOUT
th
_IN[9]
CGOUT
th
IN[10]
th CGOUT
20 parameter
1 - _R_HIZ COS10_R_GS[5:0] 18
_IN[10]
CGOUT
st
IN[11]
CGOUT
nd
_IN[11]
rd CGOUT
23 parameter 1 - _L_HIZ_
COS12_L_GS[5:0] 18

HX8394-F
IN[12]
CGOUT
th
_IN[12]
th CGOUT
25 parameter
1 - _L_HIZ_ COS13_L_GS[5:0] 18
IN[13]
CGOUT
th
_IN[13]
th CGOUT
27 parameter
1 - _L_HIZ_ COS14_L_GS[5:0] 18
IN[14]
CGOUT
th
_IN[14]
CGOUT
th
IN[15]
th CGOUT
30 parameter
1 - _R_HIZ COS15_R_GS[5:0] 18
_IN[15]
CGOUT
st
IN[16]
CGOUT
nd
_IN[16]
CGOUT
rd
IN[17]
CGOUT
th
_IN[17]
th CGOUT
35 parameter
1 - _L_HIZ_ COS18_L_GS[5:0] 18
IN[18]
CGOUT
th
_IN[18]
th CGOUT
37 parameter
1 - _L_HIZ_ COS19_L_GS[5:0] 18
IN[19]
CGOUT
th
_IN[19]
CGOUT
th
IN[20]
th CGOUT
40 parameter
1 - _R_HIZ COS20_R_GS[5:0] 18
_IN[20]
CGOUT
st
IN[21]
CGOUT
nd
_IN[21]
CGOUT
rd
IN[22]
CGOUT
th
_IN[22]
CGOUT_L_HIZ_IN[n]: Set the CGOUTL_n output = Hi-Z, n=1~20
CGOUT_R_HIZ_IN[n]: Set the CGOUTR_n output = Hi-Z, n=1~20
0: Normal output
1: Hi-Z
Description
COSn_L_GS[3:0]: When GS_Panel=1, select CGOUTL_n output, n=1~20
COSn_R_GS[3:0]: When GS_Panel=1, select CGOUTR_n output, n=1~20

HX8394-F
COSn_L_GS[5:0]~
COSn_R_GS[5:0]~ Output Signal Description
n=1~22
00_0000 CK[0] GROUP0:Gate CLK
00_1010 CK[10] Gate CLK
00_1011 CK[11] Gate CLK
00_1100 CK[12] Gate CLK
00_1101 CK[13] Gate CLK
00_1110 CK[14] Gate CLK
00_1111 CK[15] Gate CLK
01_0000 CK_1[0] GROUP1:Gate CLK
01_0001 CK_1 [1] Gate CLK
01_0010 CK_1 [2] Gate CLK
01_0011 CK_1 [3] Gate CLK
01_0100 CK_1 [4] Gate CLK
01_0101 CK_1 [5] Gate CLK
01_0110 CK_1 [6] Gate CLK
01_0111 CK_1 [7] Gate CLK
01_1000 1'b0 VGL
01_1001 1'b1 VGH
01_1010 GPWR1
(Non-overlap)
01_1011 GPWR2
(Non-overlap)
01_1100 GPWR1
(overlap)
01_1101 GPWR2
(overlap)
01_1110 - -
01_1111 - -
10_0000 STV[0] GROUP 0 SHR0[11:0]
10_0001 STV[1] SHR0[11:0]+SHR0_1[3:0]
10_0010 STV[2] SHR0[11:0]+SHR0_2[3:0]
10_0011 STV[3] SHR0[11:0]+SHR0_3[3:0]
10_0100 STV[4] GROUP 1 SHR1[11:0]
10_0101 STV[5] SHR1[11:0]+SHR1_1[3:0]
10_0110 STV[6] SHR1[11:0]+SHR1_2[3:0]
10_0111 STV[7] SHR1[11:0]+SHR1_3[3:0]
10_1000 STV[8] GROUP-2 SHR2[11:0]
10_1001 STV[9] SHR2[11:0]+SHR2_1[3:0]
10_1010 STV[10] SHR2[11:0]+SHR2_2[3:0]
10_1011 STV[11] SHR2[11:0]+SHR2_3[3:0]
Others inhibited -

HX8394-F
Status Availability

HX8394-F
5.19.22 SETGPO (D9h)
SETGPO
D9H
Command 0 1 1 0 1 1 0 0 1 D9
st ESD_D
1 parameter 1
ET
- - - TE_GPO[3:0]
nd
2 parameter 1 - - - - TE1_GPO[3:0]
rd
3 parameter 1 - - - - CABC_GPO[3:0]
th
4 parameter 1 - - - - SDO_GPO[3:0]
ESD_DET: ESD detection bit, read ‘1’ for the following conditions: OSC_EN=0, GAS, STB=1,
DSI suspend
TE_GPO[3:0]: Set the output pin TE.
TE1_GPO[3:0]: Set the output pin TE1.
CABC_GPO[3:0]: : Set the output pin CABC_PWM_OUT.
SDO_GPO[3:0]: Set the output pin SDO.
TE_GPO[3:0]/ TE1_GPO[3:0]/ CABC_GPO[3:0]/ TE/ TE1/ CABC_PWM_OUT/ SDO

SDO_GPO[3:0] Output signal
0 0 0 0 TE
Description 0 0 0 1 TE1
0 0 1 0 BC
0 0 1 1 HSYNC
0 1 0 0 VSYNC
0 1 0 1 DE
0 1 1 0 DSI_ERR_RPT
0 1 1 1 SDO
1 0 0 0 STB
1 0 0 1 CABC_LED_EN_IN
1 0 1 0 ESD_DET

Status Availability

HX8394-F
5.19.23 SETSCALING (DDh)
SETSCALING
DDH
Command 0 1 1 0 1 1 1 0 1 DD
SCALI
st SCALIN
1 parameter 1 - - - - - - NG_T
G_EN
00
YPE
SCALING_EN: Set”1” enable scaling function.
SCALING_TYPE:
Description 0: 1.33x scaling: 540RGBx960 scales to 720RGBx1280
1: 1.5x scaling: 480RGBx854 scales to 720RGBx1280

Status Availability

HX8394-F
5.19.24 SETIDLE (DFh)
SETIDLE
D9H
Command 0 1 1 0 1 1 1 1 1 DF
st
1 parameter 1 - - - - - NW_I[2:0] 00
nd
2 parameter 1 BP_I[7:0] 1C
rd
3 parameter 1 FP_I[7:0] 0B
th
4 parameter 1 RTN_I[7:0] 45
th
5 parameter 1 VCMC_F_I[7:0] 34
h
6 parameter 1 VCMC_B_I[7:0] 34
th VCMC VCMC_
7 parameter 1 AP_I[2:0] - - -
_B_I[8] F_I[8]
83
Set Idle mode related setting.
NW_I[2:0]: Inversion type setting in idle mode.

NW_I[2:0] Inversion type
0 0 0 Column inversion
1 0 1 Zig-zag inversion
1 1 0 2-dot-2 inversion
BP_I[7:0] : Specify the amount of scan line for back porch(BP) in idle mode.
FP_I[7:0]: Specify the amount of scan line for front porch (FP) in idle mode.
FP[7:0]_I / BP_I[7:0] Number of front porch/ back porch Lines

8h’00 2 lines
8h’01 3 lines
8h’02 4 lines
8h’03 5 lines
Description
8h’04 6 lines
8h’05 7 lines
: :
8h’FB 253 lines
8h’FC 254 lines
8h’FD 255 lines
8h’FE 256 lines
8h’FF 257 lines
Note: Set BP_I[7:0] = VS + VBP – 2, and FP_I[7:0] = VFP – 2.
RTN_I[7:0]: A cycle time of line width in idle mode.

(1 TCON clock period= 1/22MHz)
RTN_I[7:0] Clock per Line
8h’00 97 TCON CLK
8h’01 98 TCON CLK
8h’02 99 TCON CLK
: :
8’hFD 350 TCON CLK
8’hFE 351 TCON CLK
8’hFF 352 TCON CLK
VCMC_F_I[8:0]: Forward scan VCOM voltage control in Idle mode.

HX8394-F
VCMC_B_I[8:0]: Backward scan VCOM voltage control in Idle mode.
VCMC_F_I[8:0]/VCMC_B_I[8:0] VCOM
0 0 0 0 0 0 0 0 0 VSSA
0 0 0 0 0 0 0 0 1 -4.00V
0 0 0 0 0 0 0 1 0 -4.00V
0 0 0 0 0 0 0 1 1 -4.00V
0 0 0 0 0 0 1 0 0 -4.00V
0 0 0 0 0 0 1 0 1 -4.00V
0 0 0 0 0 0 1 1 0 -4.00V
0 0 0 0 0 0 1 1 1 -4.00V
0 0 0 0 0 1 0 0 0 -4.00V
0 0 0 0 0 1 0 0 1 -3.99V
0 0 0 0 0 1 0 1 0 -3.98V
0 0 0 0 0 1 0 1 1 -3.97V
: :
1 1 0 0 1 0 1 1 0 -0.02V
1 1 0 0 1 0 1 1 1 -0.01V
1 1 0 0 1 1 0 0 0 VSSA
1 1 0 0 1 1 0 0 1 0.01V
1 1 0 0 1 1 0 1 0 0.02V
1 1 0 0 1 1 0 1 1 0.03V
: :
1 1 1 1 1 1 0 1 0 0.98V
1 1 1 1 1 1 0 1 1 0.99V
1 1 1 1 1 1 1 0 0 1V
1 1 1 1 1 1 1 0 1 1V
1 1 1 1 1 1 1 1 0 1V
1 1 1 1 1 1 1 1 1 HZ
AP_I[2:0]: Adjust the amount of fixed current from the fixed current source for the operational
amplifier in idle mode.
AP_I[2:0] Constant Current of Operational Amplifier
0 0 0 Stop
0 0 1 0.5µA
0 1 0 1.0µA
0 1 1 1.5µA
1 0 0 2.0µA
1 0 1 2.5µA
1 1 0 3.0µA
1 1 1 3.5µA

HX8394-F
Status Availability

HX8394-F
5.19.25 SETGAMMA: Set gamma curve related setting (E0h)
SETGAMMA ( Set Gamma Curve Related Setting )

E0H
Command 0 1 1 1 0 0 0 0 0 E0
st
1 Parameter 1 - VHP0[6:0] 00
nd
2 parameter 1 - VHP1[6:0] 04
rd
th
4 parameter 1 - VHP3[6:0] 0C
th
th
th
th
8 parameter 1 - VHP7[6:0] 1C
th
9 parameter 1 VMP0[7:0] 20
th
st
nd
12 parameter 1 VMP3[7:0] 2C
rd
th
th
th
th
th
th
th
st
21 Parameter 1 VMP12[7:0] 50
nd
22 parameter 1 - VLP0[6:0] 54
rd
th
24 parameter 1 - VLP2[6:0] 5C
th
th
th
th
28 parameter 1 - VLP6[6:0] 6C
th
29 parameter 1 - VLP7[6:0] 7F
th
30 parameter 1 - VHN0[6:0] 00
st
31 Parameter 1 - VHN1[6:0] 04
nd
rd
33 parameter 1 - VHN3[6:0] 0C
th
th
th
th
37 parameter 1 - VHN7[6:0] 1C
th
38 parameter 1 VMN0[7:0] 04
th
39 parameter 1 VMN1[7:0] 0C
th
40 parameter 1 VMN2[7:0] 0D
st
41 Parameter 1 VMN3[7:0] 0A
nd
rd
th
44 parameter 1 VMN6[7:0] 0D
th
th
th
47 parameter 1 VMN9[7:0] 0C
th
48 parameter 1 VMN10[7:0] 0F
th
th
st
51 Parameter 1 - VLN0[6:0] 54
nd
52 parameter 1 - VLN1[6:0] 58
HX8394-F
rd
53 parameter 1 - VLN2[6:0] 5C
th
th
th
th
57 parameter 1 - VLN6[6:0] 6C
th
58 parameter 1 - VLN7[6:0] 7F
This command is to set gamma register.
Register Positive Negative

Description
Groups Polarity Polarity
Up Edge VHP3 6-0 VHN3 6-0 128-to-1 selector (voltage level of grayscale 5)
adjustment VHP4 6-0 VHN4 6-0 128-to-1 selector (voltage level of grayscale 7)
Description VMP4 7-0 VMN4 7-0 255-to-1 selector (voltage level of grayscale 76)
Center
adjustment
Down Edge VLP3 6-0 VLN3 6-0 128-to-1 selector (voltage level of grayscale 248)
adjustment VLP4 6-0 VLN4 6-0 128-to-1 selector (voltage level of grayscale 250)
Restriction SETEXTC turn on to enable this command.
Status Availability

HX8394-F
5.19.26 SETCHEMODE_DYN (E4h)
SETCHEMODE_DYN (Set color enhancement mode, dynamic)

E4H
Command 0 1 1 1 0 0 1 0 0 E4
st DYN_C
1 parameter 1 - - - - - - -
EH_EN
01
nd
2 parameter 1 HUE_MODE[1:0] SE_MODE[1:0] BE_MODE[1:0] CE_MODE[1:0] 00
This command is to set color enhanment and dynamic mode.
DYN_CHE_EN: Select the color enhancement reload mode. 0: static mode, 1: dynamic mode.
CE_MODE[1:0]: Set color (saturation) enhancement.
BE_MODE[1:0]: Set brightness enhancement.
SE_MODE[1:0]: Set sharpness enhancement.
HUE_MODE[1:0]: Set hue enhancement.
In Static mode:
Enhancement level selection: when SE/BE/CE/HUE is turn on, the enhancement effect
depends on the gobal gain curve set.
Description CE_MODE[1:0]/ BE_MODE[1:0]/ SE_MODE[1:0]/ HUE_MODE[1:0] Enhance

0 0 Off
0 1
1 0 On
1 1
In Dynamic mode:
Enhance level selection. wWhen SE/BE/CE/HUE turn on, the enhancement gain setting will be
read from the ROM table. Three sets of enhancement gain are provide for selection.
CE_MODE[1:0]/ BE_MODE[1:0]/ SE_MODE[1:0]/ HUE_MODE[1:0] Enhance
0 0 Off
0 1 Low
1 0 Medium
1 1 High

Status Availability

HX8394-F
5.19.27 SETCHE (E5h)
SETCHE (Set color enhancement, static/OTP)

E5H Def
DCX D7 D6 D5 D4 D3 D2 D1 D0
Val
Command 0 1 1 1 0 0 1 0 1 E5
st
1 parameter 1 - - - SG0_F[4:0] -
nd
2 parameter 1 - - - SG64_F[4:0] -
rd
3 parameter 1 - - - SG128_F[4:0] -
th
4 parameter 1 - - - SG192_F[4:0] -
th
5 parameter 1 - - - SG255_F[4:0] -
th
6 parameter 1 TH_SAT[7:0] -
th
7 parameter 1 TH_WHITE[7:0] -
th
8 parameter 1 TH_COLOR[7:0] -
th
9 parameter 1 TH_GRAY[7:0] -
th
10 parameter 1 - - - CG0_F[4:0] -
st
11 parameter 1 - - - CG64_F[4:0] -
nd
12 parameter 1 - - - CG128_F[4:0] -
rd
13 parameter 1 - - - CG192_F[4:0] -
th
14 parameter 1 - - - CG255_F[4:0] -
th
15 parameter 1 THC[7:0] -
th
16 parameter 1 - - - - EG2_F[1:0] EG1_F[1:0] -
th
17 parameter 1 TH_RFL[7:0]
th
18 parameter 1 - - - SG16_F[4:0] -
th
19 parameter 1 - - - SG32_F[4:0] -
th
20 parameter 1 - - - SG48_F[4:0] -
st
21 parameter 1 - - - SG80_F[4:0] -
nd
22 parameter 1 - - - SG96_F[4:0] -
rd
23 parameter 1 - - - SG112_F[4:0] -
th
24 parameter 1 - - - SG144_F[4:0] -
th
25 parameter 1 - - - SG160_F[4:0] -
th
26 parameter 1 - - - SG176_F[4:0] -
th
27 parameter 1 - - - SG208_F[4:0] -
th
28 parameter 1 - - - SG224_F[4:0] -
th
29 parameter 1 - - - SG240_F[4:0] -
th
30 parameter 1 - - - CG16_F[4:0] -
st
31 parameter 1 - - - CG32_F[4:0] -
nd
32 parameter 1 - - - CG48_F[4:0] -
rd
33 parameter 1 - - - CG80_F[4:0] -
th
34 parameter 1 - - - CG96_F[4:0] -
th
35 parameter 1 - - - CG112_F[4:0] -
th
36 parameter 1 - - - CG144_F[4:0] -
th
37 parameter 1 - - - CG160_F[4:0] -
th
38 parameter 1 - - - CG176_F[4:0] -
th
39 parameter 1 - - - CG208_F[4:0] -
th
40 parameter 1 - - - CG224_F[4:0] -
st
41 parameter 1 - - - CG240_F[4:0] -
Parameters for CE function.
SG0_F[4:0]: L:00h; M:04h; H:08h;
SG16_F[4:0]: L:02h; M:05h; H:08h;
SG32_F[4:0]: L:04h; M:08h; H:09h;
SG48_F[4:0]: L:06h; M:0Ah; H:0Ah;
Description
SG64_F[4:0]: L:08h; M:0Bh; H:0Eh;
SG80_F[4:0]: L:08h; M:0Bh; H:0Eh;
SG96_F[4:0]: L:08h; M:0Ah; H:0Bh;
SG112_F[4:0]: L:07h; M:09h; H:0Bh;
SG128_F[4:0]: L:06h; M:08h; H:0Ah;

HX8394-F
SG144_F[4:0]: L:06h; M:08h; H:0Ah;
SG160_F[4:0]: L:06h; M:08h; H:0Ah;
SG176_F[4:0]: L:05h; M:07h; H:09h;
SG192_F[4:0]: L:04h; M:06h;H:08h;
SG208_F[4:0]: L:03h; M:05h;H:06h;
SG224_F[4:0]: L:02h; M:04h;H:05h;
SG240_F[4:0]: L:01h; M:02h;H:03h;
SG255_F[4:0]: L:00h; M:00h; H:00h;
TH_SAT[7:0]: L:20h; M:20h; H:20h;
TH_WHITE[7:0]: L:20h; M:20h; H:20h;
TH_COLOR[7:0]: L:20h; M:20h; H:20h;
TH_GRAY[7:0]: L:10h; M:10h; H:10h;
TH_RFL[7:0]: L:20h; M:20h; H:20h;
Parameters for BE function

CG0_F[4:0]: L:00h; M:04h; H:08h;
CG16_F[4:0]: L:02h; M:05h; H:09h;
CG32_F[4:0]: L:03h; M:07h; H:0Ah;
CG48_F[4:0]: L:05h; M:09h; H:0Bh;
CG64_F[4:0]: L:08h; M:0Ah H:0Ch;
CG80_F[4:0]: L:08h; M:0Ah; H:0Ch;
CG96_F[4:0]: L:07h; M:0Ah; H:0Bh;
CG112_F[4:0]: L:07h; M:09h; H:0Bh;
CG128_F[4:0]: L:06h; M:08h; H:0Ah;
CG144_F[4:0]: L:06h; M:08h; H:0Ah;
CG160_F[4:0]: L:05h; M:07h; H:0Ah;
CG176_F[4:0]: L:05h; M:07h; H:09h;
CG192_F[4:0]: L:04h; M:06h;H:08h;
CG208_F[4:0]: L:03h; M:05h; H:07h;
CG224_F[4:0]: L:02h; M:04h; H:06h;
CG240_F[4:0]: L:01h; M:03h; H:03h;
CG255_F[4:0]: L:00h; M:00h; H:00h;
THC[7:0]: L:80h; M:80h; H:80h;
Parameters for SE function

EG2_F[1:0], EG1_F[1:0]: L:0Ah; M: 09h; H:08h;

Status Availability

HX8394-F
5.19.28 SETCESEL: Enable color enhance (E6h)
SETCESEL(Enable color enhancement)

E6H
Command 0 1 1 1 0 0 1 1 0 E6
REG_
st
1 parameter 1 CE_vv - - - - - - - -
_en
REG_
REG_
BE_1
nd CE_1
2 parameter 1 - - - 6 - - - -
6BN_
BN_E
EN
N
rd
3 parameter 1 - -
th
4 parameter 1 - -
th
5 parameter 1 - -
th
6 parameter 1 CS_RING(1)[7:0] -
th
7 parameter 1 CS_RING(2) [7:0] -
th
8 parameter 1 CS_RING(3) [7:0]
th
th
th
th
th
th
th
th
th
REG_CE_vv_en : 1:Enable TH_SAT, TH_WHITE, TH_RFL local gain function

0: Disable TH_SAT, TH_WHITE, TH_RFL local gain function
REG_BE_16BN_EN : 1:Enable 16-band global gain curve for BE

0: Disable 16-band global gain curve for BE
REG_CE_16BN_EN : 1:Enable 16-band global gain curve for CE

0: Disable 16-band global gain curve for CE
CS_RING(1)[7:0]~CS_RING(12)[7:0]: parameters for 12 hue gain adjustment. The

available value for CS_RING(x)[7:0] is 00h~20h, other settings are not applicable.
12 hues can be adjusted to enhance the specified colors.
Description
CS_RING(1): L:10h; M:13h; H:1Ch;

HX8394-F
CS_RING(2): L:0Ah; M:0Bh; H:18h;
CS_RING(3): L:10h; M:13h; H:1Ch;
CS_RING(4): L:20h; M:20h; H:20h;
CS_RING(5): L:20h; M:20h; H:20h;
CS_RING(6): L:20h; M:20h; H:20h;
CS_RING(7): L:0Ch; M:12h; H:16h;
CS_RING(8): L:08h; M:0Ch; H:12h;
CS_RING(9): L:0Fh; M:13h; H:16h;
CS_RING(10): L:20h; M:20h; H:20h;
CS_RING(11): L:20h; M:20h; H:20h;
CS_RING(12): L:20h; M:20h; H:20h;

Status Availability

HX8394-F
5.19.29 SET_SP_CMD (E9h)
GETHXID
E9H
Command 0 1 1 1 1 0 1 0 0 F4
RAND_
st FORCE WR_SE
1 parameter 1
_OPT RIAL_E
RAND_WR_CNT[5:0] 98
N
This command is used to directly set register value of specific parameter.
FORCE_OPT: 0: disable, 1: enable
Description RAND_WR_SERIAL_EN: Set to ”1” for more than 1 parameter access.
RAND_WR_CNT[5:0]: Specify the parameter index.

Status Availability

HX8394-F
5.19.30 SETREADINDEX: Set SPI Read Index (FEh)
SET SPI READ INDEX (Set SPI READ Command Address)

FEH
Command 0 1 1 1 1 1 1 1 0 FE
st
1 parameter 1 CMD_ADD[7:0] -
Description SET SPI Read Command Address for User Define Command.
Status Availability

HX8394-F
5.19.31 GETSPIREAD: SPI Read Command Data (FFh)
GETSPIREAD (Read Command Data)

FFH
Command 0 1 1 1 1 1 1 1 1 FF
st
1 parameter 1 CMD_DATA1[7:0] -
: 1 : -
th
n parameter 1 CMD_DATAn[7:0] -
Description Read SPI Command Data for User Define Command.
Status Availability

HX8394-F
6. Layout Recommendation
6.1 Maximum layout resistance
Maximum series
Name Type Unit
resistance
VDD1 Power supply 5 Ω
VDD3 Power supply 5 Ω
VPP Power supply 5 Ω
HS_VCC Power supply 5 Ω
HS_VSS Power supply 5 Ω
VSSD Power supply 5 Ω
VSSA Power supply 5 Ω
VSSAC Power supply 20 Ω
BS[2:0] Input 100 Ω
PCCS[1:0] Input 100 Ω
CSX, DCX, RESX, SCL Input 100 Ω
HSYNC, DE, VSYNC, PCLK Input 100 Ω
SDI Input 100 Ω
SDO Output 100 Ω
DB[23:0] Input 100 Ω
CABC_PWM_OUT, TE, TE1 Output 100 Ω
VCOM Output 10 Ω
VCOMR Input 100 Ω
HS_CP, HS_CN Input 5 Ω
HS_D0P, HS_D0N Input / Output 5 Ω
HS_D1P, HS_D1N Input 5 Ω
VDDD Capacitor Connection 5 Ω
VCL Capacitor Connection 10 Ω
VSP, VSN Capacitor Connection 10 Ω
VSPR, VSNR Capacitor Connection 50 Ω
VREF Capacitor Connection 20 Ω
VGH, VGL Capacitor Connection 10 Ω
HS_LDO Capacitor Connection 5 Ω
OSC Input 100 Ω
C21P, C21N, C22P, C22N,
Capacitor Connection 5 Ω
C31P, C31N, C41P, C41N
VCSW1, VCSW2 Output 10 Ω
GOUT_L1~22, GOUT_R1~22 Output 10 Ω
TEST[2:0] Input 100 Ω
FRM Input 100 Ω
VTESTOUTP, VTESTOUTN Output 100 Ω
Table 6.1: Maximum layout resistance

HX8394-F
6.2 External components connection
HX5186-A/B/C mode:
Typical
Pad Name Symbol Connection
Component Value
VDD3 C1 Connect to Capacitor (Max 10V): VDD3 ---(+)----| |--- (-)-----VSSA 2.2 µF
C41P – C41N C3 Connect to Capacitor (Max 6V): C41P ---(+)----| |--- (-)-----C41N 1.0 µF
VCL C4 Connect to Capacitor (Max 6V): VCL ---(-)----| |--- (+)----- VSSA 1.0 µF
C8 Connect to Capacitor (Max 25V): VGL ---(-)----| |--- (+)----- VSSA 1.0 µF
VF < 0.4V / 20mA @
VGL 25°C, VR ≥30V
D1 Connect to Schottky Diode(VR≥30V): VSSA ---(-)----∫◄--- (+)---- VGL (Recommended
diode: RB521S-30)
VGH C9 Connect to Capacitor (Max 25V): VGH ---(+)----| |--- (-)----- VSSA 1.0 µF
VREF C10 Connect to Capacitor (Max 6V): VREF ---(+)----| |--- (-)-----VSSA 1.0 µF
VCOM C11 Connect to Capacitor (Max 6V): VCOM ---(-)----| |--- (+)----- VSSA 2.2 µF
VSNR C12 Connect to Capacitor (Max 10V): VSNR ---(+)----| |--- (-)-----VSSA 1.0 µF
VSPR C13 Connect to Capacitor (Max 10V): VSPR ---(-)----| |--- (+)-----VSSA 1.0 µF
VDDD C14 Connect to Capacitor (Max 6V): VDDD ---(+)----| |--- (-)-----VSSA 2.2 µF
HS_LDO C15 Connect to Capacitor (Max 6V): HS_LDO ---(+)----| |--- (-)----HS_VSS 1.0 µF
VSP C16 Connect to Capacitor (Max 10V): VSP ---(+)----| |--- (-)-----VSSA 2.2 µF
VSN C17 Connect to Capacitor (Max 10V): VSN ---(-)----| |--- (+)-----VSSA 2.2 µF
HX5186-A/B/C U1 Please refer HX5186-A/B/C datasheet -
HX5186 C18 Please refer HX5186-A datasheet 1.0uF
Table 6.2: HX5186-A/B/C mode external components

HX8394-F
PFM type A mode:
Typical
Component Value
VF < 0.4V / 20mA @
diode: RB521S-30)
VSNR C12 Connect to Capacitor (Max 10V):VSNR ---(+)----| |--- (-)-----VSSA 1.0 µF
VSPR C13 Connect to Capacitor (Max 10V):VSPR ---(-)----| |--- (+)-----VSSA 1.0 µF
VSN C16 Connect to Capacitor (Max 10V):VSN ---(-)----| |--- (+)-----VSSA 4.7 µF
VSP C17 Connect to Capacitor (Max 10V):VSP ---(+)----| |--- (-)-----VSSA 4.7 µF
PFM L1 Inductance,please refer PFM type A connection. 10.0uH
VF < 0.4V / 20mA @
25°C, VR ≥30V
PFM D2 Schottky Diode , please refer PFM type A connection. (Recommended
diode: RB521S-30)
VF < 0.4V / 20mA @
25°C, VR ≥30V
PFM D3 Schottky Diode , please refer PFM type A connection. (Recommended
diode: RB521S-30)
PFM SW1 MOS switch, please refer PFM type A connection. -
PFM SW2 MOS switch, please refer PFM type A connection. -
Table 6.3: PFM type A external components

HX8394-F
PFM type C mode:
Typical
Component Value
VF < 0.4V / 20mA @
diode: RB521S-30)
VDDD C14 Connect to Capacitor (Max 6V): VDDD ---(+)----| |--- (-)-----VSSA 2.2µF
PFM L1 Inductance,please refer PFM type C connection. 10uH
VF < 0.4V / 20mA @
25°C, VR ≥30V
PFM D2 Schottky Diode, please refer PFM type C connection. (Recommended
diode: RB521S-30)
VF < 0.4V / 20mA @
25°C, VR ≥30V
diode: RB521S-30)
VF < 0.4V / 20mA @
25°C, VR ≥30V
diode: RB521S-30)
PFM SW1 MOS switch, please refer PFM type C connection. -
PFM C18 Capacitor, please refer PFM type C connection. 1.0 µF
Table 6.4: PFM type C external components

HX8394-F
PFM type D mode:
Typical
Component Value
VF < 0.4V / 20mA @
diode: RB521S-30)
PFM L1 Inductance,please refer PFM type D connection. 10.0uH
VF < 0.4V / 20mA @
25°C, VR ≥30V
PFM D2 Schottky Diode, please refer PFM type D connection. (Recommended
diode: RB521S-30)
PFM SW1 MOS switch, please refer PFM type Dconnection. -
Table 6.5: PFM type D external components

HX8394-F
External VDD1/ VSP / VSN / VGH / VGL mode:
Typical
Component Value
VF < 0.4V / 20mA @
D1 Connect to Schottky Diode(VR≥30V): VSN ---(-)----∫◄--- (+)---- VGL (Recommended
diode: RB521S-30)
Table 6.6: External VDD1 / VSP / VSN / VGH / VGL external components

HX8394-F
External VDD1/ VSP / VSN mode:
Typical
Component Value
VF < 0.4V / 20mA @
D1 Connect to Schottky Diode(VR≥30V): VSN ---(-)----∫◄--- (+)---- VGL (Recommended
diode: RB521S-30)
Table 6.7: External VDD1 / VSP / VSN external components

HX8394-F
7. Electrical Characteristics
7.1 Absolute maximum ratings
The absolute maximum ratings are list on Table 7.1. When used out of the absolute
maximum ratings, the LSI may be permanently damaged. Using the LSI within the
following electrical characteristics limit is strongly recommended for normal operation.
If these electrical characteristic conditions are exceeded during normal operation, the
LSI will malfunction and cause poor reliability.
Spec.
Parameter Symbol Unit Note
Min. Typ. Max.
(1),(2)
Power Supply Voltage 1 VDD1~ VSSD -0.3 - +3.6 V Note
(1) (4)
Power Supply Voltage 2 VDD3 ~ VSSA -0.3 - +3.6 V Note
HS_VCC ~ (1) (5)
Power Supply Voltage 3 -0.3 - +3.6 V Note
HS_VSS
(6)
Power Supply Voltage 4 VSP ~ VSSA -0.3 - +6.6 V Note
(7)
Power Supply Voltage 5 VSSA ~ VSN -6.6 - 0 V Note
(8)
Power Supply Voltage 6 VGH ~ VSSA -0.3 - +19.6 V Note
(9)
Power Supply Voltage 7 VSSA ~ VGL -16 - 0 V Note
(10)
Operating Temperature Topr -40 - +85 °C Note
(11)
Storage Temperature Tstg -55 - +110 °C Note
(12)
Input Voltage VIN -0.3 - VDD1+0.3 V Note
(13)
HS Input Voltage VHSIN -0.3 - +2 V Note
Note: (1) VDD1, VSSD must be maintained.
(2) To make sure VDD1 ≥ VSSD.
(4) To make sure VDD3≥ VSSA.
(5) To make sure HS_VCC ≥ HS_VSS.
(6) To make sure VSP ≥ VSSA.
(7) To make sure VSSA ≥ VSN
(8) To make sure VGH ≥ VSSA.
(9) To make sure VSSA ≥ VGL, VGH +|VGL| < 32V
(10) For die and wafer products, specified up to +85 . ℃
(11) This temperature specifications apply to the TCP package.
(12) This specifications include input signals but without following: CP, CN, D0P, D0N, D1P, D1N, D2P,
D2N, D3P, D3N.
(13) This specifications include following signals: CP, CN, D0P, D0N, D1P, D1N, D2P, D2N, D3P, D3N.
Table 7.1: Absolute maximum rating

HX8394-F
7.2 DC characteristics
(VDD3=2.5 ~ 3.6V, VDD1=1.65~3.6V, TA=-40 ~ 85 °C)

Parameter Symbol Test condition Spec. Unit Note
Min. Typ. Max.
Input high voltage VIH VDD1= 1.65 ~ 3.6V 0.7 VDD1 - VDD1 V -
Input low voltage VIL VDD3= 2.5 ~ 3.6V 0 - 0.3 VDD1 V -
VIH V
VPP VPP 7.25 7.5 7.75 (1)
VIL V
Output high voltage
VOH1 IOH = -1.0 mA 0.8 VDD1 - VDD1 V -
(SDO, CABC_PWM_OUT)
Output low voltage VDD1= 1.65 ~ 3.6V
VOL1 0 - 0.2 VDD1 V -
(SDO, CABC_PWM_OUT) IOL = 1.0 mA
VSYNC, HSYNC - - 1 uA -
IIH
RESX, DCX, CSX, SCL - - 1 -
Logic High level input current
DB[23:0], SDI, DCX - - 1 uA -
IIHD
DB[23:0] - - 1
VSYNC, HSYNC -1 - - uA -
IIL
RESX, DCX, CSX, SCL -1 - - -
Logic Low level input current
DB[23:0], SDI, DCX -1 - - uA
IILD
DB[23:0] -1 - - -
Current consumption
IST(VDD) - -- 30 µA -
standby mode (VDD3-VSSA)
Current consumption
VDD3/HS_VCC=2.8V,
standby mode IST(VDD1)
VDD1=1.8V
- -- 75 µA -
( VDD1– VSSD)
TA =25°C
Current consumption
(DSI Ultra Low Power mode)
standby mode which include
IST(VDD1) - -- 10 µA -
HS_VCC
( HS_VCC-HS_VSS)
Oscillator tolerance OSC △ TA =25°C -5 - 5 % -
Note: (1) The VPP pin is open on normal mode and in used while OTP programming condition.
Table 7.2: DC characteristic

HX8394-F
7.3 AC characteristics
7.3.1 DBI Type C interface characteristics
Figure 7.1: DBI Type C interface characteristics
(VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA = 25°C)

Parameter Signal Symbol Description Spec. Unit
Min. Max.
Chip select setup time
(Write) tCSS 40 -
Chip select setup time
CSX tCSH
-
40 -
ns
(Read)
Address setup time
tAST 10 -
Address hold time DCX tAHT
-
10 -
ns
(Write/Read)
Write cycle tWC 100 -
Control pulse “H” duration
WRX_SCL tWRH - 40 - ns
Control pulse “L” duration (Write) tWRL 40 -
Read cycle tRC 150 -
Control pulse “H” duration
WRX_SCL tRDH - 60 - ns
Control pulse “L” duration (Read) tRDL 60 -
For maximum
Data setup time SDI/SDO tDS
CL=30pF
30 -
ns
Data hold time (Input) tDT 30 -
For minimum CL=8pF
Read access time SDI/SDO tRACC 10 -
ns
Output disable time (Output) tOD 10 50
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals.
Table 7.3: DBI Type C interface characteristics

HX8394-F
7.3.2 DSI D-PHY electrical characteristics
7.3.2.1 Electrical characteristics of D-PHY layer
In general, the DSI D-PHY may contain the following electrical functions: High-Speed
Receiver (HS-RX), Low Power Transmitter (LP-TX), a Low-Power Receiver (LP-RX), and
the Low-Power Contention Detector (LP-CD). Figure 7.5 shows the complete set of
electrical functions required for a fully featured PHY transceiver.
Figure 7.2: Electrical functions of a fully D-PHY transceiver
Where, the HS receiver utilize low-voltage swing differential signaling for signal
transmission. The LP transmitter and LP receiver serve as a low power signaling
mechanism. The Figure 7.6 shows both the HS and LP signal levels on the left and
right sides, respectively.
Because the HS signaling levels are below the LP low-level input threshold, Lane
switches between Low-Power and High-Speed mode during normal operation.
Figure 7.3: Shows both the HS and LP signal levels

HX8394-F
7.3.2.2 Electrical characteristics of low-power transmitter
The Low-Power transmitter shall be a slew-rate controlled push-pull driver. It is used

for driving the Lines in all Low-Power operating modes It is therefore important that
the static power consumption of a LP transmitter be as low as possible. Under tables
list DC and AC characteristic for LP-TX.
Spec.
Parameter Description Unit Note
Min. Typ. Max.
VOL Thevenin output low level -50 - 50 mV -
VOH Thevenin output high level 1.1 1.2 1.3 V -
ZOLP Output impedance of LP-TX 110 - - Ω (1)
Note: (1)Though no maximum value for ZOLP is specified, the LP transmitter output impedance shall
ensure the tRLP/tFLP specification is met.
Table 7.4: LP transmitter DC specifications
Spec.
Min. Typ. Max.
15%-85% rise time and fall
tRLP/tFLP - - 25 ns (1)
time
Slew rate @ CLOAD=0pF - - 500 mV/ns (1),(3),(5),(6)
δV/δtSR Slew rate @ CLOAD=0 to 70pF
30 - - mV/ns (1),(2),(3)
(Falling Edge Only)
Slew rate @ CLOAD=0 to 70pF
30 - - mV/ns (1),(3),(7)
(Rising Edge Only)
Slew rate @ CLOAD=0 to 70pF 30 – 0.075 *
- - mV/ns (1),(8),(9)
(Rising Edge Only) (VO,INST- 700)
CLOAD Load capacitance 0 - 70 pF -
Note: (1) CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and
RX are assumed to always be <10pF. The distributed line capacitance can be up to 50pF for a transmission
line with 2ns delay.
(2) When the output voltage is between 400 mV and 930 mV.
(3) Measured as average across any 50 mV segment of the output signal transition.
(4) This parameter value can be lower than TLPX due to differences in rise vs. fall signal slopes and trip levels
and mismatches between Dp and Dn LP transmitters.
(5) This value represents a corner point in a piecewise linear curve.
(6) When the output voltage is in the range specified by VPIN(absmax).
(8) Where VO,INST is the instantaneous output voltage, VDP or VDN, in millivolts.
Table 7.5: LP transmitter AC specifications

HX8394-F
7.3.2.3 Electrical characteristics of receiver
This part will contain two parts which High-Speed Receiver and Low-Power Receiver.
Because their have differential DC and AC characteristic, describe HS-RX first then
describe LP-RX.
7.3.2.4 High-speed receiver
The HS receiver is a differential line receiver. It contains a switch-able parallel input

termination, ZID, between the positive input pin Dp and the negative input pin Dn.
Under Tables list DC and AC characteristic for HS-RX.
Spec.
Min. Typ. Max.
VIDTH Differential input high threshold - - 70 mV (1)
VIDTL Differential input low threshold -70 - - mV (1)
VILHS Single-ended input low voltage -40 - - mV (2)
VIHHS Single-ended input high voltage - - 460 mV (2)
VCMRXDC Common-mode voltage HS receive mode 70 - 330 mV (2),(3)
ZID Differential input impedance 80 100 125 Ω -
Note: (1) +/-70mV only for reference, related to power and ground noise on system environment, this spec need to check
on panel performance to fine tune.
(2) Excluding possible additional RF interference of 100mV peak sine wave beyond 450MHz.
(3) This table value includes a ground difference of 50mV between the transmitter and the receiver, the static
common-mode level tolerance and variations below 450MHz
Table 7.6: HS receiver DC Specifications
Figure 7.4: Differential HS signals for HS receiver
Spec.
Min. Typ. Max.
∆VCMRX(HF) Common mode interference beyond 450 MHz - - 100 mVPP (1)
CCM Common mode termination - - 60 pF (2)
Note: (1) ∆VCMRX(HF) is the peak amplitude of a sine wave superimposed on the receiver inputs.
(2) For higher bit rates a 14pF capacitor will be needed to meet the common-mode return loss specification.
Table 7.7: HS receiver AC Specifications

HX8394-F
7.3.2.5 Low-power receiver
The low power receiver is an un-terminated, single-ended receiver circuit. The LP

receiver is used to detect the Low-Power state on each pin. For high robustness, the
LP receiver shall filter out noise pulses and RF interference. It is recommended the
implementer optimize the LP receiver design for low power. The LP receiver shall
reject any input glitch when the glitch is smaller than eSpike. The filter shall allow
pulses wider than TMIN to propagate through the LP receiver. The related diagram
shows as Figure 7.7 Input Glitch Rejection of Low-Power Receivers. Besides, under
tables list DC and AC characteristic for LP-RX.
Figure 7.5: Input glitch rejections of low-power receivers
Spec.
Min. Typ. Max.
VIL Logic 0 input threshold - - 550 mV -
VIH Logic 1 input threshold 880 - - mV -
Table 7.8: LP receiver DC specifications
Spec.
Min. Typ. Max.
(1), (2),
eSPIKE Input pulse rejection - - 300 V.ps
(3)
TMIN-RX Minimum pulse width response 20 - - ns (4)
VINT Peak-to-peak interference voltage - - 200 mV -
fINT Interference frequency 450 - - MHz -
Note: (1) Time-voltage integration of a spike above VIL when being in LP-0 state or below VIH when being in LP-1 state
(2) An impulse less than this will not change the receiver state.
(3) In addition to the required glitch rejection, implementers shall ensure rejection of known RF-interferers.
(4) An input pulse greater than this shall toggle the output.
Table 7.9: LP receiver AC specifications

HX8394-F
7.3.2.6 Line contention detection
Contention can be inferred from any of the following conditions:
A. An LP high fault shall be detected when the LP transmitter is driving high and the
pin voltage is less than VIL.
B. An LP low fault shall be detected when the LP transmitter is driving low and the
pad pin voltage is greater than VIL.
Spec.
Min. Typ. Max.
VIHCD Logic 1 contention threshold 450 - - mV -
VILCD Logic 0 contention threshold - - 200 mV -
Table 7.10: Contention detector DC specifications

HX8394-F
7.3.2.7 High-speed data-clock timing
This section specifies the required timings on the high-speed signaling interface
independent of the electrical characteristics of the signal. The PHY is a source
synchronous interface in the Forward direction.
The Master side of the Link shall send a differential clock signal to the Slave side to
be used for data sampling. This signal shall be a DDR (Half-rate) clock and shall have
one transition per data bit time. All timing relationships required for correct data
sampling are defined relative to the clock transitions. Therefore, implementations
may use frequency spreading modulation on the clock to reduce EMI.
The DDR clock signal shall maintain a quadrature phase relationship to the data
signal. Data shall be sampled on both the rising and falling edges of the Clock signal.
The term “rising edge” means “rising edge of the differential signal, i.e. CP – CN, and
similarly for “falling edge”. Therefore, the period of the Clock signal shall be the sum
of two successive instantaneous data bit times. This relationship is shown in Figure
7.6.
Figure 7.6: DDR clock definition

The same clock source is used to generate the DDR Clock and launch the serial data.
Since the Clock and Data signals propagate together over a channel of specified
skew, the Clock may be used directly to sample the Data lines in the receiver. Such a
system can accommodate large instantaneous variations in UI.
The allowed instantaneous UI variation can cause large, instantaneous data rate
variations. Therefore, devices shall either accommodate these instantaneous
variations with appropriate FIFO logic outside of the PHY or provide an accurate
clock source to the Lane Module to eliminate these instantaneous variations.

HX8394-F
The UIINST specifications for the Clock signal are summarized in Table 7.11.
Spec.
Min. Typ. Max.
UI instantaneous UIINST - - 12.5 ns (1), (2), (3)
Note: (1) This value corresponds to a minimum 80 Mbps data rate.
(2) The minimum UI shall not be violated for any single bit period, i.e., any DDR half cycle within a data burst.
(3) Maximum total bit rate is 2.2 Gbps of 4 data lanes 24-bit data format/ 1.5Gbps of 4 data lane 18-bit data
format/ 1.33Gbps of 4 data lane 16-bit data format.
Table 7.11: Reverse HS data transmission timing parameters
The timing relationship of the DDR Clock differential signal to the Data differential
signal is shown in Figure 7.7. Data is launched in a quadrature relationship to the
clock such that the Clock signal edge may be used directly by the receiver to sample
the received data.
The transmitter shall ensure that a rising edge of the DDR clock is sent during the first
payload bit of a transmission burst such that the first payload bit can be sampled by
the receiver on the rising clock edge, the second bit can be sampled on the falling
edge, and all following bits can be sampled on alternating rising and falling edges.
All timing values are measured with respect to the actual observed crossing of the
Clock differential signal. The effects due to variations in this level are included in the
clock to data timing budget.
Receiver input offset and threshold effects shall be accounted as part of the receiver
setup and hold parameters.
Figure 7.7: Data to clock timing definitions

HX8394-F
7.3.2.8 Data-clock timing specifications
The Data-Clock timing specifications are shown in Table 7.12. Implementers shall
specify a value UIINST,MIN that represents the minimum instantaneous UI possible
within a High-Speed data transfer for a given implementation. Parameters in Table
7.12 are specified as a part of this value. The skew specification, TSKEW[TX], is the
allowed deviation of the data launch time to the ideal ½UIINST displaced quadrature
clock edge. The setup and hold times, TSETUP[RX] and THOLD[RX], respectively, describe
the timing relationships between the data and clock signals. TSETUP[RX] is the minimum
time that data shall be present before a rising or falling clock edge and THOLD[RX] is the
minimum time that data shall remain in its current state after a rising or falling clock
edge. The timing budget specifications for a receiver shall represent the minimum
variations observable at the receiver for which the receiver will operate at the
maximum specified acceptable bit error rate.
The intent in the timing budget is to leave 0.4*UIINST, i.e. ±0.2*UIINST for degradation
contributed by the interconnect.
Spec.
Min. Typ. Max.
Data to Clock Setup Time [Receiver] TSETUP[RX] 0.15 - - UIINST (1)
Clock to Data Hold Time [Receiver] THOLD[RX] 0.15 - - UIINST (1)
Note: (1) Total setup and hold window for receiver of 0.3*UIINST.
(2) 0.15UI is only for reference, related to the signal jitter caused by the transmittion path, this spec need to
check on panel performance to fine tune.
Table 7.12: Data to clock timing specifications
Figure 7.8: Skew window of transmittor and receiver

HX8394-F
7.3.3 Timings for DSI video mode
7.3.3.1 Vertical timings
Figure 7.9: Vertical timings for DSI I/F
Resolution=800x1280(VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C)

Spec.
Parameter Symbol Condition Unit
Min. Typ. Max.
Vertical cycle VP - 1286 - - Line
Vertical low pulse width VS - 2 - Note(1) Line
Vertical front porch VFP - 2 - - Line
Vertical back porch VBP - 2 - Note(1) Line
Vertical data start point - VS+VBP 4 - Note(1) Line
Vertical blanking period VBL VS+VBP+VFP 6 - - Line
Vertical active area - VDISP - 1280 - Line
Vertical Refresh rate VRR - - 60 - Hz
Note: (1) The VS and VBP pulse width are related to GSP and GCK timing. The GSP and GCK must be set at
corresponding position for LCD normal display.
Table 7.13: Vertical timings for DSI I/F

HX8394-F
7.3.3.2 Horizontal timings
BP HSS BP Packed Pixel Stream BP HSS BP

(24-bit RGB)
HP
HFP HS HBP HFP
HDISP
Invalid data Valid data Invalid data
(PCLK depend on DSI

clock and data lanes)
Figure 7.10: Horizontal timing for DSI video mode I/F
Resolution=720x1280 (VSSA=0V, VDD1=1.8V, VDD2=VDD3=VCC=2.8V, TA=25°C)

Spec.
Parameter Symbol Condition Unit
Min. Typ. Max.
HS low pulse width HS - 0.1 - - µs
Horizontal back porch HBP - 0.4 - - µs
Horizontal front porch HFP - 0.1 - - µs
Horizontal data start point - HS+HBP 0.5 - - µs
Horizontal blanking period HBLK HS+HBP+HFP 0.6 - - µs
Horizontal active area HDISP - - 720 - DCK
Table 7.14: Horizontal timings for DSI video mode I/F

HX8394-F
8. Ordering Information
Part no. Package
PD: mean COG
HX8394-F PDxxx
xxx: mean chip thickness (µm), (default: 250 µm)

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( DOC No.

Revision History December, 2014

Himax Confidential - P.2-

List of Contents December, 2014

1. GENERAL DESCRIPTION .......................................................................................11

Himax Confidential - P.6-

List of Figures December, 2014

Himax Confidential - P.8-

List of Tables December, 2014

Himax Confidential - P.10-

Preliminary Version 01 December, 2014

Himax Confidential - P.11-

Single chip solution for a WXGA type TFT LCD display

2.2 Display module

Support 2162 source channel outputs

Himax Confidential - P.12-

External charge pump: support HX5186-C mode

2.4 Display / Control interface

Display interface types supported

2.5 Input power

Logic and interface power supply (VDD1): 1.65V to 3.6V

Software programmable color depth mode

Himax Confidential - P.13-

Himax Confidential - P.14-

Chip select signal. For test only.

TE O 6 MPU Tearing Effect pin.

PCCS[1:0] must be connected to VSSD (logic=0) or VDD1(logic=1).

Himax Confidential - P.17-

4.1.1 Serial data transfer interface(MIPI DBI type C)

Himax Confidential - P.18-

Figure 4.1: Serial data stream, write mode

Figure 4.2: Serial data stream, write mode

Himax Confidential - P.19-

Figure 4.3: Type C:Serial interface protocol 3-wire/4-wire read mode

If there is a break on data transmission when transmit a command before a whole

Figure 4.4: Display module data transfer recovery

Himax Confidential - P.20-

The selection of interface is by BS[2:0]=”000”~”111“ the DSI specifies the interface

Figure 4.5: DSI transmitter and receiver interface

The data lane number is selected by register RBAh.

Himax Confidential - P.21-

The Lane Management Layer specifies DSI is Lane-scalable for increased

The Application Layer describes higher-level encoding and interpretation of data

Figure 4.6: DSI transmitter and receiver interface

Himax Confidential - P.22-

The state code of HS and LP Lane pair are defined as below:

Line Voltage Levels High-Speed Low-Power

Himax Confidential - P.23-

Enter LP Stop State:

Enter HS transmission mode:

Figure 4.7: Clock lane mode state diagram

(1) After Initial state. (HW reset, SW reset, Power on sequence)

Himax Confidential - P.24-

Himax Confidential - P.25-

HS-Prpr HS-Rqst STOP LP-Rqst

HS-Prpr HS-Rqst STOP LP-Rqst

Figure 4.8: Data lane mode state diagram

Himax Confidential - P.26-

Figure 4.9: Escape mode state machine