ATME COLLEGE OF ENGINEERING

13th KM Stone, Bannur Road, Mysore - 570 028

DEPARTMENT OF ELECTRICAL & ELECTRONICS

ENGINEERING

NOTES

SUBJECT: ANALOG ELECTRONIC CIRCUITS

SUB CODE: 18EE34

SEMESTER: III

Prepared by

Department of EEE,
ATME College of Engineering
 INSTITUTIONAL VISION AND MISSION

VISION:
Development of academically excellent, culturally vibrant, socially responsible and
globally competent human resources.

MISSION:
To keep pace with advancements in knowledge and make the students competitive and
capable at the global level.
To create an environment for the students to acquire the right physical, intellectual,
emotional and moral foundations and shine as torchbearers of tomorrow's society.
To strive to attain ever-higher benchmarks of educational excellence.

Department Vision and Mission

Vision:

To create Electrical and Electronics Engineers who excel to be technically competant

and fulfill the cultural and social aspirations of the society.

Mission:

To provide knowledge to students that builds a strong foundation in the basic

principles of electrical engineering, problem solving abilities, analytical skills, soft
skills and communication skills for their overall development.
To offer outcome based technical education.
To encourage faculty in training & development and to offer consultancy through
research & industry interaction.
 Program Educational Objectives (PEOs)
PEO1:
To produce Electrical and Electronics Engineers who will exhibit the technical and managerial
skills with professional ethics for the societal progress.
PEO2:
To make students continuously acquire, enhance their technical and socio-economic skills and
also to be globally competent.
PEO3:
To impart the experience of research and development to students so that they develop
abilities in offering solutions to relevant diverse career path.
PEO4:
To produce quality engineers with a team leading capabilities, also show good coordination to
contribute towards real time application of projects

Program Outcomes (POs)

Engineering Graduates will be able to:

PO1: Engineering Knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals and an engineering specialization to the solution of complex
engineering problems.
PO2: Problem Analysis: Identify, formulate, review research literature, and analyze
complex engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
PO3: Design / Development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified needs with
appropriate consideration for the public health and safety, and the cultural, societal, and
environmental considerations.
PO4: Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions.

PO5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
PO6: The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
PO7: Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
PO8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.
PO9: Individual and team work: Function effectively as an individual and as a member or
leader in diverse teams, and in multidisciplinary settings.

PO10: Communication: Communicate effectively on complex engineering activities with

the engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, and give and
receive clear instructions.
PO11: Project management and finance: Demonstrate knowledge and understanding of
the engineering management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
PO12: Life-long learning: Recognize the need for and have the preparation and ability to
engage in independent and lifelong learning in the broadest context of technological change.

Program Specific Outcomes (PSOs)

The students will develop an ability to produce the following engineering traits:

PSO1: $SSO\WKHFRQFHSWVRI(OHFWULFDODQG(OHFWURQLFV(QJLQHHULQJWRHYDOXDWHWKHSHUIRUPDQFH
RISRZHV\VWHPDQGDOVRWRFRQWUROLQGXVWULDOGULYHVE\XVLQJSRZHUHOHFWURQLFV

PSO2: Demonstarte the concepts of process control for Industrial Automation, design models for
environmental and social concerns and also exhibit continuous self-learning.
Analog Electronic Circuits_18EE34 2020-21

Module – I

Contents:
Diode Circuits: Diode clipping and clamping circuits.
Transistor biasing and stabilization: Operating point, analysis and design of fixed bias circuit,
self- bias circuit, Emitter stabilized bias circuit, voltage divider bias circuit, stability factor of
different biasing circuits. Problems and Transistor switching circuits.

Objectives:
1. To study the concepts of diode clipping and clamping circuits.
2. To design and analyse the transistor biasing circuits and switching circuits.

1.1. Diode Circuits

1.1.1. Diode Clipping Circuits or Limiting Circuits:
Clipping circuits are used to remove a portion of a time varying input signal without
distorting the remaining part of the applied waveform. One simple example of a clipper is a
half-wave rectifier which transfers only one half cycle of the input to the output, while clipping
off the other half cycle. By changing orientation of the diode in the circuit, positive or negative
portion of the input signal can be clipped off.

A. Shunt or Parallel Clipper:

In parallel clipper the diode appears in the parallel branch or shunt with the applied
input signal. The Fig.1 shows a shunt clipper with bias or reference voltage VR.

Fig.1.1: Shunt Clipper

The input signal can be any periodic signal such as sine, square, triangle etc. with peak
value VM greater than reference voltage VR. If VM < VR, the clipping does not takes place. Just
before the diode conducts, the current through R is zero and hence input signal is V I is directly
available at the anode of the diode as shown in Fig.1.2.

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Fig.1.2: Voltage at diode terminals

For the ideal diode to conduct, it is enough that the anode voltage just equals the cathode
voltage. For the circuit in Fig.1.1 the diode conducts for vI ≥ VR + VK. The equivalent circuit
during the diode conduction is shown in Fig.1.3 (a).

Fig.1.3 (a): Diode Conduction Fig.1.3 (b): Diode Off

From the circuit of Fig.1.3 (a) we find that

vO = VR + VK for vI ≥ VR + VK ---------- (1)

For vI ≤ VR + VK, the diode is off and the equivalent circuit is shown in Fig.1.3 (b). By
applying KVL to the circuit we get,

vi – iR - vo = 0

vo = vi, for vi ≤ VR + VK -------------- (2)

The output waveforms are shown in Fig.1.4. The circuit clips off a portion of the input
signal which lies above VR+VK and retains the remaining part as it is.

Fig.1.4: Waveforms of shunt clipper with positive clipping.

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Transfer Characteristics:

The transfer characteristics are obtained by plotting vo as a function of vi. Transfer

characteristics can be easily constructed by evaluating slope ∆vo/∆vi.

For vI ≥ VR + VK from equation (1), vo = VR + VK = constant

∆vo = 0

Hence slope ------------------ (3)

for vi ≤ VR + VK, from equation (2), vo = vi

∆vo = ∆vi

Hence slope ------------- (4)

The Fig.1.5 shows the transfer characteristics of shunt clipper along with output
waveform for sinusoidal input.

Fig.1.5: Transfer characteristics and output waveform of shunt clipper.

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B. Series Clipper:
In series clipper the diode appears in series with the input or it appears in the series
branch as shown in Fig.1.6. The voltage on diode terminals is shown in Fig.1.7.

Fig.1.6: Series Clipper.

Fig.1.6: Voltage on Diode Terminals.

The diode conducts for vI ≥ VR + VK. The equivalent circuit during diode conduction is shown
in Fig.1.7 (a).

Fig.1.7 (a): Diode Conduction Fig.1.7 (b): Diode Off

Applying KVL to the circuit shown in Fig.1.7 (a) we have,

vi – [VR + VK] – vo = 0

vo = vi – [VR + VK] for vI ≥ VR + VK ------------- (5)

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Since VR + VK is constant

∆vo = ∆vi

Hence slope

From equation (5), when vi = vm,

vo = vm – [VR + VK] ----------------- (6)

For vI ≤ VR + VK, the diode is off and the equivalent circuit is shown in Fig.1.7 (b). By
applying KVL to the circuit we get,

vo = iR = 0

Hence slope 0 --------------- (7)

The transfer characteristics and the output voltage waveform are shown in Fig.1.8.

Fig.1.8: Transfer Characteristics and Output voltage Waveform.

C. Clipping at Two Independent Levels (Double ended clipper):

Two shunt clippers can be combined to obtain clipping at two independent levels. The
Fig.1.9 shows the double ended clipper circuit which uses two reference voltages.

Fig.1.9: Double ended clipper circuit.

Note that VR1 and VR2 are positive. VR1 forward biases D1 and VR2 reverse biases D2 and
also VR2 > VR1. The voltages on the terminals of diode D1 is shown in Fig.1.10.

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Fig.1.10: Terminal Voltages on D1

The diode D1 conducts for vI ≤ VR1 - VK. The equivalent circuit is shown in Fig.1.11 (a). We
can find that;

vo = VR1 - VK for vI ≤ VR1 - VK

Hence slope 0 --------------- (8)

The diode D2 conducts for vI ≥ VR2 + VK. The equivalent circuit is shown in Fig.1.11
(b). We can find that;

vo = VR2 + VK for vI ≥ VR2 + VK

Hence slope 0 ------------- (9)

For (VR1 - VK) < vi < (VR2 + VK), neither D1 nor D2 conducts. The equivalent circuit is
shown in Fig.1.11 (c). From the circuit we get;

vo = vi

Hence slope ----------------- (10)

Fig.1.11 (a): Equivalent circuit for vI ≤ VR1 - VK Fig.1.11 (b): Equivalent circuit for v I ≥ VR2 + VK

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Fig.1.11 (c): Equivalent circuit for (VR1 - VK) < vi < (VR2 + VK).

Table 1.1: Summary on Operation of Double ended clipper.

The transfer characteristics along with output waveforms are shown in Fig.1.12.

Fig.1.12: Transfer characteristics and output voltage waveform.

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1.1.2. Clamping Circuits:

Clamping circuits are used to add dc level to the input signal. Clamping circuits are also
called as dc inserters or dc restorers. Clamping circuits uses diode, resistor and capacitor.

A. Negative Clamper:
The circuit of negative clamper is shown in Fig.1.13. A simple negative clamper circuit
is used to add a negative level to the ac output. The following assumptions are made
while analysing the clamper circuit.
1. The diode is ideal in behaviour.
2. The time constant τ = RC is designed to very large by selecting large values of R
and C.

Fig.1.13: Negative clamper circuit.

The input is square wave which swings between the ±VM with a period of T = 1/f.
During the positive half cycle of the input the diode conducts and charges the capacitor. The
charging time constant is τf = rfC. Since the diode resistance is very small τf << T/2 and hence
capacitor gets charged quickly to the peak value VM of the input signal VI. The equivalent
circuit during diode conduction is shown in Fig.1.14 (a).

Fig.1.14 (a): Diode is ON Fig.1.14 (b): Diode is OFF

Apply KVL to the circuit shown in Fig.1.14 (a) we get;

vi – vc – VK = 0 ----------- (11)

vc = VK – vi

When vi = VM; vc = VK - VM -------------- (12)

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During the negative half cycle of the input supply, the diode turns off. Now the capacitor
discharges into R. The discharge time constant is τ = RC. The capacitor should not loose much
of charge during discharge. To meet this requirement, the values of R & C are selected such that
5τ >> T/2 = 5RC >> T/2.

The equivalent circuit during the capacitor discharge is shown in Fig.1.14 (b). Apply the
KVL for the circuit we get;

vi – vc – vo = 0 ----------- (13)

vo = vi - vc

When vc = VM - VK; vo = vi – [VM - VK] ------------ (14)

Table 1.2: Output voltage levels of negative clamper

The output voltage waveforms of negative clamper circuit are shown in Fig.1.15. From the
waveforms we can observe that;

Peak to peak input voltage = peak to peak output voltage = 2 VM

Fig.1.15 (a): Output waveform for Practical diode Fig.1.14 (b): Output waveform for Ideal diode

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B. Positive Clamper:
The positive clamper circuit is obtained by reversing the diode direction in the negative
clamper circuit. The positive clamper circuit is shown in Fig.1.16. The positive clamper circuit
adds the positive dc level to the input signal.

Fig.1.16: Positive clamper circuit

During the negative half cycle of the input supply, the diode gets forward biased and
almost instantaneously capacitor gets charged equal to the maximum value VM of the input
signal. The capacitor once charged acts as a battery of voltage VM. This is because RC time
constant is very large hence capacitor holds its entire charge all the time.

In the positive half cycle the diode is reverse biased and the capacitor gets discharging
through load resistance. Due to large time constant, it hardly gets discharged during the positive
half cycle of the input supply. The waveforms of positive clamper circuit are shown in Fig.1.17.

Fig.1.17 (a): Output waveform for Practical diode Fig.1.17 (b): Output waveform for Ideal diode

Table 1.3: Output voltage levels of negative clamper

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1.2. Transistor Biasing and Stabilization

The biasing of a bipolar junction transistor is to establish the desired value of collector
to emitter voltage VCE and Collector current IC, to ensure that the amplifier will have proper
gain and input impedance with undistorted output voltage swing. The values of VCE and IC
together are known as operating point or quiescent point (Q-point). The operating point
must be stable for proper operation of the transistor. However, the operating point shifts with
changes in transistor parameters such as β (Current Gain), ICO & VBE.

1.2.1. Operating Point

The transistor can be operated in three regions cut-off, active and saturation regions. In
order to operate transistor in the desired region we have to apply external dc voltages of correct
polarity and magnitude to the two junctions of the transistor. This is nothing but the biasing of
the transistor. Let us consider the common emitter configuration of NPN transistor and its
output characteristics as shown in Fig.1.18.

Fig.1.18: Common-Emitter configuration and its output characteristics.

The region in the characteristics above IB = 0 mA and to the right of the few tenths of
volts of VCE is the active region. In this region the collector current increases with increase in
the base current. The base-emitter junction is forward biased and base-collector junction is
reverse biased in this region.

The region where the base-emitter junction is reverse biased below 0.1V for germanium
and below 0V for silicon is the cut-off region. In this region base-emitter junction and base-
collector junction is reverse biased. The emitter current is zero and the transistor is non-
conducting in this region.

The region very close to VCE = 0 where all curves appear to merge and fall rapidly to the
origin is called saturation region. In this region base-emitter and base-collector junctions are
forward biased. The collector current is considerably large and VCE is few tenths of volts.

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The transistor is required to be biased from cut-off to saturation and vice-versa when it is
being used as a switch. It must be biased in the active region when it is being used as an
amplifier. The transistor functions linearly when its operation is restricted to the active region.

There are several circuit configurations through which the transistor current and voltage
can be adjusted in order to fix the operating point. Fixed bias, emitter bias or self-bias and
voltage divider bias are some configurations.

1.2.2. Fixed Bias Configuration:

The fixed bias circuit is shown in Fig.1.19 (a). It is the simplest dc bias configuration.
For the dc analysis we can replace capacitor with an open circuit (since capacitor blocks dc)
because the reactance of capacitor is infinity. The dc equivalent circuit is shown in Fig.1.19 (b).

Fig.1.19 (a): Fixed bias circuit Fig.1.19 (b): DC equivalent circuit of fixed bias

Apply KVL to the base circuit we get;

VCC – IBRB – VBE = 0

----------- (15)

The magnitudes of collector current and base current neglecting ICO are related by,

IC = βIB ---------------- (16)

Where, β = dc current gain of Common Emitter configuration. IB is decided by RB and IC

is decided by β. Thus RC has no role in the value of IC when the transistor is in active region.

Applying KVL to the circuit shown in Fig.1.19 (a) we get;

VCC = ICRC + VCE

VCE = VCC - ICRC ---------- (17)

The transistor circuit operating in saturation region is shown in Fig.1.19 (c). Apply KVL to the
circuit we get;

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VCC - IC(sat)RC - VCE(sat) = 0

--------- (18)

But VCE(sat) ≈ 0

--------------- (19)

Fig.1.19 (c): Transistor operating in Saturation region.

Solved Examples:

1. For the fixed bias circuit shown, assuming VBE = 0.7V and β = 60 find:
a. Quiescent values of base and collector currents.
b. Quiescent value of VCE.
c. Base-ground and collector-ground voltages.
d. Base-collector voltage
e. Quiescent values of IC and VCE for β = 110.

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Solution: Consider the coupling capacitors as open circuit and mention various currents
and voltages in the circuit as shown below.

a. Quiescent values of base current and collector current.

b. Quiescent value of VCE.

c. Base and collector voltages with respect to ground.

d. Base-collector voltage.

e. When β = 110.

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The Q-points are indicated in the dc load line as shown in the figure.

Observe that when β changes from 60 to 110, the Q-point shift from the middle of the
active region to near saturation region. Therefore the fixed bias circuit has very poor stability of
operating point.

2. For the fixed bias circuit shown, find collector current, collector resistance, base
resistance and VCE. Assume β = 80 and VBE = 0.7V

Solution:
Collector current:

Collector resistance:

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Base Resistance:

1.2.3. Emitter Stabilized Bias Configuration

To improve the stability of the biasing circuit over a fixed bias circuit, the emitter
resistance is connected in the biasing circuit. Such biasing circuit is known as emitter bias
circuit. The circuit of emitter bias configuration is shown in Fig.1.20 (a).

Fig.1.20 (a): Emitter Bias Circuit. Fig.1.20 (b): Base-Emitter Circuit.

Circuit Analysis: The base emitter circuit is shown in Fig.1.20 (b). Applying KVL to the base-
emitter circuit we get;

---------------- (20)

Using IC = βIB;

------------------- (21)

------- (22)

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The collector-emitter circuit is shown in Fig.1.20 (c).

Fig.1.20 (c): Collector-Emitter Circuit

Applying KVL to the collector-emitter circuit we get;

---------- (22)

Substituting IE = IC.

------------ (23)

Let,

VC = Voltage from collector to ground

VB =Voltage from base to ground

VE = Voltage from emitter to ground

Therefore, VE = Voltage across RE

----------------- (24)

-------- (25)

From equation 22, Substitute for (VCE+IERE) we get;

--------- (26)

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Saturation Level: When transistor is in saturation

Substituting this condition in equation 22 and taking IE = IC we have;

---------- (27)

Solved Examples:

1. For the emitter-bias shown using silicon transistor with VBE = 0.7 V and β = 60,
find;
a. Base current and collector current
b. Collector-Emitter voltage
c. Collector, emitter and base voltages to ground
d. Base-collector voltage

Solution: For dc analysis the capacitors are acts as open circuit.

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a. Base current and collector current

IC = βIB = 60 * 36.34 = 2.18 mA

b. Collector-emitter voltage

c. Collector, emitter and base voltages to ground

d. Base-collector voltage
VBC = VB – VC
VBC = 2.88 – 15.64 = -12.76 V

2. For the emitter bias circuit shown using silicon transistor VBE = 0.7 V and β = 100.
Find;
a. Quiescent values of base current, collector current and collector to emitter
voltage.
b. Voltage at collector, base and emitter with respect to ground.

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Solution:

IC = βIB = 100 * 29.18 = 2.92 mA

VCE = VCC – IC (RC+RE) = 20 – 2.92m (2.4k+1.5k) = 8.61V

VE = IERE = [IB + IC] RE = [29.18µ+2.92 m] 1.5k = 4.42V

VB = VBE + VE = 0.7 + 4.42 = 5.12V

1.2.4. Voltage Divider Bias Configuration

In the fixed bias and the emitter bias circuits, the collector current and collector-emitter
voltage that is operating point is a function of dc current gain β of the transistor. The current
gain is sensitive to temperature and its value keeps varying. A biasing circuit independent or
less dependent on β such as the voltage divider bias circuit is desirable. The voltage divider
circuit is shown in Fig.1.21 (a).

Fig.1.21 (a): Voltage divider bias circuit

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Exact Analysis: The base circuit is redrawn as shown in Fig.1.21 (b) for the dc analysis. The
Thevenin equivalent circuit is shown in Fig.1.22 (a).

Fig.1.21 (b): Base circuit of Voltage divider bias configuration

Fig.1.22: a. Thevenin Equivalent b. Determination of RTh c. Determination of VTh

To find Thevenin resistance RTh, VCC is reduced to zero in the circuit of Fig.1.22 (a). The
resulting circuit is shown in Fig.1.22 (b).

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From the Fig.1.22 (c), the Thevenin Voltage can be obtained,

The circuit shown in Fig.1.21 (b) can be redrawn as shown in Fig.1.23 after substituting
the Thevenin equivalent between B and N.

Fig.1.23: Base circuit with Thevenin Equivalent

Apply KVL to the base circuit shown in Fig.1.23 we get;

VTh - IBRTh – VBE – IERE = 0

VTh = IBRTh + VBE + IERE ________ (28)

Now, IE = IC + IB ______________ (29)

IC = βIB

Substituting in equation 29 we get

IE = βIB+IB = (1+β)IB ___________ (30)

VTh = IBRTh + VBE + (1+β)IB RE

VTh - VBE = IB[RTh + (1+β) RE]

________ (31)

The collector circuit is shown in Fig.1.24. Apply KVL to the circuit we get;

VCC - ICRC – VCE – IERE = 0

VCC = ICRC + VCE+ IERE

IE = IC

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VCE = VCC – IC(RC + RE) ________ (32)

Voltage across emitter:

VE = IERE _________________ (33)

Collector to ground Voltage:

VC = VCE+IERE = VCE+VE _______ (34)

Base to ground Voltage:

VB = VBE + VE __________ (35)

Fig.1.24: Collector circuit of Voltage Divider Bias Configuration

Transistor Saturation: When transistor is in saturation, VCE = VCE(sat) ≈ 0 and IC = IC(sat). From
equation (32) we get;

VCC = IC(sat)[RC + RE]

______ (36)

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Approximate Analysis:

The resistance RE in the emitter circuit gets reflected as (1+β)RE in the base circuit.
Therefore the circuit between base and ground of Fig.1.21 (b) can be replaced by an equivalent
resistance Ri = (1+β)RE as shown in Fig.1.25.

Fig.1.25: Input circuit of Approximate Analysis

Apply KCL to the above circuit we get;

I1 = I2 + IB

Ri = (1+β) RE ≈ βRE, since β >>1

If Ri = (1+β) RE >> 10 R2, _________ (37)

Then IB << 0.1 * I2, We neglect IB, as a result we get;

I1 ≈ I2

Apply KVL to the above circuit we get;

VCC = I1R1 + I2R2

VCC = I2(R1+R2)

VB = I2*R2

_________ (38)

VB = VBE + VE

VE = VB - VBE

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The emitter current IE is given by;

And IC ≈ IE

From KVL equation of collector-emitter circuit we get;

VCE = VCC – ICRC – IERE

VCE = VCC – IC (RC+RE) ___________ (39)

Solved Examples:

Example 1:

a. Find the quiescent base current, collector current and VCE for the circuit shown
using silicon transistor with VBE = 0.7V and β = 80.
b. Determine the values of collector, emitter and base voltages with respect to ground.
c. Repeat (a) for β = 150.
d. Draw the dc load line and locate the Q-points corresponding to two ‘β’ values.

Solution:

Given Data: VCC = 16V, R1 = 62kΩ, R2 = 9.1k Ω, RC = 3.9k Ω, RE = 680 Ω, C1 = C2 = 10µF,

CE = 50µF, VBE = 0.7V and β = 80.

The dc equivalent circuit is shown below.

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a. Base current, Collector current and Collector-Emitter Voltage.

IC = βIB = 80 * 21.42 = 1.71 mA

VCE = VCC – IC (RC+RE) = 16 – 1.71m (3.9k+680) = 8.17V

b. Collector, emitter and base voltages with respect to ground.

VC = VCC – ICRC = 16 – (1.71m*3.9k) = 9.33 V

VE = IERE ≈ ICRC = (1.71m*3.9k) = 1.16 V

VB = VBE + VE = 0.7 + 1.16 = 1.86V

c. For β = 150: Base current, Collector current and Collector-Emitter Voltage.

IC = βIB = 150 * 12.2 = 1.83 mA

VCE = VCC – IC (RC+RE) = 16 – 1.83m (3.9k+680) = 7.62V

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d. DC load line curve:

DC load line curve

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Example 2:

For the voltage divider bias configuration shown below, Find

a. IC and VCE using exact analysis

b. IC and VCE using approximate analysis
c. IC(sat)
d. Compare the results obtained in (a) and (b) and comment

Assume silicon transistor with β = 150.

Solution:

Given Data: VCC = 20V, R1 = 40kΩ, R2 = 4k Ω, RC = 10k Ω, RE = 1.5k Ω, C1 = C2 = 10µF, CE

= 47µF, VBE = 0.7V and β = 150.

a. Exact Analysis:

IC = βIB = 150 * 4.86 = 0.729 mA

VCE = VCC – IC (RC+RE) = 20 – 0.729m (10k+1.5k) = 11.62V

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b. Approximate Analysis:

βRE = 150*1.5k = 225kΩ

10R2 = 10*4k = 40kΩ

Note that βRE > 10R2, hence we can use approximate analysis.

(Same as VTh)

VE = VB – VBE = 1.82 – 0.7 = 1.12 V

IC ≈ I E

VCE = VCC – IC (RC+RE) = 20 – 0.746m (10k+1.5k) = 11.42V

c.

d. The results of exact and approximate analysis are compared in the following table.

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1.2.5. Transistor Switching Networks and Switching Characteristics

To operate BJT as s switch, it is to be operated in two regions namely, cut-off and

saturation region. In cut-off region both the junctions are reverse biased and only reverse
current flows which is very small and can be neglected. Thus no current flows through transistor
in cut-off region, hence it acts as open switch. (Figure.1.26)

In saturation region both the junctions are forward biased. The voltage VCE drops to very
small value about 0.2V to 0.3V. The collector current is very large and controlled by external
resistance in collector circuit. Thus the transistor acts as a closed switch. (Figure 1.27)

Fig.1.26: Cut-off region (Open switch)

Fig.1.27: Saturation region (Closed switch)

Switching Characteristics:

When the base current is applied, the transistor does not switch on immediately. This is
because of junction capacitance and the transition time of electrons across the junctions. The
time between the application of input pulse and the commencement of current flow is termed as
delay time, Td. The time required for the collector current to reach 90% of its maximum level
from 10% level is called rise time, Tr. The turn-on time is the addition of rise time and delay
time (Ton = Td + Tr).

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When the input current is switched off, the collector current does not go to zero level
immediately. It goes to zero level after turn-off time, which is the sum of storage time Ts, and
fall time Tf. The fall time is specified as the time required for collector current to go from 90%
to 10% of its maximum level. The switching characteristic of transistor is shown in figure
1.28.

Fig.1.28: Transistor switching characteristics

1.2.6. Stability factors

The operating point of the transistor is affected by the parameters reverse leakage
current ICO, current gain β and Base-emitter voltage drop VBE with variation in temperature.
The transistor biasing circuits are to provide stability of collector current against the variations
in ICO, β and VBE. The stability factor indicates the degree of change in operating point due to
variation in temperature.

, β and VBE are constant

, β and ICO are constant

, VBE and ICO are constant

Stability factor (SICO): General expression

For common emitter configuration;

IC = ICEO + β*IB

IC = (1+β)ICBO + β*IB

When ICBO changes by ICBO, IB changes by IB and IC changes by IC we get;

IC = (1+β) ICBO + β* IB

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1 = (1+β) + β*

1 - β* = (1+β)

= [1 - β* / (1+β)

------------- (40)

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