Partitioning

Partitioning
System design

Decomposition of a complex system into smaller subsystems.

Each subsystem can be designed independently speeding up

the design process.

Decomposition scheme has to minimize the interconnections

between the subsystems.

Decomposition is carried out hierarchically until each

subsystem is of managable size.

Module 1 Module 2 Module 3 Module n Interface

Information

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 Partitioning

Partitioning of A Circuit
Input size = 48

(a)
~

(b)

Cut 1 = 4 Cut 2 = 4
Size 1 = 15 Size 2 = 16 Size 3 = 17

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 Partitioning

Partitioning at dierent levels

Partitioning

System Board Chip

Level Level Level

System

Board
System
Level

Chip Board Board Board

Level Level Level

Chip Chip Chip

Level Level Level

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 Partitioning

Hierarchical Partitioning
The levels of partitioning are:
1. System Level Partitioning: A system is partitioned into a set of
subsystems such that each subsystem can be designed and
fabricated independently on a single PCB.

~
2. Board Level Partitioning: The circuit assigned to a PCB is
partitioned into subcircuits such that each subcircuit can be
fabricated as a VLSI chip.
3. Chip Level Partitioning: The circuit assigned to a chip is
partitioned into smaller subcircuits.
Chip level partitioning is physically not necessary.

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System Hierarchy

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Dierent Delays in A Computer System

A
A B
X
10X

C
10X C
B

20X

(b)
(a)

No critical net should cut boundaries if delay is not justified.

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Problem Formulation
1. Interconnections between partitions:
k X
X k
Obj1 :
i=1 j =1
cij ; (i 6= j ) is minimized
2. Delay due to partitioning:
Obj2 : max
p 2P
i
(H (pi)) is minimized
~ 3. Number of terminals:
Cons1 : Count(Vi)  Ti; 1  i  k
where,
cij is the cutsize between partitions Vi and Vj .
H (pi) is the number of times a hyperpath pi is cut.
Count(Vi) is the terminal count for partition Vi.

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Problem Formulation

1. Area of each partition:

i  Area(Vi )  Ai ; i = 1; 2; : : : ; k
Cons2 : Amin
max

~
2. Number of partitions:
Cons3 : Kmin  k  Kmax

The partitioning problem at any level or design style deals with

one or more of the above parameters.

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 Partitioning

Classication of Partitioning Algorithms

Partitioning Algorithms

Group Migration Simulation Based Performance Driven Others

Kerninghan-Lin Simulated Annealing Lawler, Levitt, Turner Metric Allocation

Simulated Evolution
Fiduccia-Mattheyses
Goldberg Burstein
Component Replication
Ratio Cut

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Kernighan-Lin Algorithm

 It is a bisectioning algorithm
 The input graph is partitioned into two subsets of equal sizes.
 Till the cutsize keeps improving,
{ Vertex pairs which give the largest decrease in cutsize
~
are exchanged
{ These vertices are then locked
{ If no improvement is possible and some vertices are still
unlocked, the vertices which give the smallest
increase are exchanged
~ W. Kernighan and S. Lin, Bell System Technical Journal, 1970.

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Kernighan-Lin Algorithm
Algorithm KL
begin
INITIALIZE();
while( IMPROVE(table) = TRUE ) do
(* if an improvement has been made during last iteration,
the process is carried out again. *)
while ( UNLOCK(A) = TRUE ) do
(* if there exists any unlocked vertex in A,
more tentative exchanges are carried out. *)
for ( each a 2 A ) do
if (a = unlocked) then
~
for( each b 2 B ) do
if (b = unlocked) then
if (Dmax < D(a) + D(b)) then
Dmax = D(a) + D(b);
amax = a;
bmax = b;
TENT-EXCHGE(amax; bmax);
LOCK(amax; bmax);
LOG(table);
Dmax = ;1;
ACTUAL-EXCHGE(table);
end.

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A Graph Bisected by K-L Algorithm

1 5 1 8

2 6
2 6 3 7

3 7

4 8 5 4

(a) Initial Bisections (b) Final Bisections

i Vertex Pair g(i) Pi g (i) Cutsize

j =1
0 - - - 9
~
1 (3,5) 3 3 6
2 (4,6) 5 8 1
3 (1,7) -6 2 7
4 (2,8) -2 0 9

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Drawbacks of K-L Algorithm

 K-L algorithm considers balanced partitions only.

 As vertices have unit weights, it is not possible to
~ allocate a vertex to a partition.
 The K-L algorithm considers edges instead of hyperedges.
 High, O(n3) complexity.

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 Partitioning

Fiduccia-Mattheyses Algorithm

This algorithm is a modied version of Kernighan-Lin Algorithm.

 A single vertex is moved across the cut in a single move which
permits handling of unbalanced partitions.
 The concept of cutsize is extended to hypergraphs.
~  Vertices to be moved are selected in a way to improve
time complexity.
 A special data structure is used to do this.
 Overall time complexity of the algorithm is O(n2).
C. M. Fiduccia and R. M. Mattheyses, 19th DAC, 1982.

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Data Structure Used in Fiduccia-Mattheyses Algorithm

+pmax Ist Partition

Vertex # Vertex #

-pmax
Vertex
1 2 ......... n List of free
vertices
+pmax IInd Partition

Vertex # Vertex #

-pmax
Vertex
1 2 ......... n

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 Partitioning

Goldberg and Burstein Algorithm

 Performance of K-L algorithm depends on the ratio R, of edges to vertices
~
 K-L algorithm yield good bisections if R > 5
 In a typical VSLI design problem, 1.8  R  2.5
 Goldberg and Burstein improve K-L algorithm to increase R
 Find a matching M in graph G
 Each edge in the matching is contracted
to increase the density of graph.
~
 Any bisection algorithm is applied
to the modied graph
 Edges are uncontracted within each partition.
~ M. K. Goldberg and M. Burstein, ICCD, 1983.

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Example of Goldberg and Burstein Algorithm

v3 v5

v4 v6 v 3-4 v 5-6

v2 v8
v1 v7 v 1-2 v 7-8

v 12 v 10
v 11-12 v 9-10

v 11 v9
Matching
(a) Matching of Graph (b) After Contracting

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Component Replication to Reduce Cutsize

 Vertices are replicated to improve cutsize

 Good results if limited number of components are replicated
A A
A A

B B
B B

~
(a)
(b)

Fig(a) shows a 4-way partition before component replication with total

cutsize=16
Fig(b) shows the 4-way partition after component replication with total
cutsize=10
~ C. Kring and A. R. Newton, ICCAD, 1991.

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Comparison of Dierent Circuits

Circuit Type Maximum Circuit Net Cutsize Component

Expansion Reduction Replication
~
Combinational 10% 41% 3.2%
30% 43% 3.9%
Industrial 10% 15% 0.7%
30% 9% 0.3%

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Ratio Cut

 Locates natural clusters in the circuit

 Forces partitions to be of equal size
~
 Each edge has a capacity dened for it
 The algorithm tries to minimize the ratio of capacity of
the edge going in between the partitions to the product of number of
nodes in the partitions.
~ Y. Wei and C. Cheng, ICCAD, 1989.

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 Partitioning

Simulated Annealing Algorithm

 Concept analogous to the annealing process

used for metals and glass.
 A random initial partition is available as input.
 A new partitioning is generated by
~
exchanging some elements.
 If the partitions improve the move
is always accepted.
 If not then the move is accepted with a
probability which decreases with
the increase in a parameter called temperature T

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The Annealing curve

Temp

Local Minima’s

Global Minima

Time

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Simulated Annealing Algorithm

Algorithm SA
begin
t = t0;
cur part = ini part;
cur score = SCORE(cur part);
repeat
repeat
comp1 = SELECT(part1);
comp2 = SELECT(part2);
trial part = EXCHANGE(comp1; comp2; cur part);
trial score = SCORE(trial part);
s = trial score ; cur score;
~ if (s < 0) then
cur score = trial score;
cur part = MOVE(comp1; comp2);
else
r = RANDOM(0; 1);
if (r < e; ) then
s
t

cur score = trial score;

cur part = MOVE(comp1; comp2 );
until (equilibrium at t is reached)
t = t (* 0 <  <1 *)
until (freezing point is reached)
end.

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Simulated Evolution Algorithm

 Each feasible solution to the problem is considered as a generation.
 The bad individuals in the population are eliminated to generate a
new generation.
A B C D

~
Ist Generation

AB A’B AB’ A’B’ CD C’D CD’ C’D’

IInd Generation

~ Y. Saab and V. Rao, DAC 1990.

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Simulated Evolution Algorithm

Algorithm SE
begin
S = S0; (* initial state *)
SBEST = S ; (* save initial state *)
p = p0; (* initialize control parameter *)
= 0; (* initialize counter *)
repeat
Cpre = COST(S );
S = PERTURB(S; p);
~
Ccur = COST(S );
UPDATE(p; Cpre; Ccur );
if (COST(S ) < COST(SBEST )) then
SBEST = S ; (* save best state *)
= ; R; (* decrement counter *)
else
= + 1; (* increment counter *)
until ( > R); (* stopping criterion *)
return (SBEST ); (* report best state *)
end.

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PERTURB and UPDATE Procedures

Procedure PERTURB(S )
begin
for( each m 2 M ) do
S 0 = SUB-MOVE(S; m);
Gain(m) = COST(S ) - COST(S 0);
if Gain(m) > RANDOM(p; 0)
S = S 0;
S = MAKE-STATE(S );
return S ;
~
end.
Procedure UPDATE(p; Cpre; Ccur)
begin
if Cpre = Ccur then
p = p ; 1;
else
p = p0;
end.
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METRIC-PARTITION Algorithm
 Input is a set V of the nodes and a set S = S1; S2; :::; SN of the nets.
 A metric value over V  V is computed
 Nodes in V are then partitioned into subsets
 Partitions meet area constraints and
terminal constraints
Algorithm METRIC-PARTITION
~
begin
for(i = 1 to N ) do
CONSTRUCT-ST( Si );
ADD-EDGES( Si; L);
SORT-ASCENDING(L; metric);
no groups = INITIALIZE-GROUPS( V );
while( L 6=  ) do

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METRIC-PARTITION Algorithm
eij = SELECT-EDGE(L);
if( (Gi 6= Gj ) and
(AREA(Gi) + AREA(Gj )  A) and
(COUNT(Gi) + COUNT(Gj )  T ) )
MERGE-GROUPS( Gi, Gj );
no groups = no groups ; 1;
if(no groups  K )
return(G);
else
~
continue;
while( no groups > K ) do
Gi = SELECT SMALL();
for(j = 1 to no groups) do
if( i 6= j ) and
(AREA(Gi) + AREA(Gj )  A) and
(COUNT(Gi) + COUNT(Gj )  T ) )
STORE-MIN( Gj );

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METRIC-PARTITION Algorithm
merge success = TRUE;
MERGE-GROUPS( Gi, RESTORE-MIN(Gj ) );
if( no groups  K )
return( G );
if( merge success = FALSE )
if( SIZE( Gi) = 1 )
~
return(  ); ~

else
Gj = SELECT LARGE();
DECOMPOSE( Gj , Gk , Gl );
end.

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Lawler, Levitt and Turner (LLT) Algorithm

 Performance driven approach.

 Unit delay model is used.
 Circuit is represented by a directed graph.
 Each vertex has a weight indicating area occupied.
 Vertices are labelled as follows:
~ { All input nodes are labelled `0'.
{ A node is given the same label as its predecessor if it
can be accomodated.
 All nodes with same label are grouped in a cluster.
 Minimizes the maximum delay of signal under area constraints.
 Assumption: Delay within a cluster is negligible.
~ E. L. Lawler, K. N. Levitt and J. Turner, IEEE Transactions on Computers, 1969.

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Example of LLT Alogrithm

1 2

0 1
2 1 2 1

0 0 1 2

4 3

1 2

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 Partitioning
Summary
Objectives
Hierarchical Partitions System

Reduction of cutsize
A B C
Balanced Partitions

D E F

System Partitioning Algorithms Interface Information

speed,
performance

Group Migration Simulation

based

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