XC 5200

Product Obsolete or Under Obsolescence
R XC5200 Series
Field Programmable Gate Arrays
November 5, 1998 (Version 5.2) 0 7* Product Specification
Features - Footprint compatibility in common packages within

the XC5200 Series and with the XC4000 Series
• Low-cost, register/latch rich, SRAM based - Over 150 device/package combinations, including
reprogrammable architecture advanced BGA, TQ, and VQ packaging available
- 0.5µm three-layer metal CMOS process technology • Fully Supported by Xilinx Development System
- 256 to 1936 logic cells (3,000 to 23,000 “gates”) - Automatic place and route software
- Price competitive with Gate Arrays - Wide selection of PC and Workstation platforms
• System Level Features - Over 100 3rd-party Alliance interfaces
- System performance beyond 50 MHz - Supported by shrink-wrap Foundation software
- 6 levels of interconnect hierarchy
- VersaRing™ I/O Interface for pin-locking Description
- Dedicated carry logic for high-speed arithmetic
functions The XC5200 Field-Programmable Gate Array Family is
- Cascade chain for wide input functions engineered to deliver low cost. Building on experiences
- Built-in IEEE 1149.1 JTAG boundary scan test gained with three previous successful SRAM FPGA fami-
circuitry on all I/O pins lies, the XC5200 family brings a robust feature set to pro-
- Internal 3-state bussing capability grammable logic design. The VersaBlock™ logic module,
- Four dedicated low-skew clock or signal distribution the VersaRing I/O interface, and a rich hierarchy of inter-
nets connect resources combine to enhance design flexibility
• Versatile I/O and Packaging and reduce time-to-market. Complete support for the
XC5200 family is delivered through the familiar Xilinx soft-
7
- Innovative VersaRing™ I/O interface provides a high
logic cell to I/O ratio, with up to 244 I/O signals ware environment. The XC5200 family is fully supported on
- Programmable output slew-rate control maximizes popular workstation and PC platforms. Popular design
performance and reduces noise entry methods are fully supported, including ABEL, sche-
- Zero Flip-Flop hold time for input registers simplifies matic capture, VHDL, and Verilog HDL synthesis. Design-
system timing ers utilizing logic synthesis can use their existing tools to
- Independent Output Enables for external bussing design with the XC5200 devices.
.
Table 1: XC5200 Field-Programmable Gate Array Family Members
Device XC5202 XC5204 XC5206 XC5210 XC5215
Logic Cells 256 480 784 1,296 1,936
Max Logic Gates 3,000 6,000 10,000 16,000 23,000
Typical Gate Range 2,000 - 3,000 4,000 - 6,000 6,000 - 10,000 10,000 - 16,000 15,000 - 23,000
VersaBlock Array 8x8 10 x 12 14 x 14 18 x 18 22 x 22
CLBs 64 120 196 324 484
Flip-Flops 256 480 784 1,296 1,936
I/Os 84 124 148 196 244
TBUFs per Longline 10 14 16 20 24
November 5, 1998 (Version 5.2) 7-83

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XC5200 Series Field Programmable Gate Arrays
XC5200 Family Compared to Table 2: Xilinx Field-Programmable Gate Array

Families
XC4000/Spartan™ and XC3000
Series Parameter XC5200 Spartan XC4000 XC3000
For readers already familiar with the XC4000/Spartan and CLB function
4 3 3 2
XC3000 FPGA Families, this section describes significant generators
differences between them and the XC5200 family. Unless CLB inputs 20 9 9 5
otherwise indicated, comparisons refer to both
XC4000/Spartan and XC3000 devices. CLB outputs 12 4 4 2
Configurable Logic Block (CLB) Resources Global buffers 4 8 8 2

Each XC5200 CLB contains four independent 4-input func- User RAM no yes yes no
tion generators and four registers, which are configured as
four independent Logic Cells™ (LCs). The registers in each Edge decoders no no yes no
XC5200 LC are optionally configurable as edge-triggered
D-type flip-flops or as transparent level-sensitive latches. Cascade chain yes no no no
The XC5200 CLB includes dedicated carry logic that pro- Fast carry logic yes yes yes no
vides fast arithmetic carry capability. The dedicated carry
logic may also be used to cascade function generators for Internal 3-state yes yes yes yes
implementing wide arithmetic functions.
Boundary scan yes yes yes no
XC4000 family: XC5200 devices have no wide edge
decoders. Wide decoders are implemented using cascade Slew-rate control yes yes yes yes
logic. Although sacrificing speed for some designs, lack of
wide edge decoders reduces the die area and hence cost Routing Resources
of the XC5200.
The XC5200 family provides a flexible coupling of logic and
XC4000/Spartan family: XC5200 dedicated carry logic
local routing resources called the VersaBlock. The XC5200
differs from that of the XC4000/Spartan family in that the
VersaBlock element includes the CLB, a Local Interconnect
sum is generated in an additional function generator in the
Matrix (LIM), and direct connects to neighboring Versa-
adjacent column. This design reduces XC5200 die size and
Blocks.
hence cost for many applications. Note, however, that a
loadable up/down counter requires the same number of The XC5200 provides four global buffers for clocking or
function generators in both families. XC3000 has no dedi- high-fanout control signals. Each buffer may be sourced by
cated carry. means of its dedicated pad or from any internal source.
XC4000/Spartan family: XC5200 lookup tables are opti- Each XC5200 TBUF can drive up to two horizontal and two
mized for cost and hence cannot implement RAM. vertical Longlines. There are no internal pull-ups for
XC5200 Longlines.
Input/Output Block (IOB) Resources
Configuration and Readback
The XC5200 family maintains footprint compatibility with
the XC4000 family, but not with the XC3000 family. The XC5200 supports a new configuration mode called
Express mode.
To minimize cost and maximize the number of I/O per Logic
Cell, the XC5200 I/O does not include flip-flops or latches. XC4000/Spartan family: The XC5200 family provides a
global reset but not a global set.
For high performance paths, the XC5200 family provides
direct connections from each IOB to the registers in the XC5200 devices use a different configuration process than
adjacent CLB in order to emulate IOB registers. that of the XC3000 family, but use the same process as the
XC4000 and Spartan families.
Each XC5200 I/O Pin provides a programmable delay ele-
ment to control input set-up time. This element can be used XC3000 family: Although their configuration processes dif-
to avoid potential hold-time problems. Each XC5200 I/O fer, XC5200 devices may be used in daisy chains with
Pin is capable of 8-mA source and sink currents. XC3000 devices.
IEEE 1149.1-type boundary scan is supported in each XC3000 family: The XC5200 PROGRAM pin is a sin-
XC5200 I/O. gle-function input pin that overrides all other inputs. The
PROGRAM pin does not exist in XC3000.
7-84 November 5, 1998 (Version 5.2)

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XC3000 family: XC5200 devices support an additional pro-

Input/Output Blocks (IOBs)
gramming mode: Peripheral Synchronous.
XC3000 family: The XC5200 family does not support
Power-down, but offers a Global 3-state input that does not
reset any flip-flops. VersaRing
XC3000 family: The XC5200 family does not provide an GRM GRM GRM
on-chip crystal oscillator amplifier, but it does provide an Versa- Versa- Versa-
internal oscillator from which a variety of frequencies up to Block Block Block
12 MHz are available.
VersaRing
VersaRing
GRM GRM GRM
Architectural Overview Versa- Versa- Versa-
Block Block Block
Figure 1 presents a simplified, conceptual overview of the
XC5200 architecture. Similar to conventional FPGAs, the
XC5200 family consists of programmable IOBs, program- GRM GRM GRM
mable logic blocks, and programmable interconnect. Unlike Versa- Versa- Versa-
Block Block Block
other FPGAs, however, the logic and local routing
resources of the XC5200 family are combined in flexible VersaRing
VersaBlocks (Figure 2). General-purpose routing connects
to the VersaBlock through the General Routing Matrix X4955
(GRM).
Figure 1: XC5200 Architectural Overview
VersaBlock: Abundant Local Routing Plus
Versatile Logic
GRM
4 4
The basic logic element in each VersaBlock structure is the
24
Logic Cell, shown in Figure 3. Each LC contains a 4-input 24
7
function generator (F), a storage device (FD), and control TS
CLB
logic. There are five independent inputs and three outputs LC3
to each LC. The independence of the inputs and outputs LC2
4
4 4
allows the software to maximize the resource utilization 4 4
LC1
within each LC. Each Logic Cell also contains a direct
LC0
feedthrough path that does not sacrifice the use of either
the function generator or the register; this feature is a first LIM
for FPGAs. The storage device is configurable as either a D
4 4
flip-flop or a latch. The control logic consists of carry logic
for fast implementation of arithmetic functions, which can Direct Connects X5707
also be configured as a cascade chain allowing decode of

very wide input functions. Figure 2: VersaBlock
CO
DO
DI
D Q
F4
FD
F3
F2 F
F1
X
CI CE CK CLR
X4956
Figure 3: XC5200 Logic Cell (Four LCs per CLB)

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The XC5200 CLB consists of four LCs, as shown in The LIM provides 100% connectivity of the inputs and out-
Figure 4. Each CLB has 20 independent inputs and 12 puts of each LC in a given CLB. The benefit of the LIM is
independent outputs. The top and bottom pairs of LCs can that no general routing resources are required to connect
be configured to implement 5-input functions. The chal- feedback paths within a CLB. The LIM connects to the
lenge of FPGA implementation software has always been GRM via 24 bidirectional nodes.
to maximize the usage of logic resources. The XC5200 The direct connects allow immediate connections to neigh-
family addresses this issue by surrounding each CLB with boring CLBs, once again without using any of the general
two types of local interconnect — the Local Interconnect interconnect. These two layers of local routing resource
Matrix (LIM) and direct connects. These two interconnect
improve the granularity of the architecture, effectively mak-
resources, combined with the CLB, form the VersaBlock,
ing the XC5200 family a “sea of logic cells.” Each
represented in Figure 2. Versa-Block has four 3-state buffers that share a common
enable line and directly drive horizontal and vertical Lon-
CO glines, creating robust on-chip bussing capability. The
LC3
DO VersaBlock allows fast, local implementation of logic func-
DI tions, effectively implementing user designs in a hierarchi-
D Q cal fashion. These resources also minimize local routing
F4 congestion and improve the efficiency of the general inter-
FD
F3 connect, which is used for connecting larger groups of
F2 F logic. It is this combination of both fine-grain and
F1
coarse-grain architecture attributes that maximize logic uti-
X lization in the XC5200 family. This symmetrical structure
takes full advantage of the third metal layer, freeing the
placement software to pack user logic optimally with mini-
LC2 mal routing restrictions.
DO
DI
D Q
VersaRing I/O Interface
F4
FD
The interface between the IOBs and core logic has been
F3 redesigned in the XC5200 family. The IOBs are completely
F2 F decoupled from the core logic. The XC5200 IOBs contain
F1 dedicated boundary-scan logic for added board-level test-
X ability, but do not include input or output registers. This
approach allows a maximum number of IOBs to be placed
around the device, improving the I/O-to-gate ratio and
LC1
DO decreasing the cost per I/O. A “freeway” of interconnect
DI cells surrounding the device forms the VersaRing, which
D Q provides connections from the IOBs to the internal logic.
F4 These incremental routing resources provide abundant
FD
F3 connections from each IOB to the nearest VersaBlock, in
F2 F addition to Longline connections surrounding the device.
F1
The VersaRing eliminates the historic trade-off between
X high logic utilization and pin placement flexibility. These
incremental edge resources give users increased flexibility
in preassigning (i.e., locking) I/O pins before completing
LC0 their logic designs. This ability accelerates time-to-market,
DO
DI since PCBs and other system components can be manu-
D Q factured concurrent with the logic design.
F4
FD General Routing Matrix
F3
F2 F The GRM is functionally similar to the switch matrices
F1
found in other architectures, but it is novel in its tight cou-
X pling to the logic resources contained in the VersaBlocks.
CI CE CK CLR Advanced simulation tools were used during the develop-
ment of the XC5200 architecture to determine the optimal
X4957
level of routing resources required. The XC5200 family
Figure 4: Configurable Logic Block contains six levels of interconnect hierarchy — a series of

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single-length lines, double-length lines, and Longlines all Detailed Functional Description
routed through the GRM. The direct connects, LIM, and
logic-cell feedthrough are contained within each Configurable Logic Blocks (CLBs)
Versa-Block. Throughout the XC5200 interconnect, an effi-
cient multiplexing scheme, in combination with three layer Figure 4 shows the logic in the XC5200 CLB, which con-
metal (TLM), was used to improve the overall efficiency of sists of four Logic Cells (LC[3:0]). Each Logic Cell consists
of an independent 4-input Lookup Table (LUT), and a
silicon usage.
D-Type flip-flop or latch with common clock, clock enable,
Performance Overview and clear, but individually selectable clock polarity. Addi-
tional logic features provided in the CLB are:
The XC5200 family has been benchmarked with many
designs running synchronous clock rates beyond 66 MHz. • An independent 5-input LUT by combining two 4-input
The performance of any design depends on the circuit to be LUTs.
implemented, and the delay through the combinatorial and • High-speed carry propagate logic.
sequential logic elements, plus the delay in the intercon- • High-speed pattern decoding.
nect routing. A rough estimate of timing can be made by • High-speed direct connection to flip-flop D-inputs.
assuming 3-6 ns per logic level, which includes direct-con- • Individual selection of either a transparent,
nect routing delays, depending on speed grade. More level-sensitive latch or a D flip-flop.
accurate estimations can be made using the information in • Four 3-state buffers with a shared Output Enable.
the Switching Characteristic Guideline section.
5-Input Functions
Taking Advantage of Reconfiguration Figure 5 illustrates how the outputs from the LUTs from
FPGA devices can be reconfigured to change logic function LC0 and LC1 can be combined with a 2:1 multiplexer
while resident in the system. This capability gives the sys- (F5_MUX) to provide a 5-input function. The outputs from
tem designer a new degree of freedom not available with the LUTs of LC2 and LC3 can be similarly combined.
any other type of logic.
Hardware can be changed as easily as software. Design 7
CO
updates or modifications are easy, and can be made to
DO
products already in the field. An FPGA can even be recon- DI
D Q
figured dynamically to perform different functions at differ- FD
ent times. I1
F4
F3
I2
I3 F2 F
Reconfigurable logic can be used to implement system I4 F1 X
self-diagnostics, create systems capable of being reconfig- LC1

F5_MUX
ured for different environments or operations, or implement DO
DI out
I5
multi-purpose hardware for a given application. As an
D Q
added benefit, using reconfigurable FPGA devices simpli- Qout
FD
fies hardware design and debugging and shortens product F4
time-to-market. F3
F2 F X
F1
CI CE CK CLR LC0
5-Input Function X5710
Figure 5: Two LUTs in Parallel Combined to Create a

5-input Function

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carry out
CO carry3
A3 DO CO DO
DI DI
or
B3 D Q D Q
F4 CY_MUX FD FD
F4
F3 F3
A3 and B3
F2 XOR F2 XOR
to any two
F1 X half sum3 F1 X sum3
LC3 LC3
A2
DI DO carry2 DO
or DI
B2 D Q D Q
CY_MUX FD FD
F4 F4
F3 F3
A2 and B2
to any two F2 XOR F2 XOR
half sum2 sum2
F1 X F1 X
LC2 LC2
A1 DI DO carry1 DO
or DI
B1 D Q D Q
F4
FD FD
CY_MUX F4
F3 F3
A1 and B1
to any two F2 XOR F2 XOR
half sum1 sum1
F1 X F1 X
LC1 LC1
A0 carry0
DI DO DO
or DI
B0 D Q D Q
CY_MUX FD FD
F4 F4
F3 F3
A0 and B0
to any two F2 XOR F2
half sum0 XOR
F1 X sum0
F1 X
CI CE CK CLR LC0 CI CE CK CLR LC0
carry in
0
CY_MUX
F=0
Initialization of
carry chain (One Logic Cell) X5709
Figure 6: XC5200 CY_MUX Used for Adder Carry Propagate
Carry Function which also generates the half-sum for the four-bit adder. An
adjacent CLB is responsible for XORing the half-sum with
The XC5200 family supports a carry-logic feature that
the corresponding carry-out. Thus an adder or counter
enhances the performance of arithmetic functions such as requires two LCs per bit. Notice that the carry chain
counters, adders, etc. A carry multiplexer (CY_MUX) sym- requires an initialization stage, which the XC5200 family
bol is used to indicate the XC5200 carry logic. This symbol accomplishes using the carry initialize (CY_INIT) macro
represents the dedicated 2:1 multiplexer in each LC that and one additional LC. The carry chain can propagate ver-
performs the one-bit high-speed carry propagate per logic
tically up a column of CLBs.
cell (four bits per CLB).
The XC5200 library contains a set of Relationally-Placed
While the carry propagate is performed inside the LC, an
Macros (RPMs) and arithmetic functions designed to take
adjacent LC must be used to complete the arithmetic func-
advantage of the dedicated carry logic. Using and modify-
tion. Figure 6 represents an example of an adder function. ing these macros makes it much easier to implement cus-
The carry propagate is performed on the CLB shown,

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tomized RPMs, freeing the designer from the need to results or other incoming data in flip-flops, and connect
become an expert on architectures. their outputs to the interconnect network as well. The CLB
storage elements can also be configured as latches.
cascade out
Table 3: CLB Storage Element Functionality
(active rising edge is shown)
CO
DI DO
out
Mode CK CE CLR D Q
D Q Power-Up or
FD
X X X X 0
A15 F4
CY_MUX GR
A14 F3
AND
X X 1 X 0
A13 F2
A12 F1 X Flip-Flop __/ 1* 0* D D
LC3 0 X 0* X Q
DO
DI 1 1* 0* X Q
D Q Latch
0 1* 0* D D
CY_MUX FD
A11 F4 Both X 0 0* X Q
A10 F3
A9 F2 AND Legend:
A8 F1 X X Don’t care
LC2 __/ Rising edge
0* Input is Low or unconnected (default value)
DI DO 1* Input is High or unconnected (default value)
D Q
FD
A7 F4 CY_MUX
A6 F3
Data Inputs and Outputs
A5 F2 AND
A4 F1 X
The source of a storage element data input is programma-
LC1 ble. It is driven by the function F, or by the Direct In (DI)
DO
block input. The flip-flops or latches drive the Q CLB out-
DI
D Q puts. 7
CY_MUX FD Four fast feed-through paths from DI to DO are available,
A3 F4
A2 F3 as shown in Figure 4. This bypass is sometimes used by
A1 F2 AND
A0 F1 X
the automated router to repower internal signals. In addi-
LC0
tion to the storage element (Q) and direct (DO) outputs,
CI CE CK CLR
cascade in there is a combinatorial output (X) that is always sourced
by the Lookup Table.
CY_MUX
F=0 Initialization of The four edge-triggered D-type flip-flops or level-sensitive
carry chain (One Logic Cell) X5708
latches have common clock (CK) and clock enable (CE)
inputs. Any of the clock inputs can also be permanently
Figure 7: XC5200 CY_MUX Used for Decoder Cascade enabled. Storage element functionality is described in
Logic Table 3.
Clock Input
Cascade Function
The flip-flops can be triggered on either the rising or falling
Each CY_MUX can be connected to the CY_MUX in the
clock edge. The clock pin is shared by all four storage ele-
adjacent LC to provide cascadable decode logic. Figure 7
ments with individual polarity control. Any inverter placed
illustrates how the 4-input function generators can be con-
on the clock input is automatically absorbed into the CLB.
figured to take advantage of these four cascaded
CY_MUXes. Note that AND and OR cascading are specific Clock Enable
cases of a general decode. In AND cascading all bits are
The clock enable signal (CE) is active High. The CE pin is
decoded equal to logic one, while in OR cascading all bits
shared by the four storage elements. If left unconnected
are decoded equal to logic zero. The flexibility of the LUT
for any, the clock enable for that storage element defaults
achieves this result. The XC5200 library contains gate
to the active state. CE is not invertible within the CLB.
macros designed to take advantage of this function.
Clear
CLB Flip-Flops and Latches
An asynchronous storage element input (CLR) can be used
The CLB can pass the combinatorial output(s) to the inter- to reset all four flip-flops or latches in the CLB. This input
connect network, but can also store the combinatorial

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can also be independently disabled for any flip-flop. CLR is Three-State Buffers
active High. It is not invertible within the CLB.
The XC5200 family has four dedicated Three-State Buffers
(TBUFs, or BUFTs in the schematic library) per CLB (see
STARTUP
Figure 9). The four buffers are individually configurable
PAD GR Q2 through four configuration bits to operate as simple
GTS Q3 non-inverting buffers or in 3-state mode. When in 3-state
IBUF
Q1Q4 mode the CLB output enable (TS) control signal drives the
CLK DONEIN enable to all four buffers. Each TBUF can drive up to two
horizontal and/or two vertical Longlines. These 3-state buff-
X9009
ers can be used to implement multiplexed or bidirectional
Figure 8: Schematic Symbols for Global Reset buses on the horizontal or vertical longlines, saving logic
resources.
Global Reset
The 3-state buffer enable is an active-High 3-state (i.e. an
A separate Global Reset line clears each storage element active-Low enable), as shown in Table 4.
during power-up, reconfiguration, or when a dedicated
Table 4: Three-State Buffer Functionality
Reset net is driven active. This global net (GR) does not
compete with other routing resources; it uses a dedicated IN T OUT
distribution network. X 1 Z
GR can be driven from any user-programmable pin as a IN 0 IN
global reset input. To use this global net, place an input pad
and input buffer in the schematic or HDL code, driving the Another 3-state buffer with similar access is located near
GR pin of the STARTUP symbol. (See Figure 9.) A specific each I/O block along the right and left edges of the array.
pin location can be assigned to this input using a LOC The longlines driven by the 3-state buffers have a weak
attribute or property, just as with any other user-program- keeper at each end. This circuit prevents undefined float-
mable pad. An inverter can optionally be inserted after the ing levels. However, it is overridden by any driver. To
input buffer to invert the sense of the Global Reset signal. ensure the longline goes high when no buffers are on, add
Alternatively, GR can be driven from any internal node. an additional BUFT to drive the output High during all of the
previously undefined states.
Using FPGA Flip-Flops and Latches
Figure 10 shows how to use the 3-state buffers to imple-
The abundance of flip-flops in the XC5200 Series invites ment a multiplexer. The selection is accomplished by the
pipelined designs. This is a powerful way of increasing per- buffer 3-state signal.
formance by breaking the function into smaller subfunc-
tions and executing them in parallel, passing on the results
through pipeline flip-flops. This method should be seriously TS
considered wherever throughput is more important than
latency.
To include a CLB flip-flop, place the appropriate library
symbol. For example, FDCE is a D-type flip-flop with clock
enable and asynchronous clear. The corresponding latch CLB
CLB
symbol is called LDCE. LC3
In XC5200-Series devices, the flip-flops can be used as LC2

registers or shift registers without blocking the function LC1
generators from performing a different, perhaps unrelated
LC0
task. This ability increases the functional capacity of the
devices.
The CLB setup time is specified between the function gen-
Horizontal
erator inputs and the clock input CK. Therefore, the speci- Longlines
fied CLB flip-flop setup time includes the delay through the
function generator.
X9030
Figure 9: XC5200 3-State Buffers

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Z = DA • A + DB • B + DC • C + DN • N
~100 kΩ
DA DB DC DN
BUFT BUFT BUFT BUFT
A B C N
X6466
"Weak Keeper"
Figure 10: 3-State Buffers Implement a Multiplexer
Input/Output Blocks
User-configurable input/output blocks (IOBs) provide the Table 5: Supported Sources for XC5200-Series Device
interface between external package pins and the internal Inputs
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals. XC5200 Input Mode
5 V, 5 V,
The I/O block, shown in Figure 11, consists of an input Source
TTL CMOS
buffer and an output buffer. The output driver is an 8-mA
Any device, Vcc = 3.3 V,
full-rail CMOS buffer with 3-state control. Two slew-rate √
CMOS outputs Unreliable
control modes are supported to minimize bus transients.
Any device, Vcc = 5 V, Data
Both the output buffer and the 3-state control are invertible. √
The input buffer has globally selected CMOS or TTL input TTL outputs
thresholds. The input buffer is invertible and also provides a Any device, Vcc = 5 V,
√ √
programmable delay line to assure reliable chip-to-chip CMOS outputs
set-up and hold times. Minimum ESD protection is 3 KV
Optional Delay Guarantees Zero Hold Time
using the Human Body Model.
XC5200 devices do not have storage elements in the IOBs.
However, XC5200 IOBs can be efficiently routed to CLB 7
Vcc
flip-flops or latches to store the I/O signals.
Input Delay
Buffer The data input to the register can optionally be delayed by
Pullup
I several nanoseconds. With the delay enabled, the setup
time of the input flip-flop is increased so that normal clock
PAD Output
Buffer routing does not result in a positive hold-time requirement.
Pulldown O A positive hold time requirement can lead to unreliable,
temperature- or processing-dependent operation.
T
The input flip-flop setup time is defined between the data
Slew Rate
X9001
Control measured at the device I/O pin and the clock input at the
CLB (not at the clock pin). Any routing delay from the
device clock pin to the clock input of the CLB must, there-
Figure 11: XC5200 I/O Block fore, be subtracted from this setup time to arrive at the real
setup time requirement relative to the device pins. A short
IOB Input Signals specified setup time might, therefore, result in a negative
The XC5200 inputs can be globally configured for either setup time at the device pins, i.e., a positive hold-time
TTL (1.2V) or CMOS thresholds, using an option in the bit- requirement.
stream generation software. There is a slight hysteresis of When a delay is inserted on the data line, more clock delay
about 300mV. can be tolerated without causing a positive hold-time
The inputs of XC5200-Series 5-Volt devices can be driven requirement. Sufficient delay eliminates the possibility of a
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are data hold-time requirement at the external pin. The maxi-
in TTL mode. mum delay is therefore inserted as the software default.
Supported sources for XC5200-Series device inputs are The XC5200 IOB has a one-tap delay element: either the
shown in Table 5. delay is inserted (default), or it is not. The delay guarantees
a zero hold time with respect to clocks routed through any
of the XC5200 global clock buffers. (See “Global Lines” on
page 96 for a description of the global clock buffers in the
XC5200.) For a shorter input register setup time, with

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non-zero hold, attach a NODELAY attribute or property to For XC5200 devices, maximum total capacitive load for
the flip-flop or input buffer. simultaneous fast mode switching in the same direction is
200 pF for all package pins between each Power/Ground
IOB Output Signals pin pair. For some XC5200 devices, additional internal
Output signals can be optionally inverted within the IOB, Power/Ground pin pairs are connected to special Power
and pass directly to the pad. As with the inputs, a CLB and Ground planes within the packages, to reduce ground
flip-flop or latch can be used to store the output signal. bounce.
An active-High 3-state signal can be used to place the out- For slew-rate limited outputs this total is two times larger for
put buffer in a high-impedance state, implementing 3-state each device type: 400 pF for XC5200 devices. This maxi-
outputs or bidirectional I/O. Under configuration control, mum capacitive load should not be exceeded, as it can
the output (OUT) and output 3-state (T) signals can be result in ground bounce of greater than 1.5 V amplitude and
inverted. The polarity of these signals is independently more than 5 ns duration. This level of ground bounce may
configured for each IOB. cause undesired transient behavior on an output, or in the
internal logic. This restriction is common to all high-speed
The XC5200 devices provide a guaranteed output sink cur-
digital ICs, and is not particular to Xilinx or the XC5200
rent of 8 mA.
Series.
Supported destinations for XC5200-Series device outputs
XC5200-Series devices have a feature called “Soft
are shown in Table 6.(For a detailed discussion of how to
Start-up,” designed to reduce ground bounce when all out-
interface between 5 V and 3.3 V devices, see the 3V Prod-
puts are turned on simultaneously at the end of configura-
ucts section of The Programmable Logic Data Book.)
tion. When the configuration process is finished and the
An output can be configured as open-drain (open-collector) device starts up, the first activation of the outputs is auto-
by placing an OBUFT symbol in a schematic or HDL code, matically slew-rate limited. Immediately following the initial
then tying the 3-state pin (T) to the output signal, and the activation of the I/O, the slew rate of the individual outputs
input pin (I) to Ground. (See Figure 12.) is determined by the individual configuration option for
Table 6: Supported Destinations for XC5200-Series each IOB.
Outputs Global Three-State
XC5200 Output Mode A separate Global 3-State line (not shown in Figure 11)
5 V, forces all FPGA outputs to the high-impedance state,
Destination
CMOS unless boundary scan is enabled and is executing an
XC5200 device, VCC=3.3 V, EXTEST instruction. This global net (GTS) does not com-
√ pete with other routing resources; it uses a dedicated distri-
CMOS-threshold inputs
Any typical device, VCC = 3.3 V, bution network.
some1
CMOS-threshold inputs GTS can be driven from any user-programmable pin as a
Any device, VCC = 5 V, global 3-state input. To use this global net, place an input
√
TTL-threshold inputs pad and input buffer in the schematic or HDL code, driving
Any device, VCC = 5 V, the GTS pin of the STARTUP symbol. A specific pin loca-
√ tion can be assigned to this input using a LOC attribute or
CMOS-threshold inputs
property, just as with any other user-programmable pad. An
1. Only if destination device has 5-V tolerant inputs
inverter can optionally be inserted after the input buffer to
invert the sense of the Global 3-State signal. Using GTS is
similar to Global Reset. See Figure 8 on page 90 for
details. Alternatively, GTS can be driven from any internal
node.
OPAD
OBUFT Other IOB Options
X6702
There are a number of other programmable options in the
Figure 12: Open-Drain Output
XC5200-Series IOB.
Pull-up and Pull-down Resistors

Output Slew Rate
Programmable IOB pull-up and pull-down resistors are
The slew rate of each output buffer is, by default, reduced, useful for tying unused pins to Vcc or Ground to minimize
to minimize power bus transients when switching non-criti- power consumption and reduce noise sensitivity. The con-
cal signals. For critical signals, attach a FAST attribute or figurable pull-up resistor is a p-channel transistor that pulls
property to the output buffer or flip-flop.

R
to Vcc. The configurable pull-down resistor is an n-channel

transistor that pulls to Ground.
The value of these resistors is 20 kΩ − 100 kΩ. This high OSC1
value makes them unsuitable as wired-AND pull-up resis- OSCS
OSC2
tors.
The pull-up resistors for most user-programmable IOBs are
active during the configuration process. See Table 13 on
page 124 for a list of pins with pull-ups active before and OSC1
during configuration. CK_DIV
OSC2
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
5200_14
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resis- Figure 13: XC5200 Oscillator Macros
tor active. Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an external source. To activate the internal VersaBlock Routing
pull-up, attach the PULLUP library component to the net The General Routing Matrix (GRM) connects to the
attached to the pad. To activate the internal pull-down, Versa-Block via 24 bidirectional ports (M0-M23). Excluding
attach the PULLDOWN library component to the net direct connections, global nets, and 3-statable Longlines,
attached to the pad. all VersaBlock inputs and outputs connect to the GRM via
these 24 ports. Four 3-statable unidirectional signals
JTAG Support (TQ0-TQ3) drive out of the VersaBlock directly onto the
Embedded logic attached to the IOBs contains test struc- horizontal and vertical Longlines. Two horizontal global
tures compatible with IEEE Standard 1149.1 for boundary nets and two vertical global nets connect directly to every
scan testing, simplifying board-level testing. More informa- CLB clock pin; they can connect to other CLB inputs via the
tion is provided in “Boundary Scan” on page 98. GRM. Each CLB also has four unidirectional direct con- 7
nects to each of its four neighboring CLBs. These direct
Oscillator connects can also feed directly back to the CLB (see
XC5200 devices include an internal oscillator. This oscilla- Figure 14).
tor is used to clock the power-on time-out, clear configura- In addition, each CLB has 16 direct inputs, four direct con-
tion memory, and source CCLK in Master configuration nections from each of the neighboring CLBs. These direct
modes. The oscillator runs at a nominal 12 MHz frequency connections provide high-speed local routing that
that varies with process, Vcc, and temperature. The output bypasses the GRM.
CCLK frequency is selectable as 1 MHz (default), 6 MHz,
or 12 MHz. Local Interconnect Matrix
The XC5200 oscillator divides the internal 12-MHz clock or The Local Interconnect Matrix (LIM) is built from input and
a user clock. The user then has the choice of dividing by 4, output multiplexers. The 13 CLB outputs (12 LC outputs
16, 64, or 256 for the “OSC1” output and dividing by 2, 8, plus a Vcc/GND signal) connect to the eight VersaBlock
32, 128, 1024, 4096, 16384, or 65536 for the “OSC2” out- outputs via the output multiplexers, which consist of eight
put. The division is specified via a “DIVIDEn_BY=x” fully populated 13-to-1 multiplexers. Of the eight
attribute on the symbol, where n=1 for OSC1, or n=2 for VersaBlock outputs, four signals drive each neighboring
OSC2. These frequencies can vary by as much as -50% or CLB directly, and provide a direct feedback path to the input
+ 50%. multiplexers. The four remaining multiplexer outputs can
drive the GRM through four TBUFs (TQ0-TQ3). All eight
The OSC5 macro is used where an internal oscillator is
multiplexer outputs can connect to the GRM through the
required. The CK_DIV macro is applicable when a user
bidirectional M0-M23 signals. All eight signals also connect
clock input is specified (see Figure 13).
to the input multiplexers and are potential inputs to that
CLB.

R
To GRM
M0-M23
24 8
TS
Global Nets 4
COUT 4 To
Longlines
4 and GRM
North 4 TQ0-TQ3
CLB
South 4
5 3
East 4 LC3
West 4 Input Output
5 3
Multiplexers LC2 VCC /GND Multiplexers
4
Direct to
8 East
5 3
LC1 4
5 3
LC0
Direct North
CLK
4 CE
Feedback
4 CLR CIN
Direct West 4
Direct South X5724
Figure 14: VersaBlock Details

CLB inputs have several possible sources: the 24 signals The direct connects also provide a high-speed path from
from the GRM, 16 direct connections from neighboring the edge CLBs to the VersaRing input/output buffers, and
VersaBlocks, four signals from global, low-skew buffers, thus reduce pin-to-pin set-up time, clock-to-out, and combi-
and the four signals from the CLB output multiplexers. national propagation delay. Direct connects from the input
Unlike the output multiplexers, the input multiplexers are buffers to the CLB DI pin (direct flip-flop input) are only
not fully populated; i.e., only a subset of the available sig- available on the left and right edges of the device. CLB
nals can be connected to a given CLB input. The flexibility look-up table inputs and combinatorial/registered outputs
of LUT input swapping and LUT mapping compensates for have direct connects to input/output buffers on all four
this limitation. For example, if a 2-input NAND gate is sides.
required, it can be mapped into any of the four LUTs, and The direct connects are ideal for developing customized
use any two of the four inputs to the LUT. RPM cells. Using direct connects improves the macro per-
formance, and leaves the other routing channels intact for
Direct Connects
improved routing. Direct connects can also route through a
The unidirectional direct-connect segments are connected CLB using one of the four cell-feedthrough paths.
to the logic input/output pins through the CLB input and out-
put multiplexer arrays, and thus bypass the general routing General Routing Matrix
matrix altogether. These lines increase the routing channel
The General Routing Matrix, shown in Figure 15, provides
utilization, while simultaneously reducing the delay
flexible bidirectional connections to the Local Interconnect
incurred in speed-critical connections.

R
Matrix through a hierarchy of different-length metal seg-

ments in both the horizontal and vertical directions. A pro-
GRM GRM GRM
Versa- Versa- Versa-

Block Block Block
1
GRM GRM GRM

Block Block Block
2
GRM GRM GRM

Block Block Block 3
4
7
Six Levels of Routing Hierarchy GRM 4 4
1 Single-length Lines 24
24
TS
2 Double-length Lines CLB
LC3
4
3 Direct Connects
LC2
4 4
4 4
4 Longlines and Global Lines LC1
6 LC0
5 LIM Local Interconnect Matrix
LIM 5
Logic Cell Feedthrough
6 Path (Contained within each
Logic Cell) 4 4
Direct Connects X4963
Figure 15: XC5200 Interconnect Structure

grammable interconnect point (PIP) establishes an electri- associated routing segments combine to provide a power-
cal connection between two wire segments. The PIP, con- ful interconnect hierarchy:
sisting of a pass transistor switch controlled by a memory
• Forty bidirectional single-length segments per CLB
element, provides bidirectional (in some cases, unidirec- provide ten routing channels to each of the four
tional) connection between two adjoining wires. A collec- neighboring CLBs in four directions.
tion of PIPs inside the General Routing Matrix and in the • Sixteen bidirectional double-length segments per CLB
Local Interconnect Matrix provides connectivity between provide four routing channels to each of four other
various types of metal segments. A hierarchy of PIPs and
(non-neighboring) CLBs in four directions.
• Eight horizontal and eight vertical bidirectional Longline

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segments span the width and height of the chip, carry/cascade logic described above, implementing a wide
respectively. logic function in place of the wired function. In the case of
3-state bus applications, the user must insure that all states
Two low-skew horizontal and vertical unidirectional glo-
of the multiplexing function are defined. This process is as
bal-line segments span each row and column of the chip,
simple as adding an additional TBUF to drive the bus High
respectively.
when the previously undefined states are activated.
Single- and Double-Length Lines
Global Lines
The single- and double-length bidirectional line segments
make up the bulk of the routing channels. The dou- Global buffers in Xilinx FPGAs are special buffers that drive
ble-length lines hop across every other CLB to reduce the a dedicated routing network called Global Lines, as shown
propagation delays in speed-critical nets. Regenerating the in Figure 16. This network is intended for high-fanout
signal strength is recommended after traversing three or clocks or other control signals, to maximize speed and min-
four such segments. Xilinx place-and-route software auto- imize skewing while distributing the signal to many loads.
matically connects buffers in the path of the signal as nec- The XC5200 family has a total of four global buffers (BUFG
essary. Single- and double-length lines cannot drive onto symbol in the library), each with its own dedicated routing
Longlines and global lines; Longlines and global lines can, channel. Two are distributed vertically and two horizontally
however, drive onto single- and double-length lines. As a throughout the FPGA.
general rule, Longline and global-line connections to the
The global lines provide direct input only to the CLB clock
general routing matrix are unidirectional, with the signal
pins. The global lines also connect to the General Routing
direction from these lines toward the routing matrix.
Matrix to provide access from these lines to the function
Longlines generators and other control signals.
Four clock input pads at the corners of the chip, as shown
Longlines are used for high-fan-out signals, 3-state busses,
in Figure 16, provide a high-speed, low-skew clock network
low-skew nets, and faraway destinations. Row and column
to each of the four global-line buffers. In addition to the ded-
splitter PIPs in the middle of the array effectively double the
icated pad, the global lines can be sourced by internal
total number of Longlines by electrically dividing them into
logic. PIPs from several routing channels within the Ver-
two separated half-lines. Longlines are driven by the
saRing can also be configured to drive the global-line buff-
3-state buffers in each CLB, and are driven by similar buff-
ers.
ers at the periphery of the array from the VersaRing I/O
Interface. Details of all the programmable interconnect for a CLB is
shown in Figure 17.
Bus-oriented designs are easily implemented by using Lon-
glines in conjunction with the 3-state buffers in the CLB and
in the VersaRing. Additionally, weak keeper cells at the
periphery retain the last valid logic level on the Longlines
GCK4
when all buffers are in 3-state mode. GCK1
Longlines connect to the single-length or double-length

lines, or to the logic inside the CLB, through the General
Routing Matrix. The only manner in which a Longline can
be driven is through the four 3-state buffers; therefore, a
Longline-to-Longline or single-line-to-Longline connection
through PIPs in the General Routing Matrix is not possible.
Again, as a general rule, long- and global-line connections
to the General Routing Matrix are unidirectional, with the
signal direction from these lines toward the routing matrix.
The XC5200 family has no pull-ups on the ends of the Lon-

glines sourced by TBUFs, unlike the XC4000 Series. Con-
sequently, wired functions (i.e., WAND and WORAND) and GCK2 GCK3
wide multiplexing functions requiring pull-ups for undefined X5704
states (i.e., bus applications) must be implemented in a dif-
ferent way. In the case of the wired functions, the same Figure 16: Global Lines
functionality can be achieved by taking advantage of the

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x9010
LONG
CLB
SINGLE
CARRY
DOUBLE
7
GLOBAL
DIRECT
DIRECT
DIRECT
LONG
GLOBAL
DOUBLE
SINGLE
Figure 17: Detail of Programmable Interconnect Associated with XC5200 Series CLB

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VersaRing Input/Output Interface XC5200 devices support all the mandatory boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
The VersaRing, shown in Figure 18, is positioned between Access Port (TAP) and registers are provided that imple-
the core logic and the pad ring; it has all the routing ment the EXTEST, SAMPLE/PRELOAD, and BYPASS
resources of a VersaBlock without the CLB logic. The Ver- instructions. The TAP can also support two USERCODE
saRing decouples the core logic from the I/O pads. Each instructions. When the boundary scan configuration option
VersaRing Cell provides up to four pad-cell connections on
is selected, three normal user I/O pins become dedicated
one side, and connects directly to the CLB ports on the
inputs for these functions. Another user output pin
other side. becomes the dedicated boundary scan output.
Boundary-scan operation is independent of individual IOB
VersaRing configuration and package type. All IOBs are treated as
independently controlled bidirectional pins, including any
2 unbonded IOBs. Retaining the bidirectional test capability
8
8 8 after configuration provides flexibility for interconnect test-
2 2 ing.
Also, internal signals can be captured during EXTEST by
2 Pad
connecting them to unbonded IOBs, or to the unused out-
Pad
puts in IOBs used as unidirectional input pins. This tech-
GRM 10
Interconnect nique partially compensates for the lack of INTEST
Pad support.
4
VersaBlock 4
Pad
The user can serially load commands and data into these
devices to control the driving of their outputs and to exam-
ine their inputs. This method is an improvement over
8
bed-of-nails testing. It avoids the need to over-drive device
8
outputs, and it reduces the user interface to four pins. An
2
optional fifth pin, a reset for the control logic, is described in
the standard but is not implemented in Xilinx devices.
2 Pad
The dedicated on-chip logic implementing the IEEE 1149.1
GRM 10 Pad functions includes a 16-state machine, an instruction regis-
Interconnect
ter and a number of data registers. The functional details
Pad
4 can be found in the IEEE 1149.1 specification and are also
VersaBlock 4 Pad discussed in the Xilinx application note XAPP 017: “Bound-
2 ary Scan in XC4000 and XC5200 Series devices”
Figure 19 on page 99 is a diagram of the XC5200-Series
8 8
2 boundary scan logic. It includes three bits of Data Register
X5705
per IOB, the IEEE 1149.1 Test Access Port controller, and
the Instruction Register with decodes.
Figure 18: VersaRing I/O Interface The public boundary-scan instructions are always available
prior to configuration. After configuration, the public instruc-
Boundary Scan tions and any USERCODE instructions are only available if
The “bed of nails” has been the traditional method of testing specified in the design. While SAMPLE and BYPASS are
electronic assemblies. This approach has become less available during configuration, it is recommended that
appropriate, due to closer pin spacing and more sophisti- boundary-scan operations not be performed during this
cated assembly methods like surface-mount technology transitory period.
and multi-layer boards. The IEEE boundary scan standard In addition to the test instructions outlined above, the
1149.1 was developed to facilitate board-level testing of boundary-scan circuitry can be used to configure the FPGA
electronic assemblies. Design and test engineers can device, and to read back the configuration data.
imbed a standard test logic structure in their device to
All of the XC4000 boundary-scan modes are supported in
achieve high fault coverage for I/O and internal logic. This
the XC5200 family. Three additional outputs for the User-
structure is easily implemented with a four-pin interface on
Register are provided (Reset, Update, and Shift), repre-
any boundary scan-compatible IC. IEEE 1149.1-compatible
devices may be serial daisy-chained together, connected in
parallel, or a combination of the two.

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senting the decoding of the corresponding state of the

boundary-scan internal state machine.
DATA IN
1 sd
D Q D Q
0
LE
1
IOB.O 0
IOB.T 0
1 sd
D Q D Q 1
0
IOB IOB IOB IOB IOB LE
IOB IOB sd
1
D Q D Q
0
IOB IOB
LE
IOB IOB
1
IOB.I
0
IOB IOB
1 sd
IOB IOB D Q D Q
0
LE
IOB IOB
1
0
IOB IOB IOB.O
BYPASS
REGISTER
M TDO
IOB.T
1
0 7
U sd
INSTRUCTION REGISTER D Q D Q 1
TDI
X 0
LE
M
TDI
U INSTRUCTION REGISTER
TDO X
BYPASS 1 sd
REGISTER D Q D Q
IOB IOB 0
LE
IOB IOB
1
IOB IOB IOB.I
0
IOB IOB 1 sd
D Q D Q
0
IOB IOB
LE
IOB IOB 0
1
IOB IOB IOB.O
DATAOUT UPDATE EXTEST
IOB IOB IOB IOB IOB SHIFT/ CLOCK DATA

CAPTURE REGISTER
X1523_01
Figure 19: XC5200-Series Boundary Scan Logic

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XC5200-Series devices can also be configured through the Bit Sequence

boundary scan logic. See XAPP 017 for more information.
The bit sequence within each IOB is: 3-State, Out, In. The
Data Registers data-register cells for the TAP pins TMS, TCK, and TDI
have an OR-gate that permanently disables the output
The primary data register is the boundary scan register. buffer if boundary-scan operation is selected. Conse-
For each IOB pin in the FPGA, bonded or not, it includes quently, it is impossible for the outputs in IOBs used by TAP
three bits for In, Out and 3-State Control. Non-IOB pins inputs to conflict with TAP operation. TAP data is taken
have appropriate partial bit population for In or Out only. directly from the pin, and cannot be overwritten by injected
PROGRAM, CCLK and DONE are not included in the boundary-scan data.
boundary scan register. Each EXTEST CAPTURE-DR
state captures all In, Out, and 3-State pins. The primary global clock inputs (PGCK1-PGCK4) are
taken directly from the pins, and cannot be overwritten with
The data register also includes the following non-pin bits: boundary-scan data. However, if necessary, it is possible to
TDO.T, and TDO.O, which are always bits 0 and 1 of the drive the clock input from boundary scan. The external
data register, respectively, and BSCANT.UPD, which is clock source is 3-stated, and the clock net is driven with
always the last bit of the data register. These three bound- boundary scan data through the output driver in the
ary scan bits are special-purpose Xilinx test signals. clock-pad IOB. If the clock-pad IOBs are used for non-clock
The other standard data register is the single flip-flop signals, the data may be overwritten normally.
BYPASS register. It synchronizes data being passed Pull-up and pull-down resistors remain active during
through the FPGA to the next downstream boundary scan boundary scan. Before and during configuration, all pins
device. are pulled up. After configuration, the choice of internal
The FPGA provides two additional data registers that can pull-up or pull-down resistor must be taken into account
be specified using the BSCAN macro. The FPGA provides when designing test vectors to detect open-circuit PC
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are traces.
the decodes of two user instructions, USER1 and USER2. From a cavity-up view of the chip (as shown in XDE or
For these instructions, two corresponding pins Epic), starting in the upper right chip corner, the boundary
(BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to scan data-register bits are ordered as shown in Table 8.
be shifted out on TDO. The data register clock The device-specific pinout tables for the XC5200 Series
(BSCAN.DRCK) is available for control of test logic which include the boundary scan locations for each IOB pin.
the user may wish to implement with CLBs. The NAND of
TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE). Table 8: Boundary Scan Bit Sequence
Bit Position I/O Pad Location

Instruction Set
Bit 0 (TDO) Top-edge I/O pads (right to left)
The XC5200-Series boundary scan instruction set also Bit 1 ...
includes instructions to configure the device and read back
... Left-edge I/O pads (top to bottom)
the configuration data. The instruction set is coded as
shown in Table 7. ... Bottom-edge I/O pads (left to right)
... Right-edge I/O pads (bottom to top)
Table 7: Boundary Scan Instructions
Bit N (TDI) BSCANT.UPD
Instruction I2 Test I/O Data
TDO Source BSDL (Boundary Scan Description Language) files for
I1 I0 Selected Source
XC5200-Series devices are available on the Xilinx web site
0 0 0 EXTEST DR DR
in the File Download area.
0 0 1 SAMPLE/PR DR Pin/Logic
ELOAD Including Boundary Scan
0 1 0 USER 1 BSCAN. User Logic
If boundary scan is only to be used during configuration, no
TDO1
special elements need be included in the schematic or HDL
0 1 1 USER 2 BSCAN. User Logic code. In this case, the special boundary scan pins TDI,
TDO2 TMS, TCK and TDO can be used for user functions after
1 0 0 READBACK Readback Pin/Logic configuration.
Data
To indicate that boundary scan remain enabled after config-
1 0 1 CONFIGURE DOUT Disabled
uration, include the BSCAN library symbol and connect pad
1 1 0 Reserved — — symbols to the TDI, TMS, TCK and TDO pins, as shown in
1 1 1 BYPASS Bypass — Figure 20.
Register

R
Typically, a 0.1 µF capacitor connected near the Vcc and

Optional
Ground pins of the package will provide adequate decou-
To User
Logic pling.
IBUF
BSCAN Output buffers capable of driving/sinking the specified 8 mA
RESET loads under specified worst-case conditions may be capa-
UPDATE
ble of driving/sinking up to 10 times as much current under
SHIFT
best case conditions.
TDI TDO
TMS DRCK Noise can be reduced by minimizing external load capaci-

TCK IDLE
To User
tance and reducing simultaneous output transitions in the
From TDO1 SEL1 Logic same direction. It may also be beneficial to locate heavily
User Logic TDO2 SEL2 loaded output buffers near the Ground pads. The I/O Block
X9000
output buffers have a slew-rate limited mode (default)
Figure 20: Boundary Scan Schematic Example which should be used where output rise and fall times are
not speed-critical.
Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
GND
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by Ground and
inadvertently applying boundary scan input patterns to Vcc Ring for
I/O Drivers
these pins. The simplest way to prevent this is to keep
TMS High, and then apply whatever signal is desired to TDI
and TCK.
Avoiding Inadvertent Boundary Scan Vcc Vcc
If TMS or TCK is used as user I/O, care must be taken to

ensure that at least one of these pins is held constant dur- Logic 7
Power Grid
ing configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
GND X5422
To prevent activation of boundary scan during configura-
tion, do either of the following: Figure 21: XC5200-Series Power Distribution
• TMS: Tie High to put the Test Access Port controller

in a benign RESET state Pin Descriptions
• TCK: Tie High or Low—do not toggle this clock input. There are three types of pins in the XC5200-Series
For more information regarding boundary scan, refer to the devices:
Xilinx Application Note XAPP 017, “Boundary Scan in • Permanently dedicated pins
XC4000 and XC5200 Devices.“ • User I/O pins that can have special functions
• Unrestricted user-programmable I/O pins.
Power Distribution
Before and during configuration, all outputs not used for the
Power for the FPGA is distributed through a grid to achieve configuration process are 3-stated and pulled high with a
high noise immunity and isolation between logic and I/O. 20 kΩ - 100 kΩ pull-up resistor.
Inside the FPGA, a dedicated Vcc and Ground ring sur-
After configuration, if an IOB is unused it is configured as
rounding the logic array provides power to the I/O drivers,
an input with a 20 kΩ - 100 kΩ pull-up resistor.
as shown in Figure 21. An independent matrix of Vcc and
Ground lines supplies the interior logic of the device. Device pins for XC5200-Series devices are described in
Table 9. Pin functions during configuration for each of the
This power distribution grid provides a stable supply and
seven configuration modes are summarized in “Pin Func-
ground for all internal logic, providing the external package
power pins are all connected and appropriately decoupled.

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tions During Configuration” on page 124, in the “Configura-

tion Timing” section.
Table 9: Pin Descriptions
I/O I/O
During After
Pin Name Config. Config. Pin Description
Permanently Dedicated Pins
Five or more (depending on package) connections to the nominal +5 V supply voltage.
VCC I IAll must be connected, and each must be decoupled with a 0.01 - 0.1 µF capacitor to
Ground.
Four or more (depending on package type) connections to Ground. All must be con-
GND I I
nected.
During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-
chronous Peripheral mode, but is an input in Slave mode, Synchronous Peripheral
mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and
CCLK I or O I can be selected as the Readback Clock. There is no CCLK High time restriction on
XC5200-Series devices, except during Readback. See “Violating the Maximum High
and Low Time Specification for the Readback Clock” on page 113 for an explanation of
this exception.
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the global logic initialization and the enabling of out-
DONE I/O O puts.
The exact timing, the clock source for the Low-to-High transition, and the optional
pull-up resistor are selected as options in the program that creates the configuration bit-
stream. The resistor is included by default.
PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-
ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
PROGRAM I I
executes a complete clear cycle, before it goes into a WAIT state and releases INIT.
The PROGRAM pin has an optional weak pull-up after configuration.
User I/O Pins That Can Have Special Functions
During Peripheral mode configuration, this pin indicates when it is appropriate to write
another byte of data into the FPGA. The same status is also available on D7 in Asyn-
RDY/BUSY O I/O chronous Peripheral mode, if a read operation is performed when the device is selected.
After configuration, RDY/BUSY is a user-programmable I/O pin.
RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.
During Master Parallel configuration, each change on the A0-A17 outputs is preceded
by a rising edge on RCLK, a redundant output signal. RCLK is useful for clocked
RCLK O I/O
PROMs. It is rarely used during configuration. After configuration, RCLK is a user-pro-
grammable I/O pin.
As Mode inputs, these pins are sampled before the start of configuration to determine
the configuration mode to be used. After configuration, M0, M1, and M2 become us-
er-programmable I/O.
M0, M1, M2 I I/O
During configuration, these pins have weak pull-up resistors. For the most popular con-
figuration mode, Slave Serial, the mode pins can thus be left unconnected. A pull-down
resistor value of 3.3 kΩ is recommended for other modes.
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output, after configuration is completed.
TDO O O This pin can be user output only when called out by special schematic definitions. To
use this pin, place the library component TDO instead of the usual pad symbol. An out-
put buffer must still be used.

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Table 9: Pin Descriptions (Continued)
I/O I/O
During After
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs respectively. They come directly from the pads, bypassing the IOBs. These pins
can also be used as inputs to the CLB logic after configuration is completed.
I/O
TDI, TCK, If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-
I or I
TMS ited once configuration is completed, and these pins become user-programmable I/O.
(JTAG)
In this case, they must be called out by special schematic definitions. To use these pins,
place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-
put or output buffers must still be used.
High During Configuration (HDC) is driven High until the I/O go active. It is available as
HDC O I/O a control output indicating that configuration is not yet completed. After configuration,
HDC is a user-programmable I/O pin.
Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a
LDC O I/O control output indicating that configuration is not yet completed. After configuration,
LDC is a user-programmable I/O pin.
Before and during configuration, INIT is a bidirectional signal. A 1 kΩ - 10 kΩ external
pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low during the power stabilization and
internal clearing of the configuration memory. As an active-Low input, it can be used
INIT I/O I/O
to hold the FPGA in the internal WAIT state before the start of configuration. Master
mode devices stay in a WAIT state an additional 50 to 250 µs after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. After the I/O go active, INIT is a user-programmable I/O pin. 7
Four Global inputs each drive a dedicated internal global net with short delay and min-
imal skew. These internal global nets can also be driven from internal logic. If not used
GCK1 - Weak to drive a global net, any of these pins is a user-programmable I/O pin.
I or I/O
GCK4 Pull-up The GCK1-GCK4 pins provide the shortest path to the four Global Buffers. Any input
pad symbol connected directly to the input of a BUFG symbol is automatically placed on
one of these pins.
These four inputs are used in Asynchronous Peripheral mode. The chip is selected
when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe
(WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low
CS0, CS1, on Read Strobe (RS) changes D7 into a status output — High if Ready, Low if Busy —
I I/O
WS, RS and drives D0 - D6 High.
In Express mode, CS1 is used as a serial-enable signal for daisy-chaining.
WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write
Strobe overrides. After configuration, these are user-programmable I/O pins.
During Master Parallel configuration, these 18 output pins address the configuration
A0 - A17 O I/O
EPROM. After configuration, they are user-programmable I/O pins.
During Master Parallel, Peripheral, and Express configuration, these eight input pins re-
D0 - D7 I I/O
ceive configuration data. After configuration, they are user-programmable I/O pins.
During Slave Serial or Master Serial configuration, DIN is the serial configuration data
DIN I I/O input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is
the D0 input. After configuration, DIN is a user-programmable I/O pin.
During configuration in any mode but Express mode, DOUT is the serial configuration
data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes
on the falling edge of CCLK.
DOUT O I/O In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained
FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.

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Table 9: Pin Descriptions (Continued)
I/O I/O
During After
Unrestricted User-Programmable I/O Pins
These pins can be configured to be input and/or output after configuration is completed.
Weak
I/O I/O Before configuration is completed, these pins have an internal high-value pull-up resis-
Pull-up
tor (20 kΩ - 100 kΩ) that defines the logic level as High.
Configuration M1, and M0 inputs. There are three self-loading Master

modes, two Peripheral modes, and a Serial Slave mode,
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func- Table 10: Configuration Modes
tional operation of the internal blocks and their Mode M2 M1 M0 CCLK Data
interconnections. This is somewhat like loading the com-
Master Serial 0 0 0 output Bit-Serial
mand registers of a programmable peripheral chip.
XC5200-Series devices use several hundred bits of config- Slave Serial 1 1 1 input Bit-Serial
uration data per CLB and its associated interconnects. Master 1 0 0 output Byte-Wide,
Each configuration bit defines the state of a static memory Parallel Up increment
cell that controls either a function look-up table bit, a multi- from 00000
plexer input, or an interconnect pass transistor. The devel- Master 1 1 0 output Byte-Wide,
opment system translates the design into a netlist file. It Parallel Down decrement
automatically partitions, places and routes the logic and from 3FFFF
generates the configuration data in PROM format. Peripheral 0 1 1 input Byte-Wide
Synchronous*
Special Purpose Pins Peripheral 1 0 1 output Byte-Wide
Three configuration mode pins (M2, M1, M0) are sampled Asynchronous
prior to configuration to determine the configuration mode. Express 0 1 0 input Byte-Wide
After configuration, these pins can be used as auxiliary I/O Reserved 0 0 1 — —
connections. The development system does not use these
resources unless they are explicitly specified in the design Note :*Peripheral Synchronous can be considered byte-wide
entry. This is done by placing a special pad symbol called Slave Parallel
MD2, MD1, or MD0 instead of the input or output pad sym- which is used primarily for daisy-chained devices. The sev-
bol. enth mode, called Express mode, is an additional slave
mode that allows high-speed parallel configuration. The
In XC5200-Series devices, the mode pins have weak
coding for mode selection is shown in Table 10.
pull-up resistors during configuration. With all three mode
pins High, Slave Serial mode is selected, which is the most Note that the smallest package, VQ64, only supports the
popular configuration mode. Therefore, for the most com- Master Serial, Slave Serial, and Express modes.A detailed
mon configuration mode, the mode pins can be left uncon- description of each configuration mode, with timing infor-
nected. (Note, however, that the internal pull-up resistor mation, is included later in this data sheet. During configu-
value can be as high as 100 kΩ.) After configuration, these ration, some of the I/O pins are used temporarily for the
pins can individually have weak pull-up or pull-down resis- configuration process. All pins used during configuration
tors, as specified in the design. A pull-down resistor value are shown in Table 13 on page 124.
of 3.3kΩ is recommended.
Master Modes
These pins are located in the lower left chip corner and are
near the readback nets. This location allows convenient The three Master modes use an internal oscillator to gener-
routing if compatibility with the XC2000 and XC3000 family ate a Configuration Clock (CCLK) for driving potential slave
conventions of M0/RT, M1/RD is desired. devices. They also generate address and timing for exter-
nal PROM(s) containing the configuration data.
Configuration Modes Master Parallel (Up or Down) modes generate the CCLK
XC5200 devices have seven configuration modes. These signal and PROM addresses and receive byte parallel
modes are selected by a 3-bit input code applied to the M2, data. The data is internally serialized into the FPGA
data-frame format. The up and down selection generates
starting addresses at either zero or 3FFFF, for compatibility
with different microprocessor addressing conventions. The

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Master Serial mode generates CCLK and receives the con- Multi-Family Daisy Chain
figuration data in serial form from a Xilinx serial-configura- All Xilinx FPGAs of the XC2000, XC3000, XC4000, and
tion PROM.
XC5200 Series use a compatible bitstream format and can,
CCLK speed is selectable as 1 MHz (default), 6 MHz, or 12 therefore, be connected in a daisy chain in an arbitrary
MHz. Configuration always starts at the default slow fre- sequence. There is, however, one limitation. If the chain
quency, then can switch to the higher frequency during the contains XC5200-Series devices, the master normally can-
first frame. Frequency tolerance is -50% to +50%. not be an XC2000 or XC3000 device.
Peripheral Modes The reason for this rule is shown in Figure 25 on page 109.
Since all devices in the chain store the same length count
The two Peripheral modes accept byte-wide data from a value and generate or receive one common sequence of
bus. A RDY/BUSY status is available as a handshake sig- CCLK pulses, they all recognize length-count match on the
nal. In Asynchronous Peripheral mode, the internal oscilla- same CCLK edge, as indicated on the left edge of
tor generates a CCLK burst signal that serializes the Figure 25. The master device then generates additional
byte-wide data. CCLK can also drive slave devices. In the CCLK pulses until it reaches its finish point F. The different
synchronous mode, an externally supplied clock input to families generate or require different numbers of additional
CCLK serializes the data. CCLK pulses until they reach F. Not reaching F means that
Slave Serial Mode the device does not really finish its configuration, although
DONE may have gone High, the outputs became active,
In Slave Serial mode, the FPGA receives serial configura- and the internal reset was released. For the
tion data on the rising edge of CCLK and, after loading its XC5200-Series device, not reaching F means that read-
configuration, passes additional data out, resynchronized back cannot be initiated and most boundary scan instruc-
on the next falling edge of CCLK. tions cannot be used.
Multiple slave devices with identical configurations can be The user has some control over the relative timing of these
wired with parallel DIN inputs. In this way, multiple devices events and can, therefore, make sure that they occur at the
can be configured simultaneously. proper time and the finish point F is reached. Timing is con-
trolled using options in the bitstream generation software. 7
Serial Daisy Chain
XC5200 devices always have the same number of CCLKs
Multiple devices with different configurations can be con-
in the power up delay, independent of the configuration
nected together in a “daisy chain,” and a single combined
mode, unlike the XC3000/XC4000 Series devices. To guar-
bitstream used to configure the chain of slave devices.
antee all devices in a daisy chain have finished the
To configure a daisy chain of devices, wire the CCLK pins power-up delay, tie the INIT pins together, as shown in
of all devices in parallel, as shown in Figure 28 on page Figure 27.
114. Connect the DOUT of each device to the DIN of the
next. The lead or master FPGA and following slaves each XC3000 Master with an XC5200-Series Slave
passes resynchronized configuration data coming from a Some designers want to use an XC3000 lead device in
single source. The header data, including the length count, peripheral mode and have the I/O pins of the
is passed through and is captured by each FPGA when it XC5200-Series devices all available for user I/O. Figure 22
recognizes the 0010 preamble. Following the length-count provides a solution for that case.
data, each FPGA outputs a High on DOUT until it has
This solution requires one CLB, one IOB and pin, and an
received its required number of data frames.
internal oscillator with a frequency of up to 5 MHz as a
After an FPGA has received its configuration data, it clock source. The XC3000 master device must be config-
passes on any additional frame start bits and configuration ured with late Internal Reset, which is the default option.
data on DOUT. When the total number of configuration
One CLB and one IOB in the lead XC3000-family device
clocks applied after memory initialization equals the value
are used to generate the additional CCLK pulse required by
of the 24-bit length count, the FPGAs begin the start-up
the XC5200-Series devices. When the lead device
sequence and become operational together. FPGA I/O are
removes the internal RESET signal, the 2-bit shift register
normally released two CCLK cycles after the last configura-
responds to its clock input and generates an active Low
tion bit is received. Figure 25 on page 109 shows the
output signal for the duration of the subsequent clock
start-up timing for an XC5200-Series device.
period. An external connection between this output and
The daisy-chained bitstream is not simply a concatenation CCLK thus creates the extra CCLK pulse.
of the individual bitstreams. The PROM file formatter must
be used to combine the bitstreams for a daisy-chained con-
figuration.

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Pseudo Daisy Chain

Multiple devices with different configurations can be con-
nected together in a pseudo daisy chain, provided that all of
the devices are in Express mode. A single combined bit-
stream is used to configure the chain of Express mode
devices, but the input data bus must drive D0-D7 of each
device. Tie High the CS1 pin of the first device to be config-
OE/T
Output
Connected
ured, or leave it floating in the XC5200 since it has an inter-
Reset to CCLK nal pull-up. Connect the DOUT pin of each FPGA to the
0 0
1 0 Active Low Output
CS1 pin of the next device in the chain. The D0-D7 inputs
1 1
0 1
Active High Output are wired to each device in parallel. The DONE pins are
0 1 wired together, with one or more internal DONE pull-ups
. etc .
. . X5223 activated. Alternatively, a 4.7 kΩ external resistor can be
Figure 22: CCLK Generation for XC3000 Master used, if desired. (See Figure 37 on page 122.) CCLK pins
Driving an XC5200-Series Slave are tied together.
The requirement that all DONE pins in a daisy chain be
Express Mode wired together applies only to Express mode, and only if all
Express mode is similar to Slave Serial mode, except the devices in the chain are to become active simultaneously.
data is presented in parallel format, and is clocked into the All devices in Express mode are synchronized to the DONE
target device a byte at a time rather than a bit at a time. The pin. User I/O for each device become active after the
data is loaded in parallel into eight different columns: it is DONE pin for that device goes High. (The exact timing is
not internally serialized. Eight bits of configuration data are determined by options to the bitstream generation soft-
loaded with every CCLK cycle, therefore this configuration ware.) Since the DONE pin is open-drain and does not
mode runs at eight times the data rate of the other six drive a High value, tying the DONE pins of all devices
modes. In this mode the XC5200 family is capable of sup- together prevents all devices in the chain from going High
porting a CCLK frequency of 10 MHz, which is equivalent to until the last device in the chain has completed its configu-
an 80 MHz serial rate, because eight bits of configuration ration cycle.
data are being loaded per CCLK cycle. An XC5210 in the The status pin DOUT is pulled LOW two internal-oscillator
Express mode, for instance, can be configured in about 2 cycles (nominally 1 MHz) after INIT is recognized as High,
ms. The Express mode does not support CRC error check- and remains Low until the device’s configuration memory is
ing, but does support constant-field error checking. A full. Then DOUT is pulled High to signal the next device in
length count is not used in Express mode. the chain to accept the configuration data on the D7-D0
In the Express configuration mode, an external signal bus. All devices receive and recognize the six bytes of pre-
drives the CCLK input(s). The first byte of parallel configu- amble and length count, irrespective of the level on CS1;
ration data must be available at the D inputs of the FPGA but subsequent frame data is accepted only when CS1 is
devices a short set-up time before the second rising CCLK High and the device’s configuration memory is not already
edge. Subsequent data bytes are clocked in on each con- full.
secutive rising CCLK edge. See Figure 38 on page 123.
Setting CCLK Frequency
Bitstream generation currently generates a bitstream suffi-
For Master modes, CCLK can be generated in one of three
cient to program in all configuration modes except Express.
frequencies. In the default slow mode, the frequency is
Extra CCLK cycles are necessary to complete the configu-
nominally 1 MHz. In fast CCLK mode, the frequency is
ration, since in this mode data is read at a rate of eight bits
nominally 12 MHz. In medium CCLK mode, the frequency
per CCLK cycle instead of one bit per cycle. Normally the
is nominally 6 MHz. The frequency range is -50% to +50%.
entire start-up sequence requires a number of bits that is
The frequency is selected by an option when running the
equal to the number of CCLK cycles needed. An additional
bitstream generation software. If an XC5200-Series Master
five CCLKs (equivalent to 40 extra bits) will guarantee com-
is driving an XC3000- or XC2000-family slave, slow CCLK
pletion of configuration, regardless of the start-up options
mode must be used. Slow mode is the default.
chosen.
Table 11: XC5200 Bitstream Format
Multiple slave devices with identical configurations can be
wired with parallel D0-D7 inputs. In this way, multiple Data Type Value Occurrences
devices can be configured simultaneously.
Fill Byte 11111111 Once per bit-
Preamble 11110010 stream
Length Counter COUNT(23:0)
Fill Byte 11111111

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Table 11: XC5200 Bitstream Format CCLK and address signals continue to operate externally.
The user must detect INIT and initialize a new configuration
Data Type Value Occurrences by pulsing the PROGRAM pin Low or cycling Vcc.
Start Byte 11111110 Once per data
Data Frame * DATA(N-1:0) frame
Cyclic Redundancy Check or CRC(3:0) or Table 12: Internal Configuration Data Structure
Constant Field Check 0110
Fill Nibble 1111 PROM Xilinx
VersaBlock
Extend Write Cycle FFFFFF Device Size Serial PROM
Array
Postamble 11111110 Once per de- (bits) Needed
Fill Bytes (30) FFFF…FF vice
XC5202 8x8 42,416 XC1765E
Start-Up Byte FF Once per bit- XC5204 10 x 12 70,704 XC17128E
stream
XC5206 14 x 14 106,288 XC17128E
*Bits per Frame (N) depends on device size, as described for
table 11. XC5210 18 x 18 165,488 XC17256E
XC5215 22 x 22 237,744 XC17256E
Data Stream Format Bits per Frame = (34 x number of Rows) + 28 for the top + 28 for
the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 fill
The data stream (“bitstream”) format is identical for all con-
bits * + 24 extended write bits
figuration modes, with the exception of Express mode. In = (34 x number of Rows) + 100
Express mode, the device becomes active when DONE * In the XC5202 (8 x 8), there are 8 fill bits per frame, not 4
goes High, therefore no length count is required. Addition- Number of Frames = (12 x number of Columns) + 7 for the left
ally, CRC error checking is not supported in Express mode. edge + 8 for the right edge + 1 splitter bit
= (12 x number of Columns) + 16
The data stream formats are shown in Table 11. Express Program Data = (Bits per Frame x Number of Frames) + 48
mode data is shown with D0 at the left and D7 at the right. header bits + 8 postamble bits + 240 fill bits + 8 start-up bits
For all other modes, bit-serial data is read from left to right, = (Bits per Frame x Number of Frames) + 304
and byte-parallel data is effectively assembled from this PROM Size = Program Data
serial bitstream, with the first bit in each byte assigned to 7
D0. Cyclic Redundancy Check (CRC) for
The configuration data stream begins with a string of eight
Configuration and Readback
ones, a preamble code, followed by a 24-bit length count The Cyclic Redundancy Check is a method of error detec-
and a separator field of ones (or 24 fill bits, in Express tion in data transmission applications. Generally, the trans-
mode). This header is followed by the actual configuration mitting system performs a calculation on the serial
data in frames. The length and number of frames depends bitstream. The result of this calculation is tagged onto the
on the device type (see Table 12). Each frame begins with data stream as additional check bits. The receiving system
a start field and ends with an error check. In all modes performs an identical calculation on the bitstream and com-
except Express mode, a postamble code is required to sig- pares the result with the received checksum.
nal the end of data for a single device. In all cases, addi-
Each data frame of the configuration bitstream has four
tional start-up bytes of data are required to provide four
error bits at the end, as shown in Table 11. If a frame data
clocks for the startup sequence at the end of configuration.
error is detected during the loading of the FPGA, the con-
Long daisy chains require additional startup bytes to shift
figuration process with a potentially corrupted bitstream is
the last data through the chain. All startup bytes are
terminated. The FPGA pulls the INIT pin Low and goes into
don’t-cares; these bytes are not included in bitstreams cre-
a Wait state.
ated by the Xilinx software.
During Readback, 11 bits of the 16-bit checksum are added
In Express mode, only non-CRC error checking is sup-
to the end of the Readback data stream. The checksum is
ported. In all other modes, a selection of CRC or non-CRC
computed using the CRC-16 CCITT polynomial, as shown
error checking is allowed by the bitstream generation soft-
in Figure 23. The checksum consists of the 11 most signifi-
ware. The non-CRC error checking tests for a designated
cant bits of the 16-bit code. A change in the checksum indi-
end-of-frame field for each frame. For CRC error checking,
cates a change in the Readback bitstream. A comparison
the software calculates a running CRC and inserts a unique
to a previous checksum is meaningful only if the readback
four-bit partial check at the end of each frame. The 11-bit
data is independent of the current device state. CLB out-
CRC check of the last frame of an FPGA includes the last
puts should not be included (Read Capture option not
seven data bits.
used). Statistically, one error out of 2048 might go undetec-
Detection of an error results in the suspension of data load- ted.
ing and the pulling down of the INIT pin. In Master modes,

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Initialization
X2 X15
X16 This phase clears the configuration memory and estab-
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lishes the configuration mode.
SERIAL DATA IN The configuration memory is cleared at the rate of one

Polynomial: X16 + X15 + X2 + 1
frame per internal clock cycle (nominally 1 MHz). An
open-drain bidirectional signal, INIT, is released when the
configuration memory is completely cleared. The device
1 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5
then tests for the absence of an external active-low level on
START BIT
LAST DATA FRAME CRC – CHECKSUM

INIT. The mode lines are sampled two internal clock cycles
later (nominally 2 µs).
X1789
Readback Data Stream
The master device waits an additional 32 µs to 256 µs
Figure 23: Circuit for Generating CRC-16
(nominally 64-128 µs) to provide adequate time for all of the
slave devices to recognize the release of INIT as well. Then
Configuration Sequence the master device enters the Configuration phase.
There are four major steps in the XC5200-Series power-up

configuration sequence. Boundary Scan VCC No
Instructions 3V
Available:
• Power-On Time-Out Yes
• Initialization
Generate
• Configuration One Time-Out Pulse PROGRAM
of 4 ms = Low
• Start-Up Yes
EXTEST*
The full process is illustrated in Figure 24. SAMPLE/PRELOAD*
Completely Clear
BYPASS Configuration ~1.3 µs per Frame
CONFIGURE* Memory
Power-On Time-Out (*only when PROGRAM = High)
An internal power-on reset circuit is triggered when power INIT

High? if
No
is applied. When VCC reaches the voltage at which portions Master

Yes
of the FPGA begin to operate (i.e., performs a
LDC Output = L, HDC Output = H

Sample
write-and-read test of a sample pair of configuration mem- Mode Lines
ory bits), the programmable I/O buffers are 3-stated with Master CCLK
Goes Active after
active high-impedance pull-up resistors. A time-out delay 50 to 250 µs
Load One
— nominally 4 ms — is initiated to allow the power-supply Configuration
Data Frame
voltage to stabilize. For correct operation the power supply
must reach VCC(min) by the end of the time-out, and must Frame Yes Pull INIT Low
not dip below it thereafter. Error and Stop
No
There is no distinction between master and slave modes SAMPLE/PRELOAD Config-
uration No
BYPASS
with regard to the time-out delay. Instead, the INIT line is memory
Full
used to ensure that all daisy-chained devices have com- Yes
pleted initialization. Since XC2000 devices do not have this Pass

Configuration
signal, extra care must be taken to guarantee proper oper- Data to DOUT
ation when daisy-chaining them with XC5200 devices. For

proper operation with XC3000 devices, the RESET signal, CCLK
Count Equals No
Length
which is used in XC3000 to delay configuration, should be Count
Yes
connected to INIT.
Start-Up
If the time-out delay is insufficient, configuration should be Sequence
F
delayed by holding the INIT pin Low until the power supply
I/O Active
Operational
EXTEST
has reached operating levels. SAMPLE PRELOAD
BYPASS
If Boundary Scan
This delay is applied only on power-up. It is not applied USER 1
is Selected
USER 2
when reconfiguring an FPGA by pulsing the PROGRAM CONFIGURE X9017
READBACK
pin Low. During all three phases — Power-on, Initialization,
and Configuration — DONE is held Low; HDC, LDC, and Figure 24: Configuration Sequence
INIT are active; DOUT is driven; and all I/O buffers are dis-
abled.

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Length Count Match

CCLK Period
CCLK
F
DONE
I/O
XC2000
Global Reset
F = Finished, no more
F
configuration clocks needed
DONE Daisy-chain lead device
XC3000 must have latest F
I/O
Heavy lines describe
default timing
Global Reset
F
DONE
C1 C2 C3 C4
XC4000E/EX I/O
XC5200/ C2 C3 C4
CCLK_NOSYNC
GSR Active
C2 C3 C4
DONE IN 7
F
DONE
C1, C2 or C3
XC4000E/EX I/O
XC5200/
Di Di+1
CCLK_SYNC
GSR Active
Di Di+1
F
DONE
C1 U2 U3 U4
I/O
XC4000E/EX
XC5200/ U2 U3 U4
UCLK_NOSYNC
GSR Active
U2 U3 U4
DONE IN
F
DONE
C1 U2
I/O
XC4000E/EX
XC5200/ Di Di+1 Di+2
UCLK_SYNC
GSR Active
Di Di+1 Di+2
Synchronization
Uncertainty UCLK Period
X6700
Figure 25: Start-up Timing

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Configuration Start-Up
The length counter begins counting immediately upon entry Start-up is the transition from the configuration process to
into the configuration state. In slave-mode operation it is the intended user operation. This transition involves a
important to wait at least two cycles of the internal 1-MHz change from one clock source to another, and a change
clock oscillator after INIT is recognized before toggling from interfacing parallel or serial configuration data where
CCLK and feeding the serial bitstream. Configuration will most outputs are 3-stated, to normal operation with I/O pins
not begin until the internal configuration logic reset is active in the user-system. Start-up must make sure that
released, which happens two cycles after INIT goes High. the user-logic ‘wakes up’ gracefully, that the outputs
A master device’s configuration is delayed from 32 to 256 become active without causing contention with the configu-
µs to ensure proper operation with any slave devices driven ration signals, and that the internal flip-flops are released
by the master device. from the global Reset at the right time.
The 0010 preamble code, included for all modes except Figure 25 describes start-up timing for the three Xilinx fam-
Express mode, indicates that the following 24 bits repre- ilies in detail. Express mode configuration always uses
sent the length count. The length count is the total number either CCLK_SYNC or UCLK_SYNC timing, the other con-
of configuration clocks needed to load the complete config- figuration modes can use any of the four timing sequences.
uration data. (Four additional configuration clocks are To access the internal start-up signals, place the STARTUP
required to complete the configuration process, as dis- library symbol.
cussed below.) After the preamble and the length count
have been passed through to all devices in the daisy chain, Start-up Timing
DOUT is held High to prevent frame start bits from reaching
Different FPGA families have different start-up sequences.
any daisy-chained devices. In Express mode, the length
count bits are ignored, and DOUT is held Low, to disable The XC2000 family goes through a fixed sequence. DONE
the next device in the pseudo daisy chain. goes High and the internal global Reset is de-activated one
CCLK period after the I/O become active.
A specific configuration bit, early in the first frame of a mas-
ter device, controls the configuration-clock rate and can The XC3000A family offers some flexibility. DONE can be
increase it by a factor of eight. Therefore, if a fast configu- programmed to go High one CCLK period before or after
ration clock is selected by the bitstream, the slower clock the I/O become active. Independent of DONE, the internal
rate is used until this configuration bit is detected. global Reset is de-activated one CCLK period before or
after the I/O become active.
Each frame has a start field followed by the frame-configu-
ration data bits and a frame error field. If a frame data error The XC4000/XC5200 Series offers additional flexibility.
is detected, the FPGA halts loading, and signals the error The three events — DONE going High, the internal Reset
by pulling the open-drain INIT pin Low. After all configura- being de-activated, and the user I/O going active — can all
tion frames have been loaded into an FPGA, DOUT again occur in any arbitrary sequence. Each of them can occur
follows the input data so that the remaining data is passed one CCLK period before or after, or simultaneous with, any
on to the next device. In Express mode, when the first of the others. This relative timing is selected by means of
device is fully programmed, DOUT goes High to enable the software options in the bitstream generation software.
next device in the chain. The default option, and the most practical one, is for DONE
to go High first, disconnecting the configuration data source
Delaying Configuration After Power-Up
and avoiding any contention when the I/Os become active
To delay master mode configuration after power-up, pull one clock later. Reset is then released another clock period
the bidirectional INIT pin Low, using an open-collector later to make sure that user-operation starts from stable
(open-drain) driver. (See Figure 12.) internal conditions. This is the most common sequence,
Using an open-collector or open-drain driver to hold INIT shown with heavy lines in Figure 25, but the designer can
Low before the beginning of master mode configuration modify it to meet particular requirements.
causes the FPGA to wait after completing the configuration Normally, the start-up sequence is controlled by the internal
memory clear operation. When INIT is no longer held Low device oscillator output (CCLK), which is asynchronous to
externally, the device determines its configuration mode by the system clock.
capturing its mode pins, and is ready to start the configura-
XC4000/XC5200 Series offers another start-up clocking
tion process. A master device waits up to an additional 250
option, UCLK_NOSYNC. The three events described
µs to make sure that any slaves in the optional daisy chain
above need not be triggered by CCLK. They can, as a con-
have seen that INIT is High.
figuration option, be triggered by a user clock. This means
that the device can wake up in synchronism with the user
system.

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When the UCLK_SYNC option is enabled, the user can ship between CCLK and the user clock. This arbitration
externally hold the open-drain DONE output Low, and thus causes an unavoidable one-cycle uncertainty in the timing
stall all further progress in the start-up sequence until of the rest of the start-up sequence.
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a com- DONE Goes High to Signal End of Configuration
mon user clock, or to guarantee that all devices are suc- In all configuration modes except Express mode,
cessfully configured before any I/Os go active. XC5200-Series devices read the expected length count
If either of these two options is selected, and no user clock from the bitstream and store it in an internal register. The
is specified in the design or attached to the device, the chip length count varies according to the number of devices and
could reach a point where the configuration of the device is the composition of the daisy chain. Each device also
complete and the Done pin is asserted, but the outputs do counts the number of CCLKs during configuration.
not become active. The solution is either to recreate the Two conditions have to be met in order for the DONE pin to
bitstream specifying the start-up clock as CCLK, or to sup- go high:
ply the appropriate user clock.
• the chip's internal memory must be full, and
Start-up Sequence • the configuration length count must be met, exactly.
The Start-up sequence begins when the configuration This is important because the counter that determines
memory is full, and the total number of configuration clocks when the length count is met begins with the very first
received since INIT went High equals the loaded value of CCLK, not the first one after the preamble.
the length count. Therefore, if a stray bit is inserted before the preamble, or
The next rising clock edge sets a flip-flop Q0, shown in the data source is not ready at the time of the first CCLK,
Figure 26. Q0 is the leading bit of a 5-bit shift register. The the internal counter that holds the number of CCLKs will be
outputs of this register can be programmed to control three one ahead of the actual number of data bits read. At the
events. end of configuration, the configuration memory will be full,
but the number of bits in the internal counter will not match
• The release of the open-drain DONE output
the expected length count. 7
• The change of configuration-related pins to the user
function, activating all IOBs. As a consequence, a Master mode device will continue to
• The termination of the global Set/Reset initialization of send out CCLKs until the internal counter turns over to
all CLB and IOB storage elements. zero, and then reaches the correct length count a second
time. This will take several seconds [224 ∗ CCLK period]
The DONE pin can also be wire-ANDed with DONE pins of
— which is sometimes interpreted as the device not config-
other FPGAs or with other external signals, and can then
uring at all.
be used as input to bit Q3 of the start-up register. This is
called “Start-up Timing Synchronous to Done In” and is If it is not possible to have the data ready at the time of the
selected by either CCLK_SYNC or UCLK_SYNC. first CCLK, the problem can be avoided by increasing the
number in the length count by the appropriate value.
When DONE is not used as an input, the operation is called
“Start-up Timing Not Synchronous to DONE In,” and is In Express mode, there is no length count. The DONE pin
selected by either CCLK_NOSYNC or UCLK_NOSYNC. for each device goes High when the device has received its
quota of configuration data. Wiring the DONE pins of sev-
As a configuration option, the start-up control register
eral devices together delays start-up of all devices until all
beyond Q0 can be clocked either by subsequent CCLK
are fully configured.
pulses or from an on-chip user net called STARTUP.CLK.
These signals can be accessed by placing the STARTUP Note that DONE is an open-drain output and does not go
library symbol. High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
Start-up from CCLK default by the bitstream generation software.
If CCLK is used to drive the start-up, Q0 through Q3 pro- Release of User I/O After DONE Goes High
vide the timing. Heavy lines in Figure 25 show the default
timing, which is compatible with XC2000 and XC3000 By default, the user I/O are released one CCLK cycle after
devices using early DONE and late Reset. The thin lines the DONE pin goes High. If CCLK is not clocked after
indicate all other possible timing options. DONE goes High, the outputs remain in their initial state —
3-stated, with a 20 kΩ - 100 kΩ pull-up. The delay from
Start-up from a User Clock (STARTUP.CLK)
When, instead of CCLK, a user-supplied start-up clock is
selected, Q1 is used to bridge the unknown phase relation-

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DONE High to active user I/O is controlled by an option to

the bitstream generation software.
Q3 Q1/Q4
STARTUP DONE
Q2
IN
* IOBs OPERATIONAL PER CONFIGURATION
* GLOBAL RESET OF
ALL CLB FLIP-FLOPS/LATCHES
1
0
GR ENABLE
GR INVERT
STARTUP.GR CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
STARTUP.GTS LIBRARIES GUIDE)
GTS INVERT
GTS ENABLE
0
GLOBAL 3-STATE OF ALL IOBs
1
Q S
* DONE
" FINISHED "

1 1 ENABLES BOUNDARY
0 0 SCAN, READBACK AND
CONTROLS THE OSCILLATOR
Q0 Q1 Q2 Q3 Q4
FULL 1
S Q D Q D Q D Q D Q
LENGTH COUNT 0
K K K * K K
CLEAR MEMORY
CCLK 0
STARTUP.CLK 1
USER NET
M
CONFIGURATION BIT OPTIONS SELECTED BY USER
* * X9002
Figure 26: Start-up Logic
Release of Global Reset After DONE Goes High Configuration Through the Boundary Scan
By default, Global Reset (GR) is released two CCLK cycles Pins
after the DONE pin goes High. If CCLK is not clocked twice XC5200-Series devices can be configured through the
after DONE goes High, all flip-flops are held in their initial boundary scan pins.
reset state. The delay from DONE High to GR inactive is
controlled by an option to the bitstream generation soft- For detailed information, refer to the Xilinx application note
ware. XAPP017, “Boundary Scan in XC4000 and XC5200
Devices.”
Configuration Complete After DONE Goes High
Readback
Three full CCLK cycles are required after the DONE pin
goes High, as shown in Figure 25 on page 109. If CCLK is The user can read back the content of configuration mem-
not clocked three times after DONE goes High, readback ory and the level of certain internal nodes without interfer-
cannot be initiated and most boundary scan instructions ing with the normal operation of the device.
cannot be used. Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs.

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Note that in XC5200-Series devices, configuration data is The readback signals are located in the lower-left corner of
not inverted with respect to configuration as it is in XC2000 the device.
and XC3000 families.
Read Abort
Readback of Express mode bitstreams results in data that
does not resemble the original bitstream, because the bit- When the Read Abort option is selected, a High-to-Low
stream format differs from other modes. transition on RDBK.TRIG terminates the readback opera-
tion and prepares the logic to accept another trigger.
XC5200-Series Readback does not use any dedicated
pins, but uses four internal nets (RDBK.TRIG, After an aborted readback, additional clocks (up to one
RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be readback clock per configuration frame) may be required to
routed to any IOB. To access the internal Readback sig- re-initialize the control logic. The status of readback is indi-
nals, place the READBACK library symbol and attach the cated by the output control net RDBK.RIP. RDBK.RIP is
appropriate pad symbols, as shown in Figure 27. High whenever a readback is in progress.
After Readback has been initiated by a Low-to-High transi- Clock Select

tion on RDBK.TRIG, the RDBK.RIP (Read In Progress)
CCLK is the default clock. However, the user can insert
output goes High on the next rising edge of RDBK.CLK.
another clock on RDBK.CLK. Readback control and data
Subsequent rising edges of this clock shift out Readback
are clocked on rising edges of RDBK.CLK. If readback
data on the RDBK.DATA net.
must be inhibited for security reasons, the readback control
Readback data does not include the preamble, but starts nets are simply not connected.
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first Violating the Maximum High and Low Time
frame are always High. Specification for the Readback Clock
Each frame ends with four error check bits. They are read The readback clock has a maximum High and Low time
back as High. The last seven bits of the last frame are also specification. In some cases, this specification cannot be
read back as High. An additional Start bit (Low) and an met. For example, if a processor is controlling readback,
11-bit Cyclic Redundancy Check (CRC) signature follow, an interrupt may force it to stop in the middle of a readback. 7
before RDBK.RIP returns Low. This necessitates stopping the clock, and thus violating the
IF UNCONNECTED,
specification.
DEFAULT IS CCLK
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mech-
anism will load the data to a shift register during the last six
CLK DATA READ_DATA
MD1
READBACK
clock cycles of the frame, prior to the start bit of the follow-
OBUF
READ_TRIGGER TRIG RIP ing frame. This loading process is dynamic, and is the
MD0
IBUF X1786
source of the maximum High and Low time requirements.
Figure 27: Readback Schematic Example
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
Readback Options
clocks before the first start bit in the readback data stream.
Readback options are: Read Capture, Read Abort, and At other times, the frame data is already in the register and
Clock Select. They are set with the bitstream generation the register is not dynamic. Thus, it can be shifted out just
software. like a regular shift register.
Read Capture The user must precisely calculate the location of the read-
back data relative to the frame. The system must keep
When the Read Capture option is selected, the readback
track of the position within a data frame, and disable inter-
data stream includes sampled values of CLB and IOB sig-
rupts before frame boundaries. Frame lengths and data for-
nals. The rising edge of RDBK.TRIG latches the inverted
mats are listed in Table 11 and Table 12.
values of the CLB outputs and the IOB output and input sig-
nals. Note that while the bits describing configuration Readback with the XChecker Cable
(interconnect and function generators) are not inverted, the
CLB and IOB output signals are inverted. The XChecker Universal Download/Readback Cable and
Logic Probe uses the readback feature for bitstream verifi-
When the Read Capture option is not selected, the values cation. It can also display selected internal signals on the
of the capture bits reflect the configuration data originally PC or workstation screen, functioning as a low-cost in-cir-
written to those memory locations. cuit emulator.

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Configuration Timing There is an internal delay of 0.5 CCLK periods, which

means that DOUT changes on the falling CCLK edge, and
The seven configuration modes are discussed in detail in the next FPGA in the daisy chain accepts data on the sub-
this section. Timing specifications are included. sequent rising CCLK edge.
Slave Serial Mode Figure 28 shows a full master/slave system. An
XC5200-Series device in Slave Serial mode should be con-
In Slave Serial mode, an external signal drives the CCLK nected as shown in the third device from the left.
input of the FPGA. The serial configuration bitstream must
be available at the DIN input of the lead FPGA a short Slave Serial mode is selected by a <111> on the mode pins
setup time before each rising CCLK edge. (M2, M1, M0). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resis-
The lead FPGA then presents the preamble data—and all
tors during configuration.
data that overflows the lead device—on its DOUT pin.
NOTE: NOTE:
M2, M1, M0 can be shorted M2, M1, M0 can be shorted
to Ground if not used as I/O to VCC if not used as I/O
VCC
N/C
3.3 KΩ 3.3 KΩ 3.3 KΩ 3.3 KΩ 3.3 KΩ
3.3 KΩ
M0 M1 M0 M1 M0 M1 PWRDN
M2 N/C M2 M2
DOUT DIN DOUT DIN DOUT
VCC CCLK CCLK

XC5200
Spartan,
MASTER XC1700E +5 V XC3100A
4.7 KΩ XC4000E/EX,
SERIAL SLAVE
XC5200
CCLK CLK VPP
SLAVE
DIN DATA
PROGRAM LDC CE CEO PROGRAM RESET
DONE INIT RESET/OE DONE INIT D/P INIT
(Low Reset Option Used)
PROGRAM X9003_01
Figure 28: Master/Slave Serial Mode Circuit Diagram
DIN Bit n Bit n + 1
1 TDCC 2 TCCD 5 TCCL
CCLK
4 TCCH 3 TCCO
DOUT
Bit n - 1 Bit n
(Output)
X5379
Description Symbol Min Max Units

DIN setup 1 TDCC 20 ns
DIN hold 2 TCCD 0 ns
DIN to DOUT 3 TCCO 30 ns
CCLK
High time 4 TCCH 45 ns
Low time 5 TCCL 45 ns
Frequency FCC 10 MHz
Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Figure 29: Slave Serial Mode Programming Switching Characteristics

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Master Serial Mode The value increases from a nominal 1 MHz, to a nominal 12
MHz. Be sure that the serial PROM and slaves are fast
In Master Serial mode, the CCLK output of the lead FPGA enough to support this data rate. The Medium ConfigRate
drives a Xilinx Serial PROM that feeds the FPGA DIN input. option changes the frequency to a nominal 6 MHz.
Each rising edge of the CCLK output increments the Serial XC2000, XC3000/A, and XC3100A devices do not support
PROM internal address counter. The next data bit is put on the Fast or Medium ConfigRate options.
the SPROM data output, connected to the FPGA DIN pin.
The lead FPGA accepts this data on the subsequent rising The SPROM CE input can be driven from either LDC or
CCLK edge. DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
The lead FPGA then presents the preamble data—and all
restricted to be a permanently High user output after con-
data that overflows the lead device—on its DOUT pin.
figuration. Using DONE can also avoid contention on DIN,
There is an internal pipeline delay of 1.5 CCLK periods,
provided the DONE before I/O enable option is invoked.
which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data Figure 28 on page 114 shows a full master/slave system.
on the subsequent rising CCLK edge. The leftmost device is in Master Serial mode.
In the bitstream generation software, the user can specify Master Serial mode is selected by a <000> on the mode
Fast ConfigRate, which, starting several bits into the first pins (M2, M1, M0).
frame, increases the CCLK frequency by a factor of twelve.
CCLK
(Output)
2 TCKDS
1 TDSCK
Serial Data In n n+1 n+2

7
Serial DOUT n–3 n–2 n–1 n

(Output)
X3223

DIN setup 1 TDSCK 20 ns
CCLK
DIN hold 2 TCKDS 0 ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is valid.
2. Master Serial mode timing is based on testing in slave mode.
Figure 30: Master Serial Mode Programming Switching Characteristics

In the two Master Parallel modes, the lead FPGA directly The PROM address pins can be incremented or decre-
addresses an industry-standard byte-wide EPROM, and mented, depending on the mode pin settings. This option
accepts eight data bits just before incrementing or decre- allows the FPGA to share the PROM with a wide variety of
menting the address outputs. microprocessors and microcontrollers. Some processors
must boot from the bottom of memory (all zeros) while oth-
The eight data bits are serialized in the lead FPGA, which
ers must boot from the top. The FPGA is flexible and can
then presents the preamble data—and all data that over-
load its configuration bitstream from either end of the mem-
flows the lead device—on its DOUT pin. There is an inter-
ory.
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data (and also changes the EPROM Master Parallel Up mode is selected by a <100> on the
address) until the falling CCLK edge that makes the LSB mode pins (M2, M1, M0). The EPROM addresses start at
(D0) of this byte appear at DOUT. This means that DOUT 00000 and increment.
changes on the falling CCLK edge, and the next FPGA in Master Parallel Down mode is selected by a <110> on the
the daisy chain accepts data on the subsequent rising mode pins. The EPROM addresses start at 3FFFF and
CCLK edge.
decrement.

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HIGH TO DIN OF OPTIONAL

or DAISY-CHAINED FPGAS
3.3 K N/C
LOW
N/C
M0 M1 M2 TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS
CCLK
DOUT
NOTE:M0 can be shorted
to Ground if not used A17 ... M0 M1 M2
as I/O.
XC5200 A16 ... DIN DOUT
VCC Master
Parallel A15 ... EPROM
(8K x 8) CCLK
A14 ...
4.7K (OR LARGER)
USER CONTROL OF HIGHER XC5200/
INIT A13 ... XC4000E/EX/
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT BETWEEN Spartan
A12 A12 SLAVE
ALTERNATIVE CONFIGURATIONS
A11 A11
PROGRAM
A10 A10
PROGRAM A9 A9
DONE INIT
D7 A8 A8
D6 A7 A7 D7
D5 A6 A6 D6
D4 A5 A5 D5
D3 A4 A4 D4
D2 A3 A3 D3
D1 A2 A2 D2
D0 A1 A1 D1
A0 A0 D0
DONE OE
CE
DATA BUS 8
PROGRAM
X9004_01
Figure 31: Master Parallel Mode Circuit Diagram

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.
A0-A17
(output) Address for Byte n Address for Byte n + 1
1 TRAC
D0-D7
Byte
2 TDRC 3 TRCD
RCLK
(output)
7 CCLKs CCLK
CCLK
(output)
DOUT
(output) D6 D7
Byte n - 1 X6078

Delay to Address valid 1 TRAC 0 200 ns
CCLK Data setup time 2 TDRC 60 ns
Data hold time 3 TRCD 0 ns 7
Note: 1. At power-up, VCC must rise from 2.0 V to VCC min in less then 25 ms, otherwise delay configuration by pulling PROGRAM
Low until VCC is Valid.
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 32: Master Parallel Mode Programming Switching Characteristics

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Synchronous Peripheral Mode for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK The lead FPGA serializes the data and presents the pre-
input(s) of the FPGA(s). The first byte of parallel configura- amble data (and all data that overflows the lead device) on
tion data must be available at the Data inputs of the lead its DOUT pin. There is an internal delay of 1.5 CCLK peri-
FPGA a short setup time before the rising CCLK edge. ods, which means that DOUT changes on the falling CCLK
Subsequent data bytes are clocked in on every eighth con- edge, and the next FPGA in the daisy chain accepts data
secutive rising CCLK edge. on the subsequent rising CCLK edge.
The same CCLK edge that accepts data, also causes the In order to complete the serial shift operation, 10 additional
RDY/BUSY output to go High for one CCLK period. The pin CCLK rising edges are required after the last data byte has
name is a misnomer. In Synchronous Peripheral mode it is been loaded, plus one more CCLK cycle for each
really an ACKNOWLEDGE signal. Synchronous operation daisy-chained device.
does not require this response, but it is a meaningful signal Synchronous Peripheral mode is selected by a <011> on
the mode pins (M2, M1, M0).
NOTE:
M2 can be shorted to Ground
if not used as I/O
N/C 3.3 kΩ N/C
M0 M1 M2 M0 M1 M2
CLOCK CCLK CCLK
OPTIONAL
8 DAISY-CHAINED
DATA BUS D0-7 FPGAs
DOUT DIN DOUT
VCC XC5200
SYNCHRO- XC5200E/EX
NOUS SLAVE
4.7 kΩ PERIPHERAL
CONTROL RDY/BUSY
SIGNALS INIT DONE INIT DONE
3.3 kΩ
PROGRAM PROGRAM PROGRAM
X9005
Figure 33: Synchronous Peripheral Mode Circuit Diagram

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TCCL
CCLK
1 TIC
3 TCD
INIT 2 TDC
BYTE BYTE
D0 - D7 0 1
BYTE 0 OUT BYTE 1 OUT
DOUT 0 1 2 3 4 5 6 7 0 1
RDY/BUSY
X6096

INIT (High) setup time 1 TIC 5 µs
D0 - D7 setup time 2 TDC 60 ns
D0 - D7 hold time 3 TCD 0 ns
CCLK
CCLK High time TCCH 50 ns
CCLK Low time TCCL 60 ns
CCLK Frequency FCC 8 MHz 7
Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first data byte on the second rising edge of CCLK after INIT goes high. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name RDY/BUSY is a misnomer. In synchronous peripheral mode this is really an ACKNOWLEDGE signal.
4.Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.
Figure 34: Synchronous Peripheral Mode Programming Switching Characteristics

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Asynchronous Peripheral Mode The READY/BUSY handshake can be ignored if the delay
from any one Write to the end of the next Write is guaran-
Write to FPGA teed to be longer than 10 CCLK periods.
Asynchronous Peripheral mode uses the trailing edge of Status Read
the logic AND condition of WS and CS0 being Low and RS
and CS1 being High to accept byte-wide data from a micro- The logic AND condition of the CS0, CS1 and RS inputs
processor bus. In the lead FPGA, this data is loaded into a puts the device status on the Data bus.
double-buffered UART-like parallel-to-serial converter and • D7 High indicates Ready
is serially shifted into the internal logic. • D7 Low indicates Busy
The lead FPGA presents the preamble data (and all data • D0 through D6 go unconditionally High
that overflows the lead device) on its DOUT pin. The It is mandatory that the whole start-up sequence be started
RDY/BUSY output from the lead FPGA acts as a hand- and completed by one byte-wide input. Otherwise, the pins
shake signal to the microprocessor. RDY/BUSY goes Low used as Write Strobe or Chip Enable might become active
when a byte has been received, and goes High again when outputs and interfere with the final byte transfer. If this
the byte-wide input buffer has transferred its information transfer does not occur, the start-up sequence is not com-
into the shift register, and the buffer is ready to receive new pleted all the way to the finish (point F in Figure 25 on page
data. A new write may be started immediately, as soon as 109).
the RDY/BUSY output has gone Low, acknowledging
In this case, at worst, the internal reset is not released. At
receipt of the previous data. Write may not be terminated
best, Readback and Boundary Scan are inhibited. The
until RDY/BUSY is High again for one CCLK period. Note
length-count value, as generated by the software, ensures
that RDY/BUSY is pulled High with a high-impedance
that these problems never occur.
pull-up prior to INIT going High.
Although RDY/BUSY is brought out as a separate signal,
The length of the BUSY signal depends on the activity in
microprocessors can more easily read this information on
the UART. If the shift register was empty when the new
one of the data lines. For this purpose, D7 represents the
byte was received, the BUSY signal lasts for only two
RDY/BUSY status when RS is Low, WS is High, and the
CCLK periods. If the shift register was still full when the
new byte was received, the BUSY signal can be as long as two chip select lines are both active.
nine CCLK periods. Asynchronous Peripheral mode is selected by a <101> on
the mode pins (M2, M1, M0).
Note that after the last byte has been entered, only seven
of its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
N/C
N/C N/C
3.3 kΩ
M0 M1 M2 M0 M1 M2
DATA 8
D0–7 CCLK CCLK
BUS
OPTIONAL
DAISY-CHAINED
FPGAs
DOUT DIN DOUT
VCC ADDRESS CS0
ADDRESS DECODE XC5200
...
BUS LOGIC
ASYNCHRO- XC5200/
NOUS XC4000E/EX
4.7 kΩ
PERIPHERAL SLAVE
4.7 kΩ CS1
RS
WS
CONTROL RDY/BUSY
SIGNALS
INIT INIT
DONE DONE
REPROGRAM
PROGRAM PROGRAM
3.3 kΩ
X9006
Figure 35: Asynchronous Peripheral Mode Circuit Diagram

R
Write to LCA Read Status
WS/CS0 RS, CS0
RS, CS1 WS, CS1

1 TCA
3 TCD 7 4
2 TDC
READY D7
D0-D7
BUSY
CCLK
TWTRB 4
6 TBUSY
RDY/BUSY
DOUT Previous Byte D6 D7 D0 D1 D2
X6097

Effective Write time 1 TCA 100 ns
(CSO, WS=Low; RS, CS1=High
Write
DIN setup time 2 TDC 60 ns
DIN hold time 3 TCD 0 ns
7
RDY/BUSY delay after end of 4 TWTRB 60 ns
Write or Read
RDY/BUSY active after beginning 7 60 ns
RDY
of Read
RDY/BUSY Low output (Note 4) 6 TBUSY 2 9 CCLK
periods
Notes: 1. Configuration must be delayed until INIT pins of all daisy-chained FPGAs are high.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing
and the phase of internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Figure 36: Asynchronous Peripheral Mode Programming Switching Characteristics

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Express Mode ration memory is not already full. The status pin DOUT is
pulled Low two internal-oscillator cycles after INIT is recog-
Express mode is similar to Slave Serial mode, except that nized as High, and remains Low until the device’s configu-
data is processed one byte per CCLK cycle instead of one ration memory is full. DOUT is then pulled High to signal
bit per CCLK cycle. An external source is used to drive the next device in the chain to accept the configuration data
CCLK, while byte-wide data is loaded directly into the con- on the D0-D7 bus.
figuration data shift registers. A CCLK frequency of 10
MHz is equivalent to an 80 MHz serial rate, because eight The DONE pins of all devices in the chain should be tied
bits of configuration data are loaded per CCLK cycle. together, with one or more active internal pull-ups. If a
Express mode does not support CRC error checking, but large number of devices are included in the chain, deacti-
does support constant-field error checking. vate some of the internal pull-ups, since the Low-driving
DONE pin of the last device in the chain must sink the cur-
In Express mode, an external signal drives the CCLK input rent from all pull-ups in the chain. The DONE pull-up is
of the FPGA device. The first byte of parallel configuration activated by default. It can be deactivated using an option
data must be available at the D inputs of the FPGA a short in the bitstream generation software.
setup time before the second rising CCLK edge. Subse-
quent data bytes are clocked in on each consecutive rising XC5200 devices in Express mode are always synchronized
CCLK edge. to DONE. The device becomes active after DONE goes
High. DONE is an open-drain output. With the DONE pins
If the first device is configured in Express mode, additional
tied together, therefore, the external DONE signal stays low
devices may be daisy-chained only if every device in the until all devices are configured, then all devices in the daisy
chain is also configured in Express mode. CCLK pins are chain become active simultaneously. If the DONE pin of a
tied together and D0-D7 pins are tied together for all device is left unconnected, the device becomes active as
devices along the chain. A status signal is passed from soon as that device has been configured.
DOUT to CS1 of successive devices along the chain. The
lead device in the chain has its CS1 input tied High (or float- Express mode is selected by a <010> on the mode pins
ing, since there is an internal pullup). Frame data is (M2, M1, M0).
accepted only when CS1 is High and the device’s configu-
VCC
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
3.3 kΩ
8
To Additional
M0 M1 M2 M0 M1 M2 Optional
Daisy-Chained
Devices
CS1 DOUT CS1 DOUT
8 8
DATA BUS D0-D7 D0-D7
Optional
VCC XC5200 Daisy-Chained
XC5200
4.7KΩ
PROGRAM PROGRAM PROGRAM
INIT INIT DONE INIT DONE
CCLK CCLK
To Additional
Optional
Daisy-Chained
CCLK
Devices
X6611_01
Figure 37: Express Mode Circuit Diagram

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CCLK
1 TIC
INIT
TCD 3
2 T
DC
D0-D7 BYTE BYTE BYTE BYTE

0 1 2 3
Serial Data Out

(DOUT)
FPGA Filled
Internal INIT
RDY/BUSY
CS1 X5087

INIT (High) Setup time required 1 TIC 5 µs
DIN Setup time required 2 TDC 30 ns
DIN hold time required 3 TCD 0 ns 7
CCLK
CCLK High time TCCH 30 ns
CCLK Low time TCCL 30 ns
CCLK frequency FCC 10 MHz
Note: If not driven by the preceding DOUT, CS1 must remain high until the device is fully configured.
Figure 38: Express Mode Programming Switching Characteristics

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Table 13. Pin Functions During Configuration

CONFIGURATION MODE: <M2:M1:M0>
USER
SLAVE MASTER-SER SYN.PERIPH ASYN.PERIPH MASTER-HIGH MASTER-LOW EXPRESS OPERATION
<1:1:1> <0:0:0> <0:1:1> <1:0:1> <1:1:0> <1:0:0> <0:1:0>
A16 A16 GCK1-I/O
A17 A17 I/O
TDI TDI TDI TDI TDI TDI TDI TDI-I/O
TCK TCK TCK TCK TCK TCK TCK TCK-I/O
TMS TMS TMS TMS TMS TMS TMS TMS-I/O
I/O
M1 (HIGH) (I) M1 (LOW) (I) M1 (HIGH) (I) M1 (LOW) (I) M1 (HIGH) (I) M1 (LOW) (I) M1 (HIGH) (I) I/O
M0 (HIGH) (I) M0 (LOW) (I) M0 (HIGH) (I) M0 (HIGH) (I) M0 (LOW) (I) M0 (LOW) (I) M0 (LOW) (I) I/O
M2 (HIGH) (I) M2 (LOW) (I) M2 (LOW) (I) M2 (HIGH) (I) M2 (HIGH) (I) M2 (HIGH) (I) M2 (LOW) (I) I/O
GCK2-I/O
HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) I/O
LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) I/O
INIT-ERROR INIT-ERROR INIT-ERROR INIT-ERROR INIT-ERROR INIT-ERROR INIT-ERROR I/O
I/O
DONE DONE DONE DONE DONE DONE DONE DONE
PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM
DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) I/O
GCK3-I/O
CSO (I) I/O
RS (I) I/O
RDY/BUSY RDY/BUSY RCLK RCLK I/O
DIN (I) DIN (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) I/O
DOUT DOUT DOUT DOUT DOUT DOUT DOUT I/O
CCLK (I) CCLK (O) CCLK (I) CCLK (O) CCLK (O) CCLK (O) CCLK (I) CCLK (I)
TDO TDO TDO TDO TDO TDO TDO TDO-I/O
WS (I) A0 A0 I/O
A1 A1 GCK4-I/O
CS1 (I) A2 A2 CS1 (I) I/O
A3 A3 I/O
A4 A4 I/O
A5 A5 I/O
A6 A6 I/O
A7 A7 I/O
A8 A8 I/O
A9 A9 I/O
A10 A10 I/O
A11 A11 I/O
A12 A12 I/O
A13 A13 I/O
A14 A14 I/O
A15 A15 I/O
ALL OTHERS
Notes: 1. A shaded table cell represents a 20-kΩ to 100-kΩ pull-up resistor before and during configuration.
2. (I) represents an input (O) represents an output.
3. INIT is an open-drain output during configuration.

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Configuration Switching Characteristics

Vcc T POR
RE-PROGRAM
>300 ns
PROGRAM
T PI
INIT
T ICCK TCCLK
CCLK OUTPUT or INPUT
<300 ns
M0, M1, M2
VALID DONE RESPONSE
(Required)
X1532
<300 ns
I/O
Master Modes
Power-On-Reset TPOR 2 15 ms
Program Latency TPI 6 70 µs per CLB column
CCLK (output) Delay TICCK 40 375 µs 7
period (slow) TCCLK 640 3000 ns
period (fast) TCCLK 100 375 ns
Slave and Peripheral Modes

Power-On-Reset TPOR 2 15 ms
Program Latency TPI 6 70 µs per CLB column
CCLK (input) Delay (required) TICCK 5 µs
period (required) TCCLK 100 ns
Note: At power-up, VCC must rise from 2.0 to VCC min in less than 15 ms, otherwise delay configuration using PROGRAM until
VCC is valid.

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XC5200 Program Readback Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements.
The following guidelines reflect worst-case values over the recommended operating conditions.
Finished
Internal Net
3
T RTL
rdbk.TRIG
T RCRT
T RTRC 2
1
rdclk.I
4 T RCL T RCH 5
rdbk.RIP
6
T RCRR
rdbk.DATA DUMMY DUMMY VALID VALID
T RCRD
7
X1790

rdbk.TRIG rdbk.TRIG setup to initiate and abort Readback 1 TRTRC 200 - ns
rdbk.TRIG hold to initiate and abort Readback 2 TRCRT 50 - ns
rdclk.1 rdbk.DATA delay 7 TRCRD - 250 ns
rdbk.RIP delay 6 TRCRR - 250 ns
High time 5 TRCH 250 500 ns
Low time 4 TRCL 250 500 ns
Note 1: Timing parameters apply to all speed grades.

Note 2: rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback

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XC5200 Switching Characteristics

Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.1
XC5200 Operating Conditions

Symbol Description Min Max Units
VCC Supply voltage relative to GND Commercial: 0°C to 85°C junction 4.75 5.25 V
Supply voltage relative to GND Industrial: -40°C to 100°C junction 4.5 5.5 V
VIHT High-level input voltage — TTL configuration 2.0 VCC V
VILT Low-level input voltage — TTL configuration 0 0.8 V
VIHC High-level input voltage — CMOS configuration 70% 100% VCC
VILC Low-level input voltage — CMOS configuration 0 20% VCC
TIN Input signal transition time 250 ns
XC5200 DC Characteristics Over Operating Conditions

Symbol Description Min Max Units 7
VOH High-level output voltage @ IOH = -8.0 mA, VCC min 3.86 V
VOL Low-level output voltage @ IOL = 8.0 mA, VCC max 0.4 V
ICCO Quiescent FPGA supply current (Note 1) 15 mA
IIL Leakage current -10 +10 µA
CIN Input capacitance (sample tested) 15 pF
IRIN Pad pull-up (when selected) @ VIN = 0V (sample tested) 0.02 0.30 mA
Note: 1. With no output current loads, all package pins at Vcc or GND, either TTL or CMOS inputs, and the FPGA configured with a
tie option.
XC5200 Absolute Maximum Ratings

Symbol Description Units
VCC Supply voltage relative to GND -0.5 to +7.0 V
VIN Input voltage with respect to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output -0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) -65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 °C
TJ Junction temperature in plastic packages +125 °C
Junction temperature in ceramic packages +150 °C
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice.

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XC5200 Global Buffer Switching Characteristic Guidelines

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade -6 -5 -4 -3
Max Max Max Max
Description Symbol Device
(ns) (ns) (ns) (ns)
Global Signal Distribution TBUFG XC5202 9.1 8.5 8.0 6.9
From pad through global buffer, to any clock (CK) XC5204 9.3 8.7 8.2 7.6
XC5206 9.4 8.8 8.3 7.7
XC5210 9.4 8.8 8.5 7.7
XC5215 10.5 9.9 9.8 9.6
XC5200 Longline Switching Characteristic Guidelines

in the simulator.
Max Max Max Max
(ns) (ns) (ns) (ns)
TBUF driving a Longline TIO XC5202 6.0 3.8 3.0 2.0
TS XC5204 6.4 4.1 3.2 2.3
I O
XC5206 6.6 4.2 3.3 2.7
TBUF
XC5210 6.6 4.2 3.3 2.9
I to Longline, while TS is Low; i.e., buffer is constantly ac- XC5215 7.3 4.6 3.8 3.2
tive
TS going Low to Longline going from floating High or Low TON XC5202 7.8 5.6 4.7 4.0
to active Low or High XC5204 8.3 5.9 4.9 4.3
XC5206 8.4 6.0 5.0 4.4
XC5210 8.4 6.0 5.0 4.4
XC5215 8.9 6.3 5.3 4.5
TS going High to TBUF going inactive, not driving TOFF XC52xx 3.0 2.8 2.6 2.4
Longline
Note: 1. Die-size-dependent parameters are based upon XC5215 characterization. Production specifications will vary with array
size.

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XC5200 CLB Switching Characteristic Guidelines

in the simulator.
Min Max Min Max Min Max Min Max
Description Symbol
(ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns)
Combinatorial Delays
F inputs to X output TILO 5.6 4.6 3.8 3.0
F inputs via transparent latch to Q TITO 8.0 6.6 5.4 4.3
DI inputs to DO output (Logic-Cell TIDO 4.3 3.5 2.8 2.4
Feedthrough)
F inputs via F5_MUX to DO output TIMO 7.2 5.8 5.0 4.3
Carry Delays
Incremental delay per bit TCY 0.7 0.6 0.5 0.5
Carry-in overhead from DI TCYDI 1.8 1.6 1.5 1.4
Carry-in overhead from F TCYL 3.7 3.2 2.9 2.4
Carry-out overhead to DO TCYO 4.0 3.2 2.5 2.1
Sequential Delays
Clock (CK) to out (Q) (Flip-Flop) TCKO 5.8 4.9 4.0 4.0
Gate (Latch enable) going active to out (Q) TGO 9.2 7.4 5.9 5.5
Set-up Time Before Clock (CK) 7
F inputs TICK 2.3 1.8 1.4 1.3
F inputs via F5_MUX TMICK 3.8 3.0 2.5 2.4
DI input TDICK 0.8 0.5 0.4 0.4
CE input TEICK 1.6 1.2 0.9 0.9
Hold Times After Clock (CK)
F inputs TCKI 0 0 0 0
F inputs via F5_MUX TCKMI 0 0 0 0
DI input TCKDI 0 0 0 0
CE input TCKEI 0 0 0 0
Clock Widths
Clock High Time TCH 6.0 6.0 6.0 6.0
Clock Low Time TCL 6.0 6.0 6.0 6.0
Toggle Frequency (MHz) (Note 3) FTOG 83 83 83 83
Reset Delays
Width (High) TCLRW 6.0 6.0 6.0 6.0
Delay from CLR to Q (Flip-Flop) TCLR 7.7 6.3 5.1 4.0
Delay from CLR to Q (Latch) TCLRL 6.5 5.2 4.2 3.0
Global Reset Delays
Width (High) TGCLRW 6.0 6.0 6.0 6.0
Delay from internal GR to Q TGCLR 14.7 12.1 9.1 8.0
Note: 1. The CLB K to Q output delay (TCKO) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold-time requirement (TCKDI) of any CLB on the same die.
2. Timing is based upon the XC5215 device. For other devices, see Timing Calculator.
3. Maximum flip-flop toggle rate for export control purposes.

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XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin)

All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be
derived indirectly from the Global Buffer specifications. The delay calculator uses this indirect method, and may
overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values
listed below should be used, and the derived values should be considered conservative overestimates.
Max Max Max Max
(ns) (ns) (ns) (ns)
Global Clock to Output Pad (fast) TICKOF XC5202 16.9 15.1 10.9 9.8
CLB Direct IOB
XC5204 17.1 15.3 11.3 9.9
BUFG Q
Connect (Max) XC5206 17.2 15.4 11.9 10.8
..
FAST .. XC5210 17.2 15.4 12.8 11.2
Global Clock-to-Output Delay
XC5215 19.0 17.0 12.8 11.7
Global Clock to Output Pad (slew-limited) TICKO XC5202 21.4 18.7 12.6 11.5
CLB Direct IOB
XC5204 21.6 18.9 13.3 11.9
Connect (Max) XC5206 21.7 19.0 13.6 12.5
BUFG Q ..
.. XC5210 21.7 19.0 15.0 12.9
Global Clock-to-Output Delay XC5215 24.3 21.2 15.0 13.1
Input Set-up Time (no delay) to CLB Flip-Flop TPSUF XC5202 2.5 2.0 1.9 1.9
IOB(NODELAY) Direct CLB XC5204 2.3 1.9 1.9 1.9
Connect
Input F,DI (Min)
Set-up XC5206 2.2 1.9 1.9 1.9
& Hold
Time XC5210 2.2 1.9 1.9 1.8
BUFG XC5215 2.0 1.8 1.7 1.7
Input Hold Time (no delay) to CLB Flip-Flop TPHF XC5202 3.8 3.8 3.5 3.5
IOB(NODELAY) Direct CLB XC5204 3.9 3.9 3.8 3.6
Connect
Input F,DI (Min)
Set-up XC5206 4.4 4.4 4.4 4.3
& Hold
Time XC5210 5.1 5.1 4.9 4.8
BUFG XC5215 5.8 5.8 5.7 5.6
Input Set-up Time (with delay) to CLB Flip-Flop DI Input TPSU XC5202 7.3 6.6 6.6 6.6
IOB Connect
Direct CLB XC5204 7.3 6.6 6.6 6.6
Input DI
Set-up XC5206 7.2 6.5 6.4 6.3
& Hold
Time XC5210 7.2 6.5 6.0 6.0
BUFG XC5215 6.8 5.7 5.7 5.7
Input Set-up Time (with delay) to CLB Flip-Flop F Input TPSUL XC5202 8.8 7.7 7.5 7.5
IOB Connect
Direct CLB XC5204 8.6 7.5 7.5 7.5
Input F (Min)
Set-up XC5206 8.5 7.4 7.4 7.4
& Hold
Time XC5210 8.5 7.4 7.4 7.3
BUFG XC5215 8.5 7.4 7.4 7.2
Input Hold Time (with delay) to CLB Flip-Flop TPH XC52xx 0 0 0 0
IOB Connect
Direct CLB
Input F,DI
Set-up (Min)
& Hold
Time
BUFG
Note: 1. These measurements assume that the CLB flip-flop uses a direct interconnect to or from the IOB. The INREG/ OUTREG
properties, or XACT-Performance, can be used to assure that direct connects are used. tPSU applies only to the CLB input
DI that bypasses the look-up table, which only offers direct connects to IOBs on the left and right edges of the die. tPSUL
applies to the CLB inputs F that feed the look-up table, which offers direct connect to IOBs on all four edges, as do the CLB
Q outputs.
2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching.

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XC5200 IOB Switching Characteristic Guidelines

in the simulator.
Max Max Max Max
Description Symbol
(ns) (ns) (ns) (ns)
Input
Propagation Delays from CMOS or TTL Levels
Pad to I (no delay) TPI 5.7 5.0 4.8 3.3
Pad to I (with delay) TPID 11.4 10.2 10.2 9.5
Output
Propagation Delays to CMOS or TTL Levels
Output (O) to Pad (fast) TOPF 4.6 4.5 4.5 3.5
Output (O) to Pad (slew-limited) TOPS 9.5 8.4 8.0 5.0
From clock (CK) to output pad (fast), using direct connect between Q TOKPOF 10.1 9.3 8.3 7.5
and output (O)
From clock (CK) to output pad (slew-limited), using direct connect be- TOKPOS 14.9 13.1 11.8 10.0
tween Q and output (O)
3-state to Pad active (fast) TTSONF 5.6 5.2 4.9 4.6
3-state to Pad active (slew-limited) TTSONS 10.4 9.0 8.3 6.0
Internal GTS to Pad active TGTS 17.7 15.9 14.7 13.5 7
Note: 1. Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are
approximately two times longer than fast output rise/fall times.
2. Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors.
3. Timing is based upon the XC5215 device. For other devices, see Timing Calculator.

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XC5200 Boundary Scan (JTAG) Switching Characteristic Guidelines

The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC5200 devices unless otherwise noted.
Description Symbol Min Max Min Max Min Max Min Max
Setup and Hold
Input (TDI) to clock (TCK) TTDITCK 30.0 30.0 30.0 30.0
setup time
Input (TDI) to clock (TCK) TTCKTDI 0 0 0 0
hold time
Input (TMS) to clock (TCK) TTMSTCK 15.0 15.0 15.0 15.0
setup time
Input (TMS) to clock (TCK) TTCKTMS 0 0 0 0
hold time
Propagation Delay
Clock (TCK) to Pad (TDO) TTCKPO 30.0 30.0 30.0 30.0
Clock
Clock (TCK) High TTCKH 30.0 30.0 30.0 30.0
Clock (TCK) Low TTCKL 30.0 30.0 30.0 30.0
FMAX (MHz) FMAX 10.0 10.0 10.0 10.0
Note 1: Input pad setup and hold times are specified with respect to the internal clock.

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Device-Specific Pinout Tables

Device-specific tables include all packages for each XC5200-Series device. They follow the pad locations around the die,
and include boundary scan register locations.
Pin Locations for XC5202 Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the
availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin Description VQ64* PC84 PQ100 VQ100 TQ144 PG156 Boundary Scan Order
VCC - 2 92 89 128 H3 -
1. I/O (A8) 57 3 93 90 129 H1 51
2. I/O (A9) 58 4 94 91 130 G1 54
3. I/O - - 95 92 131 G2 57
4. I/O - - 96 93 132 G3 63
5. I/O (A10) - 5 97 94 133 F1 66
6. I/O (A11) 59 6 98 95 134 F2 69
GND - - - - 137 F3 -
7. I/O (A12) 60 7 99 96 138 E3 78
8. I/O (A13) 61 8 100 97 139 C1 81
9. I/O (A14) 62 9 1 98 142 B1 90
10. I/O (A15) 63 10 2 99 143 B2 93
VCC 64 11 3 100 144 C3 -
GND - 12 4 1 1 C4 -
11. GCK1 (A16, I/O) 1 13 5 2 2 B3 102
12. I/O (A17) 2 14 6 3 3 A1 105 7
13. I/O (TDI) 3 15 7 4 6 B4 111
14. I/O (TCK) 4 16 8 5 7 A3 114
GND - - - - 8 C6 -
15. I/O (TMS) 5 17 9 6 11 A5 117
16. I/O 6 18 10 7 12 C7 123
17. I/O - - - - 13 B7 126
18. I/O - - 11 8 14 A6 129
19. I/O - 19 12 9 15 A7 135
20. I/O 7 20 13 10 16 A8 138
GND 8 21 14 11 17 C8 -
VCC 9 22 15 12 18 B8 -
21. I/O - 23 16 13 19 C9 141
22. I/O 10 24 17 14 20 B9 147
23. I/O - 18 15 21 A9 150
24. I/O - - - 22 B10 153
25. I/O - 25 19 16 23 C10 159
26. I/O 11 26 20 17 24 A10 162
GND - - - 27 C11 -
27. I/O 12 27 21 18 28 B12 165
28. I/O - 22 19 29 A13 171
29. I/O 13 28 23 20 32 B13 174
30. I/O 14 29 24 21 33 B14 177
31. M1 (I/O) 15 30 25 22 34 A15 186
GND - 31 26 23 35 C13 -
32. M0 (I/O) 16 32 27 24 36 A16 189
VCC - 33 28 25 37 C14 -
33. M2 (I/O) 17 34 29 26 38 B15 192
34. GCK2 (I/O) 18 35 30 27 39 B16 195

R
35. I/O (HDC) 19 36 31 28 40 D14 204
36. I/O - - 32 29 43 E14 207
37. I/O (LDC) 20 37 33 30 44 C16 210
GND - - - - 45 F14 -
38. I/O - 38 34 31 48 F16 216
39. I/O 21 39 35 32 49 G14 219
40. I/O - - 36 33 50 G15 222
41. I/O - - 37 34 51 G16 228
42. I/O 22 40 38 35 52 H16 231
43. I/O (ERR, INIT) 23 41 39 36 53 H15 234
VCC 24 42 40 37 54 H14 -
GND 25 43 41 38 55 J14 -
44. I/O 26 44 42 39 56 J15 240
45. I/O 27 45 43 40 57 J16 243
46. I/O - - 44 41 58 K16 246
47. I/O - - 45 42 59 K15 252
48. I/O 28 46 46 43 60 K14 255
49. I/O 29 47 47 44 61 L16 258
GND - - - - 64 L14 -
50. I/O - 48 48 45 65 P16 264
51. I/O 30 49 49 46 66 M14 267
52. I/O - 50 50 47 69 N14 276
53. I/O 31 51 51 48 70 R16 279
GND - 52 52 49 71 P14 -
DONE 32 53 53 50 72 R15 -
VCC 33 54 54 51 73 P13 -
PROG 34 55 55 52 74 R14 -
54. I/O (D7) 35 56 56 53 75 T16 288
55. GCK3 (I/O) 36 57 57 54 76 T15 291
56. I/O (D6) 37 58 58 55 79 T14 300
57. I/O - - 59 56 80 T13 303
GND - - - - 81 P11 -
58. I/O (D5) 38 59 60 57 84 T10 306
59. I/O (CS0) - 60 61 58 85 P10 312
60. I/O - - 62 59 86 R10 315
61. I/O - - 63 60 87 T9 318
62. I/O (D4) 39 61 64 61 88 R9 324
63. I/O - 62 65 62 89 P9 327
VCC 40 63 66 63 90 R8 -
GND 41 64 67 64 91 P8 -
64. I/O (D3) 42 65 68 65 92 T8 336
65. I/O (RS) 43 66 69 66 93 T7 339
66. I/O - - 70 67 94 T6 342
67. I/O - - - - 95 R7 348
68. I/O (D2) 44 67 71 68 96 P7 351
69. I/O - 68 72 69 97 T5 360
GND - - - - 100 P6 -
70. I/O (D1) 45 69 73 70 101 T3 363
71. I/O - 70 74 71 102 P5 366
(RCLK-BUSY/RDY)
72. I/O (D0, DIN) 46 71 75 72 105 P4 372
73. I/O (DOUT) 47 72 76 73 106 T2 375

R
CCLK 48 73 77 74 107 R2 -
VCC - 74 78 75 108 P3 -
74. I/O (TDO) 49 75 79 76 109 T1 0
GND - 76 80 77 110 N3 -
75. I/O (A0, WS) 50 77 81 78 111 R1 9
76. GCK4 (A1, I/O) 51 78 82 79 112 P2 15
77. I/O (A2, CS1) 52 79 83 80 115 P1 18
78. I/O (A3) - 80 84 81 116 N1 21
GND - - - - 118 L3 -
79. I/O (A4) - 81 85 82 121 K3 27
80. I/O (A5) 53 82 86 83 122 K2 30
81. I/O - - 87 84 123 K1 33
82. I/O - - 88 85 124 J1 39
83. I/O (A6) 54 83 89 86 125 J2 42
84. I/O (A7) 55 84 90 87 126 J3 45
GND 56 1 91 88 127 H2 -
* VQ64 package supports Master Serial, Slave Serial, and Express configuration modes only.
Additional No Connect (N.C.) Connections on TQ144 Package

TQ144
135 9 41 67 98 117
136 10 42 68 99 119
140 25 46 77 103 120
7
141 26 47 78 104
4 30 62 82 113
5 31 63 83 114
Notes: Boundary Scan Bit 0 = TDO.T

Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 = BSCAN.UPD

Pin Description PC84 PQ100 VQ100 TQ144 PG156 PQ160 Boundary Scan Order
VCC 2 92 89 128 H3 142 -
1. I/O (A8) 3 93 90 129 H1 143 78
2. I/O (A9) 4 94 91 130 G1 144 81
3. I/O - 95 92 131 G2 145 87
4. I/O - 96 93 132 G3 146 90
5. I/O (A10) 5 97 94 133 F1 147 93
6. I/O (A11) 6 98 95 134 F2 148 99
7. I/O - - - 135 E1 149 102
8. I/O - - - 136 E2 150 105
GND - - - 137 F3 151 -
9. I/O - - - - D1 152 111
10. I/O - - - - D2 153 114
11. I/O (A12) 7 99 96 138 E3 154 117
12. I/O (A13) 8 100 97 139 C1 155 123
13. I/O - - - 140 C2 156 126

R
14. I/O - - - 141 D3 157 129
15. I/O (A14) 9 1 98 142 B1 158 138
16. I/O (A15) 10 2 99 143 B2 159 141
VCC 11 3 100 144 C3 160 -
GND 12 4 1 1 C4 1 -
17. GCK1 (A16, I/O) 13 5 2 2 B3 2 150
18. I/O (A17) 14 6 3 3 A1 3 153
19. I/O - - - 4 A2 4 159
20. I/O - - - 5 C5 5 162
21. I/O (TDI) 15 7 4 6 B4 6 165
22. I/O (TCK) 16 8 5 7 A3 7 171
GND - - - 8 C6 10 -
23. I/O - - - 9 B5 11 174
24. I/O - - - 10 B6 12 177
25. I/O (TMS) 17 9 6 11 A5 13 180
26. I/O 18 10 7 12 C7 14 183
27. I/O - - - 13 B7 15 186
28. I/O - 11 8 14 A6 16 189
29. I/O 19 12 9 15 A7 17 195
30. I/O 20 13 10 16 A8 18 198
GND 21 14 11 17 C8 19 -
VCC 22 15 12 18 B8 20 -
31. I/O 23 16 13 19 C9 21 201
32. I/O 24 17 14 20 B9 22 207
33. I/O - 18 15 21 A9 23 210
34. I/O - - - 22 B10 24 213
35. I/O 25 19 16 23 C10 25 219
36. I/O 26 20 17 24 A10 26 222
37. I/O - - - 25 A11 27 225
38. I/O - - - 26 B11 28 231
GND - - - 27 C11 29 -
39. I/O 27 21 18 28 B12 32 234
40. I/O - 22 19 29 A13 33 237
41. I/O - - - 30 A14 34 240
42. I/O - - - 31 C12 35 243
43. I/O 28 23 20 32 B13 36 246
44. I/O 29 24 21 33 B14 37 249
45. M1 (I/O) 30 25 22 34 A15 38 258
GND 31 26 23 35 C13 39 -
46. M0 (I/O) 32 27 24 36 A16 40 261
VCC 33 28 25 37 C14 41 -
47. M2 (I/O) 34 29 26 38 B15 42 264
48. GCK2 (I/O) 35 30 27 39 B16 43 267
49. I/O (HDC) 36 31 28 40 D14 44 276
50. I/O - - - 41 C15 45 279
51. I/O - - - 42 D15 46 282
52. I/O - 32 29 43 E14 47 288
53. I/O (LDC) 37 33 30 44 C16 48 291
54. I/O - - - - E15 49 294
55. I/O - - - - D16 50 300
GND - - - 45 F14 51 -
56. I/O - - - 46 F15 52 303

R
57. I/O - - - 47 E16 53 306
58. I/O 38 34 31 48 F16 54 312
59. I/O 39 35 32 49 G14 55 315
60. I/O - 36 33 50 G15 56 318
61. I/O - 37 34 51 G16 57 324
62. I/O 40 38 35 52 H16 58 327
63. I/O (ERR, INIT) 41 39 36 53 H15 59 330
VCC 42 40 37 54 H14 60 -
GND 43 41 38 55 J14 61 -
64. I/O 44 42 39 56 J15 62 336
65. I/O 45 43 40 57 J16 63 339
66. I/O - 44 41 58 K16 64 348
67. I/O - 45 42 59 K15 65 351
68. I/O 46 46 43 60 K14 66 354
69. I/O 47 47 44 61 L16 67 360
70. I/O - - - 62 M16 68 363
71. I/O - - - 63 L15 69 366
GND - - - 64 L14 70 -
72. I/O - - - - N16 71 372
73. I/O - - - - M15 72 375
74. I/O 48 48 45 65 P16 73 378
75. I/O 49 49 46 66 M14 74 384
76. I/O - - - 67 N15 75 387
77. I/O - - - 68 P15 76 390
7
78. I/O 50 50 47 69 N14 77 396
79. I/O 51 51 48 70 R16 78 399
GND 52 52 49 71 P14 79 -
DONE 53 53 50 72 R15 80 -
VCC 54 54 51 73 P13 81 -
PROG 55 55 52 74 R14 82 -
80. I/O (D7) 56 56 53 75 T16 83 408
81. GCK3 (I/O) 57 57 54 76 T15 84 411
82. I/O - - - 77 R13 85 420
83. I/O - - - 78 P12 86 423
84. I/O (D6) 58 58 55 79 T14 87 426
85. I/O - 59 56 80 T13 88 432
GND - - - 81 P11 91 -
86. I/O - - - 82 R11 92 435
87. I/O - - - 83 T11 93 438
88. I/O (D5) 59 60 57 84 T10 94 444
89. I/O (CS0) 60 61 58 85 P10 95 447
90. I/O - 62 59 86 R10 96 450
91. I/O - 63 60 87 T9 97 456
92. I/O (D4) 61 64 61 88 R9 98 459
93. I/O 62 65 62 89 P9 99 462
VCC 63 66 63 90 R8 100 -
GND 64 67 64 91 P8 101 -
94. I/O (D3) 65 68 65 92 T8 102 468
95. I/O (RS) 66 69 66 93 T7 103 471
96. I/O - 70 67 94 T6 104 474
97. I/O - - - 95 R7 105 480
98. I/O (D2) 67 71 68 96 P7 106 483

R
99. I/O 68 72 69 97 T5 107 486
100. I/O - - - 98 R6 108 492
101. I/O - - - 99 T4 109 495
GND - - - 100 P6 110 -
102. I/O (D1) 69 73 70 101 T3 113 498
103. I/O 70 74 71 102 P5 114 504
(RCLK-BUSY/RDY)
104. I/O - - - 103 R4 115 507
105. I/O - - - 104 R3 116 510
106. I/O (D0, DIN) 71 75 72 105 P4 117 516
107. I/O (DOUT) 72 76 73 106 T2 118 519
CCLK 73 77 74 107 R2 119 -
VCC 74 78 75 108 P3 120 -
108. I/O (TDO) 75 79 76 109 T1 121 0
GND 76 80 77 110 N3 122 -
109. I/O (A0, WS) 77 81 78 111 R1 123 9
110. GCK4 (A1, I/O) 78 82 79 112 P2 124 15
111. I/O - - - 113 N2 125 18
112. I/O - - - 114 M3 126 21
113. I/O (A2, CS1) 79 83 80 115 P1 127 27
114. I/O (A3) 80 84 81 116 N1 128 30
115. I/O - - - 117 M2 129 33
116. I/O - - - - M1 130 39
GND - - - 118 L3 131 -
117. I/O - - - 119 L2 132 42
118. I/O - - - 120 L1 133 45
119. I/O (A4) 81 85 82 121 K3 134 51
120. I/O (A5) 82 86 83 122 K2 135 54
121. I/O - 87 84 123 K1 137 57
122. I/O - 88 85 124 J1 138 63
123. I/O (A6) 83 89 86 125 J2 139 66
124. I/O (A7) 84 90 87 126 J3 140 69
GND 1 91 88 127 H2 141 -
Additional No Connect (N.C.) Connections for PQ160 Package

PQ160
8 30 89 111 136
9 31 90 112


R

Pin Description PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order
VCC 2 92 89 128 142 155 J4 183 -
1. I/O (A8) 3 93 90 129 143 156 J3 184 87
2. I/O (A9) 4 94 91 130 144 157 J2 185 90
3. I/O - 95 92 131 145 158 J1 186 93
4. I/O - 96 93 132 146 159 H1 187 99
5. I/O - - - - - 160 H2 188 102
6. I/O - - - - - 161 H3 189 105
7. I/O (A10) 5 97 94 133 147 162 G1 190 111
8. I/O (A11) 6 98 95 134 148 163 G2 191 114
9. I/O - - - 135 149 164 F1 192 117
10. I/O - - - 136 150 165 E1 193 123
GND - - - 137 151 166 G3 194 -
11. I/O - - - - 152 168 C1 197 126
12. I/O - - - - 153 169 E2 198 129
13. I/O (A12) 7 99 96 138 154 170 F3 199 138
14. I/O (A13) 8 100 97 139 155 171 D2 200 141
15. I/O - - - 140 156 172 B1 201 150
16. I/O - - - 141 157 173 E3 202 153
17. I/O (A14) 9 1 98 142 158 174 C2 203 162
18. I/O (A15) 10 2 99 143 159 175 B2 204 165
VCC 11 3 100 144 160 176 D3 205 -
7
GND 12 4 1 1 1 1 D4 2 -
19. GCK1 (A16, I/O) 13 5 2 2 2 2 C3 4 174
20. I/O (A17) 14 6 3 3 3 3 C4 5 177
21. I/O - - - 4 4 4 B3 6 183
22. I/O - - - 5 5 5 C5 7 186
23. I/O (TDI) 15 7 4 6 6 6 A2 8 189
24. I/O (TCK) 16 8 5 7 7 7 B4 9 195
25. I/O - - - - 8 8 C6 10 198
26. I/O - - - - 9 9 A3 11 201
GND - - - 8 10 10 C7 14 -
27. I/O - - - 9 11 11 A4 15 207
28. I/O - - - 10 12 12 A5 16 210
29. I/O (TMS) 17 9 6 11 13 13 B7 17 213
30. I/O 18 10 7 12 14 14 A6 18 219
31. I/O - - - - - 15 C8 19 222
32. I/O - - - - - 16 A7 20 225
33. I/O - - - 13 15 17 B8 21 234
34. I/O - 11 8 14 16 18 A8 22 237
35. I/O 19 12 9 15 17 19 B9 23 246
36. I/O 20 13 10 16 18 20 C9 24 249
GND 21 14 11 17 19 21 D9 25 -
VCC 22 15 12 18 20 22 D10 26 -
37. I/O 23 16 13 19 21 23 C10 27 255
38. I/O 24 17 14 20 22 24 B10 28 258
39. I/O - 18 15 21 23 25 A9 29 261
40. I/O - - - 22 24 26 A10 30 267
41. I/O - - - - - 27 A11 31 270

R
42. I/O - - - - - 28 C11 32 273
43. I/O 25 19 16 23 25 29 B11 33 279
44. I/O 26 20 17 24 26 30 A12 34 282
45. I/O - - - 25 27 31 B12 35 285
46. I/O - - - 26 28 32 A13 36 291
GND - - - 27 29 33 C12 37 -
47. I/O - - - - 30 34 A15 40 294
48. I/O - - - - 31 35 C13 41 297
49. I/O 27 21 18 28 32 36 B14 42 303
50. I/O - 22 19 29 33 37 A16 43 306
51. I/O - - - 30 34 38 B15 44 309
52. I/O - - - 31 35 39 C14 45 315
53. I/O 28 23 20 32 36 40 A17 46 318
54. I/O 29 24 21 33 37 41 B16 47 321
55. M1 (I/O) 30 25 22 34 38 42 C15 48 330
GND 31 26 23 35 39 43 D15 49 -
56. M0 (I/O) 32 27 24 36 40 44 A18 50 333
VCC 33 28 25 37 41 45 D16 55 -
57. M2 (I/O) 34 29 26 38 42 46 C16 56 336
58. GCK2 (I/O) 35 30 27 39 43 47 B17 57 339
59. I/O (HDC) 36 31 28 40 44 48 E16 58 348
60. I/O - - - 41 45 49 C17 59 351
61. I/O - - - 42 46 50 D17 60 354
62. I/O - 32 29 43 47 51 B18 61 360
63. I/O (LDC) 37 33 30 44 48 52 E17 62 363
64. I/O - - - - 49 53 F16 63 372
65. I/O - - - - 50 54 C18 64 375
GND - - - 45 51 55 G16 67 -
66. I/O - - - 46 52 56 E18 68 378
67. I/O - - - 47 53 57 F18 69 384
68. I/O 38 34 31 48 54 58 G17 70 387
69. I/O 39 35 32 49 55 59 G18 71 390
70. I/O - - - - - 60 H16 72 396
71. I/O - - - - - 61 H17 73 399
72. I/O - 36 33 50 56 62 H18 74 402
73. I/O - 37 34 51 57 63 J18 75 408
74. I/O 40 38 35 52 58 64 J17 76 411
75. I/O (ERR, INIT) 41 39 36 53 59 65 J16 77 414
VCC 42 40 37 54 60 66 J15 78 -
GND 43 41 38 55 61 67 K15 79 -
76. I/O 44 42 39 56 62 68 K16 80 420
77. I/O 45 43 40 57 63 69 K17 81 423
78. I/O - 44 41 58 64 70 K18 82 426
79. I/O - 45 42 59 65 71 L18 83 432
80. I/O - - - - - 72 L17 84 435
81. I/O - - - - - 73 L16 85 438
82. I/O 46 46 43 60 66 74 M18 86 444
83. I/O 47 47 44 61 67 75 M17 87 447
84. I/O - - - 62 68 76 N18 88 450
85. I/O - - - 63 69 77 P18 89 456
GND - - - 64 70 78 M16 90 -
86. I/O - - - - 71 79 T18 93 459

R
87. I/O - - - - 72 80 P17 94 468
88. I/O 48 48 45 65 73 81 N16 95 471
89. I/O 49 49 46 66 74 82 T17 96 480
90. I/O - - - 67 75 83 R17 97 483
91. I/O - - - 68 76 84 P16 98 486
92. I/O 50 50 47 69 77 85 U18 99 492
93. I/O 51 51 48 70 78 86 T16 100 495
GND 52 52 49 71 79 87 R16 101 -
DONE 53 53 50 72 80 88 U17 103 -
VCC 54 54 51 73 81 89 R15 106 -
PROG 55 55 52 74 82 90 V18 108 -
94. I/O (D7) 56 56 53 75 83 91 T15 109 504
95. GCK3 (I/O) 57 57 54 76 84 92 U16 110 507
96. I/O - - - 77 85 93 T14 111 516
97. I/O - - - 78 86 94 U15 112 519
98. I/O (D6) 58 58 55 79 87 95 V17 113 522
99. I/O - 59 56 80 88 96 V16 114 528
100. I/O - - - - 89 97 T13 115 531
101. I/O - - - - 90 98 U14 116 534
GND - - - 81 91 99 T12 119 -
102. I/O - - - 82 92 100 U13 120 540
103. I/O - - - 83 93 101 V13 121 543
104. I/O (D5) 59 60 57 84 94 102 U12 122 552
105. I/O (CS0) 60 61 58 85 95 103 V12 123 555
7
106. I/O - - - - - 104 T11 124 558
107. I/O - - - - - 105 U11 125 564
108. I/O - 62 59 86 96 106 V11 126 567
109. I/O - 63 60 87 97 107 V10 127 570
110. I/O (D4) 61 64 61 88 98 108 U10 128 576
111. I/O 62 65 62 89 99 109 T10 129 579
VCC 63 66 63 90 100 110 R10 130 -
GND 64 67 64 91 101 111 R9 131 -
112. I/O (D3) 65 68 65 92 102 112 T9 132 588
113. I/O (RS) 66 69 66 93 103 113 U9 133 591
114. I/O - 70 67 94 104 114 V9 134 600
115. I/O - - - 95 105 115 V8 135 603
116. I/O - - - - - 116 U8 136 612
117. I/O - - - - - 117 T8 137 615
118. I/O (D2) 67 71 68 96 106 118 V7 138 618
119. I/O 68 72 69 97 107 119 U7 139 624
120. I/O - - - 98 108 120 V6 140 627
121. I/O - - - 99 109 121 U6 141 630
GND - - - 100 110 122 T7 142 -
122. I/O - - - - 111 123 U5 145 636
123. I/O - - - - 112 124 T6 146 639
124. I/O (D1) 69 73 70 101 113 125 V3 147 642
125. I/O 70 74 71 102 114 126 V2 148 648
(RCLK-BUSY/RD
Y)
126. I/O - - - 103 115 127 U4 149 651
127. I/O - - - 104 116 128 T5 150 654
128. I/O (D0, DIN) 71 75 72 105 117 129 U3 151 660
129. I/O (DOUT) 72 76 73 106 118 130 T4 152 663

R
CCLK 73 77 74 107 119 131 V1 153 -
VCC 74 78 75 108 120 132 R4 154 -
130. I/O (TDO) 75 79 76 109 121 133 U2 159 -
GND 76 80 77 110 122 134 R3 160 -
131. I/O (A0, WS) 77 81 78 111 123 135 T3 161 9
132. GCK4 (A1, I/O) 78 82 79 112 124 136 U1 162 15
133. I/O - - - 113 125 137 P3 163 18
134. I/O - - - 114 126 138 R2 164 21
135. I/O (A2, CS1) 79 83 80 115 127 139 T2 165 27
136. I/O (A3) 80 84 81 116 128 140 N3 166 30
137. I/O - - - 117 129 141 P2 167 33
138. I/O - - - - 130 142 T1 168 42
GND - - - 118 131 143 M3 171 -
139. I/O - - - 119 132 144 P1 172 45
140. I/O - - - 120 133 145 N1 173 51
141. I/O (A4) 81 85 82 121 134 146 M2 174 54
142. I/O (A5) 82 86 83 122 135 147 M1 175 57
143. I/O - - - - - 148 L3 176 63
144. I/O - - - - 136 149 L2 177 66
145. I/O - 87 84 123 137 150 L1 178 69
146. I/O - 88 85 124 138 151 K1 179 75
147. I/O (A6) 83 89 86 125 139 152 K2 180 78
148. I/O (A7) 84 90 87 126 140 153 K3 181 81
GND 1 91 88 127 141 154 K4 182 -
Additional No Connect (N.C.) Connections for PQ208 and TQ176 Packages

PQ208 TQ176
195 1 39 65 104 143 158 167
196 3 51 66 105 144 169
206 12 52 91 107 155 170
207 13 53 92 117 156
208 38 54 102 118 157


Boundary Scan
Pin Description PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240
Order
VCC 2 128 142 155 183 J4 VCC* 212 -
1. I/O (A8) 3 129 143 156 184 J3 E8 213 111
2. I/O (A9) 4 130 144 157 185 J2 B7 214 114
3. I/O - 131 145 158 186 J1 A7 215 117
4. I/O - 132 146 159 187 H1 C7 216 123
5. I/O - - - 160 188 H2 D7 217 126
6. I/O - - - 161 189 H3 E7 218 129

R
Boundary Scan
Order
7. I/O (A10) 5 133 147 162 190 G1 A6 220 135
8. I/O (A11) 6 134 148 163 191 G2 B6 221 138
VCC - - - - - - VCC* 222 -
9. I/O - - - - - H4 C6 223 141
10. I/O - - - - - G4 F7 224 150
11. I/O - 135 149 164 192 F1 A5 225 153
12. I/O - 136 150 165 193 E1 B5 226 162
GND - 137 151 166 194 G3 GND* 227 -
13. I/O - - - - 195 F2 D6 228 165
14. I/O - - - 167 196 D1 C5 229 171
15. I/O - - 152 168 197 C1 A4 230 174
16. I/O - - 153 169 198 E2 E6 231 177
17. I/O (A12) 7 138 154 170 199 F3 B4 232 183
18. I/O (A13) 8 139 155 171 200 D2 D5 233 186
19. I/O - - - - - F4 A3 234 189
20. I/O - - - - - E4 C4 235 195
21. I/O - 140 156 172 201 B1 B3 236 198
22. I/O - 141 157 173 202 E3 F6 237 201
23. I/O (A14) 9 142 158 174 203 C2 A2 238 210
24. I/O (A15) 10 143 159 175 204 B2 C3 239 213
VCC 11 144 160 176 205 D3 VCC* 240 -
GND 12 1 1 1 2 D4 GND* 1 -
25. GCK1 (A16, I/O) 13 2 2 2 4 C3 D4 2 222
26. I/O (A17) 14 3 3 3 5 C4 B1 3 225
7
27. I/O - 4 4 4 6 B3 C2 4 231
28. I/O - 5 5 5 7 C5 E5 5 234
29. I/O (TDI) 15 6 6 6 8 A2 D3 6 237
30. I/O (TCK) 16 7 7 7 9 B4 C1 7 243
31. I/O - - 8 8 10 C6 D2 8 246
32. I/O - - 9 9 11 A3 G6 9 249
33. I/O - - - - 12 B5 E4 10 255
34. I/O - - - - 13 B6 D1 11 258
35. I/O - - - - - D5 E3 12 261
36. I/O - - - - - D6 E2 13 267
GND - 8 10 10 14 C7 GND* 14 -
37. I/O - 9 11 11 15 A4 F5 15 270
38. I/O - 10 12 12 16 A5 E1 16 273
39. I/O (TMS) 17 11 13 13 17 B7 F4 17 279
40. I/O 18 12 14 14 18 A6 F3 18 282
VCC - - - - - - VCC* 19 -
41. I/O - - - - - D7 F2 20 285
42. I/O - - - - - D8 F1 21 291
43. I/O - - - 15 19 C8 G4 23 294
44. I/O - - - 16 20 A7 G3 24 297
45. I/O - 13 15 17 21 B8 G2 25 306
46. I/O - 14 16 18 22 A8 G1 26 309
47. I/O 19 15 17 19 23 B9 G5 27 318
48. I/O 20 16 18 20 24 C9 H3 28 321
GND 21 17 19 21 25 D9 GND* 29 -
VCC 22 18 20 22 26 D10 VCC* 30 -
49. I/O 23 19 21 23 27 C10 H4 31 327

R
Boundary Scan
Order
50. I/O 24 20 22 24 28 B10 H5 32 330
51. I/O - 21 23 25 29 A9 J2 33 333
52. I/O - 22 24 26 30 A10 J1 34 339
53. I/O - - - 27 31 A11 J3 35 342
54. I/O - - - 28 32 C11 J4 36 345
55. I/O - - - - - D11 J5 38 351
56. I/O - - - - - D12 K1 39 354
VCC - - - - - - VCC* 40 -
57. I/O 25 23 25 29 33 B11 K2 41 357
58. I/O 26 24 26 30 34 A12 K3 42 363
59. I/O - 25 27 31 35 B12 J6 43 366
60. I/O - 26 28 32 36 A13 L1 44 369
GND - 27 29 33 37 C12 GND* 45 -
61. I/O - - - - - D13 L2 46 375
62. I/O - - - - - D14 K4 47 378
63. I/O - - - - 38 B13 L3 48 381
64. I/O - - - - 39 A14 M1 49 387
65. I/O - - 30 34 40 A15 K5 50 390
66. I/O - - 31 35 41 C13 M2 51 393
67. I/O 27 28 32 36 42 B14 L4 52 399
68. I/O - 29 33 37 43 A16 N1 53 402
69. I/O - 30 34 38 44 B15 M3 54 405
70. I/O - 31 35 39 45 C14 N2 55 411
71. I/O 28 32 36 40 46 A17 K6 56 414
72. I/O 29 33 37 41 47 B16 P1 57 417
73. M1 (I/O) 30 34 38 42 48 C15 N3 58 426
GND 31 35 39 43 49 D15 GND* 59 -
74. M0 (I/O) 32 36 40 44 50 A18 P2 60 429
VCC 33 37 41 45 55 D16 VCC* 61 -
75. M2 (I/O) 34 38 42 46 56 C16 M4 62 432
76. GCK2 (I/O) 35 39 43 47 57 B17 R2 63 435
77. I/O (HDC) 36 40 44 48 58 E16 P3 64 444
78. I/O - 41 45 49 59 C17 L5 65 447
79. I/O - 42 46 50 60 D17 N4 66 450
80. I/O - 43 47 51 61 B18 R3 67 456
81. I/O (LDC) 37 44 48 52 62 E17 P4 68 459
82. I/O - - 49 53 63 F16 K7 69 462
83. I/O - - 50 54 64 C18 M5 70 468
84. I/O - - - - 65 D18 R4 71 471
85. I/O - - - - 66 F17 N5 72 474
86. I/O - - - - - E15 P5 73 480
87. I/O - - - - - F15 L6 74 483
GND - 45 51 55 67 G16 GND* 75 -
88. I/O - 46 52 56 68 E18 R5 76 486
89. I/O - 47 53 57 69 F18 M6 77 492
90. I/O 38 48 54 58 70 G17 N6 78 495
91. I/O 39 49 55 59 71 G18 P6 79 504
VCC - - - - - - VCC* 80 -
92. I/O - - - 60 72 H16 R6 81 507
93. I/O - - - 61 73 H17 M7 82 510
94. I/O - - - - - G15 N7 84 516

R
Boundary Scan
Order
95. I/O - - - - - H15 P7 85 519
96. I/O - 50 56 62 74 H18 R7 86 522
97. I/O - 51 57 63 75 J18 L7 87 528
98. I/O 40 52 58 64 76 J17 N8 88 531
99. I/O (ERR, INIT) 41 53 59 65 77 J16 P8 89 534
VCC 42 54 60 66 78 J15 VCC* 90 -
GND 43 55 61 67 79 K15 GND* 91 -
100. I/O 44 56 62 68 80 K16 L8 92 540
101. I/O 45 57 63 69 81 K17 P9 93 543
102. I/O - 58 64 70 82 K18 R9 94 546
103. I/O - 59 65 71 83 L18 N9 95 552
104. I/O - - - 72 84 L17 M9 96 555
105. I/O - - - 73 85 L16 L9 97 558
106. I/O - - - - - L15 R10 99 564
107. I/O - - - - - M15 P10 100 567
VCC - - - - - - VCC* 101 -
108. I/O 46 60 66 74 86 M18 N10 102 570
109. I/O 47 61 67 75 87 M17 K9 103 576
110. I/O - 62 68 76 88 N18 R11 104 579
111. I/O - 63 69 77 89 P18 P11 105 588
GND - 64 70 78 90 M16 GND* 106 -
112. I/O - - - - - N15 M10 107 591
113. I/O - - - - - P15 N11 108 600
114. I/O - - - - 91 N17 R12 109 603
7
115. I/O - - - - 92 R18 L10 110 606
116. I/O - - 71 79 93 T18 P12 111 612
117. I/O - - 72 80 94 P17 M11 112 615
118. I/O 48 65 73 81 95 N16 R13 113 618
119. I/O 49 66 74 82 96 T17 N12 114 624
120. I/O - 67 75 83 97 R17 P13 115 627
121. I/O - 68 76 84 98 P16 K10 116 630
122. I/O 50 69 77 85 99 U18 R14 117 636
123. I/O 51 70 78 86 100 T16 N13 118 639
GND 52 71 79 87 101 R16 GND* 119 -
DONE 53 72 80 88 103 U17 P14 120 -
VCC 54 73 81 89 106 R15 VCC* 121 -
PROG 55 74 82 90 108 V18 M12 122 -
124. I/O (D7) 56 75 83 91 109 T15 P15 123 648
125. GCK3 (I/O) 57 76 84 92 110 U16 N14 124 651
126. I/O - 77 85 93 111 T14 L11 125 660
127. I/O - 78 86 94 112 U15 M13 126 663
128. I/O - - - - - R14 N15 127 666
129. I/O - - - - - R13 M14 128 672
130. I/O (D6) 58 79 87 95 113 V17 J10 129 675
131. I/O - 80 88 96 114 V16 L12 130 678
132. I/O - - 89 97 115 T13 M15 131 684
133. I/O - - 90 98 116 U14 L13 132 687
134. I/O - - - - 117 V15 L14 133 690
135. I/O - - - - 118 V14 K11 134 696
GND - 81 91 99 119 T12 GND* 135 -
136. I/O - - - - - R12 L15 136 699

R
Boundary Scan
Order
137. I/O - - - - - R11 K12 137 708
138. I/O - 82 92 100 120 U13 K13 138 711
139. I/O - 83 93 101 121 V13 K14 139 714
VCC - - - - - - VCC* 140 -
140. I/O (D5) 59 84 94 102 122 U12 K15 141 720
141. I/O (CS0) 60 85 95 103 123 V12 J12 142 723
142. I/O - - - 104 124 T11 J13 144 726
143. I/O - - - 105 125 U11 J14 145 732
144. I/O - 86 96 106 126 V11 J15 146 735
145. I/O - 87 97 107 127 V10 J11 147 738
146. I/O (D4) 61 88 98 108 128 U10 H13 148 744
147. I/O 62 89 99 109 129 T10 H14 149 747
VCC 63 90 100 110 130 R10 VCC* 150 -
GND 64 91 101 111 131 R9 GND* 151 -
148. I/O (D3) 65 92 102 112 132 T9 H12 152 756
149. I/O (RS) 66 93 103 113 133 U9 H11 153 759
150. I/O - 94 104 114 134 V9 G14 154 768
151. I/O - 95 105 115 135 V8 G15 155 771
152. I/O - - - 116 136 U8 G13 156 780
153. I/O - - - 117 137 T8 G12 157 783
154. I/O (D2) 67 96 106 118 138 V7 G11 159 786
155. I/O 68 97 107 119 139 U7 F15 160 792
VCC - - - - - - VCC* 161 -
156. I/O - 98 108 120 140 V6 F14 162 795
157. I/O - 99 109 121 141 U6 F13 163 798
158. I/O - - - - - R8 G10 164 804
159. I/O - - - - - R7 E15 165 807
GND - 100 110 122 142 T7 GND* 166 -
160. I/O - - - - - R6 E14 167 810
161. I/O - - - - - R5 F12 168 816
162. I/O - - - - 143 V5 E13 169 819
163. I/O - - - - 144 V4 D15 170 822
164. I/O - - 111 123 145 U5 F11 171 828
165. I/O - - 112 124 146 T6 D14 172 831
166. I/O (D1) 69 101 113 125 147 V3 E12 173 834
167. I/O (RCLK-BUSY/RDY) 70 102 114 126 148 V2 C15 174 840
168. I/O - 103 115 127 149 U4 D13 175 843
169. I/O - 104 116 128 150 T5 C14 176 846
170. I/O (D0, DIN) 71 105 117 129 151 U3 F10 177 855
171. I/O (DOUT) 72 106 118 130 152 T4 B15 178 858
CCLK 73 107 119 131 153 V1 C13 179 -
VCC 74 108 120 132 154 R4 VCC* 180 -
172. I/O (TDO) 75 109 121 133 159 U2 A15 181 -
GND 76 110 122 134 160 R3 GND* 182 -
173. I/O (A0, WS) 77 111 123 135 161 T3 A14 183 9
174. GCK4 (A1, I/O) 78 112 124 136 162 U1 B13 184 15
175. I/O - 113 125 137 163 P3 E11 185 18
176. I/O - 114 126 138 164 R2 C12 186 21
177. I/O (CS1, A2) 79 115 127 139 165 T2 A13 187 27
178. I/O (A3) 80 116 128 140 166 N3 B12 188 30
179. I/O - - - - - P4 F9 189 33

R
Boundary Scan
Order
180. I/O - - - - - N4 D11 190 39
181. I/O - 117 129 141 167 P2 A12 191 42
182. I/O - - 130 142 168 T1 C11 192 45
183. I/O - - - - 169 R1 B11 193 51
184. I/O - - - - 170 N2 E10 194 54
- - - - - - - GND* -
GND - 118 131 143 171 M3 - 196 -
185. I/O - 119 132 144 172 P1 A11 197 57
186. I/O - 120 133 145 173 N1 D10 198 66
187. I/O - - - - - M4 C10 199 69
188. I/O - - - - - L4 B10 200 75
VCC - - - - - - VCC* 201 -
189. I/O (A4) 81 121 134 146 174 M2 A10 202 78
190. I/O (A5) 82 122 135 147 175 M1 D9 203 81
191. I/O - - - 148 176 L3 C9 205 87
192. I/O - - 136 149 177 L2 B9 206 90
193. I/O - 123 137 150 178 L1 A9 207 93
194. I/O - 124 138 151 179 K1 E9 208 99
195. I/O (A6) 83 125 139 152 180 K2 C8 209 102
196. I/O (A7) 84 126 140 153 181 K3 B8 210 105
GND 1 127 141 154 182 K4 GND* 211 -
7
Additional No Connect (N.C.) Connections for PQ208 and PQ240 Packages
PQ208 PQ240
1 53 105 157 208 22 143 219
3 54 107 158 37 158
51 102 155 206 83 195
52 104 156 207 98 204
Notes: * Pins labeled VCC* are internally bonded to a VCC plane within the BG225 package. The external pins are: B2, D8, H15, R8,
B14, R1, H1, and R15.
Pins labeled GND* are internally bonded to a ground plane within the BG225 package. The external pins are: A1, D12, G7,
G9, H6, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8.
Boundary Scan Bit 0 = TDO.T

Pin Description PQ160 HQ208 HQ240 PG299 BG225 BG352 Boundary Scan Order
VCC 142 183 212 K1 VCC* VCC* -
1. I/O (A8) 143 184 213 K2 E8 D14 138
2. I/O (A9) 144 185 214 K3 B7 C14 141
3. I/O 145 186 215 K5 A7 A15 147
4. I/O 146 187 216 K4 C7 B15 150
5. I/O - 188 217 J1 D7 C15 153
6. I/O - 189 218 J2 E7 D15 159
7. I/O (A10) 147 190 220 H1 A6 A16 162

R
8. I/O (A11) 148 191 221 J3 B6 B16 165
9. I/O - - - H2 - C17 171
10. I/O - - - G1 - B18 174
VCC - - 222 E1 VCC* VCC* -
11. I/O - - 223 H3 C6 C18 177
12. I/O - - 224 G2 F7 D17 183
13. I/O 149 192 225 H4 A5 A20 186
14. I/O 150 193 226 F2 B5 B19 189
GND 151 194 227 F1 GND* GND* -
15. I/O - - - H5 - C19 195
16. I/O - - - G3 - D18 198
17. I/O - 195 228 D1 D6 A21 201
18. I/O - 196 229 G4 C5 B20 207
19. I/O 152 197 230 E2 A4 C20 210
20. I/O 153 198 231 F3 E6 B21 213
21. I/O (A12) 154 199 232 G5 B4 B22 219
22. I/O (A13) 155 200 233 C1 D5 C21 222
23. I/O - - - F4 - D20 225
24. I/O - - - E3 - A23 234
25. I/O - - 234 D2 A3 D21 237
26. I/O - - 235 C2 C4 C22 243
27. I/O 156 201 236 F5 B3 B24 246
28. I/O 157 202 237 E4 F6 C23 249
29. I/O (A14) 158 203 238 D3 A2 D22 258
30. I/O (A15) 159 204 239 C3 C3 C24 261
VCC 160 205 240 A2 VCC* VCC* -
GND 1 2 1 B1 GND* GND* -
31. GCK1 (A16, I/O) 2 4 2 D4 D4 D23 270
32. I/O (A17) 3 5 3 B2 B1 C25 273
33. I/O 4 6 4 B3 C2 D24 279
34. I/O 5 7 5 E6 E5 E23 282
35. I/O (TDI) 6 8 6 D5 D3 C26 285
36. I/O (TCK) 7 9 7 C4 C1 E24 294
37. I/O - - - A3 - F24 297
38. I/O - - - D6 - E25 303
39. I/O 8 10 8 E7 D2 D26 306
40. I/O 9 11 9 B4 G6 G24 309
41. I/O - 12 10 C5 E4 F25 315
42. I/O - 13 11 A4 D1 F26 318
43. I/O - - 12 D7 E3 H23 321
44. I/O - - 13 C6 E2 H24 327
45. I/O - - - E8 - G25 330
46. I/O - - - B5 - G26 333
GND 10 14 14 A5 GND* GND* -
47. I/O 11 15 15 B6 F5 J23 339
48. I/O 12 16 16 D8 E1 J24 342
49. I/O (TMS) 13 17 17 C7 F4 H25 345
50. I/O 14 18 18 B7 F3 K23 351
VCC - - 19 A6 VCC* VCC* -
51. I/O - - 20 C8 F2 L24 354
52. I/O - - 21 E9 F1 K25 357
53. I/O - - - B8 - L25 363

R
54. I/O - - - A8 - L26 366
55. I/O - 19 23 C9 G4 M23 369
56. I/O - 20 24 B9 G3 M24 375
57. I/O 15 21 25 E10 G2 M25 378
58. I/O 16 22 26 A9 G1 M26 381
59. I/O 17 23 27 D10 G5 N24 390
60. I/O 18 24 28 C10 H3 N25 393
GND 19 25 29 A10 GND* GND* -
VCC 20 26 30 A11 VCC* VCC* -
61. I/O 21 27 31 B10 H4 N26 399
62. I/O 22 28 32 B11 H5 P25 402
63. I/O 23 29 33 C11 J2 P23 405
64. I/O 24 30 34 E11 J1 P24 411
65. I/O - 31 35 D11 J3 R26 414
66. I/O - 32 36 A12 J4 R25 417
67. I/O - - - B12 - R24 423
68. I/O - - - A13 - R23 426
69. I/O - - 38 E12 J5 T26 429
70. I/O - - 39 B13 K1 T25 435
VCC - - 40 A16 VCC* VCC* -
71. I/O 25 33 41 A14 K2 U24 438
72. I/O 26 34 42 C13 K3 V25 441
73. I/O 27 35 43 B14 J6 V24 447
74. I/O 28 36 44 D13 L1 U23 450
7
GND 29 37 45 A15 GND* GND* -
75. I/O - - - B15 - Y26 453
76. I/O - - - E13 - W25 459
77. I/O - - 46 C14 L2 W24 462
78. I/O - - 47 A17 K4 V23 465
79. I/O - 38 48 D14 L3 AA26 471
80. I/O - 39 49 B16 M1 Y25 474
81. I/O 30 40 50 C15 K5 Y24 477
82. I/O 31 41 51 E14 M2 AA25 483
83. I/O - - - A18 - AB25 486
84. I/O - - - D15 - AA24 489
85. I/O 32 42 52 C16 L4 Y23 495
86. I/O 33 43 53 B17 N1 AC26 498
87. I/O 34 44 54 B18 M3 AA23 501
88. I/O 35 45 55 E15 N2 AB24 507
89. I/O 36 46 56 D16 K6 AD25 510
90. I/O 37 47 57 C17 P1 AC24 513
91. M1 (I/O) 38 48 58 A20 N3 AB23 522
GND 39 49 59 A19 GND* GND* -
92. M0 (I/O) 40 50 60 C18 P2 AD24 525
VCC 41 55 61 B20 VCC* VCC* -
93. M2 (I/O) 42 56 62 D17 M4 AC23 528
94. GCK2 (I/O) 43 57 63 B19 R2 AE24 531
95. I/O (HDC) 44 58 64 C19 P3 AD23 540
96. I/O 45 59 65 F16 L5 AC22 543
97. I/O 46 60 66 E17 N4 AF24 546
98. I/O 47 61 67 D18 R3 AD22 552
99. I/O (LDC) 48 62 68 C20 P4 AE23 555

R
100. I/O - - - F17 - AE22 558
101. I/O - - - G16 - AF23 564
102. I/O 49 63 69 D19 K7 AD20 567
103. I/O 50 64 70 E18 M5 AE21 570
104. I/O - 65 71 D20 R4 AF21 576
105. I/O - 66 72 G17 N5 AC19 579
106. I/O - - 73 F18 P5 AD19 582
107. I/O - - 74 H16 L6 AE20 588
108. I/O - - - E19 - AF20 591
109. I/O - - - F19 - AC18 594
GND 51 67 75 E20 GND* GND* -
110. I/O 52 68 76 H17 R5 AD18 600
111. I/O 53 69 77 G18 M6 AE19 603
112. I/O 54 70 78 G19 N6 AC17 606
113. I/O 55 71 79 H18 P6 AD17 612
VCC - - 80 F20 VCC* VCC* -
114. I/O - 72 81 J16 R6 AE17 615
115. I/O - 73 82 G20 M7 AE16 618
116. I/O - - - H20 - AF16 624
117. I/O - - - J18 - AC15 627
118. I/O - - 84 J19 N7 AD15 630
119. I/O - - 85 K16 P7 AE15 636
120. I/O 56 74 86 J20 R7 AF15 639
121. I/O 57 75 87 K17 L7 AD14 642
122. I/O 58 76 88 K18 N8 AE14 648
123. I/O (ERR, INIT) 59 77 89 K19 P8 AF14 651
VCC 60 78 90 L20 VCC* VCC* -
GND 61 79 91 K20 GND* GND* -
124. I/O 62 80 92 L19 L8 AE13 660
125. I/O 63 81 93 L18 P9 AC13 663
126. I/O 64 82 94 L16 R9 AD13 672
127. I/O 65 83 95 L17 N9 AF12 675
128. I/O - 84 96 M20 M9 AE12 678
129. I/O - 85 97 M19 L9 AD12 684
130. I/O - - - N20 - AC12 687
131. I/O - - - M18 - AF11 690
132. I/O - - 99 N19 R10 AE11 696
133. I/O - - 100 P20 P10 AD11 699
VCC - - 101 T20 VCC* VCC* -
134. I/O 66 86 102 N18 N10 AE9 702
135. I/O 67 87 103 P19 K9 AD9 708
136. I/O 68 88 104 N17 R11 AC10 711
137. I/O 69 89 105 R19 P11 AF7 714
GND 70 90 106 R20 GND* GND* -
138. I/O - - - N16 - AE8 720
139. I/O - - - P18 - AD8 723
140. I/O - - 107 U20 M10 AC9 726
141. I/O - - 108 P17 N11 AF6 732
142. I/O - 91 109 T19 R12 AE7 735
143. I/O - 92 110 R18 L10 AD7 738
144. I/O 71 93 111 P16 P12 AE6 744
145. I/O 72 94 112 V20 M11 AE5 747

R
146. I/O - - - R17 - AD6 750
147. I/O - - - T18 - AC7 756
148. I/O 73 95 113 U19 R13 AF4 759
149. I/O 74 96 114 V19 N12 AF3 768
150. I/O 75 97 115 R16 P13 AD5 771
151. I/O 76 98 116 T17 K10 AE3 774
152. I/O 77 99 117 U18 R14 AD4 780
153. I/O 78 100 118 X20 N13 AC5 783
GND 79 101 119 W20 GND* GND* -
DONE 80 103 120 V18 P14 AD3 -
VCC 81 106 121 X19 VCC* VCC* -
PROG 82 108 122 U17 M12 AC4 -
154. I/O (D7) 83 109 123 W19 P15 AD2 792
155. GCK3 (I/O) 84 110 124 W18 N14 AC3 795
156. I/O 85 111 125 T15 L11 AB4 804
157. I/O 86 112 126 U16 M13 AD1 807
158. I/O - - 127 V17 N15 AA4 810
159. I/O - - 128 X18 M14 AA3 816
160. I/O - - - U15 - AB2 819
161. I/O - - - T14 - AC1 828
162. I/O (D6) 87 113 129 W17 J10 Y3 831
163. I/O 88 114 130 V16 L12 AA2 834
164. I/O 89 115 131 X17 M15 AA1 840
165. I/O 90 116 132 U14 L13 W4 843
7
166. I/O - 117 133 V15 L14 W3 846
167. I/O - 118 134 T13 K11 Y2 852
168. I/O - - - W16 - Y1 855
169. I/O - - - W15 - V4 858
GND 91 119 135 X16 GND* GND* -
170. I/O - - 136 U13 L15 V3 864
171. I/O - - 137 V14 K12 W2 867
172. I/O 92 120 138 W14 K13 U4 870
173. I/O 93 121 139 V13 K14 U3 876
VCC - - 140 X15 VCC* VCC* -
174. I/O (D5) 94 122 141 T12 K15 V2 879
175. I/O (CS0) 95 123 142 X14 J12 V1 882
176. I/O - - - X13 - T1 888
177. I/O - - - V12 - R4 891
178. I/O - 124 144 W12 J13 R3 894
179. I/O - 125 145 T11 J14 R2 900
180. I/O 96 126 146 X12 J15 R1 903
181. I/O 97 127 147 U11 J11 P3 906
182. I/O (D4) 98 128 148 V11 H13 P2 912
183. I/O 99 129 149 W11 H14 P1 915
VCC 100 130 150 X10 VCC* VCC* -
GND 101 131 151 X11 GND* GND* -
184. I/O (D3) 102 132 152 W10 H12 N2 924
185. I/O (RS) 103 133 153 V10 H11 N4 927
186. I/O 104 134 154 T10 G14 N3 936
187. I/O 105 135 155 U10 G15 M1 939
188. I/O - 136 156 X9 G13 M2 942
189. I/O - 137 157 W9 G12 M3 948

R
190. I/O - - - X8 - M4 951
191. I/O - - - V9 - L1 954
192. I/O (D2) 106 138 159 W8 G11 J1 960
193. I/O 107 139 160 X7 F15 K3 963
VCC - - 161 X5 VCC* VCC*
194. I/O 108 140 162 V8 F14 J2 966
195. I/O 109 141 163 W7 F13 J3 972
196. I/O - - 164 U8 G10 K4 975
197. I/O - - 165 W6 E15 G1 978
GND 110 142 166 X6 GND* GND*
198. I/O - - - T8 - H2 984
199. I/O - - - V7 - H3 987
200. I/O - - 167 X4 E14 J4 990
201. I/O - - 168 U7 F12 F1 996
202. I/O - 143 169 W5 E13 G2 999
203. I/O - 144 170 V6 D15 G3 1002
204. I/O 111 145 171 T7 F11 F2 1008
205. I/O 112 146 172 X3 D14 E2 1011
206. I/O (D1) 113 147 173 U6 E12 F3 1014
207. I/O (RCLK-BUSY/RDY) 114 148 174 V5 C15 G4 1020
208. I/O - - - W4 - D2 1023
209. I/O - - - W3 - F4 1032
210. I/O 115 149 175 T6 D13 E3 1035
211. I/O 116 150 176 U5 C14 C2 1038
212. I/O (D0, DIN) 117 151 177 V4 F10 D3 1044
213. I/O (DOUT) 118 152 178 X1 B15 E4 1047
CCLK 119 153 179 V3 C13 C3 -
VCC 120 154 180 W1 VCC* VCC* -
214. I/O (TDO) 121 159 181 U4 A15 D4 0
GND 122 160 182 X2 GND* GND* -
215. I/O (A0, WS) 123 161 183 W2 A14 B3 9
216. GCK4 (A1, I/O) 124 162 184 V2 B13 C4 15
217. I/O 125 163 185 R5 E11 D5 18
218. I/O 126 164 186 T4 C12 A3 21
219. I/O (A2, CS1) 127 165 187 U3 A13 D6 27
220. I/O (A3) 128 166 188 V1 B12 C6 30
221. I/O - - - R4 - B5 33
222. I/O - - - P5 - A4 39
223. I/O - - 189 U2 F9 C7 42
224. I/O - - 190 T3 D11 B6 45
225. I/O 129 167 191 U1 A12 A6 51
226. I/O 130 168 192 P4 C11 D8 54
227. I/O - 169 193 R3 B11 B7 57
228. I/O - 170 194 N5 E10 A7 63
229. I/O - - 195 T2 - D9 66
230. I/O - - - R2 - C9 69
GND 131 171 196 T1 GND* GND* -
231. I/O 132 172 197 N4 A11 B8 75
232. I/O 133 173 198 P3 D10 D10 78
233. I/O - - 199 P2 C10 C10 81
234. I/O - - 200 N3 B10 B9 87
VCC - - 201 R1 VCC* VCC* -

R
235. I/O - - - M5 - B11 90
236. I/O - - - P1 - A11 93
237. I/O (A4) 134 174 202 N1 A10 D12 99
238. I/O (A5) 135 175 203 M3 D9 C12 102
239. I/O - 176 205 M2 C9 B12 105
240. I/O 136 177 206 L5 B9 A12 111
241. I/O 137 178 207 M1 A9 C13 114
242. I/O 138 179 208 L4 E9 B13 117
243. I/O (A6) 139 180 209 L3 C8 A13 126
244. I/O (A7) 140 181 210 L2 B8 B14 129
GND 141 182 211 L1 GND* GND* -
Additional No Connect (N.C.) Connections for HQ208 and HQ240 Packages

HQ208 HQ240
206 102 219
207 104 22
208 105 37
1 107 83
3 155 98
51 156 143
52 157 158
53 158 204
54 - - 7
Notes: * Pins labeled VCC* are internally bonded to a VCC plane within the BG225 and BG352 packages. The external pins for the
BG225 are: B2, D8, H15, R8, B14, R1, H1, and R15. The external pins for the BG352 are: A10, A17, B2, B25, D13, D19, D7,
G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC14, AC20, AC8, AE2, AE25, AF10, and AF17.
Pins labeled GND* are internally bonded to a ground plane within the BG225 and BG352 packages. The external pins for the
BG225 are: A1, D12, G7, G9, H6, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. The external pins for the BG352 are:
A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, AB1, AB26, AE1, AE26, AF1,
AF13, AF19, AF2, AF22, AF25, AF26, AF5, AF8.
Boundary Scan Bit 0 = TDO.T


R
Product Availability
PINS 64 84 100 100 144 156 160 176 191 208 208 223 225 240 240 299 352
High-Perf.
High-Perf.
Ceram.
Ceram.
Ceram.
Ceram.
VQFP
PQFP
VQFP
PQFP
PQFP
PQFP
TQFP
TQFP
PLCC
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
PGA
PGA
PGA
BGA
PGA
BGA
QFP
QFP
TYPE
HQ208
HQ240
PQ100
VQ100
PG156
PQ160
PG191
PQ208
PG223
BG225
PQ240
PG299
BG352
TQ144
TQ176
VQ64*
PC84
CODE
-6 CI CI CI CI CI CI
XC5202 -4 C C C C C C
-3 C C C C C C
XC5204 -4 C C C C C C
-3 C C C C C C
-6 CI CI CI CI CI CI CI CI
XC5206 -4 C C C C C C C C
-3 C C C C C C C C
XC5210 -4 C C C C C C C C
-3 C C C C C C C C
-5 C C C C C C
XC5215 -4 C C C C C C
-3 C C C C C C
7/8/98
C = Commercial TJ = 0° to +85°C
I= Industrial TJ = -40°C to +100°C
* VQ64 package supports Master Serial, Slave Serial, and Express configuration modes only.
User I/O Per Package

Max
Package Type
Device I/O VQ64 PC84 PQ100 VQ100 TQ144 PG156 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 PQ240 PG299 BG352
XC5202 84 52 65 81 81 84 84
XC5204 124 65 81 81 117 124 124
XC5206 148 65 81 81 117 133 148 148 148
XC5210 196 65 117 133 149 164 196 196 196
XC5215 244 133 164 196 197 244 244
7/8/98
Ordering Information
Example: XC5210-6PQ208C
Device Type Temperature Range
Speed Grade Number of Pins
Package Type

R
Revisions
Version Description
12/97 Rev 5.0 added -3, -4 specification
7/98 Rev 5.1 added Spartan family to comparison, removed HQ304
11/98 Rev 5.2 All specifications made final.

XC 5200

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Product Obsolete or Under Obsolescence

November 5, 1998 (Version 5.2) 0 7* Product Specification

Features - Footprint compatibility in common packages within

Table 1: XC5200 Field-Programmable Gate Array Family Members

Device XC5202 XC5204 XC5206 XC5210 XC5215

Logic Cells 256 480 784 1,296 1,936

Max Logic Gates 3,000 6,000 10,000 16,000 23,000

VersaBlock Array 8x8 10 x 12 14 x 14 18 x 18 22 x 22

CLBs 64 120 196 324 484

Flip-Flops 256 480 784 1,296 1,936

I/Os 84 124 148 196 244

TBUFs per Longline 10 14 16 20 24

November 5, 1998 (Version 5.2) 7-83

XC5200 Series Field Programmable Gate Arrays

XC5200 Family Compared to Table 2: Xilinx Field-Programmable Gate Array

Configurable Logic Block (CLB) Resources Global buffers 4 8 8 2

7-84 November 5, 1998 (Version 5.2)

XC5200 Series Field Programmable Gate Arrays

XC3000 family: XC5200 devices support an additional pro-

12 MHz are available.

also be configured as a cascade chain allowing decode of

Figure 3: XC5200 Logic Cell (Four LCs per CLB)

November 5, 1998 (Version 5.2) 7-85

XC5200 Series Field Programmable Gate Arrays

7-86 November 5, 1998 (Version 5.2)

XC5200 Series Field Programmable Gate Arrays

self-diagnostics, create systems capable of being reconfig- LC1

Figure 5: Two LUTs in Parallel Combined to Create a

November 5, 1998 (Version 5.2) 7-87

XC5200 Series Field Programmable Gate Arrays

Figure 6: XC5200 CY_MUX Used for Adder Carry Propagate

7-88 November 5, 1998 (Version 5.2)

XC5200 Series Field Programmable Gate Arrays

November 5, 1998 (Version 5.2) 7-89

XC5200 Series Field Programmable Gate Arrays

In XC5200-Series devices, the flip-flops can be used as LC2

Figure 9: XC5200 3-State Buffers

7-90 November 5, 1998 (Version 5.2)

XC5200 Series Field Programmable Gate Arrays

Figure 10: 3-State Buffers Implement a Multiplexer

November 5, 1998 (Version 5.2) 7-91

XC5200 Series Field Programmable Gate Arrays

Pull-up and Pull-down Resistors

7-92 November 5, 1998 (Version 5.2)

XC5200 Series Field Programmable Gate Arrays

to Vcc. The configurable pull-down resistor is an n-channel

November 5, 1998 (Version 5.2) 7-93

XC5200 Series Field Programmable Gate Arrays

Direct South X5724

Figure 14: VersaBlock Details

7-94 November 5, 1998 (Version 5.2)

XC5200 Series Field Programmable Gate Arrays

Matrix through a hierarchy of different-length metal seg-

GRM GRM GRM

Versa- Versa- Versa-

Versa- Versa- Versa-

Versa- Versa- Versa-

Six Levels of Routing Hierarchy GRM 4 4

Direct Connects X4963

Figure 15: XC5200 Interconnect Structure