89c420 Userguide

Ultra-High-Speed Flash
Microcontroller User’s Guide
33
16kB 1kB
FLASH MEMORY SRAM
DUAL DATA 25
MIPS
POINTERS FOUR
HIGH-SPEED 8-BIT
WITH AUTO- ONE CLOCK-CYCLE PARALLEL
SELECT 8051 MICROPROCESSOR PORTS
INCREMENT/ 5
DECREMENT
1
DUAL SERIAL
PORTS 0
ORIGINAL
8051 DS89C420
DS89C420
SECTION 1: INTRODUCTION
Dallas Semiconductor’s DS89C420 is an 8051-compatible micro- priority, and a crystal multiplier. The device provides 256 bytes of
controller that provides improved performance and power con- RAM for variables and stack; 128 bytes can be reached using
sumption when compared to the original 8051 version. It retains direct or indirect addressing, or using indirect addressing only.
instruction set and object code compatibility with the 8051, yet In addition to improved efficiency, the DS89C420 can operate at
performs the same operations in fewer clock cycles. a maximum clock rate of 33MHz. Combined with the 12 times per-
Consequently, greater throughput is possible for the same crys- formance, this allows for a maximum performance of 33 million
tal speed. As an alternative, the DS89C420 can be run at a instructions per second (MIPs). This level of computing power is
reduced frequency to save power. The more efficient design comparable to many 16-bit processors, but without the added
allows a much slower crystal speed to get the same results as an expense and complexity if implementing a 16-bit interface.
original 8051, using much less power.
The DS89C420 incorporates a power-management mode that
The fundamental innovation of the DS89C420 is the use of only allows the device to dynamically vary the internal clock speed
one clock per instruction cycle compared with 12 for the original from 1 clock per cycle (default) to 1024 clocks per cycle. Because
8051. This results in up to 12 times improvement in performance power consumption is directly proportional to clock speed, the
over the original 8051 architecture and up to four times improve- device can reduce its operating frequency during periods of little
ment over other Dallas Semiconductor high-speed microcon- switchback. This greatly reduces power consumption. The switch-
trollers. The DS89C420 provides several peripherals and features back feature allows the device to quickly return to highest speed
in addition to all of the standard features of an 80C32. These operation upon receipt of an interrupt or serial port activity, allow-
include 16kB of on-chip flash memory, 1kB of on-chip RAM, four 8- ing the device to respond to external events while in power-man-
bit I/O ports, three 16-bit timer/counters, two on-chip UARTs, dual agement mode.
data pointers, an on-chip watchdog timer, five levels of interrupt
________________________________________________________________________ Maxim Integrated Products 1

SECTION 2: ORDERING INFORMATION

The DS89C420 family follows the part numbering convention shown below. Note that not all combinations of devices may be current-
ly available. Contact a Maxim/Dallas Semiconductor sales office for up-to-date details.
DS89C420-QCL
SPEED: L 33MHz
TEMPERATURE: C 0°C to +70°C
N -40°C to +85°C
PACKAGE: M PDIP
Q PLCC
E Thin Quad Flat Pack (TQFP)
OPERATING VOLTAGE: 0 +5V
MEMORY TYPE: 9 Flash
SECTION 3: ARCHITECTURE
The DS89C420 architecture is based on the industry-standard 87C52 and executes the standard 8051 instruction set. The core is an
accumulator-based architecture using internal registers for data storage and peripheral control. This section provides a brief descrip-
tion of each architecture feature. Details concerning the programming model, instruction set, and register description are provided in
Section 4.
ALU
The ALU is responsible for math functions, comparisons, and general decision making in the DS89C420. The ALU is not used explic-
itly by software. Instruction decoding prepares the ALU automatically and passes it the appropriate data. The ALU primarily uses two
special-function registers (SFRs) as the source and destination for all operations. These are the accumulator and B register. The ALU
also provides status information in the program status register. The SFRs are described in the following pages.
Special-Function Registers
All peripherals and operations that are not explicitly controlled by instructions in the DS89C420 are controlled through SFRs. All SFRs are
described in Section 4. The most commonly used registers that are basic to the architecture are also described in the following pages.
Accumulator
The accumulator is the primary register used in the DS89C420. It is a source and destination for many operations involving math, data
movement, and decisions. Although it can be bypassed, most high-speed instructions require the use of the accumulator (A or ACC)
as one argument.
B Register
The B register is used as the second 8-bit argument in multiply and divide operations. When not used for these purposes, the B reg-
ister can be used as a general-purpose register.
Program Status Word
The program status word holds a selection of bit flags that include the carry flag, auxiliary carry flag, general-purpose flag, register
bank select, overflow flag, and parity flag.
Data Pointer(s)
The data pointers (DPTR and DPTR1) are used to assign a memory address for the MOVX instructions. This address can point to a
data memory location, either on- or off-chip, or a memory-mapped peripheral. When moving data from one memory area to another or
from memory to a memory-mapped peripheral, a pointer is needed for both the source and destination. The user can select the active
pointer through a dedicated SFR bit (Sel = DPS.0), or can activate an automatic toggling feature for altering the pointer selection (TSL
= DPS.5). An additional feature, if selected, provides automatic incrementing or decrementing of the current DPTR.
Stack Pointer
The stack pointer denotes the register location at the top of the stack, which is the last used value. The user can place the stack any-
where in the scratchpad RAM by setting the stack pointer to the desired location, although the lower bytes are normally used for work-
ing registers.
______________________________________________________________________________________________ 2
I/O Ports
The DS89C420 offers four 8-bit I/O ports. Each I/O port is represented by an SFR location, and can be written or read. The I/O port has
a latch that contains the value written by software. In general, software reads the state of external pins during a read operation.
Timer/Counters
Three 16-bit timer/counters are available in the DS89C420. Each timer is contained in two SFR locations that can be written or read by
software. The timers are controlled by other SFRs described in Section 4.
UARTs
The DS89C420 provides two UARTs, which are controlled and accessed by SFRs. Each UART has an address that is used to read and
write the UART. The same address is used for both read and write operations, which are distinguished by the instruction. Each UART
is controlled by its own SFR control register.
Scratchpad Registers (RAM)
The high-speed core provides 256 bytes of scratchpad RAM for general-purpose data and variable storage. The first 128 bytes are
directly available to software. The second 128 are available through indirect addressing. Selected portions of this RAM have other
optional functions.
Stack
The stack is a RAM area that the DS89C420 uses to store return address information during calls and interrupts. The user can also
place variables on the stack when necessary. The stack pointer designates the RAM location that is the top of the stack. Thus, depend-
ing on the value of the stack pointer, the stack can be located anywhere in the 256 bytes of RAM. A common location would be in the
upper 128 bytes of RAM, as these locations are accessible through indirect addressing only.
Working Registers
The first 32 bytes of the scratchpad RAM can be used as four banks of eight working registers for high-speed data movement. Using
four banks, software can quickly change context by changing to a different bank. In addition to the accumulator, the working registers
are commonly used as data source or destination. Some of the working registers can also be used as pointers to other RAM locations
(indirect addressing).
Program Counter
The program counter (PC) is a 16-bit value that designates the next program address to be fetched. On-chip hardware automatically
increments the PC value to move to the next ROM location.
Address/Data Bus
The DS89C420 addresses a 64kB program and 64kB data memory area that resides in a combination of internal and external memory.
When external memory is accessed, ports 0 and 2 are used as a multiplexed address and data bus. The DS89C420 supports three
external memory bus structures. The nonpage mode (traditional 8051) bus structure provides the address MSB on port 2 and multiplexes
port 0 between address LSB and data. The page mode 1 bus structure uses port 0 exclusively for data and multiplexes port 2 between
address MSB and address LSB. The page mode 2 bus structure uses port 0 exclusively for address LSB and multiplexes port 2 between
address MSB and data. These addressing modes are detailed later.
Watchdog Timer
The watchdog timer provides a supervisory function for applications that cannot afford to run out of control. The watchdog timer is a
programmable, free-running timer. If allowed to reach the termination of its count, if enabled, the watchdog resets the CPU software
must prevent this by clearing or resetting the watchdog prior to its timeout.
Power Monitor
The DS89C420 incorporates a bandgap reference and analog circuitry to monitor the power-supply conditions. When VCC begins to
drop out of tolerance, the power monitor issues an optional early warning power-fail interrupt. If power continues to fall, the power mon-
itor invokes a reset condition. This remains until power returns to normal operating voltage. The power monitor also functions on power-
up, holding the microcontroller in a reset state until power is stable.
Interrupts
The DS89C420 is capable of evaluating 13 interrupt sources simultaneously. Each interrupt has an associated interrupt vector, flag,
priority, and enable. These interrupts can be globally enabled or disabled.
3 ______________________________________________________________________________________________
Timing Control
The DS89C420 provides an on-chip oscillator for use with an external crystal. This can be bypassed by injecting a clock source into
the XTAL1 pin. The clock source is used to create machine cycle timing (four clocks), ALE, PSEN, watchdog, timer, and serial baud-
rate timing. In addition, an on-chip ring oscillator can be used to provide an approximately 10MHz clock source. A frequency multipli-
er feature is included, which can be selected by SFR control to multiply the input clock source by either two or four. This allows lower
frequency (and cost) crystals to be used while still allowing internal operation up to the full 33MHz limit.
Flash Memory
On-chip program memory is implemented in 16kB of flash memory. This can be programmed in-system with the standard 5V VCC sup-
ply under the control of the user software (in-application), or through a serial port (in-system) using a built-in program memory loader
(ROM loader), or by a standard flash or EPROM programmer. Full programming details are given in Section 15.
The DS89C420 incorporates a memory management unit (MMU) and other hardware to support any of the three programming meth-
ods. The MMU controls program and data memory access, and provides sequencing and timing controls for programming of the on-
chip program memory. There is also a separate security flash block that is used to support a standard three-level lock, a 64-byte
encryption array, and other flash options.
The full on-chip program memory range can be fetched by the processor automatically. Reset routines and all interrupt vectors are
located in the lower 128 bytes of the on-chip program memory area.
SECTION 4: PROGRAMMING MODEL

This section provides a programmer’s overview of the ultra-high-speed microcontroller core. It includes information on the memory
map, on-chip RAM, SFRs, and instruction set. The programming model of the ultra-high-speed microcontroller is very similar to that of
the industry-standard 80C52. The memory map is identical. It uses the same instruction set, with improved instruction timing. Several
new SFRs have been added.
Memory Organization
The DS89C420, like the 8052, uses several distinct memory areas. These areas include Registers, program memory, and data mem-
ory. Registers serve to control on-chip peripherals and as RAM. Note that registers (on-chip RAM) are separate from data memory.
Registers are divided into three categories including directly addressed on-chip RAM, indirectly addressed on-chip RAM, and SFRs.
The program and data memory areas are discussed under the Memory Map section. The registers are discussed under the Register
Map section.
Memory Map
The ultra-high-speed microcontroller uses a memory-addressing scheme that separates program memory from data memory. Each
area is 64kB beginning at address 0000h and ending at FFFFh, as shown in Figure 4-1. The program and data segments can overlap
since they are accessed in different ways. Program memory is fetched by the microcontroller automatically. These addresses are never
written by software. In fact, there are no instructions that allow the program area to be written. There is one instruction (MOVC) that is
used to explicitly read the program area. This is commonly used to read lookup tables. The data memory area is accessed explicitly
using the MOVX instruction. This instruction provides multiple ways of specifying the target address. It is used to access the 64kB of
data memory.
The address and data range of devices with on-chip program and data memory overlap the 64k memory space. When on-chip mem-
ory is enabled, accessing memory in the on-chip range causes the device to access internal memory. Memory accesses beyond the
internal range are addressed externally through ports 0 and 2.
The ROMSIZE feature allows software to dynamically configure the maximum address of on-chip program memory. This allows the
device to act as a bootstrap loader for an external flash or nonvolatile SRAM. Secondly, this method can also be used to increase the
amount of available program memory from 64kB to 80kB without bank switching. For more information on this feature, see Section 6.
Program and data memory can also be increased beyond the 64kB limit using bank-switching techniques. This is described in
Application Note 81: Memory Expansion with the High-Speed Microcontroller Family.
Register Map
The register map is illustrated in Figure 4-2. It is entirely separate from the program and data memory areas mentioned above. A sep-
arate class of instructions is used to access the registers. There are 256 potential register location values. In practice, the ultra-high-
speed microcontroller has 256 bytes of scratchpad RAM and up to 128 SFRs. This is possible since the upper 128 scratchpad RAM
locations can only be accessed indirectly. That is, the contents of a working register (R0 or R1) or the stack pointer designates the RAM
______________________________________________________________________________________________ 4
FFFFh 64k FFh 255 FFh

PROGRAM DATA DIRECT
MEMORY MEMORY INDIRECT SPECIAL
RAM FUNCTION
REGISTERS
7Fh 128 7Fh
DIRECT
RAM
0000h 0000h
Figure 4-1. Memory Map Figure 4-2. Register Map
FFh
INDIRECT RAM
7Fh
DIRECT RAM
2Fh 7F 7E 7D 7C 7B 7A 79 78
2Eh 77 76 75 74 73 72 71 70
2Dh 6F 6E 6D 6C 6B 6A 69 68
2Ch 67 66 65 64 63 62 61 60
2Bh 5F 5E 5D 5C 5B 5A 59 58
2Ah 57 56 55 54 53 52 51 50
29h 4F 4E 4D 4C 4B 4A 49 48
28h 47 46 45 44 43 42 41 40
27h 3F 3E 3D 3C 3B 3A 39 38
26h 37 36 35 34 333 32 31 30
25h 2F 2E 2D 2C 2B 2A 29 28
24h 27 26 25 24 23 22 21 20
23h 1F 1E 1D 1C 1B 1A 19 18
22h 17 16 15 14 13 12 11 10
21h 0F 0E 0D 0C 0B 0A 09 08
20h 07 06 05 04 03 02 01 00
1Fh
BANK 3
18h
17h
BANK 2
10h
0Fh
BANK 1
08h
07h
00h BANK 0
MSB LSB
Figure 4-3. Scratchpad Register Addressing
5 ______________________________________________________________________________________________
location. A direct reference to one of the lower 128 addresses (0h-7Fh) accesses the scratchpad RAM. A direct reference to one of the upper
128 addresses (80h-FFh) must be an SFR access. In contrast, indirect references can access the entire scratchpad RAM range (0h-FFh).
Scratchpad RAM is available for general-purpose data storage. It is commonly used in place of off-chip RAM when the total data con-
tents are small. When off-chip RAM is needed, the scratchpad area still provides the fastest general-purpose access. Within the 256
bytes of RAM, there are several special purpose areas. These are described as follows:
Bit Addressable Locations
In addition to direct register access, some individual bits are also accessible. These are individually addressable bits in both the RAM
and SFR area. In the scratchpad RAM area, registers 20h to 2Fh are bit addressable. This provides 128 (16 x 8) individual bits avail-
able to software. A bit access is distinguished from a full register access by the type of instruction. Addressing modes are discussed
later in this section. In the SFR area, any register location ending in a 0 or 8 is bit addressable. Figure 4-3 shows details of the on-chip
RAM addressing, including the locations of individual RAM bits.
Working Registers
As part of the lower 128 bytes of RAM, there are four banks of working registers (8 bytes each). The working registers are general-purpose
RAM locations that can be addressed in a special way. They are designated R0 through R7. Since there are four banks, the currently
selected bank is used by any instruction using R0–R7. This allows software to change context by simply switching banks. This is con-
trolled through the program status word register in the next SFR area. The working registers also allow their contents to be used for
indirect addressing of the upper 128 bytes of RAM. Thus, an instruction can designate the value stored in R0 (for example) to address
the upper RAM. This value might be the result of another calculation.
Stack
Another use of the scratchpad area is for the programmer’s stack. This area is selected using the stack pointer (SP;81h) SFR. Whenever
a call or interrupt is invoked, the return address is placed on the stack. It also is available to the programmer for variables, etc. Since
the stack can be moved, there is no fixed location within the RAM designated as stack. The stack pointer defaults to 07h upon reset.
The user can then move it as needed. A convenient location would be the upper RAM area (>7Fh), since this is only available indi-
rectly. The SP points to the last used value. Therefore, the next value placed on the stack is put at SP + 1. Each PUSH or CALL incre-
ments the SP by the appropriate value. Each POP or RET decrements as well.
Address Modes
The DS89C420 uses the standard 8051 instruction set that is supported by a wide range of third-party assemblers and compilers. Like
the 8051, the DS89C420 uses three memory areas. These are program memory, data memory, and registers. The program and data
areas are 64kB each. They extend from 0000h to FFFFh. The register areas are located between 00h and FFh, but do not overlap with
the program and data segments. This is because the DS89C420 uses different modes of addressing to reach each memory segment.
These modes are described below.
Program memory is the area from which all instructions are fetched. It is inherently read only. This is because the 8051 instruction set
provides no instructions that write to this area. Read/write access is for data memory and registers only. No special action is required
to fetch from program memory. Each instruction fetch is performed automatically by the on-chip CPU. In versions that contain on-chip
memory, the hardware decides whether the fetch is on-chip or off-chip based on the address. Explicit addressing modes are needed
for the data memory and register areas. These modes determine which register area is accessed or if off-chip data memory is used.
______________________________________________________________________________________________ 6
The ultra-high-speed microcontroller supports eight addressing modes:

• Register addressing
• Direct addressing
• Register indirect addressing
• Immediate addressing
• Register indirect addressing with displacement
• Relative addressing
• Page addressing
• Extended addressing
Five of the eight addressing modes are used to address operands. The remainder are used for program control and branching. When
writing assembly language instructions that use arguments, the convention is “destination, source.” Each mode of addressing is sum-
marized on the following pages. Note that many instructions (such as ADD) have multiple-addressing modes available.
Register Addressing
Register addressing is used for operands that are located in one of the eight working registers (R7–R0). The eight working registers
can be located in one of four working register banks found in the lower 32 bytes of scratchpad RAM, as determined by the current reg-
ister bank-select bits. A register bank is selected using two bits in the program status word (PSW;D0h). This addressing mode is pow-
erful, since it uses the active bank without knowing which bank is selected. Thus, one instruction can have multiple uses by simply
switching banks. Register addressing is also a high-speed instruction, requiring only one machine cycle. Two examples of register
addressing are provided below:
ADD A, R4 ;Add register R4 to Accumulator
INC R2 ;Increment the value in register R2
In the first case, the value in R4 is the source of the operation. In the latter, R2 is the destination. These instructions do not consider
the absolute address of the register. They act on whichever bank has been selected.
Any working register can also be accessed by direct addressing. In order to do this, the absolute address must be specified.
Direct Addressing
Direct addressing is the mode used to access the entire lower 128 bytes of scratchpad RAM and the SFR area. It is commonly used
to move the value in one register to another. Two examples are shown below:
MOV 72h, 74h ;Move the value in register 74 to
;register 72.
MOV 90h, 20h ;Move the value in register 20 to
;the SFR at 90h (Port 1)
Note that there is no instruction difference between a RAM access and an SFR access. The SFRs are register locations above 7Fh.
Direct addressing also extends to bit addressing. There is a group of instructions that explicitly use bits. The address information pro-
vided to such an instruction is the bit location, rather than the register address. Registers between 20h and 2Fh contain bits that are
individually addressable. SFRs that end in 0 or 8 are bit addressable. An example of direct bit addressing is as follows:
SETB 00h ;Set bit 00 in the RAM. This is the
;LSb of the register at address 20h
;as shown earlier in this section.
MOV C, 0B7h ;Move the contents of bit B7 to the
;Carry flag. Bit B7 is the MSb of
;register B0 (Port 3).
Register Indirect Addressing
This mode is used to access the scratchpad RAM locations above 7Fh. It can also be used to reach the lower RAM (0h–7Fh), if need-
ed. The address is supplied by the contents of the working register specified in the instruction. Thus, one instruction can be used to
reach many values by altering the contents of the designated working register. Note that, in general, only R0 and R1 can be used as
pointers. An example of register indirect addressing follows:
ANL A, @R0 ;Logical AND the Accumulator
;with the contents of the register
;pointed to by the value stored in R0.
7 ______________________________________________________________________________________________
This mode is also used for stack manipulation. This is because all stack references are directed by the value in the stack pointer reg-
ister. The push and pop instructions use this method of addressing. An example is as follows:
PUSH A ;Saves the contents of the
;accumulator on the stack.
Register indirect addressing is used for all off-chip data memory accesses. These involve the MOVX instruction. The pointer registers
can be R0, R1, DPTR0 and DPTR1. Both R0 and R1 reside in the working register area of the scratchpad RAM. They can be used to
reference a 256-byte area of off-chip data memory. When using this type of addressing, the upper address byte is supplied by the
value in the port 2 latch. This value must be selected by software prior to the MOVX instruction. An example is as follows:
MOVX @R0, A ;Write the value in the accumulator
;to the address pointed to by R0 in
;the page pointed to by P2.
The 16-bit data pointers (DPTRs) can be used as an absolute off-chip reference. This gives access to the entire 64kB data memory
map. An example is as follows:
MOVX @DPTR, A ;Write the value in the accumulator
;to the address referenced by the
;selected data pointer.
Immediate Addressing
Immediate addressing is used when one of the operands is predetermined and coded into the software. This mode is commonly used
to initialize SFRs and to mask particular bits without affecting others. An example is as follows:
ORL A, #40h ;Logical OR the Accumulator with 40h.
Register Indirect with Displacement
Register indirect addressing with displacement is used to access data in lookup tables in program memory space. The location is cre-
ated using a base address with an index. The base address can be either the PC or the DPTR. The index is the accumulator. The result
is stored in the accumulator. An example is as follows:
MOVC A, @A +DPTR ;Load the accumulator with the contents
of program memory
;pointed to by the contents of the DPTR
plus the value in
;the accumulator.
Relative Addressing
Relative addressing is used to determine a destination address for the conditional branch. Each of these instructions includes an 8-bit
value that contains a two’s complement address offset (-127 to +128), which is added to the PC to determine the destination address.
This destination is branched to when the tested condition is true. The PC points to the program memory location immediately follow-
ing the branch instruction when the offset is added. If the tested condition is not true, the next instruction is performed. An example is
as follows:
JZ $–20 ;Branch to the location (PC+2)–20
;if the contents of the accumulator = 0.
Page Addressing
Page addressing is used by the branching instructions to specify a destination address within the same 2kB block as the next con-
tiguous instruction. The full 16-bit address is calculated by taking the five highest-order bits for the next instruction (PC + 2) and
concatenating them with the lowest order 11-bit field contained in the current instruction. An example is as follows:
0870h ACALL 100h ;Call to the subroutine at address 100h
plus the
;current page address.
In this example, the current page address is 800h, so the destination address is 900h.
Extended Addressing
Extended addressing is used by the branching instructions to specify a 16-bit destination address within the 64kB address space. The
destination address is fixed in the software as an absolute value. An example is as follows:
LJMP 0F732h ;Jump to address 0F732h.
______________________________________________________________________________________________ 8
Program Status Flags

All program status flags are contained in the program status word at SFR location D0h. It contains flags that reflect the status of the CPU
and the result of selected operations. The flags are summarized below. The following table shows the instructions that affect each flag.
Bit Description*:
PSW.7 C
Carry Set when the previous operation resulted in a carry (during addition) or a borrow (during
subtraction). Otherwise cleared.
PSW.6 AC
Auxiliary Carry Set when the previous operation resulted in a carry (during addition) or a borrow (during
subtraction) from the high-order nibble. Otherwise cleared.
PSW.2 OV
Overflow For addition, OV is set when a carry is generated into a high order bit (bit 6 or bit 7), but not a carry
out of the same high-order bit. For subtraction, OV is set if a borrow is needed into a high order bit
(bit 6 or bit 7), but not into the other high-order bit. For multiplication, OV is set when the product
exceeds FFh. For division, OV is always cleared.
PSW.0 P
Parity Set to logic 1 to indicate an odd number of ones in the accumulator (odd parity). Cleared for an
even number of ones. This produces even parity.
*All of these bits are cleared to a logic 0 for all resets.
Table 4-1. Instructions that Affect Flag Settings

INSTRUCTION FLAGS INSTRUCTION FLAGS
C OV AC C OV AC
ADD X X X CLR C 0
ADDC X X X CPL C X
SUBB X X X ANL C, bit X
MUL 0 X ANL C, bit X
DIV 0 X ORL C, bit X
DA X ORL C, bit X
RRC X MOV C, bit X
RLC X CJNE X
SETB C 1 — —
Note: X indicates the modification is according to the result of the instruction.
Special Function-Registers
The DS89C420, like the 8051, uses SFRs to control peripherals and modes. In many cases, an SFR controls individual functions or
report status on individual functions. The SFRs reside in register locations 80h–FFh and are reached using direct addressing. SFRs that
end in 0 or 8 are bit addressable.
All standard SFR locations from the original 8051 are duplicated in the DS89C420, with several additions. Tables are provided to illus-
trate the locations of the SFRs for the DS89C420 device and the default reset conditions of all SFR bits. Detailed descriptions of each
SFR follow.
9 ______________________________________________________________________________________________
DS89C420 Special-Function Register Locations

REGISTER ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
P0 80h P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
SP 81h
DPL 82h
DPH 83h
DPL1 84h
DPH1 85h
DPS 86h ID1 ID0 TSL AID — — — SEL
PCON 87h SMOD_0 SMOD0 OFDF OFDE GF1 GF0 STOP IDLE
TCON 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD 89h GATE C/T M1 M0 GATE C/T M1 M0
TL0 8Ah
TL1 8Bh
TH0 8Ch
TH1 8Dh
CKCON 8Eh WD1 WD0 T2M T1M T0M MD2 MD1 MD0
P1 90h P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
EXIF 91h IE5 IE4 IE3 IE2 CKRY RGMD RGSL BGS
CKMOD 96h T2MH T1MH T0MH
SCON0 98h SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0
SBUF0 99h
ACON 9Dh PAGEE PAGES1 PAGES0
P2 A0h P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
IE A8h EA ES1 ET2 ES0 ET1 EX1 ET0 EX0
SADDR0 A9h
SADDR1 AAh
P3 B0h P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
IP1 B1h — MPS1 MPT2 MPS0 MPT1 MPX1 MPT0 MPX0
IP0 B8h — LPS1 LPT2 LPS0 LPT1 LPX1 LPT0 LPX0
SADEN0 B9h
SADEN1 BAh
SCON1 C0h SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1
SBUF1 C1h
ROMSIZE C2h PRAME RMS2 RMS1 RMS0
PMR C4h CD1 CD0 SWB CTM 4X/2X ALEON DME1 DME0
STATUS C5h PIS2 PIS1 PIS0 — SPTA1 SPRA1 SPTA0 SPRA0
TA C7h
T2CON C8h TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
T2MOD C9h — — — — — — T2OE DCEN
RCAP2L CAh
RCAP2H CBh
TL2 CCh
TH2 CDh
PSW D0h CY AC F0 RS1 RS0 OV F1 P
FCNTL D5h FBUSY FERR FC3 FC2 FC1 FC0
FDATA D6h
WDCON D8h SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT
ACC E0h
EIE E8h — — — EWDI EX5 EX4 EX3 EX2
B F0h
EIP1 F1h MPWDI MPX5 MPX4 MPX3 MPX2
EIP0 F8h — — — LPWDI LPX5 LPX4 LPX3 LPX2
Note: Shaded bits are timed-access protected.
_____________________________________________________________________________________________ 10
DS89C420 Special-Function Register Reset Values

REGISTER ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
P0 80h 1 1 1 1 1 1 1 1
SP 81h 0 0 0 0 0 1 1 1
DPL 82h 0 0 0 0 0 0 0 0
DPH 83h 0 0 0 0 0 0 0 0
DPL1 84h 0 0 0 0 0 0 0 0
DPH1 85h 0 0 0 0 0 0 0 0
DPS 86h 0 0 0 0 0 1 0 0
PCON 87h 0 0 Special Special 0 0 0 0
TCON 88h 0 0 0 0 0 0 0 0
TMOD 89h 0 0 0 0 0 0 0 0
TL0 8Ah 0 0 0 0 0 0 0 0
TL1 8Bh 0 0 0 0 0 0 0 0
TH0 8Ch 0 0 0 0 0 0 0 0
TH1 8Dh 0 0 0 0 0 0 0 0
CKCON 8Eh 0 0 0 0 0 0 0 1
P1 90h 1 1 1 1 1 1 1 1
EXIF 91h 0 0 0 0 Special Special Special 0
CKMOD 96h 1 1 0 0 0 1 1 1
SCON0 98h 0 0 0 0 0 0 0 0
SBUF0 99h 0 0 0 0 0 0 0 0
ACON 9Dh 0 0 0 1 1 1 1 1
P2 A0h 1 1 1 1 1 1 1 1
IE A8h 0 0 0 0 0 0 0 0
SADDR0 A9h 0 0 0 0 0 0 0 0
SADDR1 AAh 0 0 0 0 0 0 0 0
P3 B0h 1 1 1 1 1 1 1 1
IP1 B1h 1 0 0 0 0 0 0 0
IP0 B8h 1 0 0 0 0 0 0 0
SADEN0 B9h 0 0 0 0 0 0 0 0
SADEN1 BAh 0 0 0 0 0 0 0 0
SCON1 C0h 0 0 0 0 0 0 0 0
SBUF1 C1h 0 0 0 0 0 0 0 0
ROMSIZE C2h 1 1 1 1 0 1 0 1
PMR C4h 1 0 0 0 0 0 0 0
STATUS C5h 0 0 0 1 0 0 0 0
TA C7h 1 1 1 1 1 1 1 1
T2CON C8h 0 0 0 0 0 0 0 0
T2MOD C9h 1 1 1 1 1 1 0 0
RCAP2L CAh 0 0 0 0 0 0 0 0
RCAP2H CBh 0 0 0 0 0 0 0 0
TL2 CCh 0 0 0 0 0 0 0 0
TH2 CDh 0 0 0 0 0 0 0 0
PSW D0h 0 0 0 0 0 0 0 0
FCNTL D5h 1 0 1 1 0 0 0 0
FDATA D6h 0 0 0 0 0 0 0 0
WDCON D8h 0 Special 0 Special 0 Special Special 0
ACC E0h 0 0 0 0 0 0 0 0
EIE E8h 1 1 1 0 0 0 0 0
B F0h 0 0 0 0 0 0 0 0
EIP1 F1h 1 1 1 0 0 0 0 0
EIP0 F8h 1 1 1 0 0 0 0 0
11 _____________________________________________________________________________________________
Special-Function Registers
Most of the unique features of the ultra-high-speed microcontroller family are controlled by bits in SFRs located in unused locations in
the 8051 SFR map. This allows for increased functionality while maintaining complete instruction set compatibility.
The description for each bit indicates its read and write access, as well as its state after a power-on reset.
Port 0 (P0)
7 6 5 4 3 2 1 0
SFR 80h P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
P0.7–0 Port 0. This port functions according to the table below where PAGEE = ACON.7 and PAGES =
ACON.6-5.
Port 0 Function
PAGEE PAGES PORT 0 FUNCTION
0 XX General-Purpose I/O (code execution < ROMSIZE.2-0)
0 XX Multiplexed Address LSB / Data (code execution > ROMSIZE.2-0)
1 00, 01, 10 Data
1 11 Address LSB
When serving as general-purpose I/O (GPIO), the port is open-drain and requires pullups. Writing
a 1 to one of the bits of this register configures the associated port 0 pin as an input. All read oper-
ations, with the exception of read-modify-write instructions, leave the port latch unchanged. During
external memory addressing and data memory write cycles, the port has high-and-low drive capa-
bility. During external memory data read cycles, the port is held in a high-impedance state.
Stack Pointer (SP)
7 6 5 4 3 2 1 0
SFR 81h SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
SP.7–0 Stack Pointer. This stack pointer is written by software to identify the location where the stack
Bits 7–0 begins. The stack pointer is incremented before every PUSH operation and is decremented fol-
lowing every POP operation. This register defaults to 07h after reset.
Data Pointer Low 0 (DPL)

7 6 5 4 3 2 1 0
SFR 82h DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0
DPL.7–0 Data Pointer LOW 0. This register is the low byte of the standard 80C32 16-bit data pointer. DPL
Bits 7–0 and DPH are used to point to nonscratchpad data RAM.
Data Pointer High 0 (DPH)

7 6 5 4 3 2 1 0
SFR 83h DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0
DPH.7–0 Data Pointer High 0. This register is the high byte of the standard 80C32 16-bit data pointer. DPL
Bits 7–0 and DPH are used to point to nonscratchpad data RAM.
_____________________________________________________________________________________________ 12
Data Pointer Low 1 (DPL1)

7 6 5 4 3 2 1 0
SFR 84h DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DL1H.0
DPL1.7–0 Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL
Bits 7–0 bit (DPS.0) is set, DPL1 and DPH1 are used in place of DPL and DPH during DPTR operations.
Data Pointer High 1 (DPH1)

7 6 5 4 3 2 1 0
SFR 85h DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
DPH1.7–0 Data Pointer Low 1. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL
Bits 7–0 bit (DPS.0) is set, DPL1 and DPH1 are used in place of DPL and DPH during DPTR operations.
Data Pointer Select (DPS)
7 6 5 4 3 2 1 0
SFR 86h ID1 ID0 TSL AID — — — SEL
RW-0 RW-0 RW-0 R-0 R-0 R-1 R-0 RW-0
ID1 Increment/Decrement Select for DPTR1. This bit determines the effect of the INC DPTR instruction
Bit 7 on DPTR1 when selected (SEL = 1) as the active data pointer.
0 = INC DPTR increments DPTR1 (default)
1 = INC DPTR decrements DPTR1
ID0 Increment/Decrement Select for DPTR. This bit determines the effect of the INC DPTR instruction
Bit 6 on DPTR when selected (SEL = 0) as the active data pointer.
0 = INC DPTR increments DPTR (default)
1 = INC DPTR decrements DPTR
TSL Toggle Select. When clear (= 0), DPTR-related instructions do not affect the SEL bit. When set (= 1),
Bit 5 the SEL bit is toggled following execution of any of the below DPTR-related instructions:
INC DPTR
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
AID Autoincrement/Decrement Enable. When set, the active data pointer is automatically incremented
Bit 4 or decremented (as determined by ID1, ID0 bit settings) following execution of any of the below
DPTR-related instructions:
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
Bits 3, 2, 1 Reserved. These bits read 010b.
13 _____________________________________________________________________________________________
SEL Data Pointer Select. This bit selects the active data pointer.
Bit 0 0 = Instructions that use the DPTR use DPL and DPH.
1 = Instructions that use the DPTR use DPL1 and DPH1.
Power Control (PCON)

7 6 5 4 3 2 1 0
SFR 87h SMOD_0 SMOD0 OFDF OFDE GF1 GF0 STOP IDLE
RW-0 RW-0 RW-0* RW-0* RW-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset, * = See description
SMOD_0 Serial Port 0 Baud Rate Doubler Enable. This bit enables/disables the serial baud rate doubling
Bit 7 function for Serial Port 0.
0 = Serial Port 0 baud rate is that defined by baud rate generation equation.
1 = Serial Port 0 baud rate is double that defined by baud rate generation equation.
SMOD0 Framing Error Detection Enable. When clear (= 0), SCON1.7 and SCON0.7 serve as mode select
Bit 6 bit SM0 for the respective serial ports. When set (= 1), SCON1.7 and SCON0.7 report whether a
Framing Error has been detected.
OFDF Oscillator Fail Detect Flag. When OFDE = 1, this flag will be set if a reset condition is generated
Bit 5 due to oscillator failure. This bit is cleared on a power-on reset and is unchanged by other reset
sources. This bit must be cleared by software.
OFDE Oscillator Fail Detect Enable. When set (= 1), the oscillator fail detect circuitry and flag generation
Bit 4 are enabled. An oscillator fail detection occurs if the crystal oscillator falls below ~20kHz. An oscillator
fail detection does not occur if the oscillator is halted through software setting of the STOP bit
(PCON.1) or when running from the internal ring oscillator source. When clear (= 0), the oscillator
fail detect circuitry is disabled.
GF1 General-Purpose User Flag 1. This is a general-purpose flag for software control.
Bit 3
GF0 General-Purpose User Flag 0. This is a general-purpose flag for software control.
Bit 2
STOP Stop Mode Select. Setting this bit stops program execution, halts the CPU oscillator and internal
Bit 1 timers, and places the CPU in a low-power mode. This bit always be reads as a 0. Setting both the
STOP bit and the IDLE bit causes the device to enter stop mode; however, doing this is not advised.
IDLE Idle Mode Select. Setting this bit stops program execution but leaves the CPU oscillator, timers,
Bit 0 serial ports, and interrupts active. This bit is always read as a 0. Setting both the STOP bit and
the IDLE bit causes the device to enter stop mode; however, doing this is not advised.
_____________________________________________________________________________________________ 14
Timer/Counter Control (TCON)

7 6 5 4 3 2 1 0
SFR 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TF1 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined
Bit 7 by the current mode. This bit can be cleared by software and is automatically cleared when the
CPU vectors to the Timer 1 interrupt service routine.
0 = No Timer 1 overflow has been detected.
1 = Timer 1 has overflowed its maximum count.
TR1 Timer 1 Run Control. This bit enables/disables the operation of Timer 1.
Bit 6 0 = Timer 1 is halted.
1 = Timer 1 is enabled.
TF0 Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined
Bit 5 by the current mode. This bit can be cleared by software and is automatically cleared when the
CPU vectors to the Timer 0 interrupt service routine or by software.
0 = No Timer 0 overflow has been detected.
1 = Timer 0 has overflowed its maximum count.
TR0 Timer 0 Run Control. This bit enables/disables the operation of Timer 0.
Bit 4 0 = Timer 0 is halted.
IE1 Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected.
Bit 3 If IT1 = 1, this bit remains set until cleared in software or until the start of the External Interrupt 1
service routine. If IT1 = 0, this bit inversely reflects the state of the INT1 pin.
IT1 Interrupt 1 Type Select. This bit selects whether the INT1 pin detects edge- or level-triggered
Bit 2 interrupts.
0 = INT1 is level triggered.
1 = INT1 is edge triggered.
IE0 Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected.
Bit 1 If IT0 = 1, this bit remains set until cleared in software or until the start of the External Interrupt 0
service routine. If IT0 = 0, this bit inversely reflects the state of the INT0 pin.
IT0 Interrupt 0 Type Select. This bit selects whether the INT0 pin detects edge- or level-triggered
Bit 0 interrupts.
0 = INT0 is level triggered.
1 = INT0 is edge triggered.
15 _____________________________________________________________________________________________
Timer Mode Control (TMOD)

7 6 5 4 3 2 1 0
SFR 89h GATE C/T M1 M0 GATE C/T M1 M0
GATE Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment.
Bit 7 0 = Timer 1 clocks when TR1 = 1, regardless of the state of INT.
1 = Timer 1 clocks only when TR1 = 1 and INT1 = 1.
C/T Timer 1 Counter/Timer Select.
Bit 6 0 = Timer 1 is incremented by internal clocks.
1 = Timer 1 is incremented by pulses on T1 when TR1 (TCON.6) is 1.
M1, M0 Timer 1 Mode Select. These bits select the operating mode of Timer 1.
Bits 5, 4 Timer 1 Mode Selection
M1 M0 MODE
0 0 Mode 0: 8 bits with 5-bit prescale
0 1 Mode 1: 16 bits
1 0 Mode 2: 8 bits with autoreload
1 1 Mode 3: Timer 1 is halted, but holds its count
GATE Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment.
Bit 3 0 = Timer 0 clocks when TR0 = 1, regardless of the state of INT0.
1 = Timer 0 clocks only when TR0 = 1 and INT0 = 1.
C/T Timer 0 Counter/Timer Select.
Bit 2 0 = Timer incremented by internal clocks.
1 = Timer 1 is incremented by pulses on T0 when TR0 (TCON.4) is 1.
M1, M0 Timer 0 Mode Select. These bits select the operating mode of Timer 0. When Timer 0 is in mode
Bits 1, 0 3, TL0 is started/stopped by TR0 and TH0 is started/stopped by TR1. Run control from Timer 1 is
then provided by the Timer 1 mode selection.
Timer 0 Mode Selection
M1 M0 MODE
0 0 Mode 0: 8 bits with 5-bit prescale
0 1 Mode 1: 16 bits
1 0 Mode 2: 8 bits with autoreload
1 1 Mode 3: Timer 0 is two 8-bit counters
_____________________________________________________________________________________________ 16
Timer 0 LSB (TL0)

7 6 5 4 3 2 1 0
SFR 8Ah TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
TL0.7–0 Timer 0 LSB. This register contains the least significant byte of Timer 0.
Bits 7–0
Timer 1 LSB (TL1)

7 6 5 4 3 2 1 0
SFR 8Bh TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0
Bits 7–0
Timer 0 MSB (TH0)

7 6 5 4 3 2 1 0
SFR 8Ch TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0
TH0.7–0 Timer 0 MSB. This register contains the most significant byte of Timer 0.
Bits 7–0
Timer 1 MSB (TH1)
7 6 5 4 3 2 1 0
SFR 8Dh TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0
Bits 7–0
Clock Control (CKCON)

7 6 5 4 3 2 1 0
SFR 8Eh WD1 WD0 T2M T1M T0M MD2 MD1 MD0
WD1, WD0 Watchdog Timer Mode Select 1-0. These bits determine the watchdog timer timeout period for
Bits 7, 6 the watchdog timer. The timer divides the crystal (or external oscillator) frequency by a program-
mable value as shown on the next page. The divider value is expressed in crystal (oscillator)
cycles. The settings of the system clock control bits 4X/2X (PMR.3) and CD1:0 (PMR.7-6) affect the
clock input to the watchdog timer and therefore its timeout period as shown below. All watchdog
timer reset timeouts follow the setting of the interrupt flag by 512 system clocks.
17 _____________________________________________________________________________________________
Watchdog Interrupt Flag Timeout Periods (in Oscillator Clocks)

4X / 2X CD1:0 WD1:0 = 00 WD1:0 = 01 WD1:0 = 10 WD1:0 = 11
1 00 215 218 221 224
0 00 216 219 222 225
X 01 217 220 223 226
X 10 217 220 223 226
X 11 227 230 233 236
T2M Timer 2 Clock Select. This bit controls the input clock that drives Timer 2. This bit has no effect
Bit 5 when the timer is in baud rate generator or clock output modes. See Timer Operation table.
T1M Timer 1 Clock Select. This bit controls the input clock that drives Timer 1. See Timer Operation table.
Bit 4
T0M Timer 0 Clock Select. This bit controls the input clock that drives Timer 0. See Timer Operation table.
Bit 3
Timer Operation (in Oscillator Clocks)
OSCILLATOR CLOCKS OSCILLATOR CLOCKS PER
PER TIMER (0, 1, 2) CLOCK TIMER 2 CLOCK (BAUD RATE GEN)
4X/2X CD1:0 TxMH, TxM = T2MH, T2M =
00 01 1X XX
1 00 12 1 0.25 2
0 00 12 2 0.5 2
X 01 12 4 1 2
X 10 12 4 1 2
X 11 3072 1024 1024 2048
MD2, MD1, MD0 Stretch MOVX Select 2-0. These bits select the time by which external MOVX cycles are to be
Bits 2, 1, 0 stretched. This allows slower memory or peripherals to be accessed without using ports or manual
software intervention. The RD or WR strobe is stretched by the specified interval, which is transparent
to the software except for the increased time to execute to MOVX instruction. All internal MOVX
instructions are executed at the two machine cycle rate (0 stretch) independent of these bit settings.
MOVX Instruction
MD2, MD1, MD0 STRETCH VALUE MOVX DURATION
000 0 2 machine cycles
3 machine cycles
001 1
(default)
_____________________________________________________________________________________________ 18
Port 1 (P1)
7 6 5 4 3 2 1 0
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
SFR 90h
INT5 INT4 INT3 INT2 TXD1 RXD1 T2EX T2
P1.7–0 General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all
Bits 7–0 the pins have an alternative function listed below. Each of the functions is controlled by several
other SFRs. The associated Port 1 latch bit must contain a logic 1 before the pin can be used in its
alternate function capacity.
INT5 External Interrupt 5. A falling edge on this pin causes an external interrupt 5 if enabled.
Bit 7
INT4 External Interrupt 4. A rising edge on this pin causes an external interrupt 4 if enabled.
Bit 6
INT3 External Interrupt 3. A falling edge on this pin causes an external interrupt 3 if enabled.
Bit 5
INT2 External Interrupt 2. A rising edge on this pin causes an external interrupt 2 if enabled.
Bit 4
TXD1 Serial Port 1 Transmit. This pin transmits the serial port 1 data in serial port modes 1, 2, 3 and
Bit 3 emits the synchronizing clock in serial port mode 0.
RXD1 Serial Port 1 Receive. This pin receives the serial port 1 data in serial port modes 1, 2, 3 and is a
Bit 2 bidirectional data transfer pin in serial port mode 0.
T2EX Timer 2 Capture/Reload Trigger. A 1-to-0 transition on this pin causes the value in the T2
Bit 1 registers to be transferred into the capture registers if enabled by EXEN2 (T2CON.3). When in auto-
reload mode, a 1-to-0 transition on this pin reloads the Timer 2 registers with the value in RCAP2L
and RCAP2H if enabled by EXEN2 (T2CON.3).
T2 Timer 2 External Input. A 1-to-0 transition on this pin causes Timer 2 increment or decrement bit
Bit 0 depending on the timer configuration.
External Interrupt Flag (EXIF)
7 6 5 4 3 2 1 0
SFR 91h IE5 IE4 IE3 IE2 CKRY RGMD RGSL BGS
RW-0 RW-0 RW-0 RW-0 R-* R-* RW-* RT-0
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset,* = See description.
IE5 External Interrupt 5 Flag. This bit is set when a falling edge is detected on INT5. This bit must
Bit 7 be cleared manually by software. Setting this bit in software causes an interrupt if enabled.
IE4 External Interrupt 4 Flag. This bit is set when a rising edge is detected on INT4. This bit must
IE3 External Interrupt 3 Flag. This bit is set when a falling edge is detected on INT3. This bit must
IE2 External Interrupt 2 Flag. This bit is set when a rising edge is detected on INT2. This bit must
CKRY Clock Ready. This bit indicates the status of the startup period for the crystal oscillator or crystal
Bit 3 multiplier warm-up period. This bit is cleared after a reset or when exiting STOP mode. It is also
cleared when the clock multiplier is enabled (setting of PMR.4 = 1). Once CKRY is cleared, a
65,536 clock count must take place before CKRY is set and the lockout preventing modification of
CD1:CD0 is removed. Once CKRY is set (= 1), the clock multiplier can then be selected as the
clock source or switchover from the ring oscillator to the crystal oscillator can occur.
RGMD Ring Mode Status. This status bit indicates the current clock source for the device. This bit is
19 _____________________________________________________________________________________________
Bit 2 cleared to 0 after a power-on reset, and unchanged by all other forms of reset.
0 = Device is operating from the external crystal or oscillator.
1 = Device is operating from the ring oscillator.
RGSL Ring Oscillator Select. When set (= 1), this bit enables operation using the on-chip ring oscillator
Bit 1 as the clock source until the oscillator warm-up period has completed (CKRY = 1). Using the ring
oscillator to resume from stop mode allows almost instantaneous startup. This bit is cleared to 0
after a power-on reset, and unchanged by all other forms of reset.
0 = Device operation is held until completion of the crystal oscillator warm-up delay period.
1 = The device begins operating from the ring oscillator and switch over to the crystal oscillator
upon completion of the warm-up delay period.
BGS Bandgap Select. This bit enables/disables the bandgap reference during stop mode. Disabling
Bit 0 the bandgap reference provides significant power savings in stop mode, but sacrifices the ability
to perform a power-fail interrupt or power-fail reset while stopped. This bit can only be modified
with a timed access procedure.
0 = The bandgap reference is disabled in stop mode but functions during normal operation.
1 = The bandgap reference operates in stop mode.
Timer and Serial Port Clock Mode Register (CKMOD)
7 6 5 4 3 2 1 0
SFR 96h — — T2MH T1MH T0MH — — —
T2MH Timer 2 Clock Mode High-Speed Select. When set (= 1), the system clock is used as the input
Bit 5 clock for Timer 2 and the T2M bit (CKCON.5) setting is ignored. When clear (= 0), the input
clock for Timer 2 is selected using the T2M bit.
Serial Port 0 Control (SCON0)
7 6 5 4 3 2 1 0
SFR 98h SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0
SM0–2 Serial Port Mode. These bits control the mode of serial port 0. In addition the SM0 and SM2_0 bits
Bits 7, 6, 5 have secondary functions as shown below.
_____________________________________________________________________________________________ 20
Serial Port Mode Functions

SM0 SM1 SM2 MODE FUNCTION LENGTH (BITS) PERIOD
0 0 0 0 Synchronous 8 See PMR register
0 1 X 1 Asynchronous 10 Timer 1 or 2 baud rate equation
1 0 0 2 Asynchronous 11 See PMR register
Asynchronous with multiprocessor
1 0 1 2 11 See PMR register
communication
1 1 0 3 Asynchronous 11 Timer 1 or 2 baud rate equation
1 1 1 3 11 Timer 1 or 2 baud rate equation
communication
SM0/FE_0 Framing Error Flag. When SMOD0 (PCON.6) = 0, this bit is used as a mode select bit (SM0) for
Bit 7 serial port 0. When SMOD0 (PCON.6) = 1, this bit becomes a framing error (FE) bit, which reports
detection of an invalid stop bit. When used as FE, this bit must be cleared in software. Once the
SMOD0 bit is set, modifications to this bit do not affect the serial port mode settings. Although
accessed from the same register, the data for bits SM0 and FE are stored internally in different
physical locations.
SM1_0 No alternate function.
Bit 6
SM2_0 Multiple CPU Communications. The function of this bit is dependent on the serial port 0 mode.
Bit 5 Mode 0: Selects period for synchronous serial port 0 data transfers.
Mode 1: When set, reception is ignored (RI_0 is not set) if invalid stop bit received.
Modes 2/3: When this bit is set, multiprocessor communications are enabled in modes 2 and 3.
This prevents the RI_0 bit from being set, and an interrupt being asserted, if the 9th bit received is not 1.
REN_0 Receiver Enable. This bit enable/disables the serial port 0 receiver shift register.
Bit 4 0 = Serial port 0 reception disabled.
1 = Serial port 0 receiver enabled (modes 1, 2, 3). Initiate synchronous reception (mode 0).
TB8_0 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial port 0
Bit 3 modes 2 and 3.
RB8_0 9th Received Bit State. This bit identifies that state of the 9th reception bit of received data in
Bit 2 serial port 0 modes 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop
bit. RB8_0 is not used in mode 0.
TI_0 Transmitter Interrupt Flag. This bit indicates that data in the serial port 0 buffer has been
Bit 1 completely shifted out. In serial port mode 0, TI_0 is set at the end of the 8th data bit. In all other
modes, this bit is set at the end of the last data bit. This bit must be manually cleared by software.
RI_0 Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial port
Bit 0 0 buffer. In serial port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set
after the last sample of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0
is set after the last sample of RB8_0. This bit must be manually cleared by software.
Serial Data Buffer 0 (SBUF0)

7 6 5 4 3 2 1 0
SFR 99h SBUF0.7 SBUF0.6 SBUF0.5 SBUF0.4 SBUF0.3 SBUF0.2 SBUF0.1 SBUF0.0
SBUF0.7–0 Serial Data Buffer 0. Data for serial port 0 is read from or written to this location. The serial
Bits 7–0 transmit and receive buffers are separate registers, but both are addressed at this location.
21 _____________________________________________________________________________________________
Address Control (ACON)

7 6 5 4 3 2 1 0
SFR 9Dh PAGEE PAGES1 PAGES0 — — — — —
RT-0 RT-0 RT-0 R-1 R-1 R-1 R-1 R-1
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset
PAGEE Page Mode Enable. When set (= 1), page mode access is enabled for external bus operations
Bits 7 as configured by the page mode select bits PAGES1, PAGES0. When clear (= 0), external bus
operations default to the standard 8051 expanded bus configuration.
PAGES1, PAGES0 Page Mode Select. If PAGEE = 1, these bits select the page mode configuration that is followed
Bits 6, 5 for external bus operations. The four possible configurations are summarized in the table below.
Mode 1 results in Port 0 serving as the data bus and Port 2 being the multiplexed address
MSB/LSB. Mode 2 results in Port 0 being used strictly for address LSB and Port 2 being multiplexed
between address MSB and data.
Memory Access Cycle
PAGES 1-0 MODE PAGE-HIT PAGE-MISS
00 1 1 2
01 1 2 4
10 1 4 8
11 2 2 4
Bits 4–0 Reserved. Read data is 1.

Port 2 (P2)
7 6 5 4 3 2 1 0
SFR A0h P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
P2.7–0 Port 2. This port functions according to the table below where PAGEE = ACON.7 and PAGES =
Bits 7–0 ACON.6-5.
Port 2 Functions
PAGEE PAGES PORT2 FUNCTION
0 XX General-Purpose I/0 (code execution < ROMSIZE.2-0)
0 XX Address MSB (code execution > ROMSIZE.2-0)
1 00, 01, 10 Multiplexed Address MSB/LSB
1 11 Multiplexed Address MSB/Data
Writing a 1 to an SFR bit configures the associated port pin as an input. All read operations, with
the exception of read-modify-write instructions, leave the port latch unchanged. During external
memory addressing and data memory write cycles, the port has high and low drive capability.
During external memory data read cycles, the port is held in a high-impedance state.
_____________________________________________________________________________________________ 22
Interrupt Enable (IE)

7 6 5 4 3 2 1 0
SFR A8h EA ES1 ET2 ES0 ET1 EX1 ET0 EX0
EA Global Interrupt Enable. This bit controls the global masking of all interrupts except power-fail
Bit 7 interrupt, which is enabled by the EPFI bit (WDCON.5).
0 = Disable all interrupt sources. This bit overrides individual interrupt mask settings.
1 = Enable all individual interrupt masks. Individual interrupts occur if enabled.
ES1 Enable Serial Port 1 Interrupt. This bit controls the masking of the serial port 1 interrupt.
Bit 6 0 = Disable all serial port 1 interrupts.
1 = Enable interrupt requests generated by the RI_1 (SCON1.0) or TI_1 (SCON1.1) flags.
ET2 Enable Timer 2 Interrupt. This bit controls the masking of the Timer 2 interrupt.
Bit 5 0 = Disable all Timer 2 interrupts.
1 = Enable interrupt requests generated by the TF2 flag (T2CON.7).
ES0 Enable Serial Port 0 Interrupt. This bit controls the masking of the serial port 0 interrupt.
Bit 4 0 = Disable all serial port 0 interrupts.
1 = Enable interrupt requests generated by the RI_0 (SCON0.0) or TI_0 (SCON0.1) flags.
1 = Enable all interrupt requests generated by the TF1 flag (TCON.7).
EX1 Enable External Interrupt 1. This bit controls the masking of external interrupt 1.
Bit 2 0 = Disable external interrupt 1.
1 = Enable all interrupt requests generated by the INTO pin.
1 = Enable all interrupt requests generated by the TF0 flag (TCON.5).
EX0 Enable External Interrupt 0. This bit controls the masking of external interrupt 0.
1 = Enable all interrupt requests generated by the INTO pin.
Slave Address Register 0 (SADDR0)

.
7 6 5 4 3 2 1 0
SFR A9h SADDR0.7 SADDR0.6 SADDR0.5 SADDR0.4 SADDR0.3 SADDR0.2 SADDR0.1 SADDR0.0
SADDR0.7–0 Slave Address Register 0. This register is programmed with the given or broadcast address
Bits 7–0 assigned to serial port 0.
23 _____________________________________________________________________________________________
Slave Address Register 1 (SADDR1)

7 6 5 4 3 2 1 0
SFR AAh SADDR1.7 SADDR1.6 SADDR1.5 SADDR1.4 SADDR1.3 SADDR1.2 SADDR1.1 SADDR1.0
SADDR1.7–0 Slave Address Register 1. This register is programmed with the given or broadcast address
Bits 7–0 assigned to serial port 1.
Port 3 (P3)
7 6 5 4 3 2 1 0
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
SFR B0h
RD WR T1 T0 INT1 INT0 TXD0 RXD0
P3.7–0 Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins
Bits 7–0 have an alternative function listed below. Each of the functions is controlled by several other SFRs.
The associated port 3 latch bit must contain a logic 1 before the pin can be used in its alternate
function capacity.
RD External Data Memory Read Strobe. This pin provides an active-low read strobe to an external
Bit 7 memory device.
WR External Data Memory Write Strobe. This pin provides an active-low write strobe to an external
Bit 6 memory device.
T1 Timer/Counter External Input. A 1-to-0 transition on this pin increments Timer 1.
Bit 5
T0 Counter External Input. A 1-to-0 transition on this pin increments Timer 0.
Bit 4
INT1 External Interrupt 1. A falling edge/low level on this pin causes an external interrupt 1 if enabled.
Bit 3
INT0 External Interrupt 0. A falling edge/low level on this pin causes an external interrupt 0 if enabled.
Bit 2
TXD0 Serial Port 0 Transmit. This pin transmits the serial port 0 data in serial port modes 1, 2, 3 and
Bit 1 emits the synchronizing clock in serial port mode 0.
RXD0 Serial Port 0 Receive. This pin receives the serial port 0 data in serial port modes 1, 2, 3 and is a
Bit 0 bidirectional data transfer pin in serial port mode 0.
Interrupt Priority 1 (IP1)
7 6 5 4 3 2 1 0
SFR B1h — MPS1 MPT2 MPS0 MPT1 MPX1 MPT0 MPX0
R-1 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
IP17.0
Bit 7 Reserved. Read data is 1.
MPS1 Most Significant Priority Select Bit for Serial Port 1 Interrupt. This is the most significant bit of
Bit 6 the bit pair MPS1, LPS1 (IP0.6) that designates priority level for the serial port 1 interrupt.
MPT2 Most Significant Priority Select Bit for Timer 2 Interrupt. This is the most significant bit of the
Bit 5 bit pair MPT2, LPT2 (IP0.5) that designates priority level for the timer 2 interrupt.
_____________________________________________________________________________________________ 24
MPS0 Most Significant Priority Select Bit for Serial Port 0 Interrupt. This is the most significant bit of
Bit 4 the bit pair MPS0, LPS0 (IP0.4) that designates priority level for the serial port 0 interrupt
Bit 3 bit pair MPT1, LPT1 (IP0.3) that designates priority level for the timer 1 interrupt.
MPX1 Most Significant Priority Select Bit for External Interrupt 1. This is the most significant bit
Bit 2 of the bit pair MPX1, LPX1 (IP0.2) that designates priority level for external interrupt 1
Bit 1 bit pair MPT0, LPT0 (IP0.1) that designates priority level for the timer 0 interrupt
MPX0 Most Significant Priority Select Bit for External Interrupt 0. This is the most significant bit of the
Bit 0 bit pair MPX0, LPX0 (IP0.0) that designates priority level for external interrupt 0.
Interrupt priority level for the above sources is assigned using one bit from register IP1 (B1h) and
one bit from IP0 (B8h). The bit from IP1 serves as the most significant bit and the bit from IP0 serves
as the least significant bit in forming a 2-bit binary number. This number represents the priority level.
Higher priority interrupts, when enabled, take precedence over lower priority sources. The power-
fail warning interrupt source is assigned priority level 4.
Most Significant Priority Select Bit Levels
MP (IP1.X) LP (IP0.X) PRIORITY LEVEL
0 0 0 (natural priority)
0 1 1
1 0 2
1 1 3 (high priority)
Interrupt Priority 0 (IP0)

7 6 5 4 3 2 1 0
SFR B8h — LPS1 LPT2 LPS0 LPT1 LPX1 LPT0 LPX0
R-1 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
IP07.0
Bit 7 Reserved. Read data is 1.
LPS1 Least Significant Priority Select Bit for Serial Port 1 Interrupt. LPS1 is the least significant bit
Bit 6 of the bit pair MPS1 (IP1.6), LPS1 that designates priority level for the serial port 1 interrupt.
LPT2 Least Significant Priority Select Bit for Timer 2 Interrupt. LPT2 is the least significant bit of the
Bit 5 bit pair MPT2 (IP1.5), LPT2 that designates priority level for the Timer 2 interrupt.
LPS0 Least Significant Priority Select Bit for Serial Port 0 Interrupt. MPS0 is the least significant bit
Bit 4 of the bit pair MPS0 (IP1.4), LPS0 that designates priority level for the serial port 0 interrupt.
LPT1 Least Significant Priority Select Bit for Timer 1 Interrupt. MPT1 is the least significant bit of the
LPX1 Least Significant Priority Select Bit for External Interrupt 1. MPX1 is the least significant bit of
Bit 2 the bit pair MPX1 (IP1.2), LPX1 that designates priority level for external interrupt 1.
LPT0 Least Significant Priority Select Bit for Timer 0 Interrupt. MPT0 is the least significant bit of the
25 _____________________________________________________________________________________________
Least Significant Priority Select Bit Levels
0 1 1
1 0 2
Slave Address Mask Enable Register 0 (SADEN0)

7 6 5 4 3 2 1 0
SFR B9h SADEN0.7 SADEN0.6 SADEN0.5 SADEN0.4 SADEN0.3 SADEN0.2 SADEN0.1 SADEN0.0
SADEN0.7–0 Slave Address Mask Enable Register 0. This register functions as a mask when comparing
Bits 7–0 serial port 0 addresses for automatic address recognition. When a bit in this register is set, the cor-
responding bit location in the SADDR0 register is exactly compared with the incoming serial port 0
data to determine if a receiver interrupt should be generated. When a bit in this register is cleared,
the corresponding bit in the SADDR0 register becomes a “don’t care” and is not compared against
the incoming data. All incoming data generates a receiver interrupt when this register is cleared.
Slave Address Mask Enable Register 1 (SADEN1)

7 6 5 4 3 2 1 0
SFR BAh SADEN1.7 SADEN1.6 SADEN1.5 SADEN1.4 SADEN1.3 SADEN1.2 SADEN1.1 SADEN1.0
SADEN1.7–0 Slave Address Mask Enable Register 1. This register functions as a mask when comparing
Bits 7–0 serial port 1 addresses for automatic address recognition. When a bit in this register is set, the
corresponding bit location in the SADDR1 register is exactly compared with the incoming serial
port 1 data to determine if a receiver interrupt should be generated. When a bit in this register is
cleared, the corresponding bit in the SADDR1 register becomes a “don’t care” and is not compared
against the incoming data. All incoming data generates a receiver interrupt when this register is
cleared.
Serial Port 1 Control (SCON1)
7 6 5 4 3 2 1 0
SFR C0h SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1
SM0–2 Serial Port 1 Mode. These bits control the mode of serial port 1 as shown in the following table.
Bits 7, 6, 5 In addition, the SM0 and SM2 bits have secondary functions as shown.
Serial Port 1 Modes and Functions

SM0 SM1 SM2 MODE FUNCTION LENGTH (BITS) PERIOD
0 1 X 1 Asynchronous 10 Timer 1 or 2 baud rate equation
1 0 0 2 Asynchronous 11 See PMR register
1 0 1 2 11 See PMR register
communication
1 1 0 3 Asynchronous 11 Timer 1 or 2 baud rate equation
1 1 1 3 11 Timer 1 or 2 baud rate equation
communication
_____________________________________________________________________________________________ 26
SM0/FE_1 Framing Error Flag. When SMOD0 (PCON.6) = 0, this bit is used as a mode select bit (SM0) for
Bit 7 serial port 1. When SMOD0 (PCON.6) = 1, this bit becomes a framing error (FE) bit, which reports
detection of an invalid stop bit. When used as FE, this bit must be cleared in software. Once the
SMOD0 bit is set, modifications to this bit does not affect the serial port mode settings. Although
accessed from the same register, the data for bits SM0 and FE are stored internally in different
physical locations.
SM1_1 No alternate function.
Bit 6
SM2_1 Multiple CPU Communications. The function of this bit is dependent on the serial port 1 mode.
Bit 5 Mode 0: Selects period for synchronous port 1 data transfers.
Mode 1: When this bit is set, reception is ignored (RI_1 is not set) if invalid stop bit received.
Modes 2/3: When this bit is set, multiprocessor communications are enabled in mode 2 and 3. This
prevents RI_1 from being set, and an interrupt being asserted, if the 9th bit received is not 1.
REN_1 Receive Enable. This bit enables/disables the serial port 1 receiver shift register.
Bit 4 0 = Serial port 1 reception disabled.
1 = Serial port 1 receiver enabled (modes 1, 2, 3). Initiate synchronous reception (mode 0).
TB8_1 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial port 1
Bit 3 modes 2 and 3.
RB8_1 9th Received Bit State. This bit identifies the state for the 9th reception bit received data in serial
Bit 2 port 1 modes 2 and 3. In serial port mode 1, when SM2_1 = 0, RB8_1 is the state of the stop bit.
RB8_1 is not used in mode 0.
TI_1 Transmitter Interrupt Flag. This bit indicates that data in the serial port 1 buffer has been com-
Bit 1 pletely shifted out. In serial port mode 0, TI_1 is set at the end of the 8th data bit. In all other modes,
this bit is set at the end of the last data bit. This bit must be manually cleared by software.
RI_1 Transmitter Interrupt Flag. This bit indicates that a byte of data has been received in the serial
Bit 0 port 1 buffer. In serial port mode 1, RI_1 is set at the end of the 8th bit. In serial port mode 1, RI_1
is set after the last sample of the incoming stop bit subject to the state of SM2_1. In modes 2 and
3, RI_1 is set after the last sample of RB8_1. This bit must be manually cleared by software.
Serial Data Buffer 1 (SBUF1)

7 6 5 4 3 2 1 0
SFR C1h SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
SBUF1.7–0 Serial Data Buffer 1. Data for serial port 1 is read from or written to this location. The serial
Bits 7–0 transmit and receive buffers are separate registers, but both are addressed at this location.
27 _____________________________________________________________________________________________
ROM Size Select (ROMSIZE)
7 6 5 4 3 2 1 0
SFR C2h — — — — PRAME RMS2 RMS1 RMS0
R-1 R-1 R-1 R-1 RT-0 RT-1 RT-0 RT-1
LPX0 Least Significant Priority Select Bit for External Interrupt 0. MPX0 is the least significant bit of
Bit 0 the bit pair MPX0 (IP1.0), LPX0 that designates priority level for external interrupt 0.
Bits 7–3 These bits are reserved. Read data is 1.
PRAME Program RAM Enable. When set (= 1), the internal 1k RAM is mapped as internal program
Bit 3 space between addresses 0400h–07FFh. All program fetches and MOVC accesses are directed
to this 1k RAM. When serving as program memory, the RAM continues to be accessible as MOVX
data space (if DME0 = 1). The 1k RAM is not accessible as program space when EA = 0. When
clear (= 0), the internal 1k RAM is not accessible as program space.
RMS2–0 ROM Memory Size Select 2-0. This register is used to select the maximum on-chip decoded
Bits 2–0 address. Care must be taken that the memory location of the current program counter is valid
both before and after modification. These bits can only be modified using a timed-access procedure.
The EA pin overrides the function of these bits when asserted, forcing the device to access external
program memory only. Configuring this register to a setting that exceeds the maximum amount of
internal memory can corrupt device operation. These bits default on reset to the maximum amount
of internal program memory (i.e., 16k for DS89C420).
On-Chip ROM Address
.
RS2 RS1 RS0 MAXIMUM ON-CHIP ROM ADDRESS
0 0 0 0kB/Disable on-chip ROM
0 0 1 1kB/03FFh
0 1 0 2kB/07FFh
0 1 1 4kB/0FFFh
1 0 0 8kB/1FFFh
1 0 1 16kB/3FFFh (default)
1 1 0 32kB/7FFFh
1 1 1 64kB/FFFFh
Power Management Register (PMR)

7 6 5 4 3 2 1 0
SFR C4h CD1 CD0 SWB CTM 4X / 2X ALEON DME1 DME0
RW*-1 RW*-0 RW-0 RW*-0 RW*-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset, * = See description
CD1, CD0 Clock Divide Control 1-0. These bits select the number of crystal oscillator clocks required to
Bits 7, 6 generate one machine cycle. Switching between modes requires a transition through the default
divide-by-1 mode (CD1, CD0 = 10b). Attempts to perform an invalid transition are ignored. For
example, going from the crystal multiplier 2X mode to the divide-by-1024 mode would require first
switching from the 2X crystal multiplier mode to the divide-by-1 mode, followed by the switch from
the divide-by-1 to the divide-by-1024 mode. These bits cannot be modified when running from the
internal ring oscillator (RGMD = 1). The divide-by-1024 setting (CD1,CD0 = 11b) cannot be selected
when switchback is enabled (SWB = 1) and a switchback source (serial port or external interrupt)
is active.
CD1,
CLOCK FUNCTION
CD0
00 Crystal multiplier (4X or 2X mode as determined by PMR.3)
01 Reserved (forced into divide-by-1 mode if set)
10 Divide-by-1 (default state)
11 Divide-by-1024
The setting of these bits affects timer and serial port operation. Tables located in the SFR decription
for CKCON (8Eh) detail the respective operational dependencies on these bits.
_____________________________________________________________________________________________ 28
Serial Port Operation (in Oscillator Clocks)
4X/2X CD1:0 CLOCK (MODE 0) CLOCK (MODE 2)
SM2 = 0 SM2 = 1 SMOD = 0 SMOD = 1
1 00 3 1 64 32
0 00 6 2 64 32
X 01 12 4 64 32
X 10 12 4 64 32
X 11 3072 1024 16384 8192
SWB Switchback Enable. This bit allows an enabled external interrupt or serial port activity to force the
Bit 5 clock divide control bits to the divide-by-1 state (01b). Upon acknowledgement of an external
interrupt source, the device switches modes in order to service the interrupt. Note that this means
that an external interrupt must actually be recognized (i.e., be enabled and not masked by higher
priority interrupts) for the switchback to occur. For serial port reception, the switch occurs at the
start of the instructions following the falling edge of the start bit.
CTM Crystal Multiplier Enable. This bit enables (= 1) or disables (= 0) the crystal multiplier function.
Bit 4 When set (= 1), the CKRY bit (EXIF.3) is cleared and the multiplier circuitry begins a stabilization
warm-up period to provide the clock multiplication factor specified by the 4X/2X bit (PMR.3). Upon
completion of the warm-up delay, the CKRY bit is set and the user can then modify CD1,CD0
(PMR.1, PMR.0) to select the crystal multiplier clock output. When clear (= 0), the crystal multipler
circuitry is disabled to conserve power. The CTM bit cannot be changed unless CD1,CD0 = 10b
and RGMD (EXIF.2) is cleared to 0. This bit is automatically cleared to 0 when the processor enters
stop mode.
4X/2X Clock Multiplier Selection. This bit selects the clock multiplication factor as shown. 4X/2X = 0
Bit 3 The frequency multiplier is set to two times the incoming clock by 4X/2X = 0. 4X/2X = 1 sets the
frequency multiplier to 4 times the incoming clock. This bit can only be altered when the crystal
multiplier enable bit (CTM) is cleared. Therefore, it must be set for the desired multiplication factor
prior to setting the CTM bit.
ALEON ALE Enable. When set (= 1), this bit enables the ALE signal output during on-chip program and
Bit 2 data memory accesses. When clear (= 0), the ALE signal output is disabled during on-chip program
and data memory accesses. External memory access automatically enables ALE independent of
the state of ALEON.
DME1, DME0 Data Memory Enable 1-0. These bits determine the functional relationship of the first 1024 bytes
Bits 1, 0 of data memory. Two memory configurations are supported to allow either external data memory
access through the expanded bus of port 0 and port 2, or internal SRAM data memory access.
Note these bits are cleared after a reset, so access to the internal SRAM is prohibited until these
bits are modified.
Data Memory Access
DATA MEMORY
DME1 DME0 ADDRESS MEMORY ACCESS
RANGE
0 0 0000h–FFFFh External Data Memory (default)
0000h–03FFh Internal SRAM Data Memory
X 1
0400h–FFFFh External Data Memory
1 0 Reserved Reserved
Status Register (STATUS)

7 6 5 4 3 2 1 0
SFR C5 PIS2 PIS1 PIS0 — SPTA1 SPRA1 SPTA0 SPRA0
R-0 R-0 R-0 R-1 R-0 R-0 R-0 R-0
PIS2-0 Priority Interrupt Status Bits 2-0. These bits indicate the level of interrupt that is
Bit 7, 6, 5 currently being serviced. (Interrupt levels 0-3 are associated with interrupt sources using the MP,LP
bits found in the IP1 and IP0 SFRS.)
29 _____________________________________________________________________________________________
PIS2-0 INTERRUPT PRIORITY LEVEL

000 No interrupt in progress
001 Level 0 interrupt in progress
101 Power fail warning interrupt in progress
Bit 4 This bit is reserved and reads a logic 1.

SPTA1 Serial Port 1 Transmit Activity Monitor. When set, this bit indicates that data is currently being
Bit 3 transmitted by serial port 1. It is cleared when the internal hardware sets the TI_1 bit. Do not alter
the clock divide control bits (PMR.7-6) while this bit is set or serial port data can be lost.
SPRA1 Serial Port 1 Receive Activity Monitor. When set, this bit indicates that data is currently being
Bit 2 received by serial port 1. It is cleared when the internal hardware sets the RI_1 bit. Do not alter the
clock divide control bits (PMR.7-6) while this bit is set or serial port data can be lost.
SPTA0 Serial Port 0 Transmit Activity Monitor. When set, this bit indicates that data is currently being
Bit 1 transmitted by serial port 0. It is cleared when the internal hardware sets the TI_1 bit. Do not alter
the clock divide control bits (PMR.7-6) while this bit is set or serial port data can be lost.
SPRA0 Serial Port 0 Receive Activity Monitor. When set, this bit indicates that data is currently being
Bit 0 received by serial port 0. It is cleared when the internal hardware sets the RI_1 bit. Do not alter the
clock divide control bits (PMR.7-6) while this bit is set or serial port data can be lost.
Timed Access Register (TA)
7 6 5 4 3 2 1 0
SFR C7h TA.7 TA.6 TA.5 TA.4 TA.3 TA.2 TA.1 TA.0
W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1
W = Unrestricted write, -n = Value after reset
TA.7–0 Timed Access. Correctly accessing this register permits modification of timed access protected
Bits 7–0 bits. Write AAh to this register first, followed within 3 cycles by writing 55h. Timed access protected
bits can then be modified for a period of 3 cycles measured from the writing of the 55h
TF2 Timer 2 Overflow Flag. This flag is set when Timer 2 overflows from FFFFh or the count equal
Bit 7 to the capture register in down count mode. It must be cleared by software. TF2 is only set if RCLK
and TCLK are both cleared to 0.
Timer 2 Control (T2CON)

7 6 5 4 3 2 1 0
SFR C8h TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
EXF2 Timer 2 External Flag. A negative transition on the T2EX pin (P1.1) or timer 2 underflow/overflow
Bit 6 causes this flag to set based on the CP/RL2 (T2CON.0), EXEN2 (T2CON.3), and DCEN
(T2MOD.0) bits (see the following table). If set by a negative transition, this flag must be cleared to
0 by software. Setting this bit in software or detection of a negative transition on the T2EX pin forces
a timer interrupt if enabled.
_____________________________________________________________________________________________ 30
CP/RL2 EXEN2 DCEN RESULT

1 0 X Negative transitions on P1.1 do not affect this bit.
1 1 X Negative transitions on P1.1 set this bit.
0 0 0 Negative transitions on P1.1 do not affect this bit.
0 1 0 Negative transitions on P1.1 set this bit.
Bit toggles whenever Timer 2 underflows/overflows
0 X 1 and can be used as a 17th bit of resolution. In this
mode, EXF2 does not cause an interrupt.
RCLK Receive Clock Flag. This bit determines the serial port 0 time base when receiving data in serial
Bit 5 modes 1 or 3. Setting this bit forces Timer 2 into baud-rate generation mode. The timer operates
from a divide-by-2 of the external clock.
0 = Timer 1 overflow is used to determine receiver baud rate for serial port 0.
1 = Timer 2 overflow is used to determine receiver baud rate for serial port 0.
TCLK Transmit Clock Flag. This bit determines the serial port 0 time base when transmitting data in
Bit 4 serial modes 1 or 3. Setting this bit forces Timer 2 into baud rate generation mode. The timer operates
from a divide-by-2 of the external clock.
0 = Timer 1 overflow is used to determine transmitter baud rate for serial port 0.
1 = Timer 2 overflow is used to determine transmitter baud rate for serial port 0.
EXEN2 Timer 2 External Enable. This bit enables the capture/reload function on the T2EX pin if Timer 2
Bit 3 is not generating baud rates for the serial port.
0 = Timer 2 ignores all external events at T2EX.
1 = Timer 2 captures or reload a value if a negative transition is detected on the T2EX pin.
TR2 Timer 2 Run Control. This bit enables/disables the operation of Timer 2. Halting this timer preserves
Bit 2 the current count in TH2, TL2.
0 = Timer 2 is halted.
C/T2 Counter/Timer Select. This bit determines whether Timer 2 functions as a timer or counter.
Bit 1 Independent of this bit, Timer 2 runs at 2 clocks per tick when used in either baud-rate generator
or clock-output mode.
0 = Timer 2 function as a timer.
1 = Timer 2 counts negative transitions on the T2 pin (P1.0).
CP/RL2 Capture/Reload Select. This bit determines whether the capture or reload function is used for
Bit 0 Timer 2. When set (= 1), Timer 2 captures occur when a falling edge is detected on T2EX(P1.1)
if EXEN2 = 1. When clear (= 0), Timer 2 functions in an autoreload mode. An autoreload occurs
following each overflow if RCLK or TCLK is set or if a falling edge is detected on T2EX if EXEN2 = 1.
0 = Autoreloads occur when Timer 2 overflows or a falling edge is detected on T2EX if EXEN2 = 1.
1 = Timer 2 captures occur when a falling edge is detected on T2EX if EXEN2 = 1.
Timer 2 Mode (T2MOD)

7 6 5 4 3 2 1 0
SFR C9h — — — — — — T2OE DCEN
R-1 R-1 R-1 R-1 R-1 R-1 RW-0 RW-0
31 _____________________________________________________________________________________________
T2MOD 7–2
T2OE Timer 2 Output Enable. This bit enables/disables the clock output function of the T2 pin (P1.0).
Bit 1 When set (= 1), Timer 2 drives the T2 pin with a clock output if C/(T2CON.1) = 0. For this setting,
Timer 2 rollovers do not cause interrupts. When clear (= 0), the T2 pin functions as either a standard
port pin or as a counter input for Timer 2.
DCEN Down Count Enable. This bit, in conjunction with the T2EX (P1.1) pin, controls the direction that
Bit 0 Timer 2 counts in 16-bit autoreload mode.
DCEN T2EX DIRECTION

1 1 Up
1 0 Down
0 X Up
Timer 2 Capture LSB (RCAP2L)

7 6 5 4 3 2 1 0
SFR CAh RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0
RCAP2L.7–0 Timer 2 Capture LSB. This register is used to capture the TL2 value when Timer 2 is configured
Bits 7–0 in capture mode. RCAP2L is also used as the LSB of a 16-bit reload value when Timer 2 is configured
in autoreload mode.
Timer 2 Capture LSB (RCAP2H)
7 6 5 4 3 2 1 0
SFR CBh RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0
RCAP2H.7–0 Timer 2 Capture MSB. This register is used to capture the TH2 value when Timer 2 is configured
Bits 7–0 in capture mode. RCAP2H is also used as the MSB of a 16-bit reload value when Timer 2 is con-
figured in autoreload mode.
Timer 2 LSB (TL2)

7 6 5 4 3 2 1 0
SFR CCh TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 TL2.1 TL2.0
Bits 7–0
Timer 2 MSB (TH2)

7 6 5 4 3 2 1 0
SFR CDh TH2.7 TH2.6 TH2.5 TH2.4 TH2.3 TH2.2 TH2.1 TH2.0
Bits 7–0
_____________________________________________________________________________________________ 32
Program Status Word (PSW)

7 6 5 4 3 2 1 0
SFR D0h CY AC F0 RS1 RS0 0V F1 PARITY
CY Carry Flag. This bit is set if the last arithmetic operation resulted in a carry (during addition)
Bit 7 or a borrow (during subtraction). Otherwise, it is cleared to 0 by all arithmetic operations.
AC Auxiliary Carry Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry into
Bit 6 (during addition) or a borrow (during subtraction) from the high-order nibble. Otherwise, it is
cleared to 0 by all arithmetic operations.
F0 User Flag 0. This is a bit-addressable, general-purpose flag for software control.
Bit 5
RS1, RS0 Register Bank Select 1–0. These bits select which register bank is addressed during register
Bits 4-3 accesses.
Register Bank Addresses
RS1 RS0 REGISTER BANK ADDRESS
0 0 0 00h – 07h
0 1 1 08h – 0Fh
1 0 2 10h – 17h
1 1 3 18h – 1Fh
OV Overflow Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry (addition),
Bit 2 borrow (subtraction), or overflow (multiplication or division). Otherwise it is cleared to 0 by all arith-
metic operations.
F1 User Flag 1. This is a bit-addressable, general-purpose flag for software control.
Bit 1
PARITY Parity Flag. This bit is set to 1 if the module-2 sum of the 8 bits of the accumulator is 1 (odd parity),
Bit 0 and cleared to 0 on even parity.
Flash Memory Control (FCNTL)

7 6 5 4 3 2 1 0
SFR D5h FBUSY FERR — — FC3 FC2 FC1 FC0
R-1 R-0 R-1 R-1 RT-0 RT-0 RT-0 RT-0
FBUSY Flash Busy. This status bit held low (= 0) to indicate that an erase/program operation is in
Bit 7 progress by the MMU. Upon completion of the operation or in the event that an error occurs, this
bit returned to a logic high (= 1).
FERR Flash Error. This status bit will be set (= 1) if an error occurs during any flash program/erase
Bit 6 operation or if an invalid flash command is written to FC3-0. The bit can be cleared only by writing
the flash command bits (FC3-0) to 0000b.
Bits 5-4 Reserved. Read data is 1.
FC3-0 Flash Command Bits 3-0. These command bits provide an interface for executing flash
Bits 3-0 operations. See the Flash Command Bit Operations Table for the list of flash commands rec-
ognized during in-application programming. Note that these bits must always be in the 0000b
(read mode) state to allow program execution from the upper memory bank (2000h – 3FFFh).
33 _____________________________________________________________________________________________
Flash Command Bit Operations

FC3-0 IN-APPLICATION PROGRAMMING
OPERATION
BITS FLASH COMMAND
None–Flash blocks are in read mode. FC3-0 must always be in the 0000b (read mode) state to allow code
0000 Read Mode (default)
execution from the upper memory bank (2000h–3FFFh).
0001 Verify Option Control Register OCR contents presented in FDATA following this command write.
A write of FDATA, specifying an address, returns the byte contents of that memory location to FDATA. Valid
0010 Verify Security Block
address range : (00–3Fh—encryption array); (40h bits 5,4,3 are LB3, LB2, and LB1, respectively).
Sequential writes of address MSB, address LSB to FDATA return the byte contents of that flash memory
0011 Verify Upper Program Memory Bank
location to the FDATA register. Valid address range: (2000h–3FFFh).
0100 Verify Bank Select Bank select bit present in FDATA.0 after issuing this command.
0101 Reserved.
0110 Reserved.
0111 Reserved.
1000 Complement Memory Bank Select Complements the flash memory bank select bit.
1001 Write Option Control Register Writes to FDATA update OCR after issuing this command.
First write to FDATA specify, address, the second write to FDATA should contain data to be written. Valid
1010 Write Security Block
address range : (00–3Fh — encryption array); (40h bits 5,4,3 = LB3, LB2, and LB1, respectively).
Sequential writes of address MSB, address LSB to FDATA causes the next byte written to FDATA to be
1011 Write Upper Program Memory Bank
programmed in the flash memory at that address location. Valid address range: (2000h-3FFFh).
1100 Erase Option Control Register OCR erased to the FFh state.
1101 Erase Security Block Encryption array bytes (00h–3Fh) and lock bits (40h) erased to the FFh state.
1110 Erase Upper Program Memory Bank Upper memory bank (2000h–3FFFh) erased to the FFh state.
This generates a system reset which logically swaps the two banks of flash memory if the bank select bits
1111 System Reset
have been complemented.
Option Control Register

Bits 7–4, 2–0 The Option Control Register is a special flash memory location. These bits are accessible to the
user for storing nonvolatile system information.
Bit 3 This bit designates the POR default state for the watchdog timer reset. If programmed (= 0),
WDCON.1 automatically sets on a power-on reset.
1 = Watchdog reset function disabled on POR.
0 = Watchdog reset function enabled automatically on POR.
Definition of Lock Bits

These bits show the status of firmware security of the on-chip flash memory. For in-application programming, the lock bits are accessed as
part of the security block at address 40h bit positions 5, 4, and 3. The unprogrammed state is a 1 and the programmed state is a 0.
Lock Bit Protection Modes

LEVEL LB3 LB2 LB1 PROTECTION MODE
1 1 1 1 No program lock.
Execution of external MOVC instruction on internal program memory is disabled. Parallel programming
2 1 1 0
and ROM loader programming of the flash memory are disabled.
In addition to level 2, verify operations are disabled and access to internal MOVX data from external
3 1 0 0
program is prohibited.
4 0 0 0 In addition to level 3, external execution is disabled.
_____________________________________________________________________________________________ 34
Flash Memory Data (FDATA)

7 6 5 4 3 2 1 0
SFR D6h FDATA.7 FDATA.6 FDATA.5 FDATA.4 FDATA.3 FDATA.2 FDATA.1 FDATA.0
RW*-0 RW*-0 RW*-0 RW*-0 RW*-0 RW*-0 RW*-0 RW*-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset, * = see description
FDATA.7–0 Flash Memory Data. This register is used by the ROM loader or user software to support the flash
Bits 7–0 memory program/erase operations. Writes to this register are only permitted when a valid flash
command has been loaded into the flash command bits FC3-0 (FCNTL.3-0).
Watchdog Control (WDCON)
7 6 5 4 3 2 1 0
SFR D8h SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT
RW-0 RT-* RW-0 RW-* RT-0 RW-* RT-* RT-0
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset, * = see description
SMOD_1 Serial Modification. This bit controls the doubling of the serial port 1 baud rate in modes 1, 2, and 3.
Bit 7 0 = Serial port 1 baud rate operates at normal speed.
1 = Serial port 1 baud rate is doubled.
POR Power-on Reset Flag. This bit indicates whether the last reset was a power-on reset. This bit is
Bit 6 typically interrogated following a reset to determine if the reset was caused by a power-on reset. It
must be cleared by a timed access write before the next reset of any kind or user software may
erroneously determine that another power-on reset has occurred. This bit is set following a power-
on reset and unaffected by all other resets. This bit automatically cleared when the ROM loader is
invoked.
0 = Last reset was from a source other than a power-on reset.
1 = Last reset was a power-on reset.
EPFI Enable Power-Fail Interrupt. This bit enables/disables the ability of the internal bandgap
Bit 5 reference to generate a power-fail interrupt when VCC falls below approximately 4.5V. While in stop
mode, both this bit and the bandgap Select bit, BGS (EXIF.0), must be set to enable the power-fail
interrupt.
0 = Power-fail interrupt disabled.
1 = Power-fail interrupt enabled during normal operation. Power-fail interrupt enabled in stop mode
if BGS is set.
PFI Power-Fail Interrupt Flag. When set, this bit indicates that a power-fail interrupt has occurred. This
Bit 4 bit must be cleared in software before exiting the interrupt service routine, or another interrupt is
generated. Setting this bit in software generate a power-fail interrupt, if enabled. This bit is auto-
matically cleared when the ROM loader is invoked..
WDIF Watchdog Interrupt Flag. This bit indicates if a watchdog timer event has occurred. The timeout
Bit 3 period of the watchdog timer is controlled by the Watchdog Timer Mode Select bits (CKCON.7-6).
The Watchdog Timer Interrupt Enable bit, EWDI (EIE.4), and Enable Watchdog Timer Reset bit,
EWT (WDCON.1), determine what action is taken. This bit must be cleared in software before
exiting the interrupt service routine, or another interrupt is generated. Setting this bit in software
generates a watchdog interrupt if enabled. This bit can only be modified using a Timed Access
Procedure.
WTRF Watchdog Timer Reset Flag. When set, this bit indicates that a watchdog timer reset has
Bit 2 occurred. It is typically interrogated to determine if a reset was caused by watchdog timer reset. It
is cleared by a power-on reset but otherwise must be cleared by software before the next reset
of any kind or software can erroneously determine that a watchdog timer reset has occurred.
Setting this bit in software does not generate a watchdog timer reset. If the EWT bit is cleared, the
watchdog timer has no effect on this bit. This bit is automatically cleared when the ROM loader is
invoked.
35 _____________________________________________________________________________________________
EWT Enable Watchdog Timer Reset. This bit enables/disables the generation of a watchdog timer
Bit 1 reset 512 system clocks after the occurrence of a watchdog timeout. This bit can only be modi-
fied using a Timed Access Procedure and is unaffected by all other resets. The default power-on
reset state of EWT is determined by Option Control Register bit 3 (OCR.3) located in flash memo
ry. This bit will automatically be cleared when the ROM loader is invoked.
0 = A watchdog reset is not generated after a watchdog timeout
1 = A watchdog reset is generated 512 system clocks after a watchdog timeout unless RWT is
strobed or EWT is cleared.
RWT Reset Watchdog Timer. Setting this bit resets the watchdog timer count. This bit must be set
Bit 0 using a Timed Access procedure before the watchdog timer expires, or a watchdog timer reset
and/or interrupt is generated if enabled. The timeout period is defined by the Watchdog Timer
Mode Select bits (CKCON.7-6). This bit is always be 0 when read.
Accumulator (A or ACC)
7 6 5 4 3 2 1 0
SFR E0h ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
ACC.7–0 Accumulator. This register serves as the accumulator for arithmetic operations.
Bits 7–0
Extended Interrupt Enable (EIE)

7 6 5 4 3 2 1 0
SFR E8h — — — EWDI EX5 EX4 EX3 EX2
R-1 R-1 R-1 RW-0 RW-0 RW-0 RW-0 RW-0

EWDI Watchdog Interrupt Enable. This bit enables/disables the watchdog interrupt.
Bit 4 0 = Disable the watchdog interrupt.
1 = Enable interrupt requests generated by the watchdog timer.
EX5 External Interrupt 5 Enable. This bit enables/disables external interrupt 5.
1 = Enable interrupt requests generated by the INT5 pin.
_____________________________________________________________________________________________ 36
B Register (B)
7 6 5 4 3 2 1 0
SFR F0h B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0
B.7–0 B Register. This register serves as a second accumulator for certain arithmetic operations.
Bits 7–0
Extended Interrupt Priority 1 (EIP1)
7 6 5 4 3 2 1 0
SFR F1h — — — MPWDI MPX5 MPX4 MPX3 MPX2
R-1 R-1 R-1 RW-0 RW-0 RW-0 RW-0 RW-0

MPWDI Most significant priority select bit for watchdog interrupt. Most significant bit of the bit pair
Bit 4 MPWDI, LPWDI (EIP0.4) that designates priority level for the watchdog interrupt.
MPX5 Most significant priority select bit for external interrupt 5. Most significant bit of the bit pair
Bit 3 MPX5, LPX5 (EIP0.3) that designates priority level for external interrupt 5.
Interrupt priority level for the above sources is assigned using one bit from register EIP1 (F1h) and
one bit from EIP0 (F8h). The bit from EIP1 serves as the most significant bit and the bit from EIP0
serves as the least significant bit, in forming a 2-bit binary number. This number represents the pri
ority level. Higher priority interrupts, when enabled, take precedence over lower priority sources.
The power-fail warning interrupt source is assigned Priority Level 4.
Most Significant Priority Select Bit Levels
MP (EIP1.x) LP (EIP0.x) PRIORITY LEVEL
0 1 1
1 0 2
Extended Interrupt Priority 0 (EIP0)

7 6 5 4 3 2 1 0
SFR F8h — — — LPWDI LPX5 LPX4 LPX3 LPX2
R-1 R-1 R-1 RW-0 RW-0 RW-0 RW-0 RW-0
37 _____________________________________________________________________________________________
LPWDI Least significant priority select bit for watchdog interrupt. This is the least significant bit of the
Bit 4 bit pair MPWDI (EIP1.4), LPWDI that designates priority level for the watchdog interrupt.
LPX5 Least significant priority select bit for external interrupt 5. This is the least significant bit of the
Bit 3 bit pair MPX5 (EIP1.3), LPX5 that designates priority level for external interrupt 5.
Least Significant Priority Select Bit Levels

0 1 1
1 0 2
SECTION 5: CPU TIMING

The timing of the ultra-high-speed microcontroller is the area with the greatest departure from the original 8051 series. This section
explains the timing and compares it to the original 8051.
OSCILLATOR
The ultra-high-speed microcontroller provides an on-chip oscillator circuit that can be driven by an external crystal or by an off-chip
TTL clock source. The oscillator circuit provides the internal clocking signals to the on-chip CPU and I/O circuits. In many designs, a
crystal is the preferred clock source. Figure 5-1 shows the required connections for a crystal and typical capacitor values. Some
designs may prefer using an off-chip clock oscillator as the primary clock source. This configuration is illustrated in Figure 5-2. When
using an off-chip oscillator, the duty cycle becomes important. As near as possible, a 50% duty cycle should be supplied.
XTAL1
This pin is the input to an inverting high-gain amplifier. It also serves as the input for an off-chip oscillator. Note that, when using an off-
chip oscillator, XTAL2 is left unconnected.
XTAL2
This pin is the output of the crystal amplifier. It can be used to distribute the clock to other devices on the same board. If using a crys-
tal, the loading on this pin should be kept to a minimum, especially capacitive loading.
OSCILLATOR CHARACTERISTICS
The ultra-high-speed microcontroller was designed to operate with a parallel resonant AT-cut crystal. The crystal should resonate at the
desired frequency in its primary or fundamental mode. The oscillator employs a high-gain amplifier to assure a clean waveform at high
frequency. Due to the high-performance nature of the product, both clock edges are used for internal timing. Therefore, the duty cycle
of the clock source is of importance. A crystal circuit balances itself automatically. Thus crystal users do not need to take extra pre-
cautions concerning duty cycle.
CRYSTAL SELECTION
The ultra-high-speed microcontroller family was designed to operate with fundamental mode crystals for improved stability. Although
most high-speed (i.e., greater than 25MHz) crystals operate from their third overtone, fundamental mode crystals are available from
most major crystal suppliers. Designers are cautioned to ensure that high-speed crystals being specified for use in their application
do operate at the rated frequency in their fundamental mode. The use of a third overtone crystal will typically result in oscillation rates
at one-third the desired speed.
_____________________________________________________________________________________________ 38
ULTRA-HIGH-SPEED ULTRA-HIGH-SPEED
MICROCONTROLLER MICROCONTROLLER
XTAL1 TO INTERNAL CLOCK XTAL1 TO INTERNAL
CIRCUITS OSCILLATOR CIRCUITS
18pF 18pF XTAL2 XTAL2
Figure 5-1. Crystal Connection Figure 5-2. Clock Source Input
SYSTEM CLOCK DIVIDE CONTROL

The DS89C420 provides the ability to speed up or slow down the system clock that is used internally by the CPU. The system clock
divide ratio can be configured to 0.25 (4X multiply mode), 0.5 (2X multiply mode), 1 (default), or 1024 (power management mode) and
is controlled by the CD1:0 bits (PMR.7, PMR.6).
To use the crystal multiply mode, the multiplier circuit must be prompted to warmup in the desired 4X or 2X configuration. The 4X/2X
bit defines the crystal multiplying factor. This bit can be altered only from the divide-by-1 (default) mode, while the crystal multiplier is
disabled (CTM = 0). Once the 4X/2X bit has been configured as desired, setting the CTM bit (PMR.4) initiates the crystal multiplier
warmup period. The CTM bit can only be altered when the CD1:0 bits are set to divide-by-1 mode and the RGMD bit is cleared to 0.
During the multiplier warmup period the CKRY bit remains cleared and the CD1:0 clock control bits cannot be set to 00b. When the
crystal multiplier circuit has completed the warmup and is ready for use, the CKRY (EXIF.3) bit set to a logic 1. At this point, the CD1:0
bits can be modified to select the multiplier output for use as the internal system clock. Specifics of hardware restrictions associated
with the use of the 4X/2X CTM, CKRY, CD1, and CD0 bits are outlined in the SFR descriptions. The prescribed sequence for selecting
the the crystal multiplier is as follows:
1) Ensure that the current clock mode is set to divide-by-1 (CD1:0 = 10b) and that RGMD (EXIF.2) = 0.
2) Clear the CTM bit.
3) Put the 4X/2X bit in the desired state.
4) Set the CTM bit.
5) Poll for the CKRY (EXIF.3) bit to be set (= 1). This takes ~65536 external clock cycles.
6) Set CD1:0 = 00b. The frequency multiplier is engaged on the memory cycle following the writing of these bits.
An additional circuit provides a divide-by-1024 clock source that can be selected as the internal system clock. When programmed to
the divide-by-1024 mode, the user may wish to set the switchback bit (PMR.5: SWB) to force the clock divide control bits automatical-
ly back to the divide-by-1 mode whenever the system detects an externally enabled interrupt or an incoming serial port start bit. This
automatic switchback is only enabled during divide-by-1024 mode, and all other clock control settings are unaffected by interrupts and
serial port activity. The power management mode is detailed further in Section 7 (Power Management).
It is important to remember that changing the system clock frequency affects all aspects of system operation, including timers and ser-
ial port baud rates. These effects are detailed in Section 11 (Programmable Timers) and Section 12 (Serial I/O). The following diagram
illustrates the system clock control function.
4X / 2X
CTM
CRYSTAL CLOCK
OSCILLATOR MULTIPLIER MUX
00
01, 10
SYSTEM
DIVIDE 1024 11 CLOCK
RING
OSCILLATOR
RING
ENABLE
CD0 SELECTOR
CD1
Figure 5-3. System Clock Sources
39 _____________________________________________________________________________________________
EXECUTION MEMORY CYCLE

MUX
INTERNAL SYSCLK/1
00 SYSTEM EXTERNAL MEMORY
01, 10 CLOCK NON PAGE SYSCLK/4 CYCLE
PAGE MODE 1 (1-CYCLE) SYSCLK/1
11 PAGE MODE 1 (2-CYCLE) SYSCLK/2
PAGE MODE 1 (3-CYCLE) SYSCLK/4
PAGE MODE 2 SYSCLK/2 (PROG)
SYSCLK/4 (DATA)
Figure 5-4. Instruction Memory Cycle Determination
INSTRUCTION TIMING
The ultra-high-speed microcontroller executes the industry standard 8051 instruction set. Each instruction requires a minimum of one
memory cycle of execution time, and may require as many as ten memory cycles (DIV AB only). The number of memory cycles required
to execute any given 8051 instruction is documented at the end of this section and can be found in Section 14 (Instruction Set Details).
A memory cycle is the basic timing unit for the ultra-high-speed microcontroller. If internal program code is being executed, a memo-
ry cycle always consists of one system clock. If external program code is being executed, a memory cycle is then composed of 1, 2,
or 4 system clocks, as defined by the external bus configuration (non page mode, page mode 1, or page mode 2).
Calculating the number of external crystal or oscillator clock periods (tCLCL) per memory cycle additionally depends upon how the
user has configured the system clock as a function of the external clock. The system clock control function was covered earlier in the
section. As an example, if the crystal multiplier is used to generate a system clock frequency four times the frequency of the external
clock source, a nonpaged mode external memory cycle would consist of one external clock.
All instructions are coded within an 8-bit field called an op code. This single byte must be fetched from program memory. The CPU
decodes the op code to determine what action the microcontroller must take or whether additional information is needed from memo-
ry. If no other memory is needed, then only 1 byte was required. Thus, the instruction is called a 1-byte instruction. In some cases,
more data is needed. These are 2- or 3-byte instructions.
SINGLE-BYTE INSTRUCTIONS
A single-byte instruction can require anywhere between one and ten memory cycles to execute. When the execution cycle count
exceeds the byte count, the program counter must stall until instruction execution is completed. All MOVX data memory access instruc-
tions have a single-byte op code, but require more memory cycles so that data may be accessed. The MOVX instruction timing is cov-
ered in Section 6 (Memory Access). Following are examples of single byte instructions, each requiring a different number of execution
cycles:
OPCODE NO. OF CYCLES
RRC A 13h 1
DA A D4h 2
RET 22h 3
MUL AB A4h 9
DIV AB 84h 10
2-BYTE INSTRUCTIONS
All 2-byte instructions require a minimum of two cycles, since fetching each byte requires a separate memory access. The first byte is
the instruction op code that is decoded by the CPU. The second byte is normally an operand, or it can specify the location of the
operand. For example, “ADD A, direct” is a 2-byte, two cycle instruction where the second byte specifies the direct address location
of the operand. Due to internal access restrictions, certain direct addressing instructions require one extra memory cycle when oper-
ating on the PSW, SP, DPS, IE, EIE, IP0, IP1, EIP0, or EIP1 register. Following are examples of these and other 2-byte instructions:
OPCODE OPERAND/LOCATION NO. OF CYCLES
ADD A, direct 25h <addr7-0> 2
ADD A, #data 24h <data7-0> 2
SJMP rel 80h <addr7-0> 3
_____________________________________________________________________________________________ 40
ANL direct, A 52h <addr7-0> 2 or 3
ORL direct, A 42h <addr7-0> 2 or 3
DJNZ Rn, direct D8h-DFh <addr7-0> 4
3-BYTE INSTRUCTIONS
Three-byte instructions require a minimum of three cycles since each byte fetch requires one memory cycle. The first byte, the opcode,
instructs the CPU on how to handle the next two bytes. Most 3-byte instructions involve comparison or branching, but not all. Just like
the 2-byte instructions, certain 3-byte instructions may require 1 extra memory cycle when operating on the PSW, SP, DPS, IE, EIE, IP0,
IP1, EIP0, or EIP1 register. Following are examples of 3-byte instructions.
OPCODE OPERAND(s)/LOCATION(s) NO. Of CYCLES
LJMP addr16 02h <addr15-8><addr7-0> 3
MOV dptr, #data16 90h <data15-8><data7-0> 3
MOV direct, direct 85h <addr7-0><addr7-0> 3 or 4
JBC bit, rel 10h <addr7-0><addr7-0> 4 or 5
DJNZ direct, rel D5h <addr7-0><addr7-0> 5
NONPAGE MODE EXTERNAL TIMING

The DS89C420 defaults to a nonpage mode external memory interface. The nonpage mode bus structure requires four system clock
cycles per memory cycle. In the nonpage mode, the ALE signal latches the address LSB on each program fetch. When the cycle count
of an instruction exceeds the byte count, “dummy” fetches are performed each cycle until instruction execution is complete. The fol-
lowing diagrams demonstrate the basic timing for nonpage mode instruction execution.
The first diagram below shows the execution of the DA A instruction (1 byte, two cycles) followed by execution of the RRC A (1 byte,
one cycle) instruction. When a code fetch is made from a different 256-byte page, the new address MSB is presented on port 2.
The second diagram below shows the execution of the INC direct instruction (2 bytes) for the cases where an extra memory cycle is
not (INC DPL) and is (INC DPS) required.
NONPAGE MODE: DA A – RRC A
SYSCLK
ALE
PSEN
PORT 2 MSB ADDRESS MSB ADDRESS
PORT 0 LSB D4 LSB 13 LSB 13 LSB
DA A RRC A
NONPAGE MODE: INC DIRECT (2 CYCLES) – INC DIRECT (3 CYCLES)
SYSCLK
ALE
PSEN
PORT 2 MSB ADDRESS
PORT 0 05 LSB 82 LSB 05 LSB 86 LSB E0 LSB E0
INC DPL INC DPS
41 _____________________________________________________________________________________________
NONPAGE MODE EXTERNAL TIMING (CONTINUED)

The first diagram below illustrates an ACALL instruction (2 bytes, two cycles) with a destination address residing on a different 256-
byte page. This is indicated only by the MSB address change on port 2. The memory cycle duration remains constant.
The second diagram below shows execution of the RET instruction (1 byte, three cycles). Because the cycle count of the RET instruc-
tion exceeds the byte count, two stall cycles (“dummy” fetches) are inserted to allow execution to complete. In this example, the return
address and the RET instruction are on different 256-byte pages (signified by the MSB address change on port 2).
NONPAGE MODE: ACALL – NOP
SYSCLK
ALE
PSEN
PORT 0 LSB 71 LSB 33 LSB 00 LSB
ACALL NOP
NONPAGE MODE: RET – NOP
SYSCLK
ALE
PSEN
PORT 0 LSB 22 LSB LSB LSB 00 LSB
RET NOP
_____________________________________________________________________________________________ 42
PAGE MODE 1 EXTERNAL TIMING—PAGES 1:0 = 10b (FOUR CYCLES)

The page mode 1 external bus structure multiplexes port 2 to provide the address MSB and LSB. Data transactions occur exclusive-
ly on port 0. ALE is used to latch the address MSB only when needed, and PSEN serves as the enable for external program memory.
Page mode 1 must be initiated by internal code memory. To invoke 4-cycle page mode 1 operation, the PAGES1:0 bits must be set to
10b, followed by the setting of the PAGEE bit. In the four-cycle page mode 1 configuration, a page-hit memory cycle is four system
clocks in length, while the page-miss memory cycle requires eight system clocks.
The first diagram below shows the fetch of the DA A instruction (1 byte, two cycles) during a page-miss memory cycle as would occur
when a page boundary is crossed. Like nonpage mode operation, a “dummy” or stall cycle must then be inserted for the single-byte
DA A instruction, since it requires two cycles of execution time. After stalling for one cycle, the real fetch of the RRC A instruction takes
place.
The second diagram below illustrates the fetch of the DA A instruction as the last byte of a 256-byte page. In this case, the stall cycle
needed in executing the DA A instruction coincides with a page-miss memory cycle instead of a page hit (as in the first diagram).
FOUR-CYCLE PAGE MODE 1: (PAGE MISS) – DA A – RRC A
SYSCLK
ALE
PSEN
MISS STALL HIT HIT
PORT 2 MSB ADDRESS LSB ADDRESS LSB ADDRESS LSB ADDRESS
PORT 0 D4 13 13
DA A RRC A
NONPAGE MODE: DA A – (PAGE MISS) – RRC A
SYSCLK
ALE
PSEN STALL
HIT MISS HIT HIT
PORT 2 LSB ADDRESS MSB ADDRESS LSB ADDRESS LSB ADDRESS LSB ADDRESS
PORT 0 D4 13 13
DA A RRC A
43 _____________________________________________________________________________________________

(CONTINUED)
The first diagram below shows execution of the INC direct instruction (2 byte, two or three cycles) for the cases where an extra memory cycle is not
(INC DPL) and is (INC DPS) required.
The second diagram illustrates execution of the ACALL instruction whose destination address is on a different 256-byte page. Therefore, the second
execution cycle of the ACALL instruction is a page-miss memory cycle that requires an ALE signal toggle to be used in order to latch a new address
MSB.
FOUR-CYCLE PAGE MODE 1: INC DIRECT (TWO CYCLES) – INC DIRECT (THREE CYCLES)
SYSCLK
ALE
PSEN
HIT HIT HIT STALL HIT
PORT 2 MSB ADDRESS LSB ADDRESS LSB ADDRESS LSB ADDRESS
PORT 0 05 82 05 86 E0 E0
INC DPL INC DPS
FOUR-CYCLE PAGE MODE: ACALL – (PAGE MISS)
SYSCLK
ALE
PSEN
HIT HIT MISS HIT
PORT 2 LSB ADDRESS LSB ADDRESS MSB ADDRESS LSB ADDRESS LSB ADDRESS
PORT 0 71 33
ACALL
_____________________________________________________________________________________________ 44

(CONTINUED)
The two diagrams below demonstrate the execution of the RET (1 byte, three cycles) instruction. In the first diagram, the return address resides on
the same 256-byte page as that of the executed RET instruction. Two stall cycles are inserted followed by a page-hit memory cycle. In the second
diagram, the return address is on a different 256-byte page from where the RET instruction was executed. In this case, two stall cycles are inserted,
followed by a page-miss memory cycle.
FOUR-CYCLE PAGE MODE 1: RET
SYSCLK
ALE
PSEN
HIT STALL STALL HIT HIT
PORT 2 LSB ADDRESS LSB ADDRESS LSB ADDRESS LSB ADDRESS
PORT 0 22
RET
FOUR-CYCLE PAGE MODE 1: RET – (PAGE MISS)
SYSCLK
ALE
PSEN
HIT STALL STALL MISS
PORT 2 LSB ADDRESS LSB ADDRESS MSB ADDRESS LSB ADDRESS
PORT 0 22
ACALL
45 _____________________________________________________________________________________________
PAGE MODE 1 EXTERNAL TIMING—PAGES 1:0 = 01b (TWO CYCLES)

The page mode 1 external bus structure multiplexes port 2 to provide the address MSB and LSB. Data transactions occur exclusively on port 0. ALE
is used to latch the Address MSB only when needed, and PSEN serves as the enable for external program memory. To invoke two-cycle page mode
1 operation, the PAGES1:0 bits must be set to 01b, followed by the setting of the PAGEE bit. In the two-cycle page mode 1 configuration, a page-hit-
memory cycle is two system clocks in length, while the page-miss memory cycle requires four system clocks.
The first diagram below shows the fetch of the CLR C instruction (1 byte, one cycle) during a page-miss memory cycle, followed by the fetch of the
RRC A instruction (1 byte, one cycle) during a page-hit memory cycle. Since the next instruction, XCH A, @R0 (1 byte, three cycles), requires three
memory cycles to execute, two stall cycles must be inserted for it to complete prior to the next instruction being read.
The second diagram below illustrates the LJMP (3 bytes, three cycles) instruction, whose destination address is on a different 256-byte page than
the LJMP instruction, thus resulting in a page-miss memory cycle.
TWO-CYCLE PAGE MODE 1: (PAGE MISS) – CLR C – RRC A – XCH A, @R0
SYSCLK
ALE
PSEN
MISS HIT HIT STALL STALL HIT HIT
PORT 2 MSB LSB LSB LSB LSB ADDRESS LSB
PORT 0 C3 13 C6
CLR C RRC A XCH A, @R0
TWO-CYCLE PAGE MODE 1: (PAGE MISS) – LJMP ADDR16 – (PAGE MISS)
SYSCLK
ALE
PSEN
MISS HIT HIT MISS HIT HIT
PORT 2 MSB LSB LSB LSB MSB LSB LSB LSB
PORT 0 02 50 00
LJMP ADDR16
_____________________________________________________________________________________________ 46
PAGE MODE 1 EXTERNAL TIMING—PAGES 1:0 = 00b (ONE CYCLE)

The page mode 1 external bus structure multiplexes port 2 to provide the address MSB and LSB. Data transactions occur exclusive-
Note that the one-cycle configuration differs slightly from the two-cycle and four-cycle configurations of the page mode 1 bus structure
in that PSEN does not toggle for consecutive page hits, but stays in the active-low state. To invoke one-cycle page mode 1 operation,
the PAGES 1:0 bits must be set to 00b, followed by the setting of the PAGEE bit. In the 1-cycle Page Mode 1 configuration, a page-hit
memory cycle is one system clock in length, while the page-miss memory cycle requires two system clocks.
In the following first diagram, the CLR C (1 byte, one cycle) instruction fetch occurs during a page-miss memory cycle, followed by the
RRC A instruction (1 byte, 1 cycle) instruction fetch during a page-hit memory cycle. The MUL AB (1 byte, nine cycles) instruction,
which occurs next, requires that the program counter be stalled for eight additional memory cycles so that execution can complete. In
a similar fashion, the DA A (1 byte, two cycles) instruction, which follows the multiply, requires that one stall be inserted.
The second diagram illustrates the memory cycle dependence of some direct instructions on the SFR addressed. The ORL direct, A
is shown for cases where P1 and IE are being addressed.
ONE-CYCLE PAGE MODE 1: (PAGE MISS) – CLR C – MUL AB – DA A – NOP
SYSCLK
ALE
PSEN
MISS HIT HIT STALLS HIT STALL HIT HIT
PORT 2 LSB ADDRESS
PORT 0 C3 13 A4 D4 00
CLR C RRC A MUL AB DA A NOP
ONE-CYCLE PAGE MODE 1: (PAGE MISS) – ORL DIRECT, A (TWO CYCLES) – ORL DIRECT, A (THREE CYCLES) – NOP
SYSCLK
ALE
PSEN
MISS HIT HIT HIT HIT STALL HIT HIT HIT HIT HIT HIT HIT HIT HIT
PORT 2 LSB
PORT 0 45 90 45 A8 00
ORL, P1, A MUL AB NOP
47 _____________________________________________________________________________________________
PAGE MODE 1 EXTERNAL TIMING—PAGES 1:0 = 00b ONE CYCLE) (CONTINUED)

The first diagram below illustrates the JBC bit, rel (3 bytes, four cycles) instruction for the case where the tested bit is clear and the
jump is not taken. Note that one stall cycle must be inserted since the cycle count exceeds the byte count by one. The RET (1 byte,
three cycles) instruction that follows requires insertion of two stall cycles. In this example, the return address is on a different 256-byte
page than the RET instruction, thus resulting in a page-miss memory cycle. The MOV direct, #data (3 bytes, three cycles) executed
next provides an example of an instruction not requiring any stall cycles.
The second diagram shows the same JBC bit, rel instruction for the case where the tested bit is set and the jump is taken. Since the
bit must be cleared and involves one of the special registers (PSW, SP, DPS, IE, EIE, IP0, IP1, EIP0, EIP1), a fifth memory cycle is
required. For this example, the jump taken by the JBC instruction crosses a 256-byte page boundary, while the RET instruction stays
on the same page.
1-CYCLE PAGE MODE 1: (PAGE MISS) – JBC bit, rel (4 CYCLES) – RET – (PAGE MISS) – MOV direct, data
SYSCLK
ALE
PSEN
MISS HIT HIT stall HIT stall stall MISS HIT HIT HIT HIT HIT HIT
PORT2 LSB LSB
10 D1 1D 22 75 90 55
PORT0
JBC PSW.1, $+20h RET MOV P1,#55h
1-CYCLE PAGE MODE 1: (PAGE MISS) – JBC bit, rel (5 CYCLES) – (PAGE MISS) -- RET – MOV direct, data
SYSCLK
ALE
PSEN
MISS HIT HIT stall stall MISS stall stall HIT HIT HIT HIT HIT HIT
PORT2 LSB
10 D1 1D 22 75 90 55
PORT0
JBC PSW.1, $+20h RET MOV P1,#55h
_____________________________________________________________________________________________ 48
PAGE MODE 2 EXTERNAL TIMING—PAGES 1:0 = 11b

The page mode 2 external bus structure multiplexes port 2 between address MSB and data. The address LSB is provided exclusive-
To invoke page mode 2 operation, the PAGES 1:0 bits must be set to 11b, followed by the setting of the PAGEE bit. In the page mode
2 configuration, a page-hit program memory cycle is two system clocks in length, while the page-miss program memory cycle requires
four system clocks. All data memory cycles are four system clocks in length.
The first diagram below shows the fetch of the CLR C instruction (1 byte, 1 cycle) during a page-miss memory cycle, followed by the
fetch of the RRC A instruction (1 byte, one cycle) during a page-hit memory cycle. The next instruction, XCH A, @R0 (1 byte, three
cycles), requires three memory cycles to execute, so two stall cycles must be inserted for it to complete prior to the next instruction
being read.
The second diagram below illustrates the LJMP (3 bytes, three cycles) instruction, whose destination address is on a different 256-byte
page than the LJMP instruction, thus resulting in a page-miss memory cycle.
PAGE MODE 2: (PAGE MISS) – CLR C – RRC A – XCH A, @R0
SYSCLK
ALE
PSEN
MISS HIT HIT stall stall HIT HIT
PORT2 MSB C3 13 C6
PORT0 LSB LSB LSB LSB Address LSB
CLR C RRC A XCH A, @R0
PAGE MODE 2: (PAGE MISS) – LJMP addr16 – (PAGE MISS)
SYSCLK
ALE
PSEN
MISS HIT HIT MISS HIT HIT
PORT2 MSB 02 50 00 MSB
PORT0 LSB LSB LSB LSB LSB LSB
LJMP addr16
COMPARISON TO THE 8051

The original 8051 needed 12 clocks per machine cycle and most instructions executed in either one or two machine cycles. Thus,
except for the MUL and DIV instructions, the 8051 used either 12 or 24 clocks for each instruction. Furthermore, each machine cycle
in the 8051 used two memory fetches. In many cases the second fetch was a dummy, and the extra clock cycles were wasted.
The ultra-high-speed microcontroller uses one clock per memory (or machine) cycle. Where there were primarily one- and two-cycle
instructions before, an instruction on the ultra-high-speed microcontroller may take between one and ten cycles. The divide instruction,
for example, requires 10 cycles. Note however, that the 10 cycles needed for the DIV AB instruction can be executed at one clock per
cycle (10 x 1 = 10 total clock cycles). The instruction is executed 4.8 times faster than the original 8051 architecture which required
four cycles at a rate of 12 clocks per cycle (4 x 12 = 48 total clock cycles). Each instruction is at least four times faster, with the high-
est throughput improvement being 24 times that of the original 8051 architecture.
49 _____________________________________________________________________________________________
Table 5-1 shows each instruction, the number of clocks used in the ultra-high-speed microcontroller, and the number used in the 8051 for
comparison. The factor by which the ultra-high-speed microcontroller improves on the 8051 is shown as the speed advantage. A speed
advantage of 12 means that the ultra-high-speed microcontroller performs the same instruction 12 times faster than the original 8051.
Table 5-2 provides a summary by instruction type. Note that many of the instructions provide multiple op codes. As an example, the
ADD A, Rn instruction can act on one of eight working registers. There are eight op codes for this instruction because it can be used
on eight independent locations. Table 5-2 shows totals for both number of instructions and number of op codes. Averages are provid-
ed in the tables. However, the real speed improvement seen in any system depends on the instruction mix.
Table 5-1. INSTRUCTION TIMING COMPARISON

Ultra-high-speed microcontroller is abbreviated as UHSM.
UHSM UHSM 8051 8051 UHSM vs.
HEX CLOCK TIME CLOCK TIME 8051 SPEED
INSTRUCTION CODE CYCLES @ 25MHz CYCLES @ 25MHz ADVANTAGE
ADD A, Rn 28..2F 1 40 ns 12 480 ns 12
ADD A, direct 25 2 80 ns 12 480 ns 6
ADD A, @Ri 26..27 2 80 ns 12 480 ns 6
ADD A, #data 24 2 80 ns 12 480 ns 6
ADDC A, Rn 38..3F 2 80 ns 12 480 ns 6
ADDC A, direct 35 2 80 ns 12 480 ns 6
ADDC A, @Ri 36..37 2 80 ns 12 480 ns 6
ADDC A, #data 34 2 80 ns 12 480 ns 6
SUBB A, Rn 98..9F 1 40 ns 12 480 ns 12
SUBB A, direct 95 2 80 ns 12 480 ns 6
SUBB A, @Ri 96..97 2 80 ns 12 480 ns 6
SUBB A, #data 94 2 80 ns 12 480 ns 6
INC A 04 1 40 ns 12 480 ns 12
INC Rn 08..0F 1 40 ns 12 480 ns 12
INC direct 05 2 80 ns 12 480 ns 6
INC @Ri 06..07 2 80 ns 12 480 ns 6
INC DPTR A3 1 40 ns 24 960 ns 24
DEC A 14 1 40 ns 12 480 ns 12
DEC Rn 18..1F 1 40 ns 12 480 ns 12
DEC direct 15 2 80 ns 12 480 ns 6
DEC @Ri 16..17 2 80 ns 12 480 ns 6
MUL AB A4 9 360 ns 48 960 ns 5.33
DIV AB 84 10 400 ns 48 960 ns 4.80
DA A D4 2 80 ns 12 480 ns 6
ANL A, Rn 58..5F 1 40 ns 12 480 ns 12
ANL A, direct 55 2 80 ns 12 480 ns 6
ANL A, @Ri 56..57 2 80 ns 12 480 ns 6
ANL A, #data 54 2 80 ns 12 480 ns 6
ANL direct, A 52 2 80 ns 12 480 ns 6
ANL direct, #data 53 3 120 ns 24 960 ns 8
_____________________________________________________________________________________________ 50

ORL A, Rn 48..4F 1 40 ns 12 480 ns 12
ORL A, direct 45 2 80 ns 12 480 ns 6
ORL A, @Ri 46..47 2 80 ns 12 480 ns 6
ORL A, #data 44 2 80 ns 12 480 ns 6
ORL direct, A 42 2 80 ns 12 480 ns 6
ORL direct, #data 43 3 120 ns 24 960 ns 8
XRL A, Rn 68..6F 1 40 ns 12 480 ns 12
XRL A, direct 65 2 80 ns 12 480 ns 6
XRL A, @Ri 66..67 2 80 ns 12 480 ns 6
XRL A, #data 64 2 80 ns 12 480 ns 6
XRL direct, A 62 2 80 ns 12 480 ns 6
XRL direct, #data 63 3 120 ns 24 960 ns 8
CLR A E4 1 40 ns 12 480 ns 12
CPL A F4 1 40 ns 12 480 ns 12
RL A 23 1 40 ns 12 480 ns 12
RLC A 33 1 40 ns 12 480 ns 12
RR A 03 1 40 ns 12 480 ns 12
RRC A 13 1 40 ns 12 480 ns 12
SWAP A C4 1 40 ns 12 480 ns 12
MOV A, Rn E8..EF 1 40 ns 12 480 ns 12
MOV A, direct E5 2 80 ns 12 480 ns 6
MOV A, @Ri E6..E7 2 80 ns 12 480 ns 6
MOV A, #data 74 2 80 ns 12 480 ns 6
MOV Rn, A F8..FF 1 40 ns 12 480 ns 12
MOV Rn, direct A8..AF 2 80 ns 24 960 ns 12
MOV Rn, #data 78..7F 2 80 ns 12 480 ns 6
MOV direct, A F5 2 80 ns 12 480 ns 6
MOV direct, Rn 88..8F 2 80 ns 24 960 ns 12
MOV direct, direct 85 3 120 ns 24 960 ns 8
MOV direct, @Ri 86..87 2 80 ns 24 960 ns 12
MOV direct, #data 75 3 120 ns 24 960 ns 8
MOV @Ri, A F6..F7 1 40 ns 12 480 ns 12
MOV @Ri, direct A6..A7 2 80 ns 24 960 ns 12
MOV @Ri, #data 76..77 2 80 ns 12 480 ns 6
MOV DPTR, #data 16 90 3 120 ns 24 960 ns 8
MOVC A, @A+DPTR 93 3 120 ns 24 960 ns 8
MOVC A, @A+PC 83 3 120 ns 24 960 ns 8
MOVX A, @Ri E2..E3 2 80 ns 24 960 ns 12
MOVX A, @DPTR E0 2 80 ns 24 960 ns 12
MOVX @Ri, A F2..F3 2 80 ns 24 960 ns 12
51 _____________________________________________________________________________________________

MOVX @DPTR, A F0 2 80 ns 24 960 ns 12
PUSH direct C0 2 80 ns 24 960 ns 12
POP direct D0 2 80 ns 24 960 ns 12
XCH A, Rn C8..CF 2 80 ns 12 480 ns 6
XCH A, direct C5 3 120 ns 12 480 ns 4
XCH A, @Ri C6..C7 3 120 ns 12 480 ns 4
XCHD A, @Ri D6..D7 3 120 ns 12 480 ns 4
CLR C C3 1 40 ns 12 480 ns 12
CLR bit C2 2 80 ns 12 480 ns 6
SETB C D3 1 40 ns 12 480 ns 12
SETB bit D2 2 80 ns 12 480 ns 6
CPL C B3 1 40 ns 12 480 ns 12
CPL bit B2 2 80 ns 12 480 ns 6
ANL C, bit 82 2 80 ns 24 960 ns 12
ANL C, B0 2 80 ns 24 960 ns 12
ORL C, bit 72 2 80 ns 24 960 ns 12
ORL C, A0 2 80 ns 24 960 ns 12
MOV C, bit A2 2 80 ns 12 480 ns 6
MOV bit, C 92 2 80 ns 24 960 ns 12
ACALL addr 11 Hex code
Hex codes = 11, 31, 51, Byte 1 2 80 ns 24 960 ns 12
71, 91, B1, D1, or F1
LCALL addr 16 12 3 120 ns 24 960 ns 8
RET 22 3 120 ns 24 960 ns 8
RETI 32 3 120 ns 24 960 ns 8
AJMP addr 11 Hex code
Hex code = 01, 21, 41, Byte 1 2 80 ns 24 960 ns 12
61, 81, A1, C1, or E1
LJMP addr 16 02 3 120 ns 24 960 ns 8
JMP @A+DPTR 73 3 120 ns 24 960 ns 8
SJMP rel 80 3 120 ns 24 960 ns 8
JZ rel 60 3 120 ns 24 960 ns 8
JNZ rel 70 3 120 ns 24 960 ns 8
JC rel 40 3 120 ns 24 960 ns 8
JNC rel 50 3 120 ns 24 960 ns 8
JB bit, rel 20 4 160 ns 24 960 ns 6
JNB bit, rel 30 4 160 ns 24 960 ns 6
JBC bit, rel 10 4 160 ns 24 960 ns 6
CJNE A, direct, rel B5 5 200 ns 24 960 ns 4.8
_____________________________________________________________________________________________ 52

CJNE A, #data, rel B4 4 160 ns 24 960 ns 6
CJNE Rn, #data, rel B8..BF 4 160 ns 24 960 ns 6
CJNE @Ri, #data, rel B6..B7 5 200 ns 24 960 ns 4.8
DJNZ Rn, rel D8..DF 4 160 ns 24 960 ns 6
DJNZ direct, rel D5 5 200 ns 24 960 ns 4.8
NOP 00 1 40 ns 12 480 ns 12
Table 5-2. INSTRUCTION SPEED SUMMARY

SPEED
INSTRUCTION CATEGORY QUANTITY
ADVANTAGE
Total instructions: 1 byte 4.0 2
4.8 1
5.3 1
6.0 12
8.0 5
12.0 27
24.0 1
6.0 27
8.0 5
12.0 13
6.0 5
8.0 8
Average across all instructions 8.5 111
SPEED
OPCODE CATEGORY ADVANTAGE QUANTITY
Total opcodes: 1 byte 4.0 4
4.8 1
5.3 1
6.0 35
8.0 5
12.0 93
24.0 1
Total opcodes: two byte 4.0 1
6.0 42
8.0 5
12.0 43
Total opcodes: three byte 4.8 4
6.0 12
8.0 8
Average across all opcodes 9.4 255
SECTION 6: MEMORY ACCESS

The DS89C420 ultra-high-speed microcontroller supports the memory interface convention established for the industry standard
80C51, but also implements two new page mode memory interfaces needed to support ultra-high-speed external operation. These
external page mode interfaces are described later in this section.
53 _____________________________________________________________________________________________
Program and data memory areas can be implemented on-chip, off-chip, or as a combination. When opting not to use the internal mem-
ory provided, or when exceeding the maximum address of on-chip program or data memory, the device performs an external mem-
ory access using the expanded memory bus on ports 0 and 2. While serving as a memory bus, port 0 and port 2 cannot function as
I/O ports. The PSEN signal is driven active low to function as a chip enable or output enable when performing external code memory
fetches. The RD and WR signals serve as enables when accessing external SRAM data memory.
Program execution always begins at the reset vector, address 0000h. If on-chip program memory is enabled, program execution
begins at internal location 0000h; otherwise, external program memory is used. Any reset causes the next program fetch to begin at
this location. Subsequent branches and interrupts determine how program memory fetches deviate from sequential addressing.
INTERNAL FLASH MEMORY
The DS89C420 ultra-high-speed microcontroller contains five physically distinct blocks of embedded flash memory. The two largest
blocks, each 8kB, provide a total of 16kB for use as internal program memory. A 64-byte flash security block has been incorporated
to allow encryption during program memory verify operations. To further protect internal code against undesirable access, a three-level
lock system has been implemented in a separate flash memory block. This single-byte block contains three lock bits (LB1, LB2, LB3),
each of which can individually enable higher lock levels and greater code protection. The fifth flash memory block resident to the
DS89C420 is the option control register. This byte contains a bit to enable or disable the watchdog timer reset function (EWT =
WDCON.1) on a power-on reset.
The two 8kB program memory blocks form a contiguous 16kB address range extending from 0000h through 3FFFh. The on-chip
decoded address range is controlled in hardware by the EA pin, and in software through the ROMSIZE feature. The EA pin enables or
disables the ability to access internal program memory and overrides any software configured bit settings. The logic state of the EA
pin should be changed only when the microcontroller is being held in reset. The EA pin is sampled on each exit from the reset state to
determine whether program fetching should begin internally or externally. When the EA pin is low, all code fetches are done external-
ly through the expanded bus. When the EA pin is high, code fetches begin from internal program memory. Code fetches exceeding
the maximum address of on-chip program memory cause the device to access off-chip program memory. The maximum on-chip
decoded address is selectable by software using the ROMSIZE feature.
ROMSIZE FEATURE
Using the ROMSIZE feature, software can allow the DS89C420 to behave like a device with less on-chip memory. The maximum mem-
ory size is dynamically variable. Thus, a portion of memory can be removed from the memory map to access off-chip memory, then
restored to access on-chip memory. In fact, all of the on-chip memory can be removed from the memory map, allowing the full 64kB
of external memory space to be addressed.
The ROMSIZE feature has two primary uses. In the first instance, it allows the device to act as a bootstrap loader for a flash memory
or nonvolatile SRAM (NVSRAM). The internal program memory can contain a bootstrap loader, which can program the external mem-
ory device. Secondly, this method can be used to increase the amount of available program memory from 64kB to 80kB without bank
switching.
The maximum amount of on-chip memory is selected by configuring the ROM size select register bits RMS2, RMS1, RMS0 (ROM-
SIZE.2-0). The reset default condition gives access to the maximum on-chip program memory of 16kB. In this configuration, only code
addresses greater than 16kB result in external program memory accesses. The possible settings for the ROM size select register are
shown in the following table.
Table 6-1. ROMSIZE REGISTER SETTINGS
RMS2 RMS1 RMS0 MAX ON-CHIP PROGRAM MEMORY
0 0 0 0kB
0 0 1 1kB (0-03FFh)
0 1 0 2kB (0-07FFh)
0 1 1 4kB (0-0FFFh)
1 0 0 8kB (0-1FFFh)
1 0 1 16kB (0-3FFFh) DEFAULT
1 1 0 INVALID – RESERVED
1 1 1 INVALID – RESERVED
Modification of the ROMSIZE (C2h) special function register requires using the timed access procedure and must be followed by a two
machine cycle delay, such as executing two NOP instructions, before jumping to the new address range. Interrupts must be disabled
during this operation, because a call to an interrupt vector during the changing of the memory map can cause erratic results. To select
_____________________________________________________________________________________________ 54
a different internal program memory size, software must alter bits RMS2–RMS0. The procedure to reconfigure the size of on-chip mem-
ory should be done as follows:
1) Jump to a location in program memory that is unaffected by the change.
2) Disable interrupts by clearing the EA bit (IE.7).
3) Write AAh to the timed access register (TA;C7h).
4) Write 55h to the timed access register (TA;C7h).
5) Modify the ROM size select bits (RMS2-RMS0).
6) Delay 2 machine cycles (2 NOP instructions).
7) Enable interrupts by setting the EA bit (IE.7).
As noted in the first step above, ensure that changes the ROMSIZE register do not corrupt program execution. For example, assume
that a DS89C420 is executing instructions from internal program memory near the 12kB boundary (~3000h) and the ROMSIZE regis-
ter is still configured to the default 16kB internal program space. If software reconfigures the ROMSIZE register for a maximum of 4kB
(0000h–0FFFh) internal program space (RMS2–0 = 011b), the device immediately accesses external program memory since current
program execution no longer resides within the new on-chip decoded range. This could result in code misalignment and execution of
an invalid instruction. The recommended method is to modify the ROMSIZE register from a location in memory that is internal (or exter-
nal) both before and after the operation. In the above example, the instruction which modifies the ROMSIZE register should be locat-
ed below the 4kB (1000h) boundary or above the 16kB boundary, so that it is unaffected by the memory modification. The same rule
applies when executing from external program memory and increasing the on-chip decoded address range.
If the 0kB of internal program memory setting is selected, take extra precautions. In this case, it is necessary to duplicate the interrupt
vector table in external program memory. This is because the interrupt vector table is located in the lower 1kB of memory, and the
device automatically redirects any fetches from the interrupt vector table to external memory. Be careful when assembling or compil-
ing the program so that all the modules are located at the correct starting address, including the interrupt vector table.
FLASH SECURITY BLOCK/LOCK BITS

The DS89C420 incorporates a 64-byte encryption array, allowing the user to verify program codes while viewing the data in encrypt-
ed form. The encryption array, often referred to as the security block, has the same electrical and timing characteristics as the on-chip
program memory. Once the encryption array is programmed to non-FFh, the data presented in the verify mode is encrypted. Each byte
of data is XNORed with a byte in the encryption array during verification. If the security block is used, program unused portions of the
internal 16kB flash program memory range with random data so that the encryption vector cannot be easily extracted.
The single byte, which contains the 3 lock bits, logically resides at byte address 40h of the security block. The 3 lock bits (LB3, LB2,
and LB1) can be accessed in bit positions 5, 4, and 3, respectively. By programming the 3 lock bits, the user may select a level of
security as specified in table below. Once a security level is selected and programmed, the setting of the lock bits remains. Only a
mass erase erases these bits and allows reprogramming the security level to a less restricted protection.
Table 6-2. Flash Memory Lock Bits

LEVEL LB1 LB2 LB3 PROTECTION
1 1 1 1 No program lock. Encrypted verify if encryption array is programmed.
Prevent MOVC in external memory from reading program code in internal memory.
2 0 1 1 EA is sampled and latched on reset. Allow no further parallel or program memory
Loader programming.
Level 2 plus no verify operation. Also prevent MOVX in external memory from
3 X 0 1
reading internal SRAM.
4 X X 0 Level 3 plus no external execution.
The read/write accessibility of the flash memory during in-application programming is not affected by the state of the lock bits. However,
the lock bits do affect the read/write accessibility in program memory loader and parallel programming modes.
OPTION CONTROL REGISTER BYTE

The DS89C420 provides user-selectable options that must be set before beginning software execution. The option control register uses
flash bits, rather than SFRs, and is individually erasable and programmable as a byte-wide register. Bit 3 of this register is defined as
the watchdog POR default. Setting this bit to 1 disables the watchdog reset function on power-up, and clearing this bit to 0 enables
55 _____________________________________________________________________________________________
the watchdog reset function automatically. Other bits of this register are undefined and are at logic 1 when read. The value of this reg-
ister can be read at address FCh in parallel programming mode or by executing the verify option control register instruction in ROM
Loader or in-application programming mode.
FFFF FFFF
Note: The hatched areas shown on the internal and external

memory are disabled on power-up (Default)
INTERNAL
MEMORY
03FF
1kB x 8
SRAM External External
Program Data
INTERNAL SCRATCH Data OR Memory Memory
REGISTERS PAD prog mem
addr from
128 Bytes SFR 0000
400–7FF
4000
FF 3FFF
8kB x 8
128 Bytes Flash
Indirect Memory
Addressing (Program)
2000
80
7F
1FFF
2F
20 Bit Addressable 8kB x 8
1F Flash
Bank 3
Memory 03FF
Bank 2 Non-usable if
(Program)
Bank 1 Internal SRAM
Bank 0 is activated
00 0000 0000 0000
Figure 6-1. Memory Map
INTERNAL SRAM MEMORY

The DS89C420 ultra-high-speed microcontroller incorporates an internal 1kB SRAM that is usable as data, program, or merged pro-
gram/data memory. Upon a power-on reset, the internal 1kB memory is disabled and transparent to both program and data memory
maps.
When used for data, the memory is addressed through MOVX commands, and is in addition to the 256 bytes of scratchpad memory.
To enable the 1kB SRAM as internal data memory, software must set the DME0 bit (PMR.0). After setting this bit, all MOVX accesses
within the first 1kB (0000h–03FFh) is directed to the internal SRAM. Any data memory accesses outside of this range are still directed
to the expanded bus. One advantage of using the internal data memory is that MOVX operations automatically default to the fastest
access possible. Note that the DME0 bit is cleared after any reset, so access to the internal data memory is prohibited until this bit is
modified. The contents of the internal data memory are not affected by the changing of the data memory enable (DME0) bit. Table 6-
3 shows how the DME1, DME0 bits affect the data memory map.
_____________________________________________________________________________________________ 56
Table 6-3. Data Memory Access Control

DME1 DME0 DATA MEMORY ADDRESS RANGE DATA MEMORY LOCATION
0 0 0000h–FFFFh External Data Memory (default)
X 1 0000h–03FFh Internal Data Memory
1 0 Reserved Reserved
PSEN OE
ALE CK
LSB ADDRESS (8)
74F373
PORT 0 LATCH 32kB X 8
MEMORY
DS80C320 DATA BUS (8)

CE
MSB ADDRESS (7)

PORT 2
Figure 6-2. Program Memory Interconnect (Nonpage Mode)
When configured as program memory, code fetches and MOVC read operations can be directed to this 1kB internal SRAM. To enable
the 1kB SRAM as internal program memory, software must set the PRAME bit (ROMSIZE.3). After setting this bit, code accesses to the
address range 0400h–07FFh are made to the internal 1kB SRAM in place of the program memory previously mapped to that address
range. For applications using only external program memory (EA = 0), the internal 1kB SRAM cannot be enabled as program space.
The internal 1kB SRAM can serve as merged program/data memory if both the DME0 and PRAME bits have been set. This feature can
be effective for changing small pieces of frequently executed code, but be cautious when employing self-modifying code techniques.
PROGRAM MEMORY INTERFACE—NONPAGE MODE

The DS89C420 defaults to a nonpage mode, external program memory interface. This memory interconnect scheme is the same as is
used for the high-speed microcontroller family, and is shown in Figure 6-2. This example uses the DS89C420 and one 32k x 8 memo-
ry device. The program store enable (PSEN) signal is used to provide an output enable to the memory. It can also be used to provide
a chip enable, but this generally results in less-favorable timing. The address LSB and data are multiplexed on port 0, and the address
MSB is provided on port 2. An external latch, shown in the diagram as a 74F373, is used to latch the lower byte of the address to the
memory device. The address latch enable (ALE) signal controls the timing of the latch so that the operation is performed in the prop-
er sequence. The signals and relative timing for a program access are shown in Figure 6-3.
When implementing a high-speed memory interface, the F series (or faster) logic should be used. HC logic has worst-case propaga-
tion delays that are too long. Specifications for all devices should be checked. More information on the nonpage mode memory inter-
face timing can be found in Application Note 57 (DS80C320 Memory Interface Timing) and Application Note 85 (High-Speed
Microcontroller Interface Timing).
The DS89C420 provides an extremely high-speed interface to external memory. This allows for use of the slowest, and least expen-
sive, memory device for a given crystal speed. The DS89C420 provides very fast slew rates to allow the maximum possible time for
memory access. Refer to the electrical specifications for exact timing.
Figure 6-3 shows the timing relationship for internal and external nonpage mode code fetches when CD1:0 = 10b. Note that an exter-
nal program fetch takes four system clocks, and an internal program fetch requires only one system clock.
57 _____________________________________________________________________________________________
Internal Memory Cycles Ext Memory Cycle Ext Memory Cycle

C1 C2 C3 C4 C1 C2 C3 C4
XTAL1
ALE
PSEN
LSB Add Data LSB Add Data
Port 0
Port 2 MSB Add MSB Add
Figure 6-3. External Program Memory Access (Nonpage Mode and CD1:0 = 10b)
As illustrated in that same figure, ALE is deasserted when executing an internal memory fetch. The DS89C420 provides a program-
mable user option (ALEON bit = PMR.2) to turn on the ALE signal during internal program memory operation. The ALE signal is
automatically enabled for external code fetches, independent of the setting of this bit. PSEN is asserted only for external code fetch-
es, and is inactive during internal execution.
PROGRAM MEMORY INTERFACE—PAGE MODES

Page mode retains the basic external circuitry requirements as the original 8051 external memory interface, but modifies the
address/data roles of P0 and P2 in order to achieve the most efficient single-cycle external operation possible. The functions of ALE
and PSEN are also altered to support page mode operation.
Page mode is enabled by setting the PAGEE (ACON.7) bit to a logic 1. Clearing the PAGEE bit disables the page mode and returns
the DS89C420 to the traditional external bus structure of the 8051 (nonpage mode). The DS89C420 supports page mode in two exter-
nal bus structures. The page mode select bits (PAGES1:0) contained in the ACON register determine the external bus structure and
the number of system clocks per basic memory cycle. The following table summarizes the four options available through the PAGES
bits. The first three selections all represent the page mode 1 external bus structure, but with different memory cycle timings. The last
configuration (PAGES = 11b) selects the page mode 2 bus structure.
Table 6-4. Page Mode Select

EXTERNAL ADDRESSING CLOCKS PER MEMORY CYCLE
MODE PAGES1:PAGES0 PAGE HIT PAGE MISS EXTERNAL BUS STRUCTURE
Page mode 1 (1 cycle) 00 1 2 PAGE MODE 1
Page mode 2 11 2* 4 PAGE MODE 2
Note: External data memory accesses always require four clock cycles, regardless of page hit or page miss.
_____________________________________________________________________________________________ 58
PAGE MODE 1: P0: Primary data bus.

P2: Primary address bus, multiplexing the upper byte and lower byte of address.
PAGE MODE 2: P0: Lower address byte.
P2: Upper address byte is multiplexed with the data byte.
In addition to being accessible to the user application code, the page mode enable and select bits can also be modified while in boot-
strap loader mode. This allows in-system MOVX read/write access to external memory already connected according to the page mode
1 or page mode 2 bus structure. Since all resets, including the one generated when exiting bootstrap loader mode, return the
DS89C420 to the nonpage mode external bus structure, user application code must always configure the ACON register appropriate-
ly before addressing page mode external memory. Write access to the ACON register requires using the timed access procedure.
PAGE MODE 1 BUS STRUCTURE

The page mode 1 external bus structure uses P2 as the primary address bus (multiplexing both the most significant byte and least sig-
nificant byte of the address for each external memory cycle), and P0 is used as the primary data bus. This program memory inter-
connect scheme is depicted in Figure 6-4.
PSEN OE
ALE CK
MSB ADDRESS (7)
74F373
LATCH
PORT 2 32kB X 8
MEMORY
LSB ADDRESS (8)
DS80C320
CE
DATA BUS (8)

PORT 0
Figure 6-4 Program Memory Interconnect (Page Mode 1)
During external code fetches, P0 is held in a high-impedance state by the processor. Opcodes are driven by the external memory onto
P0 and latched on the rising edge of PSEN at the end of the external fetch cycle.
• A page miss occurs when the most significant byte of the subsequent address is different from the last address. The exter
nal memory machine cycle can be 2, 4, or 8 system clocks in length for a page miss.
• A page hit occurs when the most significant byte of the subsequent address does not change from the last address. The exter-
nal memory machine cycle can be 1, 2, or 4 system clocks in length for a page hit.
During a page hit, P2 drives Addr [7:0] of the 16-bit address while the most significant address byte is held in the external address latch-
es. PSEN, RD, and RD strobe accordingly for the appropriate operation on the P0 data bus. There is no ALE assertion for page hits.
59 _____________________________________________________________________________________________
During a page miss, P2 drives the Addr [15:8] of the 16-bit address and holds it for the duration of the first half of the memory cycle
to allow the external address latches to latch the new most significant address byte. ALE is asserted to strobe the external address
latches. During this operation, PSEN, RD, and WR are all held in inactive states and P0 is in a high-impedance state. The following half-
memory cycle is executed as a page-hit cycle and the appropriate operation takes place.
A page-miss can occur at set intervals or during external operations that require a memory access into a page of memory that has not
been accessed during the last external cycle. Generally, the first external memory access causes a page miss. The new page address
is stored internally and is used to detect a page miss for the current external memory cycle.
Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to 00b:
• PSEN is asserted for both page hit and page miss for a full clock cycle.
• The execution of external MOVX instruction causes a page miss.
• A page miss occurs when fetching the next external instruction following the execution of an external MOVX instruction.
The figure below shows external memory cycles for the page mode 1 bus structure. The first case illustrates a back-to-back MOVX
execution sequence for one-cycle page mode (PAGES 1:0 = 00b). PSEN remains active during page-hit cycles, and page misses are
forced during and after MOVX executions, independent of the most significant byte of the subsequent addresses. The second case
illustrates a MOVX execution sequence for two-cycle page mode (PAGES 1:0 = 01b). PSEN is active for a full clock cycle in code fetch-
es. Note that the page misses in this sequence are caused by changing of the most significant byte of the data address. The third case
illustrates a MOVX execution sequence for four-cycle page mode (PAGES 1:0 = 10b). There is no page-miss in this execution cycle,
as the most significant byte of the data address is assumed to match the last program address.
Internal Memory Cycles External Memory Cycles
XTAL1
ALE
PSEN
RD / WR
PAGES=00
Port 0 Inst Inst MOVX MOVX Data Inst Data
Port 2 MSB LSB LSB LSB LSB MSB LSB MSB LSB MSB LSB MSB
Page Miss Page Hit Data Access Page Miss Data Access
MOVX executed MOVX executed
ALE
PSEN
RD / WR PAGES=01
Port 0 MOVX Inst Data
Port 2 MSBAdd LSB Add LSB Add MSBAdd LSB Add MSBAdd
Page Miss Page Hit Data Access Page Miss
MOVX executed next instruction
ALE
PSEN
RD / WR
PAGES=10
Port 0 Inst Data
Port 2 MSBAdd LSB Add LSB Add
Page Miss Data Access
Figure 6-5. Page Mode 1 External Memory Cycle (CD1:0 = 10b)
_____________________________________________________________________________________________ 60
PAGE MODE 2 BUS STRUCTURE

The page mode 2 external bus structure multiplexes the most significant address byte with data on P2 and uses P0 for the least sig-
nificant address byte. An illustration of this memory interface is provided in the Figure 6-6.
This bus structure speeds up external code fetches only. Aside from the different functions of P0 and P2 when operating in page mode
2, the external memory accesses are equal in duration and timing to those made in the nonpage mode. Figure 6-7 illustrates memory
cycles for the page mode 2 bus structure.
DATA MEMORY INTERFACE
As described in Section 4, the ultra-high-speed microcontroller provides a small amount of RAM mapped as registers for on-chip direct
access. This is not considered data memory and does not fall into the memory map. Systems that require more RAM or memory-
mapped peripherals must use the data memory area. This segment is a 64kB space located between 0000h and FFFFh. It is reached
PSEN OE
ALE CK
MSB ADDRESS (7)
74F373
PORT 2 LATCH
32kB X 8
MEMORY
CE
LSB ADDRESS (8)

PORT 0
Figure 6-6. Program Memory Interconnect (Page Mode 2)
Ext Code Fetches

Internal Memory Cycles
Page Miss Page Hit Page Hit
C1 C2 C3 C4 C1 C2 C1 C2
XTAL1
ALE
PSEN
Port 0 LSB Add LSB Add LSB Add
Port 2 MSB Add Data Data Data
Figure 6-7. Page Mode 2 External Code Fetch Cycle (CD1:0 = 10B)
61 _____________________________________________________________________________________________
using the MOVX instruction. Any use of this instruction automatically accesses the data area. Although the original 8051 convention
placed all data memory off-chip, the DS89C420 incorporates 1kB of on-chip data memory. The means for enabling and accessing this
1kB SRAM was covered earlier in this section.
From a software standpoint, the physical location of the data area is not relevant because the same instructions are used. Like the pro-
gram segment, if software accesses a data address that is above the on-chip data area, this access is automatically routed to the
expanded bus. Thus, data or peripherals that are off-chip can be used in conjunction with on-chip memory by selecting addresses
that do not overlap. For example, since the DS89C420 microcontroller has 1kB of on-chip data memory, an MOVX instruction at loca-
tion 0400h is directed off-chip through the expanded bus.
The DS89C420 external data memory interface follows the same bus structure as defined for program memory. The page mode enable
(PAGEE) and page mode select (PAGES 1:0) bits control whether the external bus structure follows the nonpage mode, page mode 1,
or page mode 2 scheme. During external data read/write operations, P0 or P2 (depending upon external memory mode) serves as the
bidirectional data bus. This port is held in a high-impedance state for external reads from data memory, and driven with data during
external writes to data memory. The read and write strobes used to access external data memory are provided on P3.7 and P3.6,
respectively.
EXTERNAL DATA MEMORY INTERFACE—NONPAGE MODE

Data memory is accessed through use of the MOVX instruction. This instruction requires two basic memory cycles: a program-fetch
memory access, and then a read or write memory access. Just like the program memory cycle, a basic internal data memory cycle
contains one system clock, and a basic external data memory cycle contains four system clocks for nonpage mode operation. The
program-fetch memory cycle for an MOVX instruction is no different from any other instruction. The unique timing occurs for the sec-
ond memory cycle when data is accessed.
The DS89C420 allows software to adjust the speed of external data memory access by stretching the memory bus cycle. The MD2:0
bits contained in the CKCON (8Eh) SFR provide the means to modify the stretch value. This stretch feature allows the application to
dynamically select the minimum (fastest) access time to each data memory peripheral device. The table below shows the data mem-
ory cycle stretch values and their effect on the read and write control signals associated with the external MOVX memory bus cycle. A
stretch machine cycle always contains four system clocks.
As illustrated in Table 6-5, the stretch feature supports eight external data memory access cycles, which can be categorized into three
timing groups. When the stretch value is cleared to 000b, there is no stretch on external data memory access and a MOVX instruction
is completed in two basic memory cycles. When the stretch value is set to 001b, 010b, or 011b, the external data memory access is
extended by 1, 2, or 3 stretch machine cycles, respectively. Note that the 001b stretch value does not add four system clocks to the
RD or WR control signals but instead uses one system clock to create additional address setup and data bus float time and one sys-
tem clock to create additional address and data hold time. When using very slow RAM and peripherals, a larger stretch value (4–7)
can be selected. In this stretch category, one stretch machine cycle (four system clocks) is used to stretch the ALE pulse width, one
stretch machine cycle is used to create additional setup, and one stretch machine cycle is used to create additional hold time.
Table 6-5. Nonpage Mode Data Memory Stretch Values

MD2: MD0 (STRETCH VALUE) STRETCH CYCLES 4X/2X, CD1, CD0 = 100 4X/2X, CD1, CD0 = 000 4X/2X, CD1, CD0 = X10 4X/2X, CD1, CD0 = X11
000 0 0.5 1 2 2048
001 1 1 2 4 4096
010 2 2 4 8 8192
011 3 3 6 12 12288
100 7 4 8 16 16384
101 8 5 10 20 20480
110 9 6 12 24 24576
111 10 7 14 28 28672
_____________________________________________________________________________________________ 62
ALE CK
LSB ADDRESS (8)
74F373
PORT 0 LATCH
64kB X 8
SRAM
CE
MSB ADDRESS (8)

PORT 2
RD (P3.7) OE
WR (P3.6) WE
Figure 6-8. Data Memory Interconnect (Nonpage Mode)
EXTERNAL DATA MEMORY INTERFACE—PAGE MODES

The DS89C420 allows software to adjust the speed of external data memory access by stretching the memory bus cycle in page mode
operation just like nonpage mode operation. The tables below summarize the stretch values for page mode 1 and page mode 2. The
number of stretch cycles added to the external MOVX operation and the control signal pulse width (in terms of the number of oscilla-
tor clocks) are provided. A stretch machine cycle always contains four system clocks, independent of the logic value of the page mode
select bits.
Just like nonpage mode operation, the stretch feature supports eight stretched external data memory access cycles that can be cat-
egorized into three timing groups. When the stretch value is cleared to 000b, there is no stretch on external data memory access and
a MOVX instruction is completed in two basic memory cycles. When the stretch value is set to 001b, 010b, or 011b, the external data
memory access is extended by 1, 2, or 3 stretch machine cycles, respectively. The 001b stretch value does not add four system clocks
to the RD or WR control signals, but instead uses one system clock to create additional address setup and data bus float time and one
system clock to create additional address and data hold time. When using very slow RAM and peripherals, a larger stretch value (4–7)
can be selected. In this stretch category, one stretch machine cycle (four system clocks) is used to stretch the ALE pulse width, one
stretch machine cycle is used to create additional setup and one stretch machine cycle is used to create additional hold time.
Table 6-6. Page Mode 1—Data Memory Stretch Values 1 Cycle (PAGES 1:0 = 00b)
RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
MD2:MD0 STRETCH
(STRETCH VALUE) CYCLES 4X/2X, CD1, CD0 = 100 4X/2X, CD1, CD0 = 000 4X/2X, CD1, CD0 = X10 4X/2X, CD1, CD0 = X11
000 0 0.25 0.5 1 1024

001 1 0.75 1.5 3 3072
010 2 1.75 3.5 7 7168
011 3 2.75 5.5 11 11264
100 7 3.75 7.5 15 15360
101 8 4.75 9.5 19 19456
110 9 5.75 11.5 23 23552
111 10 6.75 13.5 27 27648
63 _____________________________________________________________________________________________
Table 6-7. Page Mode 1—Data Memory Stretch Values Two Cycles (PAGES 1:0 = 01b)
MD2:MD0 STRETCH
000 0 0.25 0.5 1 1024

001 1 0.75 1.5 3 3072
010 2 1.75 3.5 7 7168
011 3 2.75 5.5 11 11264
100 7 3.75 7.5 15 15360
101 8 4.75 9.5 19 19456
110 9 5.75 11.5 23 23552
111 10 6.75 13.5 27 27648
Table 6-8. Page Mode 1—Data Memory Stretch Values Four Cycles (PAGES 1:0 = 10b)
MD2:MD0 STRETCH
000 0 0.5 1 2 2048

001 1 1 2 4 4096
010 2 2 4 8 8192
011 3 3 6 12 12288
100 7 4 8 16 16384
101 8 5 10 20 20480
110 9 6 12 24 24576
111 10 7 14 28 28672
Table 6-9. Page Mode 2—Data Memory Stretch Values (PAGES 1:0 = 11b)
MD2:MD0 STRETCH
000 0 0.5 1 2 2048

001 1 1 2 4 4096
010 2 2 4 8 8192
011 3 3 6 12 12288
100 7 4 8 16 16384
101 8 5 10 20 20480
110 9 6 12 24 24576
111 10 7 14 28 28672
_____________________________________________________________________________________________ 64
Figures 6-9 and 6-10 below show data memory interconnect examples for page mode 1 and page mode 2.
ALE CK
MSB ADDRESS (8)
74F373
PORT 2 LATCH
64kB X 8
SRAM
DS80C320 LSB ADDRESS (8)
CE
DATA BUS (8)

PORT 0
RD (P3.7) OE
WR (P3.6) WE
Figure 6-9. Data Memory Interconnect (Page Mode 1)
ALE CK
MSB ADDRESS (8)
74F373
PORT 2 LATCH 64kB X 8
SRAM

CE
LSB ADDRESS (8)

PORT 0
RD (P3.7) OE
WR (P3.6) WE
Figure 6-10. Data Memory Interface (Page Mode 2)
The following pages provide timing diagrams to illustrate the external data memory timing for the nonpage and page mode external
bus structures.
65 _____________________________________________________________________________________________
NONPAGE MODE DATA MEMORY TIMING

The first diagram below shows execution of the MOVX instruction from internal program memory with stretch value = 0 assigned
(MD2:0 = 000b). Note that the internal memory cycles consist of one system clock while the external memory cycles always consist of
four system clocks.
The second diagram illustrates the same MOVX instruction with a default stretch value (MD2:0 = 001b). The stretch cycle (four system
clocks) is distributed as follows: one system clock added for address setup, two system clocks being added to the RD or WR pulse
duration, and one system clock added for address/data hold. For subsequent stretch values of 2 or 3, the full stretch cycle is added
to the duration of the RD or WR pulse.
NONPAGE MODE: MOVX (TWO CYCLES)
SYSCLK
ALE
PSEN
WR / RD
PORT2 MOVX MSB
LSB DATA
PORT0
MOVX
MOVX INST INSTRUCTIONS
Data Access
NONPAGE MODE: MOVX (THREE CYCLES)
SYSCLK
ALE
PSEN
WR / RD
PORT2 MOVX MSB
MOVX LSB MOVX DATA

PORT0
MOVX INST MOVX Data Access INSTRUCTIONS

(1 Stretch C y cle)
_____________________________________________________________________________________________ 66
PAGE MODE 1 DATA MEMORY TIMING–PAGES 1:0 = 10b (FOUR CYCLES)

The first diagram below shows execution of the MOVX instruction from internal program memory with stretch value = 0 assigned
(MD2:0 = 000b). Note that the internal memory cycles consist of one system clock while the external memory cycles consist of four
system clocks (page hit) or eight system clocks (page miss).
The second diagram illustrates the same MOVX instruction with a default stretch value (MD2:0 = 001b). The stretch cycle (four system
clocks) is distributed as follows: one system clock added for address setup, two system clocks being added to the RD or WR pulse
duration, and one system clock added for address/data hold. For subsequent stretch values of 2 or 3, the full stretch cycle is added
to the duration of the RD or WR pulse.
FOUR-CYCLE PAGE MODE 1: MOVX (TWO CYCLES)
SYSCLK
ALE
PSEN
WR / RD
PORT2 MOVX MSB MOVX LSB
PORT0 DATA
MOVX INST MOVX Data Access INSTRUCTIONS

(Page Miss)
FOUR-CYCLE PAGE MODE 1: MOVX (THREE CYCLES)
SYSCLK
ALE
PSEN
WR / RD
PORT2 MOVX MSB MOVX LSB
PORT0 MOVX DATA
MOVX INST MOVX Data Access INST INST

(Page Miss + 1 Stretch Cycle)
= STRETCH CYCLE
67 _____________________________________________________________________________________________
PAGE MODE 1 DATA MEMORY TIMING–PAGES 1:0 = 01b (TWO CYCLES)

The first diagram below shows execution of back-to-back MOVX instructions from internal flash memory. A stretch value = 0 (MD2:0 =
000b) has been assigned. Note that the internal memory cycles consist of one system clock while the external memory cycles consist
of two system clocks (page hit) or four system clocks (page miss).
The second diagram below illustrates the timing of the MOVX operation with stretch value = 1 (MD2:0 = 001b). The stretch cycle (four
system clocks) is distributed as follows: one system clock added for address setup, two system clocks being added to the RD or WR
pulse duration, and one system clock added for address/data hold. For subsequent stretch values of 2 or 3, the full stretch cycle is
added to the duration of the RD or WR pulse.
2-CYCLE PAGE MODE 1: MOVX (2 CYCLE) — MOVX (2 CYCLES)
SYSCLK
ALE
PSEN
WR / RD
MOVX #1 MOVX #1 MOVX #2 MOVX #2

PORT2 MSB LSB MSB LSB
MOVX MOVX
PORT0 DATA DATA
MOVX #1
MOVX MOVX INST MOVX #2 INSTRUCTIONS
Data Access
#1 #2 Data Access
(Page Miss)
(Page Miss)
2-CYCLE PAGE MODE 1: MOVX (3 CYCLES)
SYSCLK
ALE
PSEN
WR / RD
MOVX MSB MOVX LSB

PORT2
MOVX DATA
PORT0
MOVX INST MOVX INSTRUCTIONS

Data Access
= STRETCH CYCLE
_____________________________________________________________________________________________ 68
PAGE MODE 1 DATA MEMORY TIMING–PAGES 1:0 = 01b (TWO CYCLES) (CONTINUED)
The first diagram below shows execution of a MOVX instruction with default stretch value = 1 (MD2:0 = 001b) from external program
memory. The most probable case, where a page-miss is needed for the MOVX instruction, is given here. However, if the MOVX address
happened to coincide with the current code execution page, a page hit would occur.
The second diagram illustrates the MOVX timing that would occur if the address MSB for the MOVX data were to coincide with the
code execution pages before and after the data access. Since a different MSB would not need to be latched, neither of the page-miss
cycles seen in the third diagram would occur.
TWO-CYCLE PAGE MODE 1: MOVX (THREE CYCLE) EXTERNAL CODE EXECUTION WITH PAGE MISSES
SYSCLK
ALE
PSEN
WR / RD
MOVX MOVX
PORT2 LSB LSB MSB MSB LSB
LSB
MOVX
PORT0 DATA
MOVX INST MOVX INST

(Page Hit) Data Access (Page Miss)
TWO-CYCLE PAGE MODE 1: MOVX (THREE CYCLE) EXTERNAL CODE EXECUTION - NO PAGE MISSES
SYSCLK
ALE
PSEN
WR / RD
PORT2 LSB LSB MOVX LSB LSB LSB

LSB
MOVX
PORT0 DATA
MOVX INST MOVX INST INST INST

#1 (Page Hit) Data Access (Page Hit) (Page Hit) (Page Hit)
(Page Hit + 1 Stretch Cycle)
= STRETCH CYCLE
69 _____________________________________________________________________________________________
PAGE MODE 1 DATA MEMORY TIMING–PAGES 1:0 = 00b (ONE CYCLE)

The first diagram below illustrates execution of back-to-back MOVX instructions from internal flash memory. The default MOVX stretch
setting (MD2:0 = 001b) has been assumed. The total duration of each MOVX instruction is seven system clocks = one system clock
(page-hit memory cycle) + 2 system clocks (page-miss memory cycle) + four system clocks (one stretch cycle). Note that all external
MOVX operations in one-cycle page mode 1 result in page-misses.
The second diagram illustrates execution of the same back-to-back MOVX instructions with a stretch value of 0 (MD2:0 = 000b).
ONE-CYCLE PAGE MODE 1: MOVX (THREE CYCLES) — MOVX (THREE CYCLES)
SYSCLK
ALE
PSEN
WR / RD
MOVX MOVX
PORT2 MSB MOVX#1 LSB Address MSB MOVX#2 LSB Address
MOVX data MOVX data

PORT0
MOVX MOVX MOVX #1 Data Access INST MOVX #2 Data Access INST
#1 #2 (Page Miss + 1 Stretch Cycle) (Page Miss + 1 Stretch Cycle)
ONE-CYCLE PAGE MODE 1: MOVX (TWO CYCLES) — MOVX (2 CYCLES)
SYSCLK
ALE
PSEN
WR / RD
MOVX MOVX MOVX MOVX

PORT2 MSB LSB MSB LSB
MOVX MOVX
PORT0 DATA DATA
MOVX MOVX MOVX #1 INST MOVX #2 INSTRUCTIONS

#1 #2 Data Access Data Access
(Page Miss) (Page Miss)
= STRETCH CYCLE
_____________________________________________________________________________________________ 70
PAGE MODE 1 DATA MEMORY TIMING–PAGES 1:0 = 00b (ONE CYCLE) (CONTINUED)
The next diagram, still using a MOVX stretch value = 0, shows the back-to-back MOVX instructions being executed from external pro-
gram memory.
The last diagram shows external code memory execution of an external MOVX instruction with stretch value = 4 (MD2:0 = 100b). It has
been assumed, for this example, that a page-miss is required for the MOVX data access. A stretch value = 4 results in the addition of
4 stretch cycles beyond the stretch value = 3. The four stretch cycles are distributed as folllows: two stretch cycles added for address
setup, one stretch cycle added to RD or WR pulse duration, and 1 stretch cycle added for address/data hold. For subsequent stretch
values of 5, 6, or 7, the added stretch cycle increases the RD or WR pulse duration.
ONE-CYCLE PAGE MODE 1: MOVX (TWO CYCLES) — MOVX (TWO CYCLES) EXTERNAL CODE EXECUTION
SYSCLK
ALE
PSEN
WR / RD
MOVX MOVX MOVX MOVX MSB LSB LSB LSB LSB LSB LSB LSB
PORT2 LSB LSB MSB LSB
MSB LSB MSB LSB
MOVX MOVX
PORT0 DATA DATA
MOVX MOVX MOVX #1 INST MOVX #2 INST INSTRUCTIONS

#1 #2 Data Access (Page Miss) Data Access (Page Miss)
(Page Miss) (Page Miss)
ONE-CYCLE PAGE MODE 1: MOVX (NINE CYCLES) EXTERNAL CODE EXECUTION
SYSCLK
ALE
PSEN Stretch #1 Stretch #2 Stretches #3-6 Stretch #7
WR / RD
LSB LSB MOVX MSB MOVX LSB MSB LSB

PORT2
MOVX DATA
PORT0
MOVX INST MOVX Data Access INST

(Page Miss + 7 Stretch Cycles) (Page Miss)
71 _____________________________________________________________________________________________
PAGE MODE 2 DATA MEMORY TIMING–PAGES 1:0 = 11B (FOUR CYCLES)

All external data memory accesses made using the page mode 2 external bus configuration require four system clocks. The MOVX
timing looks identical to the nonpage mode MOVX timing except that port 2 multiplexes the MSB and the data, while port 0 serves as
the LSB.
DATA MEMORY ACCESS

As mentioned earlier in this section, the ultra-high-speed microcontroller uses the MOVX instruction for data memory access. This
includes off-chip RAM and memory-mapped peripherals needing read/write access. Several aspects of the MOVX operation have been
enhanced as compared to the original 8051. The principal improvements are in the areas of the MOVX timing and the data pointer.
The MOVX instruction is used to generate read/write access to off-chip address locations. It has several addressing modes. The first
uses the MOVX @Ri command to reach a 256-byte block. This instruction uses the value in the designated working register to address
one of 256 locations. The upper byte of the address is supplied by the value in the port 2 latch. A second way to access data is the
data pointer (DPTR). This 16-bit register provides an absolute address for data memory access. 16-bits cover the entire 64kB area.
Thus the DPTR serves as a pointer to memory. Using the DPTR, the relevant instruction is MOVX @DPTR.
The original 8051 contained one DPTR. While this provides access to the entire memory area, it is difficult to move data from one
address to another. The ultra-high-speed microcontroller provides two data pointers. Thus software can load both a source and a des-
tination address. The MOVX instruction uses the active pointer to direct the off-chip address.
The dual data pointers are DPTR0 and DPTR1. DPTR0 is at SFR addresses 82h and 83h. These are the locations used by the original
8051. No modification of standard code is needed to use DPTR0. The new DPTR is located at SFR 84h and 85h. The data pointer select
bit (SEL) chooses the active pointer and is located in bit position 0 of the DPS (86h) SFR. When DPS is set to 0, the DPTR0 is active.
When set to 1, DPTR1 is used. All DPTR-related instructions use the currently selected DPTR for any activity.
Each data pointer (DPTR0, DPTR1) has an associated control bit (ID0, ID1) that determines whether the INC DPTR operation results in
an increment or decrement of the pointer. When the active data pointer ID (increment/decrement) control bit is clear, the INC DPTR
instruction will increment the pointer, whereas a decrement occurs if the active pointer’s ID bit is set when the INC DPTR instruction is
performed.
ID0 = DPS.6
ID1 = DPS.7
Using the dual data pointers for large block copy operations results in substantial code savings versus using a single data pointer,
since one data pointer can be used for the source address and the second pointer can be used as the destination address. The user
switches between data pointers by toggling the SEL bit. One way of accomplishing this is by executing the INC DPS instruction. For
these large-block copy operations, the user must execute this instruction frequently to toggle between DPTR0 and DPTR1. To improve
the speed and efficiency of moving data with dual data pointers, the ultra-high-speed microcontroller contains a toggle select (TSL)
bit. When this TSL bit (DPS.5) is set, execution of certain MOVX instructions automatically toggle the SEL bit in hardware, allowing
removal of the INC DPS instruction and increasing execution speed.
Copying large blocks of data also requires that the source and destination pointers index byte-by-byte through their respective data
ranges. The traditional method for incrementing each pointer is through the use of the INC DPTR instruction. The DS89C420 provides
yet another means of accelerating data transfers with the implementation of an auto increment/decrement bit (AID). When this AID bit
(DPS.4) is set, execution of certain MOVX instructions automatically increments or decrements the active data pointer.
AUTO-TOGGLE (if TSL = 1) AUTO-INC/DEC (if AID = 1)
MOVC A, @A+DPTR MOVC A, @A+DPTR
MOVX A, @DPTR MOVX A, @DPTR
MOVX @DPTR, A MOVX @DPTR, A
INC DPTR
MOV DPTR, #data16
The following table summarizes the tremendous speed improvements gained through using the dual DPTRs along with autoincrement
and autotoggle features of the DS89C420. To properly quantify the speed improvement gained with enhanced data pointer operation
versus improvement attributed to the single-cycle core architecture, execution time for the DS80C320 high-speed microcontroller (four-
cycle core) has been included where applicable. For the DS89C420, external page mode 1 (PAGES1:0 = 00b) code execution has
been assumed. It is unreasonable to expect that the address MSBs for MOVX read/write operations are the same as the address MSB
for code execution. Therefore, one clock cycle has been added to each MOVX instruction (for data access) and to the instruction that
follows the MOVX (for code fetch) to account for potential page misses. The sample code listings have been marked accordingly with
_____________________________________________________________________________________________ 72
‘+D’ to indicate a data access page-miss and ‘+C’ to indicate a code-fetch page-miss. Thus, in the case of back-to-back MOVX oper-
ations, the second MOVX operation has two clock cycles added (‘+CD’), one associated with the code fetch and one associated with
the data access.
Table 6-10. Enhanced Data Pointer Speed Improvement

DS80C320 HIGH SPEED DS89C420 ULTRA-HIGH SPEED
DATA POINTER OPERATION CLOCK CYCLES EXECUTION TIME EXECUTION TIME
CLOCK CYCLES
(4CLKS/MCLK) (AT 33MHZ) (AT 33MHZ)
Single Data Pointer 1869 x 4 227µs 1933 59µs
Dual Data Pointer 1098 x 4 133µs 1291 39µs
Dual Data Pointer w/AID — — 1169 35µs
Dual Data Pointer w/TSL — — 910 28µs
Dual Data Pointer w/AID,TSL — — 782 24µs
The sample code listings for these programs appear on the following pages.
Program 1 listed below is original code written for an 8051 and utilizes a single data pointer.
Program 2 uses the dual data pointer feature.
Program 3 uses the dual data pointer with autoincrement enhancement.
Program 4 uses the dual data pointer with autotoggle enhancement.
Program 5 uses the dual data pointer with autoincrement and autotoggle enhancements.
The relevant register and bit locations are summarized as follows:

DPL 82h Low-byte original DPTR
DPH 83h High-byte original DPTR
DPL1 84h Low-byte new DPTR
DPH1 85h High-byte new DPTR
DPS 86h SEL bit = DPS.0
AID bit = DPS.4
TSL bit = DPS.5
PROGRAM 1: 64-BYTE BLOCK MOVE (WITHOUT DUAL DATA POINTER)

; SH and SL are high and low byte source address.
; DH and DL are high and low byte of destination address.
; For cycle counts:
; HSM = High-Speed Microcontroller
; UHSM = ultra-high-speed microcontroller
# HSM/UHSM CYCLES
MOV R5, #64 ; NUMBER OF BYTES TO MOVE 2/2
MOV DPTR, #SHSL ; LOAD SOURCE ADDRESS 3/3
MOV R1, #SL ; SAVE LOW BYTE OF SOURCE 2/2
MOV R2, #SH ; SAVE HIGH BYTE OF SOURCE 2/2
MOV R3, #DL ; SAVE LOW BYTE OF DESTINATION 2/2
MOV R4, #DH ; SAVE HIGH BYTE OF DESTINATION 2/2
MOVE:
; THIS LOOP IS PERFORMED R5 TIMES, IN THIS EXAMPLE 64
MOVX A, @DPTR ; READ SOURCE DATA BYTE 2/3 +D
MOV R1, DPL ; SAVE NEW SOURCE POINTER 2/3 +C
MOV R2, DPH ; 2/2
MOV DPL, R3 ; LOAD NEW DESTINATION 2/2
MOV DPH, R4 ; 2/2
73 _____________________________________________________________________________________________
# HSM/UHSM CYCLES
MOVX @DPTR, A ; WRITE DATA TO DESTINATION 2/3 +D
INC DPTR ; NEXT DESTINATION ADDRESS 3/2 +C
MOV R3, DPL ; SAVE NEW DESTINATION POINTER 2/2
MOV R4, DPH ; 2/2
MOV DPL, R1 ; GET NEW SOURCE POINTER 2/2
MOV DPH, R2 ; 2/2
INC DPTR ; NEXT SOURCE ADDRESS 3/1
DJNZ R5, MOVE ; FINISHED WITH TABLE? 3/4
PROGRAM 2: 64-BYTE BLOCK MOVE (DUAL DATA POINTER)

; DPS is the data pointer select. Reset condition DPTR0.
; For cycle counts:
; HSM = High-Speed Microcontroller
; UHSM = ultra-high-speed microcontroller
# HSM/UHSM CYCLES
DPS EQU 86h ; TELL ASSEMBLER ABOUT DPS
MOV R5, #64 ; NUMBER OF BYTES TO MOVE 2/2
MOV DPTR, #DHDL ; LOAD DESTINATION ADDRESS 3/3
INC DPS ; CHANGE ACTIVE DPTR 2/3
MOV DPTR, #SHSL ; LOAD SOURCE ADDRESS 3/3
MOVE:
MOVX A, @DPTR ; READ SOURCE DATA BYTE 2/3 +D
INC DPS ; CHANGE DPTR TO DESTINATION 2/4 +C
MOVX @DPTR, A ; WRITE DATA TO DESTINATION 2/3 +D
INC DPTR ; NEXT DESTINATION ADDRESS 3/2 +C
INC DPS ; CHANGE DATA POINTER TO SOURCE 2/3
INC DPTR ; NEXT SOURCE ADDRESS 3/1
DJNZ R5, MOVE ; FINISHED WITH TABLE? 3/4
PROGRAM 3: 64-BYTE BLOCK MOVE (DUAL DATA POINTER, AID)

# UHSM CYCLES
MOV R5, #64 ; NUMBER OF BYTES TO MOVE 2
ORL DPS, #10h ; SET AUTO-INC/DEC (AID) 3
MOV DPTR, #DHDL ; LOAD DESTINATION ADDRESS 3
INC DPS ; CHANGE ACTIVE DPTR 3
MOV DPTR, #SHSL ; LOAD SOURCE ADDRESS 3
MOVE:
MOVX A, @DPTR ; READ SOURCE DATA BYTE 3 +D
INC DPS ; CHANGE DPTR TO DESTINATION 4 +C
MOVX @DPTR, A ; WRITE DATA TO DESTINATION 3 +D
INC DPS ; CHANGE DATA POINTER TO SOURCE 4 +C
DJNZ R5, MOVE ; FINISHED WITH TABLE? 4
ANL DPS, #0EFH ; CLEAR AUTO-INC/DEC 3
_____________________________________________________________________________________________ 74
PROGRAM 4: 64-BYTE BLOCK MOVE (DUAL DATA POINTER, TSL)

# UHSM CYCLES
ORL DPS, #20h ; SET TOGGLE SELECT (TSL) 3
MOVE:
MOVX @DPTR, A ; WRITE DATA TO DESTINATION 4 +CD
INC DPTR ; NEXT SOURCE ADDRESS 2 +C
INC DPTR ; NEXT DESTINATION ADDRESS 1
DJNZ R5, MOVE ; FINISHED WITH TABLE? 4
ANL DPS, #0DFh ; CLEAR TOGGLE SELECT 3
PROGRAM 5: 64-BYTE BLOCK MOVE (DUAL DATA POINTER, AID, TSL)

# UHSM CYCLES
ORL DPS, #30h ; SET TOGGLE SELECT, AUTO-INC/DEC 3
MOVE:
MOVX @DPTR, A ; WRITE DATA TO DESTINATION 4 +CD
DJNZ R5, MOVE ; FINISHED WITH TABLE? 5 +C
ANL DPS, #0CFh ; CLEAR TSL, AID 3
Note that since each pass through the loop saves additional clock cycles when compared to the single DPTR approach, efficiency
improvement when moving larger blocks is even greater using these features. Further speed improvement can be gained on the
DS89C420 when executing from internal flash program memory, since no code-fetch page misses (+C) would occur. For example, run-
ning Program 5 from internal memory at 33MHz would require only 19.8µs (= 1/33MHz x (14 + 64 x 10)).
SECTION 7: POWER MANAGEMENT

The DS89C420 has several features that relate to power consumption and management. They provide a combination of controlled
operation in unreliable power applications and reduced power consumption in portable or battery-powered applications. The range of
features is shown below with details to follow.
POWER MANAGEMENT
EARLY WARNING POWER-FAIL INTERRUPT
POWER-FAIL/POWER-ON RESET
BANDGAP SELECT
WATCHDOG WAKE-UP FROM IDLE
POWER SAVING
IDLE MODE
STOP MODE
RING WAKE-UP FROM STOP
POWER MANAGEMENT MODE
75 _____________________________________________________________________________________________
PRECISION VOLTAGE MONITOR

The DS89C420 uses a precision bandgap reference and other analog circuits to monitor the state of the power supply during power-
up and power-down transitions. This obviates the need for external circuits to perform these functions that other microcontroller sys-
tems would require. The bandgap reference provides a precise voltage to compare with VCC. When VCC begins to drop, the power
monitor compares it to its reference. This enables the analog circuits to detect when VCC passes through predetermined thresholds,
VPFW and VRST. These are specified in the DS89C420 product data sheet.
EARLY-WARNING POWER-FAIL INTERRUPT
The DS89C420, which incorporates a precision voltage reference, has the ability to generate a power-fail interrupt and/or reset in
response to a low-supply voltage. When VCC reaches the VPFW threshold, the DS89C420 can generate a power-fail interrupt. This early
warning of supply voltage failure allows the system time to save critical parameters in nonvolatile memory and put external functions
in a safe state.
The power-fail interrupt is optional and is enabled using the enable power-fail warning interrupt (EPFI) bit at WDCON.5. If enabled, VCC
dropping below VPFW causes the device to vector to address 33h. The power-fail interrupt status bit, PFI (WDCON.4), is set anytime
VCC transitions below VPFW. This flag is not cleared when VCC is above VPFW, and software should clear it immediately after reading
it. As long as the condition exists, PFI is immediately set again by hardware.
A typical application of the PFI is to place the device into a “safe mode” when a power loss appears imminent. When the interrupt
occurs, the code vectors to location 33h. At this time, software can disable the interrupt, save any critical data, clear PFI, and then con-
tinually poll the status of the power supply through the PFI flag. As long as PFI is set, power is still below VPFW. If power returns to the
proper level, PFI is not set once cleared by software. This indicates a safe operating condition. If power continues to fall, a power-fail
reset is invoked automatically.
POWER-FAIL RESET
The power-fail reset automatically invokes a reset when VCC drops below VRST. This halts device operation and places all outputs in
their reset state. This state continues to be held until VCC drops below the voltage necessary to power the port pins. Because VRST.
is lower than VPFW, the microcontroller has the option to use the power-fail interrupt to place the device into a “safe” state before the
device halts operation with a power-fail reset. The power-fail reset function cannot be disabled.
POWER-ON RESET
When VCC is applied to a system using the DS89C420, the device holds itself in reset until power is within tolerance and stable. The
internal bandgap reference provides a highly accurate and stable means of detecting power-supply levels. It requires no external cir-
cuits to accomplish this. As power rises, the processor stays in a reset state until VCC > VRST. As VCC rises above VRST, internal ana-
log circuits detect this and activate the on-chip crystal oscillator. On-chip hardware then counts 65536 oscillator clocks. During this
count, VCC must remain above VRST. or the process restarts. If an off-chip clock source is used, clock counting still begins once VCC
> VRST. This count period is used to make certain that power is within tolerance and that the oscillator has time to stabilize. This pro-
vides a very controlled and predictable startup condition.
Once the 65536 count period has elapsed, the reset condition is removed automatically, and software execution begins at the reset
vector location of 0000h. Software is able to detect the power-on reset condition using the power-on reset (POR) flag. POR is located
at WDCON.6. This bit is high to indicate that a power-on reset has occurred. It should then be cleared by software.
The complete power cycle operation is shown in Figure 7-1. Note that the interrupt threshold is fixed, but the interrupt itself is option-
al. Reset thresholds are also fixed and the reset operation is transparent. It requires no external components and no action by software
to control reset operation.
BANDGAP SELECT
The bandgap is normally disabled automatically upon entering stop mode to provide the lowest power state. Since the bandgap is
inactive, there can be no power-fail interrupt and no power-fail reset, similar to a traditional 8051.
_____________________________________________________________________________________________ 76
VCC
VPFW
VRST
VSS
INTERRUPT
SERVICE ROUTINE
tCSU
XTAL1
tPOR
INTERNAL RESET
Figure 7-1. Power Cycle Operaton
If the use of the power-fail features is desired in stop mode, the BGS bit (EXIF, 91h) can be used. When set to a logic 1 by software,
the bandgap reference and associated power monitor circuits remain active in stop mode. The price of this feature is higher power-
supply current requirements. In stop mode with the bandgap reference disabled (default), the processor draws approximately 10µA.
With the bandgap enabled, it draws approximately 75µA.
BGS allows the user to decide whether the control circuitry and its associated power consumption are needed. If the application is
such that power does not fail while in stop, or if it does not matter that power fails, the BGS should be set to 0 (default). If power can
fail at any time and cause problems, the BGS should be set to 1.
WATCHDOG WAKE-UP
The watchdog wake-up is more of an application than a feature. It allows a system to enter the idle mode for power savings, then to
wake up periodically to sample the external world. Idle mode is a low-power state described below. Any of the programmable timers
can perform this function, but the watchdog allows a much longer period to be selected. At 33MHz, the maximum watchdog timeout
is over 2s. This contrasts with 23.8ms using the 16-bit timers. Software that uses the watchdog as a wake-up alarm should enable only
the watchdog interrupt and not the reset. Note that the watchdog cannot be used to wake the system while in stop mode since no
clocks are running. Stop mode is described in the Power Management Summary section below.
POWER MANAGEMENT SUMMARY
The following is a summary of the power management bits and those that are useful or related. They are contained in the register loca-
tions WDCON;D8h, EIE;E8h, EXIF;91h, and PCON; 87h.
WDCON.6 POR: Power-on reset. Hardware sets this bit on a power-up condition. Software can read it, but must clear it man-
ually. This bit assists software in determining the cause of a reset.
WDCON.5 EPFI: enable power-fail interrupt. Setting this bit to 1 enables the power-fail interrupt. This occurs when VCC drops
to approximately 4.375V, and the processor vectors to location 33h. Setting this bit to a 0 turns off the power-fail interrupt.
WDCON.4 PFI: Power fail interrupt flag. Hardware sets this bit to a 1 when a power-fail condition occurs. Software must clear the
bit manually. Writing a 1 to this bit forces an interrupt, if enabled.
77 _____________________________________________________________________________________________
WDCON.3 WDIF: Watchdog interrupt flag. If the watchdog interrupt is enabled (EIE.4), hardware sets this bit to indicate that
the watchdog interrupt has occurred. If the interrupt is not enabled, this bit indicates that the timeout has passed. If
the watchdog reset is enabled (WDCON.1), the user has 512 system clocks to strobe the watchdog prior to a reset.
Software or any reset can clear this flag.
WDCON.2 WTRF: Watchdog timer reset flag. Hardware sets this bit when the watchdog timer causes a reset. Software can read
it, but must clear it manually. A power-fail reset also clears the bit. This bit assists software in determining the cause of
a reset. If EWT = 0, the watchdog timer has no affect on this bit.
WDCON.1 EWT: Enable watchdog timer reset. Setting this bit turns on the watchdog timer reset function. The interrupt does not
occur unless the EWDI bit in the EIE register is set. A reset occurs according to the WD1 and WD0 bits in the CKCON
register. Setting this bit to a 0 disables the resets but leaves the timer running.
WDCON.0 RWT: Reset watchdog timer. This bit serves as the strobe for the watchdog function. During the timeout period, soft-
ware must set the RWT bit if the watchdog is enabled. Failing to set the RWT causes a reset when the timeout has
elapsed. There is no need to set the RWT bit to a 0 because it is self-clearing.
EIE.4 EWDI: Enable watchdog interrupt. Setting this bit in software enables the watchdog interrupt.
EXIF.0 BGS: Bandgap select. Setting this bit to a 1 allows the use of the bandgap voltage reference while in stop mode. Since
this function uses as much as 75µA, the bandgap is optional in stop mode. Setting this bit to a 0 turns off the bandgap
while in stop mode. When BGS = 0, no power-fail interrupt or power-fail reset is available in stop mode.
PCON.1 STOP. When this bit is set, the program stops execution, clocks are stopped, and the CPU enters power-down mode.
PCON.0 IDLE. Program execution halts, leaving timers, serial ports, and clocks running.
EXIF.2 RGMD: Ring oscillator mode. Hardware sets this status bit to a 1 when the clock source is the ring oscillator.
Hardware sets this status bit to a 0 when the crystal is the clock source. Refer to RGSL for operation of the ring oscil-
lator.
EXIF.1 RGSL: Ring oscillator select. When set to a 1 by software, the DS89C420 uses a ring oscillator to come out of stop
mode without waiting for crystal startup. This allows an instantaneous startup when coming out of stop mode. It is use-
ful if software needs to perform a short task, and then return to stop. It is also useful if software must respond quickly
to an external event. After the crystal has performed 65,536 cycles, hardware switches to the crystal as its clock
source. The RGMD status bit reports on this changeover. When RGSL is set to a 0, the DS89C420 delays software exe-
cution until after the 65,536 clock crystal startup time. RGSL is only cleared by a power-on reset and is not altered by
other forms of reset.
POWER SAVING
The DS89C420 is implemented using full CMOS circuitry for low-power operation. It is fully static, so the clock speed can be run down
to DC. Like other CMOS, the power consumption is also a function of operating frequency. Although the DS89C420 is designed for
maximum performance, it also provides improved power versus work relationships compared with standard 8051 devices. These top-
ics are discussed in detail in the following pages.
CLOCK DIVIDE CONTROL
The programmable clock divide control bits CD1 and CD0 (PMR, C4h) provide the processor with the ability to adapt to different crys-
tals and also to slow the system clocks, providing lower power operation when required. An on-chip crystal multiplier allows the
DS89C420 to operate at two or four times the crystal frequency by setting the 4X/2X bit and is enabled by setting the CTM bit to a logic
1. An additional circuit provides a clock source at divide-by-1024. When used with a 10MHz crystal, for example, the processor exe-
cutes machine cycle in times ranging from 25ns (divide-by-0.25) to 102.4µs (divide-by-1024) and maintains a highly accurate, serial
port baud rate while allowing the use of more cost-effective, lower-frequency crystals. Although the clock divide control bits can be
written at any time, certain hardware features have been provided to enhance the use of these clock controls to guarantee proper ser-
ial port operation, and also to allow for a high-speed response to an external interrupt. The 01b setting of CD1 and CD0 is reserved
and has the same effect as the setting of 10b, which forces the system clock into a divide-by-1 mode. The DS89C420 defaults to divide-
by-1 clock mode on all forms of reset.
When programmed to the divide-by-1024 mode, and the switchback bit (PMR.5: SWB) is also set, the system forces the clock divide
control bits to reset automatically to the divide-by-1 mode whenever the system has detected externally enabled interrupts.
_____________________________________________________________________________________________ 78
4X/2X
CTM
Clock
Multiplier
Crystal
Oscillator
System
MUX
Clock
Divide-by-1024
Ring
Oscillator
Ring
Enable Selector
CD0
CD1
Figure 7-2. System Clock Sources
The oscillator divide ratios of 0.25, 0.5 and 1 are also used to provide standard baud rate generation for the serial ports through a
forced divide-by-12 input clocks (TxMH,TxM = 00b, x = 1, 2, or 3) to the timers. When in divide-by-1024 mode, in order to allow a quick
response to incoming data on a serial port, the system utilizes the switchback mode to automatically revert to divide-by-1 mode when-
ever a start bit is detected. This automatic switchback is only enabled during divide-by-1024 mode and all other clock modes are unaf-
fected by interrupts and serial port activity. See power management mode for more details.
Use of the divide-by-0.25 or 0.5 option through the clock divide control bits requires that the crystal multiplier be enabled and the spe-
cific system clock multiply value be established by the 4X/2X bit in the PMR register. The multiplier is enabled by the CTM (PMR.4) bit
but cannot be automatically selected until a startup delay has been established through the CKRY bit in the status register. The 4X/2X
bit can only be altered when the CTM bit is cleared to a logic 0. This prevents the system from changing the multiplier until the system
has moved back to the divide-by-1 mode and the multiplier has been disabled through the CTM bit. The CTM bit can only be altered
when the CD1 and CD0 bits are set to divide-by-1 mode and the RGMD bit is cleared to 0. Setting the CTM to a logic 1 from a previ-
ous logic 0 automatically clears the CKRY bit in the status register and starts the multiplier startup timeout in the multiplier startup
counter. During the multiplier startup period, the CKRY bit remains cleared and the CD1 and CD0 clock controls cannot be set to 00b.
The CTM bit is cleared to a logic 0 on all resets. Figure 7-2 (System Clock Sources) gives a simplified description of the generation of
the system clocks. Specifics of hardware restrictions associated with the use of the 4X/2X CTM, CKRY, CD1, and CD0 bits are outlined
in the SFR description.
The DS89C420 provides two modes (other than operating) that allow power conservation. They are similar, but have different merits
and drawbacks. These modes are idle and stop. In the original 8051, the stop mode is called power-down. These modes are invoked
in the same manner as the original 8051 series.
IDLE MODE
Idle mode suspends all CPU processing by holding the program counter in a static state. No program values are fetched and no pro-
cessing occurs. This saves considerable power versus full operation. The virtue of idle mode is that it uses half the power of the oper-
ating state, yet reacts instantly to any interrupt conditions. All clocks remain active so the timers, watchdog, serial port, and power mon-
itor functions are all working. Since all clocks are running, the CPU can exit the idle state using any of the interrupt sources.
Software can invoke the idle mode by setting the IDLE bit in the PCON register at location 87h. The bit is located at PCON.0. The
79 _____________________________________________________________________________________________
instruction that executes this step is the last instruction prior to freezing the program counter. Once in idle, all resources are preserved.
There are two ways to exit the idle mode. First, any interrupt (that is enabled) will cause an exit. This results in a jump to the appropri-
ate interrupt vector. The IDLE bit in the PCON register is cleared automatically. Upon returning from this vector using the RETI instruc-
tion, the next address is the one immediately after the instruction that invoked the idle state.
The idle mode can also be removed using a reset. Any of the three reset sources can do this. On receiving the reset stimulus, the CPU
is placed in a reset state and the idle condition cleared. When the reset stimulus is removed, software begins execution as for any
reset. Since all clocks are active, there is no delay after the reset stimulus is removed. Note that if enabled, the watchdog timer con-
tinues to run during idle and must be supported.
STOP MODE
Stop mode is the lowest power state that the DS89C420 can enter. This is achieved by stopping all on-chip clocks, resulting in a fully
static condition. No processing is possible, timers are stopped, and no serial communication is possible. Software can invoke stop
mode by setting the STOP bit in the PCON register at location 87h. The bit is located at PCON.1. Processor operation halts on the
instruction that sets the STOP bit. The internal amplifier that excites the external crystal is disabled, halting crystal oscillation in stop
mode. Stop mode takes precedence if application code attempts to set both the STOP and IDLE bits. However, doing this is not sug-
gested. Table 7-1 shows the state of the processor pins in idle and stop modes.
Stop mode can be exited in two ways. First, like the 8052 microcontrollers, a nonclocked interrupt such as the external interrupts or
the power-fail interrupt can be used. Clocked interrupts, such as the watchdog timer, internal timers, and serial ports do not operate
in stop mode. Note that the bandgap reference must be enabled in order to use the power-fail interrupt to exit stop mode, which
increases stop mode current. Processor operation resumes with the fetching of the interrupt vector associated with the interrupt that
caused the exit from stop mode. When the interrupt service routine is complete, an RETI returns the program to the instruction imme-
diately following the one that invoked the stop mode.
A second method of exiting stop mode is with a reset. The watchdog timer reset is not available as a reset source because no timers
are running in stop mode. An external reset by the RST pin unconditionally exits the device from stop mode. If the BGS bit is set, the
device provides a reset while in stop mode if VCC should drop below the VRST level. If the BGS bit is 0, then a dip in power below
VRST does not cause a reset. For example, if VCC drops to a level of VRST -0.5V, then returns to the full level, no reset is generated.
For this reason, use of the bandgap reference is recommended if a brownout condition is possible in stop mode. If power fails com-
pletely (VCC = 0V), then a power-on reset is still performed when VCC is reapplied, regardless of the state of the BGS bit. Processor
operation resumes execution from address 0000h like any other reset.
Table 7-1. Pin States in Power-Saving Modes

DEVICE EXECUTION MODE ALE PSEN P0 P1 P2 P3
Internal Idle or stop 1 1 Port data2 Port data2 Port data2 Port data2
External nonpage Idle 1 1 Latched1 Port data2 Latched3 Port data2
External page mode 1 Idle 1 1 Latched1 Port data2 Latched5 Port data2
External page mode 2 Idle 1 1 Latched5 Port data2 Latched1 Port data2
External (any) Stop 1 1 Port data 2 Port data2 Port data4 Port data2
1Port exhibits opcode following instruction that sets the idle bit.
2Port reflects data stored in corresponding port SFR. Port 0 functions as an open-drain output in this mode.
3Port exhibits address MSB of opcode following instruction that sets the idle bit.
4Port reflects data stored in corresponding port SFR. In this mode, the port uses weak pullups.
5Port exhibits address LSB of opcode following instruction that sets the idle bit.
RING OSCILLATOR WAKE-UP FROM STOP

A typical low-power application is to keep the processor in stop mode most of the time. Periodically, the system wakes up (using an
external interrupt), takes a reading of some condition, and then returns to sleep. The duration of full-power operation is as short as pos-
sible. One disadvantage to this method is that the clock must be restarted prior to performing a meaningful operation. This startup peri-
od is a waste of time and power since no work can be performed. The DS89C420 provides an alternative.
_____________________________________________________________________________________________ 80
If the ring select (RGSL) is enabled, the DS89C420 can exit stop mode running from an internal ring oscillator. Upon receipt of an inter-
rupt, this oscillator can start instantaneously, allowing software execution to begin immediately while the oscillator is stabilizing. Ring
oscillator execution cannot be used to support accurate baud-rate generation or precise timer/counter operations. Once 65,536 clock
cycles have been detected, the CPU automatically switches to the normal oscillator as its clock source. However, if the required inter-
rupt response is very short, the software can reenter stop mode before the crystal is even stable. In this case, stop mode can be
invoked and both oscillators are stopped.
SPEED REDUCTION
The DS89C420 is a fully CMOS 8051-compatible microcontroller. It can use significantly less power than other 8051 versions, because
it is more efficient. As an average, software runs 10 times faster on the DS89C420 than on other 8051 derivatives. Thus, the same job
can be accomplished by slowing down the crystal by a factor of 10. For example, an existing 8051 design that runs at 12MHz can run
at approximately 1.2MHz on the DS89C420. At this reduced speed, the ultra-high-speed microcontroller has lower power consump-
tion than an 8051, yet performs the same job.
Using the 10X factor, Table 7-2 shows the approximate speed at which the DS89C420 can accomplish the same work as an 8051. The
exact improvement varies depending on the actual instruction mix. Available crystal speeds must also be considered. Refer to Section
14 for information on instruction timing.
Table 7-2. Crystal vs. MIPS Comparison

ORIGINAL 8051 DS89C420
MIPS
CRYSTAL SPEED (MHz) CRYSTAL SPEED (MHz)
16 1.3 1.6
20 1.6 2.0
24 2.0 2.4
33 2.7 3.3
40 3.3 4.0
POWER MANAGEMENT MODES

Power consumption in CMOS microcontrollers is a function of operating frequency. The power management mode (PMM) feature, avail-
able with the DS89C420, allows software to dynamically match operating frequency and current consumption with the need for pro-
cessing power. Instead of the default one clock per machine cycle, PMM utilizes 1024 clocks per cycle to conserve power.
Several special features have been added to enhance the function of the PMM. The switchback feature allows the device to almost
instantaneously return to divide-by-1 mode upon detection of an enabled external interrupt or the receipt of a falling edge on a serial
port receiver pin. The advantages of this become apparent when one calculates the increased interrupt service time of a device oper-
ating in PMM. In addition, a device operating in PMM would normally be unable to sample an incoming serial transmission to proper-
ly receive it. The switchback feature, explained below, allows a device to return to divide-by-4 operation in time to receive incoming
serial port data and process interrupts with no loss in performance.
The DS89C420 incorporates a status register (STATUS;C5h) to prevent the device from accidentally reducing the clock rate during the
servicing of an external interrupt or serial port activity. This register can be interrogated to determine whether an interrupt is in progress,
or if serial port activity is occurring. Based on this information the software can delay or reject a planned change in the clock divider
rate.
In addition, the DS89C420 has the capability to operate from the internal ring oscillator during normal operation, not only during the
crystal warmup period. Table 7-3 summarizes the new control bits associated with the power management features.
81 _____________________________________________________________________________________________
Table 7-3. Power Management and Status Bit Summary

RESET
BIT NAME LOCATION FUNCTION READ/WRITE ACCESS
STATE
Clock divider control
CD1 CD0 osc cycles per system clock cycle Write: 10 anytime;
0 0 Crystal multiplier 00, 01, and 11 only when
CD1, CD0 PMR.7–6 10
0 1 Reserved previously in 10 state.
1 0 1 (reset default) Unrestricted read.
1 1 1024 (PMM)
Switchback enable
0 = Interrupts and serial port activity will not affect clock
SWB PMR.5 divider control bits 0 Unrestricted
1 = Enabled interrupts and serial port activity will cause a
switchback
Priority Interrupt Status
101 = Level 4 interrupt (power fail) in progress
100 = Level 3 interrupt in progress
PIS2:PIS0 STATUS.7:5 011 = Level 2 interrupt in progress 0 Read only
000 = No interrupt in progress
Serial port 1 transmitter activity status
SPTA1 STATUS.3 0 = Serial port 1 transmitter inactive 0 Read only
1 = Serial port 1 transmitter active
Serial port 1 receiver activity status
SPRA1 STATUS.2 0 = Serial port 1 receiver inactive 0 Read only
1 = Serial port 1 receiver active
Serial port 0 transmitter activity status
SPTA0 STATUS.1 0 = Serial port 0 transmitter inactive 0 Read only
1 = Serial port 0 transmitter active
Serial port 0 receiver activity status
SPRA0 STATUS.0 0 = Serial port 0 receiver inactive 0 Read only
1 = Serial port 0 receiver active
POWER MANAGEMENT MODE TIMING

The power management mode reduces power consumption by internally dividing the clock signal to the device, causing it to operate
at a reduced speed. When PMM is invoked, the external crystal continues to operate at full speed. The difference is that the device
uses 1024 external clocks to generate each system clock cycle as opposed to one clock per internal system clock cycle in the default
state. Relative timing relationships of all signals when the device is operating in PMM remains the same as the one cycle timing. Note
that all internal functions, on-board timers (including serial port baud-rate generation), watchdog timer, and software timing loops also
runs at the reduced speed. Most applications do not find it necessary to attend to this much detail, but the information is provided for
calculating critical timings. Figure 7-2 demonstrates the internal timing relationships during PMM.
PMM is entered and exited by setting the clock rate divider bits (PMR.7-6). In addition, it is possible use the switchback feature to effect
a return to the divide-by-1 mode from the power management mode. This allows both hardware and software to cause an exit from
PMM. Entry to or exit from PMM must be done through the divide-by-1 mode (CD1:0 = 10b). This means that to switch from divide-by-
1024 to the crystal multiplier 4X mode or vice versa, one must first switch back to divide-by-1 mode. Attempts to execute an illegal
speed change are ignored, and the bits remain unchanged. It is the responsibility of the software to test for serial port activity before
attempting to change speed, as a modification of the clock divider bits during a serial port operation corrupts the data.
_____________________________________________________________________________________________ 82
MINIMUM INSTRUCTION CYCLE
INTERNAL
SYSTEM
CLOCK
(PMM)
EXTERNAL
CLOCK
1024 CLOCKS
Figure 7-3. Internal Timing Relationships in PMM
PMM AND PERIPHERAL FUNCTIONS

Timers 0, 1, and 2 default on reset to a 12 clock per cycle operation to remain compatible with the original 8051 timing. The timers can
be individually configured to run at the fastest instruction cycle timing (divide-by-1) or to a system clock divide-by-4 input by setting
the relevant bits in the clock control register (CKCON;8Eh). Because the timers derive their time base from the internal clock, timers 0,
1, and 2 operate at reduced clock rates during PMM. This also affects the operation of the serial ports in PMM. In general, it is not pos-
sible to generate standard baud rates while in PMM, and the user is advised to avoid PMM, or use the switchback feature, if serial port
operation is desired. Table 7-4 shows the effect of the PMM clock divider option on timer and serial port operation.
Table 7-4. Effect of PMM Clock Mode on Timer, Serial Operation
OSC CYCLES OSC CYCLES OSC CYCLES OSC CYCLES PER

OSC PER TIMER PER TIMER 2 PER SERIAL SERIAL
CYCLES PER 0/1/2 CLOCK CLOCK, BAUD- PORT CLOCK PORT CLOCK
CD1:0
MACHINE RATE GEN. MODE 0 MODE 2
CYCLE
TxMH, TxM = TxMH, TxM = SM2 = SMOD =
00 01 1x xx 0 1 0 1
11 1024 3072 1024 1024 2048 3072 1024 16,348 8192
SWITCHBACK
The switchback feature solves one of the most vexing problems faced by power-conscious systems. Many applications are unable to
use the stop and idle modes because they require constant computation. Traditionally, system designers could not reduce the oper-
ating speed below that required to process the fastest event. This meant that system architects would be forced to operate their sys-
tems at the highest rate of speed, even when it was not required. The switchback feature allows a system to operate at a relatively slow
speed and burst to a faster mode when required by an external event. When this feature is enabled by setting the switchback enable
bit (SWB), (PMR.5), a qualified interrupt, serial port reception, or transmission causes the device to return to the default divide-by-1
mode. A qualified interrupt is defined as an interrupt that has occurred and been acknowledged. This means that an interrupt must be
enabled and also not blocked by a higher priority interrupt. After the event is complete, software can manually return the device to
PMM. The following sources can trigger a switchback:
• External interrupt 0/1/2/3/4/5
• Serial start bit detected, serial port 0/1
• Transmit buffer loaded, serial port 0/1
83 _____________________________________________________________________________________________
• Watchdog timer reset

• Power–on reset
• External reset
In the case of a serial port-initiated switchback, the switchback is not generated by the associated interrupt. This is because a device
operating in PMM is not able to correctly receive a byte of data to generate an interrupt. Instead, a switchback is generated by a ser-
ial port reception on the falling edge associated with the start bit, if the associated receiver enable bit (SCON0.4 or SCON1.4) is set.
For serial port transmissions, a switchback is generated when the serial port buffer (SBUF0;99h or SBUF1;C1h) is loaded. This ensures
the device is operating in divide-by-1 mode when the data is transmitted, and eliminates the need for a write to the CD1, CD0 bits to
exit PMM before transmitting. The switchback feature is unaffected by the state of the serial port interrupt flags (RI_0, TI_0, RI_1, TI_1).
The timing of the switchback is dependent on the source. Interrupt-initiated switchbacks occur at the start of the first clock cycle fol-
lowing the event initiating the switchback. In PMM, each internal clock cycle is 1024 external clock cycles. If the current instruction in
progress is a write to the IE, IP, EIE, or EIP registers, interrupt processing is delayed until the completion of the following instruction.
Serial transmit-initiated switchbacks occur at the start of the instruction following the MOV that loads SBUF0 or SBUF1. Serial recep-
tion-initiated switchbacks occur during the cycle in which the falling edge was detected. A few points must be considered when using
a serial port reception to generate a switchback. Under normal circumstances, noise on the line or an aborted transmission causes the
serial port to time out and the data to be ignored. This presents a problem if the switchback is used, however, because a switchback
would occur without indication to the system. If PMM and serial port switchback functions are used in a noisy environment, the user is
advised to periodically check if the device has accidentally exited PMM.
A similar problem can occur if multiprocessor communication protocols are used in conjunction with PMM. The DS89C420 family sup-
ports both the use of the SM2 flag (SCON0.5 or SCON1.5), and the slave address-recognition registers (SADDR0;A9h, SADDR1;AAh,
SADEN0;B9h, SADEN1;BAh) for multiprocessor communications. The problem is that an invalid address, which should be ignored by
a particular processor, still generates a switchback. As a result, it is not recommended to use a multiprocessor communication scheme
in conjunction with PMM. If the system power considerations allow for an occasional erroneous switchback, a polling scheme can be
used to place the device back into PMM.
CLOCK SOURCE SELECTION
The DS89C420 family supports three clock sources for operation. As with most microcontrollers, the device can be clocked from an
external crystal using the on-board crystal amplifier, or a clock source can be supplied by an external oscillator. In addition, some mem-
bers of the DS89C420 family incorporate an on-board ring oscillator to provide a quick resumption from stop mode. The ring oscillator
is a low power digital oscillator internal to the microcontroller. When enabled, it provides an approximately 10MHz clock source for
device operation without external components. The ring oscillator is not as stable as an external crystal, and software should refrain
from performing timing-dependent operations, including serial port activity, while operating from the ring oscillator.
The ring oscillator provides many advantages to the designers of microcontroller-based systems. One is that it allows Dallas
Semiconductor microcontrollers to perform a fast resume from stop mode, eliminating the crystal warmup delay when restarting the
device. The DS89C420 must begin operation following a power-on reset from an external clock source, either an external crystal or
oscillator. The control and status bits which support the new and/or enhanced features are shown in Table 7-5.
Table 7-5. Clock Control and Status Bit Summary

BIT NAME LOCATION FUNCTION RESET WRITE ACCESS
Ring Oscillator Mode Status.
RGMD EXIF.2 1 = Ring oscillator is current clock source, 0 None
0 = Crystal or external clock is current clock source.
Ring Oscillator Select, Stop Mode.

1 = Ring oscillator will be the clock source when
resuming from stop mode,
RGSL EXIF.1 0 = Crystal or external clock will be the clock Unrestricted
source when resuming from stop mode
Note: Upon completion of crystal warm up period,
the device will switch to the crystal.
_____________________________________________________________________________________________ 84
RING OSCILLATOR RESUME FROM STOP

To achieve the minimum power consumption during periods of processor inactivity, software can place the device into stop mode. Such
systems typically resume operation using an external interrupt, perform some activity, and then return to stop mode. Traditional designs
that rely upon an external crystal as the clock source must incur the startup delay of the crystal when resuming from stop mode. This
is a waste of time and power, as no work can be performed until the crystal has stabilized.
Although the ring oscillator provides an approximately 10MHz clock source for device operation, it is not as stable as an external crys-
tal. As a result, high-accuracy timing operations should be avoided while running from the ring oscillator. This includes using the timers
for pulse measurement, and the use of the serial ports in asynchronous modes (1, 2, 3). Serial ports operating in mode 0 are unaf-
fected by the stability of the clock source as a separate synchronizing clock is generated.
If the ring oscillator select bit RGSL, (EXIF.1) is set, the device resumes operation immediately using the internal ring oscillator as the
clock source. The device continues to run from the ring oscillator until the crystal warmup period of 65,536 clock cycles (measured
from the external source) has completed. At this time, the device switches to clock source active before it enters stop mode and con-
tinues operation. This allows software execution to begin immediately upon resuming from stop mode. The current clock source is indi-
cated by the ring oscillator mode bit, RGMD (EXIF.2). In stop mode, enabled interrupts become true edge triggered interrupts, com-
pared with the sampled edge detection used during normal operation. This means that external interrupts are more sensitive to noise
in stop mode than during normal operation. Applications should be carefully designed to ensure that noise will not cause an erroneous
exit from stop mode.
SECTION 8: RESET CONDITIONS

A condition that causes the DS89C420 CPU to vector to address 0000h is a reset. This can happen internally or external to the micro-
controller. The reset condition puts the microcontroller in a known state following a course of events not anticipated by the designer.
The circuit could be subjected to numerous conditions, such as power brownout, noise due to lightning strike, or corrupted code.
RESET SOURCES
The DS89C420 can enter a reset condition if invoked in one of five ways:
• Power-on/power fail reset
• Watchdog timer reset
• Oscillator fail detect reset
• Internal system reset
• External reset
The reset state of the DS89C420 is the same, regardless of the source of the reset. When in reset, the oscillator is running, but no pro-
gram execution is allowed. When the reset source is external, the user must remove the reset stimulus to continue operation. When
power is applied to the device, the power-on delay removes the stimulus automatically.
POWER-ON/POWER-FAIL RESET
The DS89C420 incorporates an internal voltage reference, which holds the device in power-on reset while VCC is out of tolerance. Once
VCC has risen above the threshold, the DS89C420 restarts the external crystal oscillator and counts 65,536 clock cycles before pro-
gram execution begins at location 0000h. The power monitor invokes a reset state when VCC drops below the threshold condition. The
condition remains in effect while power is below the minimum voltage level. When power returns above the reset threshold, a full power-
on reset is performed. This mechanism provides a controlled and predictable startup condition.
The processor exits the reset condition automatically once VCC meets the minimum voltage requirement. This helps the system main-
tain reliable operation by only permitting processor operation when voltage is in a known good state. Software can determine that a
power-on reset has occurred by checking the power-on reset flag (POR) in the WDCON register. Software should clear the POR bit
after it is read.
85 _____________________________________________________________________________________________
WATCHDOG TIMER RESET

The DS89C420 incorporates a safety feature to prevent corrupted software from controlling the CPU. This feature is called the watch-
dog timer. It is a free-running timer with a programmable interval. The watchdog supervises the processor operation by requiring soft-
ware to clear the timer before an overflow occurs. If the timer is enabled and software fails to clear it before this interval expires, the
DS89C420 is placed into a reset state. The reset state maintains for 13 clock cycles. Once the reset is removed, the processor resumes
execution at address 0000h. Software can determine if a reset is caused by a watchdog timeout by checking the watchdog timer reset
flag (WTRF) in the WDCON register. This flag is cleared by software only.
OSCILLATOR FAIL-DETECT RESET
The DS89C420 incorporates oscillator fail-detect circuitry to monitor the on-chip oscillator activity. When enabled, this circuit causes a
reset if the oscillator frequency falls below ~20kHz, and holds the chip in reset until the oscillator frequency rises back above ~20kHz.
The circuitry is enabled by setting the OFDE (PCON.4) bit to a logic 1. The OFDE bit can be cleared by software or by the occurrence
of a power-fail reset. A reset caused by an oscillator failure sets the OFDF (PCON.5) flag bit to a logic 1. This flag can be cleared by
software or by a power-on reset. The oscillator fail-detect circuitry utilizes the internal ring oscillator to clock the chip into the reset state
and maintain the reset state while the oscillator is below the minimum frequency. Note, however, that the circuitry does not force a reset
when the oscillator is purposely stopped when software invokes stop mode.
INTERNAL SYSTEM RESET
The DS89C420 supports in-system programming. The lower on-chip memory bank can be reprogrammed through a bank switch mech-
anism by complementing the logic state of the bank select bit and invoking a reset. An internal system reset can be initiated by writ-
ing a system reset or complement bank-select command to the FCNTL register. The reset state is maintained for 13 clock cycles, once
the reset is removed. The on-chip memory banks are reconfigured in an addressing order determined by the logic value of the bank-
select bit. At this point, the CPU executes code from the reset vector address 0000h.
EXTERNAL RESET
If the RST input is asserted to logic 1, the device is forced into a reset state. An external reset is accomplished by holding the RST pin
high at least four clock cycles while the oscillator is running. Once the reset state is invoked, it is maintained as long as RST is assert-
ed at logic 1. When the RST is removed, the processor exits the reset state within four clock cycles and begins execution at address
0000h.
If an RST is applied while the processor is in the stop mode, the RST causes the oscillator to begin running and forces the program
counter to 0000h. The reset delay is 65,536 clock cycles to allow the oscillator to stabilize.
The RST pin is a bidirectional I/O. If a reset is caused by a power fail reset, a watchdog timer reset, an oscillator fail detect reset, or
an internal system reset, a positive output level is also generated at the RST pin. This reset level is asserted as long as an internal reset
is asserted. The drive capability of this I/O port may be insufficient if the RST pin is connected to a RC reset circuit. Connecting the
RST pin to a capacitor would not affect the internal reset condition.
DETERMINING THE CAUSE OF A RESET
During the debugging process, it might be necessary to isolate the cause of a device reset. Because resets are initiated by a limited
number of sources, it is relatively easy to determine their source by interrogating the flag bits associated with the reset sources. The
table below lists the reset sources and flag bits. Although no flag bits are associated with the internal system reset generated by issu-
ing a system reset or complement bank-select flash command, it is unlikely that these would occur unintentionally, given that the flash
command bits (FCNTL.3-0) require a timed-access write.
Reset Source Flag Associations

RESET SOURCE FLAG BIT
Power-on reset POR – WDCON.6
Watchdog reset WTRF – WDCON.3
Oscillator fail-detect reset OFDF – PCON.5
Internal system reset None
External reset None
_____________________________________________________________________________________________ 86
SECTION 9: INTERRUPTS
The ultra-high-speed microcontroller family improves upon the traditional 8051 architecture by utilizing a five-priority interrupt system.
The five priority levels, from highest priority to lowest, are 4, 3, 2, 1, and 0. The power-fail interrupt, when enabled, always receives the
highest priority (level 4), while other interrupt sources can be configured to level 3, 2, 1, or 0. Each source has independent priority
bits, flag(s), interrupt vector, and enable. In addition, interrupts can be globally enabled (or disabled). The interrupt system is com-
patible with the original 8051 family, having all of the original interrupts available. A summary of all interrupt sources is provided in the
table below.
Table 9-1. Interrupt Summary

INTERRUPT NATURAL PRIORITY
INTERRUPT FLAG ENABLE
VECTOR ORDER CONTROL
Power-fail 33h 0 (highest) PFI (WDCON.4) EPFI (WDCON.5) N/A
MPX0 (IP1.0)
External interrupt 0 03h 1 IE0 (TCON.1)** EX0 (IE.0)
LPX0 (IP0.0)
MPT0 (IP1.1)
Timer 0 overflow 0Bh 2 TF0 (TCON.5)* ET0 (IE.1)
LPT0 (IP0.1)
MPX1 (IP1.2)
External interrupt 1 13h 3 IE1 (TCON.3)** EX1 (IE.2)
LPX1 (IP0.2)
MPT1 (IP1.3)
Timer 1 overflow 1Bh 4 TF1 (TCON.7)* ET1 (IE.3)
LPT1 (IP0.3)
RI_0 (SCON0.0), MPS0 (IP1.4)
Serial port 0 23h 5 ES0 (IE.4)
TI_0 (SCON0.1) LPS0 (IP0.4)
TF2 (T2CON.7) MPT2 (IP1.5)
Timer 2 overflow 2Bh 6 ET2 (IE.5)
EXF2(T2CON.6) LPT2 (IP0.5)
RI_1 (SCON1.0), MPS1 (IP1.6)
Serial port 1 3Bh 7 ES1 (IE.6)
TI_1 (SCON1.1) LPS1 (IP0.6)
MPX2 (EIP1.0)
External interrupt 2 43h 8 IE2 (EXIF.4) EX2 (EIE.0)
LPX2 (EIP0.0)
MPX3 (EIP1.1)
External interrupt 3 4Bh 9 IE3 (EXIF.5) EX3 (EIE.1)
LPX3 (EIP0.1)
MPX4 (EIP1.2)
External interrupt 4 53h 10 IE4 (EXIF.6) EX4 (EIE.2)
LPX4 (EIP0.2)
MPX5 (EIP1.3)
External interrupt 5 5Bh 11 IE5 (EXIF.7) EX5 (EIE.3)
LPX5 (EIP0.3)
MPWDI (EIP1.4)
Watchdog interrupt 63h 12 WDIF (WDCON.3) EWDI (EIE.4)
LPWDI (EIP0.4)
Unless marked, these flags must be cleared manually by software.

*Cleared automatically by hardware when the service routine is vectored to.
**If edge-triggered, cleared automatically by hardware when the service routine is vectored to. If level-triggered, flag follows the state of the pin.
INTERRUPT OVERVIEW
An interrupt allows the software to react to unscheduled or asynchronous events. When an interrupt occurs, the CPU is expected to
“service” the interrupt. This service takes the form of an interrupt service routine (ISR). The ISR resides at a predetermined address,
as shown in Table 9-1. When the interrupt occurs, the CPU vectors to this address and runs code created to service the interrupt. The
CPU stays in an interrupt service state until the return from interrupt instruction (RETI) is executed at completion of the ISR. When an
RETI is performed, the processorl returns to the instruction that would have been next when the interrupt occurred. Once an ISR has
begun, it can be interrupted only by a higher priority interrupt.
87 _____________________________________________________________________________________________
When an interrupt condition occurs, the processor indicates this by setting a flag bit. This flag bit cannot alone cause an interrupt, and
is set regardless of whether the interrupt is enabled. Most flags must be cleared manually by software. However, IE0 and IE1 are
cleared automatically by hardware upon vectoring to the service routine if the interrupt was edge-triggered. In level-triggered mode,
the IE0 or IE1 flags will follow the state of the pin. Flags TF0 and TF1 are always cleared automatically when the service routine is vec-
tored to. Refer to the individual bit descriptions for more details.
Each source must be individually enabled in order to generate CPU interrupts. Each interrupt source has an independent enable, as
shown in Table 9-1. In order for the processor to acknowledge the interrupt and vector to the ISR, the enable all bit (IE.7: EA) must be
set to globally enable interrupt sources. Clearing the EA bit to a logic 0 disables all interrupts, regardless of the individual interrupt
enables. The power-fail warning interrupt source is the only exception, requiring only its individual enable bit be set (WDCON.5: EPFI)
to be recognized by the CPU. The EA bit has no effect on the power-fail interrupt.
INTERRUPT SOURCES
The interrupt sources present on the ultra-high-speed microcontroller can broken into several categories: external, timer-based, serial
communication, and power-fail. Each type is described in the following pages. Interrupt sources are evaluated during the final memo-
ry cycle of each instruction to determine whether and which interrupt is serviced. If the interrupt source goes active after this evalua-
tion, it is not considered until the final memory cycle of the next instruction.
External Interrupts
The ultra-high-speed microcontroller has six external interrupt sources. These include the standard two interrupts of the 8051 archi-
tecture and four new sources. The original interrupts are INT0 and INT1. These are active-low and can be programmed to be edge- or
level-sensitive. The detection mode for each source is controlled through TCON register bits IT0 and IT1, respectively. When ITx = 0,
the interrupt is triggered by a logic 0 on the appropriate interrupt pin. The interrupt condition remains in effect as long as the pin is low.
When ITx = 1, the interrupt is pseudo-edge-triggered. This means that the interrupt is activated, if on successive samples the pin is
found to be in a low state, indicating that a falling edge occurred. Since the external interrupts are sampled, the pin driver of an edge-
triggered interrupt should hold both the high and then the low condition for at least two system clock cycles (each) to ensure detec-
tion. This means maximum sampling frequency on any interrupt pin is one-fourth of the system clock frequency.
It is important to note that level-sensitive interrupts are not latched. This is most important if using other interrupts of equal or higher
priority, because the level-sensitive interrupt request may not receive immediate service by the processor. A level-sensitive interrupt
request is missed unless the condition is held until it can be serviced.
The remaining four external interrupts are similar in nature, with two differences. First, the four new interrupts are edge-detect only. They
do not have level-detect modes. Second, INT2 and INT4 are positive-edge sensitive instead of negative-edge sensitive. All associat-
ed bits and flags operate the same and have the same polarity as the original two. A logic 1 indicates the presence of a condition, not
the logic state of the pin.
If the power management mode is utilized, the designer must remember that detection of edge-triggered interrupts is defined in rela-
tion to the system clock (= 1024 oscillator clock cycles). This means that it requires 2048 external clock cycles before detecting that
an edge has just occurred. As a result, the latency for these interrupts is much longer in power management mode.
Timer Interrupts
The DS89C420 incorporates three 16-bit programmable timers, each of which can generate an interrupt, and a programmable watch-
dog timer. The three 16-bit programmable timers operate in the same manner as the 80C52. Each timer has an independent interrupt
enable, flag, vector, and priority. The watchdog timer also has its own interrupt enable, flag, and priority.
Timers 0 and 1 set their respective interrupt flags when the timer overflows from a full condition, depending on its mode. This flag is
set regardless of the interrupt enable state. If the interrupt is enabled, this event generates a call to the corresponding interrupt vec-
tor. For timers 0 and 1, the flags are cleared when the processor jumps to the interrupt vector. Thus, these flags are not available for
use by the interrupt service routine (ISR), but are available outside of the ISR and in applications that do not acknowledge the inter-
rupt (i.e., jump to the vector). If the interrupt is not acknowledged, then software must manually clear the flag bit. In addition to having
an interrupt flag for an overflow condition (as is the case for timers 0 and 1), timer 2 has a second interrupt flag (EXF2) that is associ-
ated with detection of a falling edge on the T2EX (P1.1) pin. When timer 2 has been configured in capture mode (CP/RL2 = 1, EXEN2
= 1) or autoreload mode (CP/RL2 = 0, EXEN2 = 1, DCEN = 0), a negative transition on T2EX causes the EXF2 interrupt flag to be set.
For timer 2 interrupts, jumping to the interrupt vector does not clear either of the flags. Instead, software must ascertain which flag
caused the interrupt and clear it manually. Timer 0 and 1 flag bits reside in the TCON register. Timer 2 flag bits reside in the T2CON
register. The interrupt enables and priorities for timers 0, 1, and 2 reside in the IE and IP0, IP1 registers.
_____________________________________________________________________________________________ 88
The watchdog interrupt usually has a different connotation than the timer interrupts. Unless the watchdog is being used as a very long
timer, the interrupt means that the software has failed to reset the timer and may be lost. The watchdog ISR can attempt to determine
the system state or allow the CPU to be reset if the watchdog reset function has been enabled (EWT = 1). Like other sources, the watch-
dog timer has a flag bit, enable bit, priority bits, and its own vector.
Serial Communication Interrupts
Each UART is capable of generating an interrupt. Each UART has its own interrupt enable, vector, and priority. Each UART interrupt
has two flags (RI, TI) that are used by the ISR to determine whether the interrupt comes from a received word or a transmitted one.
Unlike the timers, the UART flags are not altered when the interrupt is serviced. Software must change them manually.
When a UART finishes the transmission of a word, the TI bit is set and an interrupt is generated (if enabled). Likewise, the UART sets
the RI bit and generates an interrupt when a word is completely received. The CPU is not notified until the word is completely received
or transmitted.
Power-Fail Interrupt
The ultra-high-speed microcontroller has the ability to generate an interrupt when VCC drops below a predetermined level. By com-
paring a fixed ratio of VCC versus an internal reference, the DS89C420 can assess when VCC drops below the VPFW level and cause
an interrupt (if enabled). The level of VPFW is provided in the data sheet on DC electrical specifications. The power-fail interrupt is a
level-sensitive condition, and remains in effect as long as VCC remains below VPFW. The power-fail interrupt has the highest priority
level, which cannot be altered by the user. The EPFI bit solely controls the enabling or disabling of the power-fail interrupt source, and
is not subject to the global interrupt enable (EA). The EPFI bit should always be cleared to a logic 0 state if the power-fail interrupt is
not needed.
Simulated Interrupts
Software can simulate any interrupt source by setting the corresponding flag bit. This forces an interrupt condition that is acknowledged
(if enabled) and is otherwise indistinguishable from the real thing. Thus, an interrupt flag bit should never be set to a logic 1 by soft-
ware inadvertently. Once an interrupt has been acknowledged, software cannot prevent or end the interrupt by clearing its flag. If, how-
ever, software clears an interrupt flag before the interrupt is acknowledged, the interrupt does occur.
INTERRUPT PRIORITIES
The ultra-high-speed microcontroller has five interrupt priority levels. The five priority levels, from highest priority to lowest, are 4, 3, 2,
1, and 0.
The power-fail interrupt, when enabled, always receives the highest priority (level 4), while the remaining interrupt sources can indi-
vidually be programmed to level 3, 2, 1, or 0. The lowest priority (level 0) is the default condition for the other sources. An interrupt
being serviced can only be interrupted by a higher priority interrupt. The power-fail interrupt source, assigned priority level 4, there-
fore, has the ability to interrupt the service routine of any other source. No interrupt source with equal or lesser priority to one current-
ly being serviced can interrupt the service routine.
If two interrupt sources of equal priority levels are requested simultaneously, natural priority is used to arbitrate. The natural priority is
given in Table 9-1. Note that natural priority is only used to resolve simultaneous requests. Once an interrupt of a given priority is
invoked, only a source that is programmed with a higher priority can intercede.
Interrupt Register Conflicts
During normal operation, there is a small but finite probability that application software might try to read or modify a register associat-
ed with interrupt functions at the same time that the interrupt hardware is modifying the register. In general, these hardware/software
interrupt conflicts are resolved according to the “hardware wins” philosophy: In the event of a conflict, the hardware modification of a
register takes precedence over the software action to ensure that the interrupt event is not missed.
To assist in prevention of hardware/software conflicts, the interrupt selection process that normally occurs in the final memory cycle of
each instruction is aborted for any instructions that write to the IP0, IP1, EIP0, EIP1, IE, or EIE registers. When the evaluation takes place
in the subsequent instruction, the interrupt source incorporates the new priority and enable values from the previous instruction. If this
situation occurs, it lengthens the interrupt latency by the length of the instruction that modified the register.
89 _____________________________________________________________________________________________
INTERRUPT ACKNOWLEDGE CYCLE

The process of acknowledging an interrupt begins with the setting of the associated flag. For edge-triggered external interrupts and
internal interrupt sources, the interrupt flags are set automatically by hardware. For level-sensitive external interrupts, the flags are actu-
ally under control of the external signal, and the flag rises and falls with the pin level. All interrupt flags are evaluated on the final exe-
cution cycle of each instruction. A priority decoding process is performed among pending and new interrupt sources in order to select
the appropriate interrupt vector address. This decoding process is accomplished in a single memory cycle using combinatorial logic.
Hardware then forces an LCALL to the selected vector address in the following memory cycle, unless blocked by one of the following
conditions:
• An interrupt of equal or greater priority has already been invoked and the RETI instruction has not been issued to terminate it,
• The current cycle is not the final cycle in the execution of the current instruction, or
• The instruction in progress is an RETI or a write to IP0, IP1, EIP0, EIP1, IE, or EIE.
INTERRUPT
INTERRUPT INTERRUPT SELECTION
FLAG ENABLE BITS PRIORITY BITS HARDWARE
BITS
HIGHEST
PRIORITY
PFI
INT0
TF0
INT1 IT1
TF1
RI 0
TI_0
INTERRUPT
TF2 VECTOR
EXF2
RI_1
TI 1
INT2
INT3
INT4
INT5
WATCHDOG
INDIVIDUAL GLOBAL
ENABLES ENABLE
Figure 9-1. Interrupt Functional Description
_____________________________________________________________________________________________ 90
INTERRUPT LATENCY
Interrupt response time is normally between 4 and 18 memory cycles, depending on the state of the microcontroller when the interrupt
occurs. If the microcontroller is performing an ISR with equal or greater priority, interrupt latency increases because the new interrupt
is not invoked. In other cases, the response time depends on the current instruction. The fastest possible response to an interrupt is
four memory cycles. The four memory cycle response time includes one cycle for detecting the interrupt and three cycles to perform
the LCALL that is inherent in the interrupt request.
The maximum response time occurs if the microcontroller is performing a JBC instruction that clears a bit in IE, IP0, EIE, or EIP0, and
then executes a DIV as the next instruction. From the time an interrupt source is activated (not detected), the longest reaction time is
18 memory cycles. This includes one cycle to detect the interrupt, four cycles to finish the JBC, ten cycles to perform the DIV, then
three cycles for the LCALL to the ISR. This maximum response time of eighteen memory cycles assumes that there are no other pend-
ing interrupts of higher priority to be serviced and that the JBC instruction is not preceded and does not jump to any instruction that
aborts the priority decoding process (RETI or writes to IP0, IP1, EIP0, EIP1, IE, or EIE).
SECTION 10: I/O PORTS

The DS89C420 provides four 8-bit I/O ports. Each port appears as a special function register that can be addressed as a byte or 8
individual bit locations. In general, the register and the port pin have identical values, and reading or writing a port is the same as read-
ing or writing the SFR for the port. The basic I/O driver function and its electrical characteristics are similar to the drivers used in the
DS87C520, with respect to individual port and pin conditions.
Port 0 and port 2 can serve either as general-purpose parallel I/O ports or as the expanded memory bus. Ports 1 and 3 can be used
as general-purpose parallel I/O ports with optional special functions associated with each pin. Enabling the special function for a pin
automatically converts the I/O pin to that function. An optional function of a pin can be turned on and off dynamically to suit the appli-
cation. Using one or more I/O pins of a port as special functions does not affect the remaining port pins. It should be noted that port
0 drivers are open-drain and require external pullups when used as general-purpose I/O ports.
EXTERNAL
ADDRESS\ ADDRESS
DATA CONTROL VCC
PORT
0.n
INTERNAL
DATA BUS
D Q
WRITE
ENABLE
READ
READ LATCH/PIN
ENABLE
Figure 10-1. Port 0 Functional Circuitry
91 _____________________________________________________________________________________________
Parallel I/O
Each I/O port can be used as a general-purpose, bidirectional parallel I/O port. Data written to the port latch serves to set both the
level and the direction of the data on the pin. The output of the port pin is established by writing to the associated port pin latch. When
logic 0 is written to the port for output, the port is pulled to ground. When logic 1 is written to ports 1, 2, or 3, a strong driver momen-
tarily drives the pin from 0 to 1, and then a weak pullup maintains the 1. A logic 1 written to port 0 causes those pins to go tri-state,
functioning as open-drain outputs. A logic 1 in the port latch also configures the port pin to the input state. Since the pin is either weak-
ly pulled up or in three-state, the pin is the same as the driven logic state. The logic state of the pin itself does not alter the logic value
of the port latch.
Port 0
This is an open drain, 8-bit, bidirectional, general-purpose I/O port. A reset condition or logic 1, written to the latches of this port, three-
state, the port pins. This condition also serves as an input mode. When used as an I/O port, external pullups are required. As an alter-
nate function, this port can be used as part of the multiplexed address/data bus to access external memory. The DS89C420 supports
both nonpage and page mode. During the original 8051 expanded bus configuration (nonpage mode), when ALE is high, the LSB of
the address is presented to P0. When ALE is low, the port transitions to a bidirectional data bus. When used in page mode 1, P0 is
used as the primary data bus only. When used in page mode 2, P0 is used for the LSB of the address only.
The use of port 0 as general-purpose I/O is not recommended if the device is used to access external memory. In this case, the state
of the pins are disturbed during the memory access. In addition, the pullups required to maintain a high state during the use as gen-
eral-purpose I/O interfere with the complementary drivers employed when the device operates as an expanded memory bus.
When port 0 is used as an address bus, the AD0-7 pins provide true drive capability for logic levels 1 and 0. No external pullups are
required. In fact, external pullups degrade the memory interface timing. The DS89C420 employs a two-state system on AD0-7. This
allows the pin to be driven hard for a period of time, allowing the greatest possible setup or access time. The pin states are then held
in a weak latch until forced to the next state or overwritten by an external device. This assures a smooth transition between logic states
and also allows a longer hold time.
ADDRESS ADDRESS
A8-A15 CONTROL
VCC
DELAY
= 2Tclk VCC
PORT
INTERNAL 2.n
DATA BUS
D Q
Q VCC
WRITE
ENABLE
READ
READ LATCH/PIN
ENABLE
Figure 10-2. Port 2 Functional Circuitry
_____________________________________________________________________________________________ 92
Internal Memory Cycles Ext Memory Cycle Ext Memory Cycle

C1 C2 C3 C4 C1 C2 C3 C4
XTAL1
ALE
PSEN
LSB Add Data LSB Add Data
Port 0
Port 2 MSB Add MSB Add
Figure 10-3. External Program Memory Access (Nonpage Model)
Port 2
Port 2 is an 8-bit bidirectional I/O port. The reset condition sets the port pins to logic 1. In this state, a weak pullup holds the port pin
high. This condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup. Writing
a logic 0 to the port pin activates a strong pulldown that remains on until a 1 is written or a reset occurs. Writing a logic 1 after the port
has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver
turns off, the pin assumes both the output high and input state. As an alternate function, port 2 can function as the MSB of the address
bus for external memory access during nonpage mode. When used in page mode 1, P2 is used for both LSB and MSB of external
address. When used in page mode 2, P2 is used for the MSB of external address and data.
Port 1
Port 1 functions as both an 8-bit bidirectional I/O port and an alternate functional interface for timer 2 I/O, external interrupts 2, 3, 4, 5,
and serial port 1. Reset conditions set these port pins to logic 1 and are held high with weak pullups. This condition also serves as an
input mode, since any external circuit that writes to the port overcomes the weak pullup. When a logic 0 is written to any port pin, the
port activates a strong pulldown that remains on until a 1 is written or a reset occurs. Writing a logic 1 after the port has been a 0 caus-
es a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the pin
assumes both the output high and input state.
Port 3
Port 3 functions as both an 8-bit bidirectional I/O port and an alternate functional interface for external interrupts 0 and 1, serial port 0,
timers 0 and 1 inputs, and external data memory strobes. The reset condition sets all bits to logic 1. In this state, a weak pullup holds
the port high. This condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup.
Writing a logic 0 to any port pin activates a strong pulldown that remains on until a 1 is written or a reset occurs. Writing a logic 1 after
the port has been a 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong
driver turns off, the pin assumes both the output high and input state.
Alternate Functions of Ports 1 and 3
When any of the pins of ports 1 and 3 is enabled as a special function, the port latch should be programmed to logic 1 to avoid poten-
tial bus contention and ensure proper operation. The drive characteristics of these pins do not change when the pins are used for gen-
eral I/O or as a special function associated with the pin. port 0 and 2 pins, as well as PSEN, ALE, P3.6 and P3.7, incorporate special
circuitry to limit the current consumed by the device.
93 _____________________________________________________________________________________________
MOVX Instruction (Page miss)

1st 2nd 3rd 4th 9th
Cycle Cycle Cycle Cycle Cycle
XTAL1
ALE
PSEN
RD / WR
Inst Inst Inst Inst Inst Inst
Port 0 Data
Port 2 LSB LSB LSB LSB MSB LSB LSB LSB
MOVX
Instruction Memory Access (Stretch = 4)
Fetch
MOVX Instruction (Page hit)
1st 2nd 3rd 4th 5th 9th

Cycle Cycle Cycle Cycle Cycle Cycle
ALE
PSEN
RD / WR
Inst Inst Inst Inst Inst Inst Inst
Port 0 Data
Port 2 LSB LSB LSB LSB LSB LSB LSB LSB
MOVX
Instruction Memory Access (Stretch = 4)
Fetch
Figure 10-4. External Program Memory Access (Page Mode 1)
EXT CODE FETCHES

INTERNAL MEMORY CYCLES
PAGE MISS PAGE HIT PAGE HIT
C1 C2 C3 C4 C1 C2 C1 C2
XTAL1
ALE
PSEN
PORT 0 LSB ADD LSB ADD LSB ADD
PORT 2 MSB ADD DATA DATA DATA
Figure 10-5. External Program Memory Access (Page Mode 2)
_____________________________________________________________________________________________ 94
The special functions and the associated port pins are listed below:
P1.0 T2 Timer 2 output
P1.1 T2EX Timer 2 capture/reload input
P1.2 RXD1 Serial receive UART1
P1.3 TXD1 Serial transmit UART1
P1.4 INT2 External interrupt 2, rising-edge active
P1.5 INT3 External interrupt 3, falling-edge active
P1.6 INT4 External interrupt 4, rising-edge active
P3.0 RXD0 Serial receive UART0
P3.1 TXD0 Serial transmit UART0
P3.4 T0 Timer 0 input
P3.5 T1 Timer 1 input
P3.6 WR External data memory-write strobe
P3.7 RD External data memory-read strobe
Read-Modify-Write
The normal read instructions associated with the I/O ports read the pin state without regard to the port latches. However, the read-mod-
ify-write instructions read the state of the port latches instead of the port pins. This type of instruction reads the contents of an SFR,
then modifies it in the ALU, and returns it to the original source. The instructions of this type are listed below:
ANL Logical AND
ORL Logical OR
XRL Logical exclusive OR
JBC Branch if bit set and clear bit
CPL Complement bit
INC Increment
DEC Decrement
DJNZ Decrement and branch if not zero
MOV Px.n, C Move carry bit to bit n of port x
CLR Px.n Clear bit n in port x
SETB Px.n Set bit n in port x
Output Functions
The DS89C420 I/O ports appear to be true I/O, but their output characteristics are dependent on the individual port and pin conditions.
When software writes logic 0 to the port for output, the port is pulled to ground. When software writes logic 1 to the port for output,
ports 1, 2, or 3 drive weak pullups (after the strong transition from 0 to 1). Thus, as long as the port is not heavily loaded, true logic val-
ues are output. Port 0, having open-drain outputs, three-states when written to logic 1 and hence requires external pullups be present
when used as an output. DC drive capability is provided in the electrical specifications. Note that the DC current available from an I/O
port pin is a function of the permissible voltage drop.
Transition current is available to help move the port pin from logic 0 to logic 1. Since the logic 0 driver is strong, no additional drive
current is needed in the 1 to 0 direction. The transition current is applied when the port latch is changed from logic 0 to logic 1. Writing
logic 1 where a 1 was already in place does not change the strength of the pullup. This transition current is applied for two oscillator
cycles. The absolute current is not guaranteed, but is approximately 2 mA at 5V.
95 _____________________________________________________________________________________________
When serving as an I/O port, the drive varies as follows: for logic 0, the port invokes a strong pulldown; for logic 1, the port invokes a
strong pullup for two oscillator cycles to assist with the logic transition. Then the port reverts to a weak pullup. This weak pullup is main-
tained until the port transitions from logic 1 to logic 0. External circuits can overdrive the weak pullup. This allows the logic 1 output
state to serve as the input state as well.
Substantial DC current is available in both the high and low levels. However, the power dissipation limitations make it inadvisable to heav-
ily load multiple pins. In general, sink and source currents should not exceed 10mA total per port (8 bits) and 25mA total per package.
Input Functions
The input state of the I/O ports is the same as that of the output logic 1. That is, the pin is pulled weakly to logic 1. This logic 1 state is
easily overcome by external components. Thus, after software writes a 1 to the port pin, the port is configured for input. When the port
is read by software, the state of the pin is read. The only exception is the read-modify-write instructions, discussed earlier. If the exter-
nal circuit is driving logic 1, then the pin is logic 1. If the external circuit is driving logic 0, then it overcomes the internal pullup. Thus,
the pin is the same as the driven logic state. Note that the port latch is not altered by a read operation. Therefore, if logic 0 is driven
onto a port pin from an external source, then removed, the pin reverts to the weak pullup, as determined by the internal latch.
SECTION 11: PROGRAMMABLE TIMERS

The ultra-high-speed microcontroller incorporates three 16-bit programmable timers and has a watchdog timer with a programmable
interval. Because the watchdog timer is significantly different from the other timers, it is described separately. The 16-bit timers are
referred to as timers.
The three timers offer the same controls and I/O functions that were available in the 80C32. As mentioned, the actual timing of these func-
tions is user selectable to be compatible with the instruction cycle of the older generation of 8051 family (12 clocks per tick) or the new
generation (1 clock per tick). The timing for each of the three timers can be selected independently and can be changed dynamically.
In most modes, the timers can be used as either counters of external events or timers. When functioning as a counter, 1 to 0 transi-
tions on a port pin are monitored and counted. When functioning as timers, they effectively count oscillator or system clock cycles. The
time base for the timer function is detailed later in this section. Because an input clock pulse must be sampled high for two system
clock cycles and low for two system clock cycles in order to be recognized, this sets the maximum sampling frequency on any timer
input at one-fourth of the main system clock frequency.
Since the ultra-high-speed microcontroller timers have a variety of features, the following lists summarize the capabilities:
Timer 0 Timer 1 Timer 2
13-bit timer/counter 13-bit timer/counter 16-bit timer/counter
16-bit timer/counter 16-bit timer/counter 16-bit timer with capture
8-bit timer w/ autoreload 8-bit timer w/ autoreload 1 6-bit autoreload timer/counter
Two 8-bit timer/counters External control pulse timer/counter 16-bit up/down autoreload
External control pulse timer/counter Baud-rate generator Timer/counter
Baud-rate generator
Timer output clock generator
16-BIT TIMERS
Timers 0 and 1 are nearly identical. Timer 2 has several additional features such as up/down counting, capture values, and an option-
al output pin that make it unique. The following table summarizes the SFR bits that control operation of timers 0, 1, and 2. Detailed bit
descriptions can be found in Section 4. After the table, timers 0 and 1 are described first, followed by a separate description for timer
2. As mentioned above, the time base for each timer can be varied, which is discussed in more detail in the following pages.
_____________________________________________________________________________________________ 96
Table 11-1. Programmable Timers

BIT NAMES DESCRIPTION REGISTER LOCATION BIT POSITIONS
GATE Gate control enable for INTO pin TMOD – 89h TMOD.3
C/T Counter/timer select TMOD – 89h TMOD.2
M1, M0 Timer mode select bits TMOD – 89h TMOD.1,0
TIMER 0
TF0 Timer overflow flag TCON – 88h TCON.5

TR0 Timer run control TCON – 88h TCON.4
T0M Input clock select (/4) CKCON – 8Eh CKCON.3
T0MH Input clock high-speed select (/1) CKMOD – 96h CKMOD.3
Timer LSB TL0 – 8Ah
Timer MSB TH0 – 8Ch
GATE Gate control enable for INT1 pin TMOD – 89h TMOD.7
C/T Counter/timer select TMOD – 89h TMOD.6
M1, M0 Timer mode select bits TMOD – 89h TMOD.5,4
TIMER 1
TF1 Timer overflow flag TCON – 88h TCON.7

TR1 Timer run control TCON – 88h TCON.6
Timer LSB TL1 – 8Bh
Timer MSB TH1 – 8Dh
TF2 Timer overflow flag T2CON – C8h T2CON.7

EXF2 Timer external flag T2CON – C8h T2CON.6
RCLK Timer 2 receive serial clock enable T2CON – C8h T2CON.5
TCLK Timer 2 transmit serial clock enable T2CON – C8h T2CON.4
EXEN2 External enable for T2EX pin T2CON – C8h T2CON.3
TR2 Timer run control T2CON – C8h T2CON.2
C/T2 Counter/timer select T2CON – C8h T2CON.1
TIMER 2
CP/RL2 Capture/reload select T2CON – C8h T2CON.0

T2OE Output enable for T2 pin T2MOD – C9h T2MOD.1
DCEN Down count enable T2MOD – C9h T2MOD.0
Timer LSB TL2 – CCh
Timer MSB TH2 – CDh
Timer capture LSB RCAP2L – CAh
Timer capture MSB RCAP2H – CBh
TIMER 0, TIMER 1 MODES

Timers 0 and 1 both have three common operating modes. They are 13-bit timer/counter, 16-bit timer/counter, and 8-bit timer/counter
with autoreload. Timer 0 can additionally be configured to operate as two 8-bit timers. These four modes, controlled by the TMOD reg-
ister, are detailed in the following pages.
MODE 0
Mode 0 configures either timer 0 or timer 1 for operation as a 13-bit timer/counter. As shown in Figure 11-1, setting TMOD register bits
M1, M0 = 00b selects this operating mode for either timer 0 or timer 1.
When using timer 0, TL0 uses only bits 0 through 4. These bits serve as the 5 LSbs of the 13-bit timer. TH0 provides the 8 MSbs of the
13-bit timer. Bit 4 of TL0 is used as a ripple out to TH0 bit 0, thereby completely bypassing bits 5 through 7 of TL0. Once the timer is
started using the TR0 (TCON.4) timer enable, the timer counts as long as GATE (TMOD.3) is 0 or GATE is 1 and pin INTO is 1. It counts
oscillator or system clock cycles if C/T (TMOD.2) is set to a logic 0 and 1 to 0 transitions on T0 (P3.4) if C/T is set to a 1. When the 13-
bit count reaches 1FFFh (all ones), the next count causes it to roll over to 0000h. The TF0 (TCON.5) flag is set and an interrupt occurs
if enabled. The upper 3 bits of TL0 are indeterminate.
97 _____________________________________________________________________________________________
Note that when used as a timer, the input clock selection can be affected by the clock divide bits (PMR.7-6), the TxM bit (in the CKCON
register), and the TxMH bit (in the CKMOD register). The time base selection is described in more detail later in this section.
Mode 0 operates identically when timer 1 is used. The same information applies to TL1 and TH1, which form the 13-bit register. TR1
(TCON.6), INT1 (P3.3), T1 (P3.5) and the relevant C/T (TMOD.6), and GATE (TMOD.7) bits have the same functions.
MODE 1
Mode 1 configures the timer for 16-bit operation as either a timer or counter. Figure 11-1 shows that setting the TMOD select bits M1,
M0 = 01b invoke this operating mode. For timer n, all of the TLn and THn registers are used. For example, if timer 1 is configured in
mode 1, then TL1 holds the LSB and TH1 holds the MSB. Rollover occurs when the timer reaches FFFFh. An interrupt also occurs if
enabled and the relevant TFn flag is set. Time-base selection, counter/timer selection, and the gate function operate as described in
mode 0.
MODE 2
This mode configures the timer as an 8-bit timer/counter with automatic reload of the start value. This configuration is shown in Figure
11-2, and is selected when bits M1and M0 of the TCON register are set to 1 and 0, respectively. When configured in mode 2, the timer
uses TLn to count and THn to store the reload value. Software must initialize both TLn and THn with the same starting value for the first
count to be correct. Once the TLn reaches FFh, it is automatically loaded with the value in THn. The THn value remains unchanged
unless modified by software. Mode 2 is commonly used to generate baud rates since it runs without continued software intervention.
As in modes 0 and 1, mode 2 allows counting of either clock cycles or pulses on pin Tn (C/T = 1) when counting is enabled by TRn
and the proper setting of GATE and INTn pins.
T0M = CKCON.3
(T1M = CKCON.4)
EXTERNAL OSCILLATOR DIVIDE-

T0MH = CKMOD.3
BY-12
0 (T1MH = CKMOD.4)
C / T = TMOD.2
DIVIDE- 1 0
INPUT TO TIMER BY-4 (C / T = TMOD.6)
CLK MODE SYSCLK TL0
DIVIDE-BY-1 OSC / 1 (TL1)
2X OSC / 0.5 1 0
CLK 0 4 7
4X OSC / 0.25
1 00 MODE 0
T0 = P3.4 M1, M0 = TMOD.1,
(T1 = P3.5) TMOD.0
(M1, M0 = TMOD.5,
01 TMOD.4)
TR0 = TCON.4
MODE 1
(TR1 = TCON.6) TH0
(TH1)
GATE = TMOD.3 0 7
(GATE = TMOD.7)
INT0 = P3.2
( INT1 = P3.3)
TF0 = TCON.5 INTERRUPT
(TF1 = TCON.7)
TIMER 1 FUNCTIONS
SHOWN IN PARENTHESES ()
NOTE: FOR POWER-MANAGEMENT MODE (DIVIDE-BY-1024) OPERATION, THE TIMER INPUT CLOCK TO THE TIMER IS
OSC / 1024 IF EITHER TXM = 1 OR TXMH = 1. OTHERWISE, THE TIMER INPUT IS OSC / 3072.
Figure 11-1. Timers/Counters 0 and 1, Modes 0 and 1
_____________________________________________________________________________________________ 98
T0M = CKCON.3
(T1M = CKCON.4)
EXTERNAL OSCILLATOR DIVIDE- T0MH = CKMOD.3

BY-12 (T1MH = CKMOD.4)
0
C / T = TMOD.2
DIVIDE- 1 0
INPUT TO TIMER (C / T = TMOD.6)
BY-4
CLK MODE SYSCLK TL0
DIVIDE-BY-1 OSC / 1 (TL1)
2X OSC / 0.5 1 0
CLK 0 RELOAD
4X OSC / 0.25 7
1
T0 = P3.4
(T1 = P3.5)
TR0 = TCON.4
(TR1 = TCON.6)
0 TH0 7
GATE = TMOD.3
(GATE = TMOD.7) (TH1)
INT0 = P3.2
( INT1 = P3.3) TF0 = TCON.5
INTERRUPT
(TF1 = TCON.7)
TIMER 1 FUNCTIONS
SHOWN IN PARENTHESES ()
Figure 11-2. Timers/Counters 0 and 1, Mode 2
MODE 3
This mode provides an 8-bit timer/counter and a second 8-bit timer as indicated in Figure 11-3. In mode 3, TL0 is an 8-bit timer/counter
controlled by the normal timer 0 bits (TR0 = TCON.4 and TF0 = TCON.5). TL0 can be used to count clock cycles or 1 to 0 transitions
on pin T0, as determined by C/T(TMOD.2). As in the other modes, the GATE function can use INT0 to give external run control of the
timer to an outside signal.
TH0 becomes an independent 8-bit timer in mode 3; however, it can only count clock cycles as shown in Figure 11-2. In this mode,
some of timer 1’s control signals are used to manipulate TH0. That is, TR1 (TCON.6) and TF1 (TCON.7) become the relevant control
and flag bits associated with TH0.
In mode 3, timer 1 stops counting and holds its value. Thus, timer 1 has no practical application while in mode 3.
As mentioned, when timer 0 is in mode 3, it uses some of timer 1’s resources (i.e., TR1 and TF1). Timer 1 can still be used in modes
0, 1, and 2 in this situation, but its flexibility becomes somewhat limited. While it maintains its basic functionality, its inputs and outputs
are no longer available. Therefore, when timer 0 is in mode 3, timer 1 can only count clock cycles, and it does not have an interrupt or
flag. With these limitations, baud-rate generation is its most practical application, but other time-base functions may be achieved by
reading the registers.
TIMER 2 MODES
Like timers 0 and 1, timer 2 is a full-function timer/counter; however, it has several additional capabilities that make it more useful. Timer
2 has independent control registers in T2CON and T2MOD, and is based on count registers TL2 and TH2. It does not offer the 13-bit
or dual 8-bit mode, but instead runs in the 16-bit mode at all times. Also note that while timers 0 and 1 have an 8-bit autoreload mode,
timer 2 provides a 16-bit autoreload mode. This mode uses the timer capture registers to hold the reload values. The modes available
on timer 2 are described in the following pages.
99 _____________________________________________________________________________________________
T0M = CKCON.3

BY-12
0 T0MH = CKMOD.3
DIVIDE- 1 C / T = TMOD.2
INPUT TO TIMER 0
BY-4
CLK MODE SYSCLK 0
DIVIDE-BY-1 OSC / 1
2X OSC / 0.5 1 CLK 0 TL0 7
4X OSC / 0.25
1
T0 = P3.4
TF0 = TCON.5 INTERRUPT
TR0 = TCON.4
GATE = TMOD.3 TF1 = TCON.7 INTERRUPT
INT0 = P3.2
TR1 = TCON.6
0 TH0 7
Figure 11-3. Timer/Counter 0, Mode 3
16-Bit Timer/Counter with Optional Capture

In this mode, timer 2 performs a simple timer or counter function where it behaves similarly to mode 1 of timers 0 and 1, but uses 16
instead of 8 bits. This mode, along with the optional capture mode described later, is illustrated in Figure 11-4. The 16-bit count values
are found in TL2 and TH2 special function registers (addresses 0CCh and 0CDh, respectively). The selection of whether a timer or
counter function is performed is made using bit C/T2 (T2CON.1). When C/T2 is set to a logic 1, timer 2 behaves as a counter where it
counts 1 to 0 transitions at the T2 (P1.0) pin. When C/T2 is set to a logic 0, timer 2 functions as a timer where it counts clock cycles.
Timing or counting is enabled by setting bit TR2 (T2CON.2) to 1, and disabled by setting it to zero. When the counter rolls over from
FFFFh to 0000h, the TF2 flag (T2CON.7) is set and causes an interrupt if timer 2’s interrupt is enabled.
A diagram of timer 2’s capture mode is shown in Figure 11-4. In this mode, the timer performs basically the same 16-bit timer/counter
function described above. However, a 1 to 0 transition on T2EX (pin P1.1) causes the value in timer 2 to be transferred into the cap-
ture registers if enabled by EXEN2 (T2CON.3). The capture registers, RCAP2L and RCAP2H, correspond to TL2 and TH2, respective-
ly. The capture function is enabled by the CP/RL2 (T2CON.0) bit. When this bit is set to logic 1, the timer is in the capture mode just
described. When set to logic 0, the timer is in autoreload mode described later.
16-Bit Autoreload Timer/Counter
This mode is illustrated in Figure 11-5. When timer 2 reaches an overflow state, i.e., rolls over from FFFFh to 0000, it sets the TF2 flag.
This flag can generate an interrupt if enabled. In addition, the timer restores its starting value and begins timing (or counting) again.
The starting value is preloaded by software into capture registers RCAP2L and RCAP2H. These registers cannot be used for capture
functions while also performing autoreload, so these modes are mutually exclusive. Autoreload is invoked by the CP/RL2 (T2CON.0)
bit. When set to a logic 0, the timer is in autoreload mode. When CP/RL2 is set to a logic 1, the timer is in capture mode described
above. If the C/T2 bit (T2CON.1) is a logic 0, the timer’s input clock is selectable as a function of the external oscillator or the system
clock. Otherwise, pulses on pin T2 (P1.0) are counted when C/T2 = 1. As in other modes, counting or timing is enabled or disabled
with TR2 (T2CON.2).
When in autoreload mode, timer 2 can also be forced to reload with the T2EX (P1.1) pin. A 1 to 0 transition forces a reload if enabled by
the EXEN2 (T2CON.3) bit. If EXEN2 is set to a logic 1, then a 1 to 0 transition on T2EX causes a reload. Otherwise, the T2EX pin is ignored.
____________________________________________________________________________________________ 100
T2M = CKCON.5

BY-12
0 T2MH = CKMOD.5
DIVIDE- 1 C / T2 = T2CON.1
INPUT TO TIMER 0
BY-4
CLK MODE SYSCLK 0
DIVIDE-BY-1 OSC / 1 CLK
2X 0 78 15
OSC / 0.5 1 TF2 =
TL2 TH2 T2CON.7
4X OSC / 0.25
1
T2 = P1.0
TR2 = T2CON.2
RCAP2L RCAP2H
T2EX = P1.1 0 78 15
CAPTURE EXF2 = TIMER 2

EXEN2 = T2CON.3 T2CON.6 INTERRUPT
Figure 11-4. Timer/Counter 2 with Optional Capture (CP/RL2 = 1)
T2M = CKCON.5

BY-12
0 T2MH = CKMOD.5
DIVIDE- 1 C / T2 = T2CON.1
INPUT TO TIMER 0
BY-4
CLK MODE SYSCLK 0
2X OSC / 0.5 1 0 78 15 TF2 =
4X OSC / 0.25 TL2 TH2 T2CON.7
1
T2 = P1.0
TR2 = T2CON.2 RCAP2L RCAP2H
T2EX = P1.1 0 78 15
TIMER 2
INTERRUPT
EXF2 =
EXEN2 = T2CON.3 T2CON.6
Figure 11-5. Timer/Counter 2 Autoreload Mode (CP/RL2 = 0, DCEN = 0)
101 ____________________________________________________________________________________________
Up/Down-Count Autoreload Timer/Counter

The up/down autoreload counter option is selected by the DCEN (T2MOD.0) bit, and is illustrated in Figure 11-6. When DCEN
(T2MOD.0) is set to a logic 1, timer 2 counts up or down as controlled by the state of pin T2EX (P1.1). T2EX causes upward counting
when a logic 1 is applied and down counting when a logic 0 is applied. When DCEN = 0, timer 2 only counts up.
When an upward counting overflow occurs, the value in RCAP2L and RCAP2H loads into TL2 and TH2. In the down-count direction,
an underflow occurs when TL2 and TH2 match the values in RCAP2L and RCAP2H, respectively. When an underflow occurs, FFFFh
is loaded into TL2 and TH2 and counting continues.
Note that, in this mode, the overflow/underflow output of the timer is provided to an edge-detection circuit as well as to the TF2 bit
(T2CON.7). This edge-detection circuit toggles the EXF2 bit (T2CON.6) on every overflow or underflow. Therefore, the EXF2 bit behaves
as a 17th bit of the counter, and may be used as such.
Baud-Rate Generator
Timer 2 can be used to generate baud rates for serial port 0 in serial mode 1 or 3. Baud-rate generator mode is invoked by setting
either the RCLK or TCLK bit in the T2CON register to a logic 1, as illustrated in Figure 11-7. In this mode, the timer continues to func-
tion in autoreload mode, but instead of setting the interrupt flag TF2 (T2CON.7) and potentially causing an interrupt, the overflow gen-
erates the shift clock for the serial port function. As in normal autoreload mode, an overflow causes RCAP2L and RCAP2H to be trans-
ferred into T2L and T2H, respectively. Note that, when RCLK or TCLK is set to 1, timer 2 is forced into 16-bit autoreload mode, regard-
less of the CP/RL2 bit.
As explained above, the timer itself cannot set the TF2 interrupt flag and, therefore, cannot generate an interrupt. However, if EXEN2
(T2CON.3) is set to 1, a 1 to 0 transition on the T2EX (P1.1) pin causes the EXF2 (T2CON.6) interrupt flag to be set. If enabled, this
causes a timer 2 interrupt to occur. Therefore, in this mode, the T2EX pin may be used as an additional external interrupt, if desired.
T2M = CKCON.5

BY-12
0 T2MH = CKMOD.5
(DOWN-COUNTING RELOAD VALUE)
C / T2 = T2CON.1 0FFH 0FFH
DIVIDE- 1 0
INPUT TO TIMER
BY-4
CLK MODE SYSCLK 0
2X OSC / 0.5 1 0 78 15
4X OSC / 0.25 TL2 TH2
1
T2 = P1.0
0 78 15
RCAP2L R AP2H
TR2 = T2CON.2
(UP-COUNTING RELOAD VALUE)
COUNT DIRECTION
(1 = UP, 0 = DOWN)
T2EX = P1.1
TF2 = TIMER 2
T2CON.7 INTERRUPT
EXF2 =
T2CON.6
Figure 11-6. Timer/Counter 2 Autoreload Mode (DCEN = 1)
____________________________________________________________________________________________ 102
TIMER 1
OVERFLOW
OSC INPUT TO TIMER
CLK MODE TIMER INPUT C / T2 = T2CON.1
DIVIDE- SMOD_0 =
DIVIDE BY 1 OSC / 2 BY-2 PCON.7
2X OSC / 2 0
4X OSC / 2
PMM ( / 1024) OSC / 2048 0 1
CLK
1 RCLK =
T2 = P1.0 0 78 15 T2CON.5
TR2 = T2CON.2 TL2 TH2
1 0
DIVIDE-
TCLK = BY-16
T2CON.4 Rx
T2EX = P1.1 RCAP2L RCAP2H 1 0 CLOCK
0 78 15
DIVIDE-
BY-1 6
EXF2 = Tx
TIMER 2 CLOCK
EXEN2 = T2CON.3 T2CON.6 INTERRUPT
Figure 11-7. Timer/Counter 2 Baud-Rate Generator Mode
Another feature of the baud-rate generator mode is that the crystal-derived time base for the timer is the crystal frequency divided by
2. No other crystal-divider selection is possible unless operating in power-management mode. If a different time base is desired, bit
C/T2 (T2CON.1) may be set to a 1, sourcing the time base from an external clock source supplied by the user on pin T2 (P1.0). The
RCAP registers may be read, but not modified, while TR2 = 1. Stop the timer (TR2 = 0) to modify these registers.
Timer Output Clock Generator
Timer 2 can also be configured to drive a clock output on port pin P1.0 (T2), as shown in Figure 11-8. To configure timer 2 for this mode,
it must first be set to 16-bit autoreload timer mode (CP/RL2 = 0, C/T2 = 0). Next, the T2OE (T2MOD.1) bit must be set to a logic 1. TR2
(T2CON.2) must also be set to a logic 1 to enable the timer.
This mode produces a 50% duty cycle square-wave output. The frequency of the square wave is given by the formula in Figure 11-7.
Each timer overflow causes an edge transition on the pin, i.e., the state of the pin toggles.
Note that this mode has two somewhat unique features in common with the baud-rate generation mode. First, the time base is the crys-
tal frequency divided by 2, and other than power-management mode operation, no other divider selection is possible. Second, the
timer itself does not generate an interrupt, but, if needed, an additional external interrupt may be caused using T2EX as described
above. Because of the two modes’ similarities, the timer can be used to generate both an external clock and a baud-rate clock simul-
taneously. Once the clock-out mode is established, either TCLK or RCLK is set to 1, and the RCAP2 registers are loaded, the timer
provides a clock to both functions.
Time-Base Selection
The ultra-high-speed microcontroller allows the user to select the time base for each timer independently. In the standard 8051, the
timers count the oscillator divided by 12, which is the standard 8051 machine cycle timing. Following a reset, the timers default to an
oscillator divided-by-12 input clock to remain drop-in compatible with the original 8051. The ultra-high-speed microcontroller timers
can additionally be configured to use the system clock or the system clock divided by 4 for the input clock. These selections, while not
affecting the CPU timing, allow for higher precision timing and faster baud rates. As an example, a user might select both the baud-
rate generator timer and another timer to run at 12 oscillator clocks per timer tick with the third timer running at four system clocks per
tick. This allows one timer to measure higher speed events or to gain better resolution.
103 ____________________________________________________________________________________________
OSC INPUT TO TIMER

CLK MODE TIMER INPUT
DIVIDE-BY-1 OSC / 2
2X OSC / 2
4X OSC / 2 0 7 8 15
PMM ( / 1024) OSC / 2048 TL2 TH2
C/T2 = T2CON.1 = 0 TR2 =

T2CON.2
RCAP2L RCAP2H
T2 = P1.0 0 7 8 15
DIVIDE-
BY-2
T2OE = T2MOD.1
T2EX = P1.1 EXF2 = TIMER 2

T2CON.6 INTERRUPT
EXEN2 = T2CON.3
T2 FREQUENCY OUT = TIMER CLOCK INPUT / (2 x (65536—RCAP2H, RCAP2L))
Figure 11-8. Timer/Counter 2 Clock Out Mode Time–Base Selection
The input clock selection is independent for each timer and the default is 12 oscillator clocks per timer tick. The control bits for the
time-base selection (TxM, TxMH) are located in the clock control register (CKCON;8Eh) and the clock-mode register (CKMOD;96h).
The TxM and TxMH bits for each of the timers enable input clock selections of the system clock divided by 4 and the system clock
divided by 1, respectively. When TxMH is set to a logic 1, the associated TxM bit for that timer is ignored. Note that, when operating
in the default system clock mode, the system clock is the same frequency as the oscillator clock. System clock mode selection is con-
trolled by the CD1, CD0 bits of the PMR register. See the PMR register description and the CPU timing section for more information on
how to modify the system clock. As described earlier, timer 2 does, however, automatically switch to two oscillator clocks per tick when
configured for baud-rate generation or clock-output mode. When the time base is derived from an external source (i.e., the T0, T1, or
T2 pins), the timer operates at the frequency of the external source and is not affected by the setting of the TxM or TxMH bits. The only
limitation is that the external source frequency can be no faster than one-fourth of the main system clock frequency. Use of power man-
agement-mode changes the input clock to the timers in a way that does not exactly follow any of the guidelines set forth to this point.
Tables 11-2 and 11-3 show the resulting timer input clock for the various system clock modes and timer control bit setting. Table 11-2
pertains only to timer 2 in the baud-rate generation or clock-output mode.
Table 11-2. Timers 0, 1, 2 Input Clock Frequency

TIMERS 0, 1, 2
PMR REGISTER BITS
SYSTEM CLOCK MODE INPUT CLOCK FREQUENCY
4X/2X, CD1, CD0
TxMH,TxM = 00 TxMH,TxM = 01 TxMH,TxM = 1x
Crystal multiply mode 4X 100 OSC / 12 OSC / 1 OSC / 0.25
Divide-by-1 (default) X01, X10 OSC / 12 OSC / 4 OSC / 1
Power-management mode
X11 OSC / 3072 OSC / 1024 OSC / 1024
(divide-by-1024)
____________________________________________________________________________________________ 104
Table 11-3. Timer 2 Baud-Rate Generation/Clock Output Mode

TIMER 2
PMR REGISTER BITS
SYSTEM CLOCK MODE BAUD-RATE GENERATION/CLOCK OUTPUT MODE
4X/2X, CD1, CD0
INPUT CLOCK FREQUENCY (TxMH, TxM = xx)
Crystal multiply mode 4X 100 OSC / 2
Divide-by-1 (default) X01, X10 OSC / 2
Power management mode
X11 OSC / 2048
(divide-by-1024)
WATCHDOG TIMER
The watchdog timer reset provides CPU monitoring by requiring software to clear the timer before the user-selected interval expires. If
the timer is not reset, the CPU can be reset by the watchdog. The watchdog function is optional and is described below.
The watchdog timer is a user-programmable clock counter that can serve as a time-base generator, an event timer, or a system super-
visor. As can be seen in Figure 11-9, the timer is driven by the main system clock that is supplied to a series of dividers. The divider
output is selectable, and determines the interval between timeouts. When the timeout is reached, an interrupt flag is set, and if enabled,
a reset occurs. The interrupt flag causes an interrupt to occur if its individual enable bit is set and the global interrupt enable is set.
The reset and interrupt are completely discrete functions that may be acknowledged or ignored, together or separately for various
applications.
The watchdog timer reset function works as follows. After initializing the correct timeout interval (discussed later), software first restarts
the watchdog using RWT (WDCON.0) and then enables, if desired, the reset function by setting the enable watchdog timer reset (EWT
= WDCON.1) bit. Any time prior to reaching its user-selected terminal value, software can set the reset watchdog timer (RWT =
WDCON.0) bit. If the watchdog timer is reset (RWT bit written to a logic 1) before the timeout period expires, the timer starts over.
Hardware automatically clears the RWT after software sets it.
XTAL1
RWT (WDCON.0)
(RESET WATCHDOG)
XTAL2
SYSTEM CLOCK DIVIDE-BY- DIVIDE-BY- DIVIDE-BY- DIVIDE-BY-
MODE CONTROL 17 3 3 3
2 2 2 2
17 20 23 26
2 2 2 2
WD1 (CKCON.7) TIMEOUT TIMEOUT
WD0 (CKCON.6) SELECTOR
SYSCLK OUTPUT
CLK MODE SYSCLK WDIF
WATCHDOG
DIVIDE-BY-1 OSC / 1 (WDCON.3) INTERRUPT
2X OSC / 0.5 EWDI (EIE.4)
4X OSC / 0.25 (ENABLE WATCHDOG TIMER)
PMM OSC / 1024
512 SYSCLK
DELAY RESET
EWT (WDCON.1) WTRF

(ENABLE WATCHDOG TIMER) (WDCON.2)
Figure 11-9. Watchdog Timer
105 ____________________________________________________________________________________________
If the timeout is reached without RWT being set, hardware generates a watchdog interrupt if the interrupt source has been enabled. If
no further action is taken to prevent a watchdog reset in the 512 system clock cycles following the timeout, hardware has the ability to
reset the CPU if EWT = 1. When the reset occurs, the watchdog timer reset flag (WTRF = WDCON.2) is automatically set to indicate
the cause of the reset; however, software must clear this bit manually.
The watchdog timer is a free-running timer. When used as a simple timer with both the reset and interrupt functions disabled (EWT =
0 and EWDI = 0), the timer continues to set the watchdog interrupt flag each time the timer completes the selected timer interval as
programmed by WD1 (CKCON.7) and WD0 (CKCON.6). Restarting the timer using the RWT (WDCON.0) bit allows software to use the
timer in a polled timeout mode. The WDIF bit is cleared by software or any reset.
The watchdog interrupt is also available for applications that do not need a true watchdog reset, but a very long timer. The interrupt is
enabled using the enable watchdog timer interrupt (EWDI = EIE.4) bit. When the timeout occurs, the watchdog timer sets the WDIF bit
(WDCON.3), and an interrupt occurs if the global interrupt enable (EA = IE.7) is set. Note that WDIF is set 512 clocks before a poten-
tial watchdog reset. The watchdog interrupt flag indicates the source of the interrupt, and must be cleared by software.
Using the watchdog interrupt during software development can allow the user to select ideal watchdog reset locations. Code is first
developed without enabling the watchdog interrupt or reset functions. Once the program is complete, the watchdog interrupt function
is enabled to identify the required locations in code to set the RWT (WDCON.0) bit. Incrementally adding instructions to reset the watch-
dog timer prior to each address location (identified by the watchdog interrupt) allows the code to eventually run without receiving a
watchdog interrupt. At this point, the watchdog timer reset can be enabled without the potential of generating unwanted resets. At the
same time, the watchdog interrupt may also be disabled. Proper use of the watchdog interrupt with the watchdog reset allows inter-
rupt software to survey the system for errant conditions.
When using the watchdog timer as a system monitor, the watchdog reset function should be used. If the interrupt function were used,
the purpose of the watchdog would be defeated. For example, assume the system is executing errant code prior to the watchdog inter-
rupt. The interrupt would temporarily force the system back into control by vectoring the CPU to the interrupt service routine. Restarting
the watchdog and exiting by an RETI or RET would return the processor to the lost position prior to the interrupt. By using the watch-
dog reset function, the processor is restarted from the beginning of the program and, therefore, placed into a known state.
The watchdog timeout selection is made using bits WD1 (CKCON.7) and WD0 (CKCON.6). The watchdog has four timeout selections
based on the system clock frequency, as shown in the figure. Since the timeout is a function of the system clock, the actual timeout
interval is dependent on both the crystal frequency and the system clock mode. Shown in Table 11-4 is a summary of the selectable
watchdog timeout intervals for the various system clock modes and WD1:0 control bit settings. The watchdog reset, if enabled, is
always scheduled to occur 512 system clocks following the timeout. Watchdog-generated resets last for 13 oscillator cycles.
As discussed above, the watchdog timer has several SFR bits that contribute to its operation. It can be enabled to function as either
a reset source, interrupt source, software polled timer, or any combination of the three. Both the reset and the interrupt have status
flags. The watchdog also has a bit that restarts the timer. Table 11-5 shows the watchdog timer-related bits. Detailed bit descriptions
can be found in Section 4.
Table 11-4. Watchdog Timeout Intervals

WATCHDOG TIMEOUT
PMR REGISTER BITS (IN NUMBER OF OSCILLATOR CLOCKS)
SYSTEM CLOCK MODE
4X/2X, CD1, CD0
WD1:0 = 00b WD1:0 = 01b WD1:0 = 10b WD1:0 = 11b
Crystal multiply mode 4X 100 215 218 221 224
Crystal multiply mode 2X 000 216 219 222 225
Divide-by-1 (default) X01, X10 217 220 223 226
Power management mode
X11 227 230 233 236
(divide-by-1024)
____________________________________________________________________________________________ 106
Table 11-5. Watchdog Timer-Related Bits

EWT Enable watchdog timer reset WDCON – D8h WDCON.1
RWT Reset watchdog timer WDCON – D8h WDCON.0
WD1,WD0 Watchdog interval control bits 1, 0 CKCON – 8Eh CKCON.7,6
WTRF Watchdog timer reset flag WDCON – D8h WDCON.2
EWDI Enable watchdog timer interrupt EIE – E8h EIE.4
WDIF Watchdog interrupt flag WDCON – D8h WDCON.3
Section 12: SERIAL I/O

The ultra-high-speed microcontroller provides two fully independent UARTs (serial ports) with framing-error detection and automatic
address recognition. The two UARTs can be operated simultaneously in identical or different modes and communication speeds. In
this documentation, all descriptions apply to both UARTs, unless stated otherwise.
Each serial port is capable of both synchronous and asynchronous modes. In the synchronous mode, the microcontroller generates
the clock and operates the UART in a half-duplex mode. In the asynchronous mode, full-duplex operation is available. Receive data is
buffered in a holding register. This allows the UART to receive an incoming word before software has read the previous value. Each
UART has an associated control register (SCON0, SCON1) and each has a transmit/receive register (SBUF0, SBUF1). The SFR loca-
tions are: SCON0, 98h; SBUF0, 99h; SCON1, C0h; SBUF1, C1h. The SBUF location provides access to both transmit and receive reg-
isters. Reads are directed to the receive buffer and writes to the transmit buffer automatically.
SERIAL MODE SUMMARY
Each port provides four operating modes. These offer different communication protocols and baud rates.
The four serial operating modes and max baud rate for each are shown in Table 12-1, followed by a brief summary of each mode.
Detailed descriptions of the modes are provided later in this section. In addition, provisions for use of the serial ports in conjunction
with the crystal multiplier and power-management mode are discussed later in this section.
MODE 0
Mode 0 provides synchronous communication with external devices. It is commonly used to communicate with serial peripherals. Serial
I/O occurs on the RXD pin. The shift clock is provided on the TXD pin. Note that, whether transmitting or receiving, the serial clock is
generated by the ultra-high-speed microcontroller. Thus, any device on the serial port in mode 0 must accept the microcontroller as
the master.
When not using power-management mode, the baud rate in mode 0 is the system clock frequency divided by either 12 or 4, as select-
ed by the SM2 bit for the associated UART. When set to a logic 0, the serial port runs at a divide-by-12. When set to a logic 1, the ser-
ial port runs at a divide-by-4. The SM2 bit for serial port 0 is located at SCON0.5 and the SM2 bit for serial port 1 is located at SCON1.5.
With the exception of the additional new divide-by-4 selection (supported by SM2), mode 0 operation is identical to the 80C32.
Table 12-1. Serial I/O Modes and Max Baud Rates

SYNC/ 9TH BIT MAX BAUD RATE
MODE BAUD CLOCK† START/STOP DATA BITS
ASYNC FUNCTION SYSCLK = 33MHz
0 Sync 4 or 12 tCLK None 8 None 8,250,000
1 Async Timer 1 or 2* 1 start, 1 stop 8 None 2,062,500
2 Async 32 or 64 tCLK 1 start, 1 stop 9 0, 1, parity 1,031,250
3 Async Timer 1 or 2* 1 start, 1 stop 9 0, 1, parity 2,062,500
†Use of the crystal multiplier or power-management mode affects the baud clock.
*Timer 2 available for serial port 0 only.
107 ____________________________________________________________________________________________
MODE 1
This mode provides standard full-duplex asynchronous communication. A total of 10 bits are transmitted including 1 start bit, 8 data
bits, and 1 stop bit. The received stop bit is stored in bit location RB8 of the relevant SCON register.
In mode 1, the baud rate is a function of timer overflow. This makes the baud rate programmable by the user. One difference that exists
between the two UARTs, with respect to mode 1 configuration, is that serial port 1 can use only timer 1, whereas serial port 0 can use
either timer 1 or 2 to generate baud rates. If both serial ports use the same timer, they run at the same baud rate, or one can run twice
as fast as the other (when baud-rate doubler bits, PCON.7 and WDCON.7, are configured differently). If the two UARTs use different
timers, the baud-rate configurations, in relation to one another, are not as restrictive. Baud rates are discussed in more detail later. Mode
1 operation is identical to the standard 80C32 when timers 1 or 2 use the default oscillator divide-by-12 as an input clock.
MODE 2
This mode is an asynchronous mode that transmits a total of 11 bits. These include 1 start bit, 9 data bits (the ninth data bit being pro-
grammable), and 1 stop bit. The ninth bit is determined by the value in TB8 (SCON0.3 or SCON1.3) for transmission. When the ninth
bit is received, it is stored in RB8 (SCON0.2 or SCON1.2). The ninth bit can be a parity value by moving the P bit (PSW.0) to TB8.
When not using the power-management mode, the baud rate for mode 2 is a function only of the oscillator frequency. It is either the
oscillator input divided by 32 or 64 as programmed by the SMOD doubler bit for the associated UART. The SMOD_0 baud-rate dou-
bler bit for serial port 0 is located at PCON.7, and the SMOD_1 baud-rate doubler bit for serial port 1 is located at WDCON.7. Mode 2
operation is identical to the standard 80C32.
MODE 3
This mode has the same functionality as mode 2, but generates baud rates like mode 1. That is, this mode transmits 11 bits, but gen-
erates baud rates through the timers. Like mode 1, either timer 1 or 2 can be used for serial port 0 and timer 1 can be used for serial
port 1. Mode 3 operation is identical to the standard 80C32 when timers 1 or 2 use the default oscillator divide-by-12 as an input clock.
SERIAL PORT INITIALIZATION
In order to use the UART function(s), the serial port must be initialized. This involves selecting the mode and time base, then initializ-
ing the baud-rate generator, if necessary. Serial communication is then available. Once the baud-rate generator is running, the UART
can receive data.
In mode 0, the high-speed microcontroller provides the clock. Serial reception is initiated by setting the RI bit to a logic 0 and REN to
a logic 1. This generates a clock on the TXD pin and a shift in the 8 bits on the RXD pin. In the other modes, setting the REN bit to a
logic 1 allows serial reception, but the external device must actually initiate it by sending a start bit. In any mode, serial transmission
is initiated by writing to either the SBUF0 or SBUF1 location.
Most of the serial port controls are provided by the SCON0 and SCON1 registers. For convenience, the Table 12-2 is provided, which
summarizes the SFRs controlling serial port operation. Detailed bit descriptions can be found in Section 4.
____________________________________________________________________________________________ 108
Table 12-2. SFR Serial Port Operation Control

SM0/FE_0 Serial mode select 0 or framing error SCON0 – 98h SCON0.7
SM1_0 Serial mode select 1 SCON0 – 98h SCON0.6
SM2_0 Serial mode select 2 SCON0 – 98h SCON0.5
REN_0 Receive enable SCON0 – 98h SCON0.4
TB8_0 9th transmit data bit SCON0 – 98h SCON0.3
SERIAL PORT 0
RB8_0 9th receive data bit SCON0 – 98h SCON0.2

TI_0 Transmit interrupt flag SCON0 – 98h SCON0.1
RI_0 Receive interrupt flag SCON0 – 98h SCON0.0
SMOD_0 Baud-rate doubler bit PCON – 87h PCON.7
RCLK Timer 2 serial receive clock enable T2CON – C8h T2CON.5
TCLK Timer 2 serial transmit clock enable T2CON – C8h T2CON.4
Serial data buffer SBUF0 – 99h
Slave address SADDR0 – A9h
Slave address mask enable SADEN0 – B9h
SM0/FE_1 Serial mode select 0 or framing error SCON1 – C0h SCON1.7

SM1_1 Serial mode select 1 SCON1 – C0h SCON1.6
SM2_1 Serial mode select 2 SCON1 – C0h SCON1.5
REN_1 Receive enable SCON1 – C0h SCON1.4
SERIAL PORT 1
TB8_1 9th transmit data bit SCON1 – C0h SCON1.3

RB8_1 9th receive data bit SCON1 – C0h SCON1.2
TI_1 Transmit interrupt flag SCON1 – C0h SCON1.1
RI_1 Receive interrupt flag SCON1 – C0h SCON1.0
SMOD_1 Baud-rate doubler bit WDCON – D8h WDCON.7
Serial data buffer SBUF1 – C1h
Slave address SADDR1 – AAh
Slave address mask enable SADEN1 – BAh
SMOD0 Enable framing error detection PCON – 87h PCON.6
BAUD RATES
Each mode has a baud-rate generator associated with it. This generator is generally the same for each UART. Several of the baud-rate
generation techniques have options that are independent for the two UARTs. The following baud-rate descriptions are separated by
mode.
Mode 0
Mode 0 is synchronous, so the shift clock output frequency is the baud rate. Table 12-3 summarizes baud-rate generation as a func-
tion of the external oscillator frequency.
The default case is divide-by-12. The user can select the shift clock frequency using the SM2 bit in the associated SCON register. For
serial port 0, the SM2_0 bit is SCON0.5. For serial port 1, the SM2_0 bit is SCON1.5.
When SM2 is set to a logic 0, the baud rate is fixed at a divide-by-12 of the system clock frequency, unless power-management mode
is invoked. When operating in power-management mode, with the SM2 bit clear ( = 0), the serial port clock frequency is the oscillator
frequency divided by 3072.
When SM2 is set to a logic 1, the baud rate is generated using the system clock frequency divided by 4, unless power-management
mode is invoked. When power-management mode is used with the SM2 bit set ( = 1), the serial port clock frequency tracks the sys-
tem clock frequency. Note that this use of SM2 differs from a standard 80C32. In that device, SM2 had no valid use when the UART
was in mode 0. Since it was generally set to a zero, for the divide-by-12, there is no compatibility problem.
109 ____________________________________________________________________________________________
Table 12-3. Mode 0 Serial Port Clock Frequency

MODE 0
PMR REGISTER BITS SERIAL PORT CLOCK FREQUENCY
SYSTEM CLOCK MODE
4X/2X, CD1, CD0
SM2 = 0 SM2 = 1
Crystal multiply mode 4X 100 OSC / 3 OSC / 1
Divide-by-1 (default) X01, X10 OSC / 12 OSC / 4
Power-management mode (/1024) X11 OSC / 3072 OSC / 1024
Mode 2
In this asynchronous mode, baud rates are derived directly from the oscillator input. The following table summarizes baud-rate gener-
ation as a function of the external oscillator frequency. This mode works identically to the original 8051 family.
The default case is divide-by-64. The user can effectively double the serial port clock frequency by setting the SMOD bit to a logic 1
for the associated UART. For serial port 0, the SMOD_0 bit is PCON.7. This is the original location in the 8051 family. For serial port 1,
the SMOD_1 bit is WDCON.7. When operating in the power management mode (CD1:0 = 11b), the serial port clock frequency is the
oscillator frequency divided by 16384 when the SMOD bit is a logic 0 and twice that frequency (OSC/8192) when the SMOD doubler
bit is a logic 1. SMOD bits default to a logic 0 on all resets.
Table 12-4. Mode 2 Serial Port Clock Frequency

MODE 2
PMR REGISTER BITS SERIAL PORT CLOCK FREQUENCY
SYSTEM CLOCK MODE
4X/2X, CD1, CD0
SMOD = 0 SMOD = 1
Divide-by-1 (default) X01, X10 OSC / 64 OSC / 32
Power-management mode (/1024) X11 OSC / 16384 OSC / 8192
Mode 1 or 3
These asynchronous modes are commonly used for communication with PCs, modems, and other similar interfaces. The baud rates
and bit timing are generated using either timer 1 or timer 2. The respective timer is placed in autoreload mode. When the timer reach-
es its rollover condition (FFFFh - timer 2 or FFh - timer 1), a clock is sent to the baud-rate circuit. The baud-rate circuit generates the
exact baud rate by further dividing the clock by 16 or 32 (depending upon the UART baud-rate doubler bit).
For serial port 0, either timer 1 or 2 can be used to generate baud rates. For serial port 1, only timer 1 can be used as the baud-rate
generator. If operated in mode 1 or 3, the two UARTs may both use timer 1 for baud-rate generation, if desired.
Using Timer 1 for Baud-Rate Generation
To use timer 1 as the baud-rate generator, it is commonly put into the 8-bit autoreload mode. In this way, the CPU is not involved in
baud-rate generation. Note that the timer interrupt should not be enabled. In the 8-bit autoreload mode (timer 1, mode 2), the reload
value is stored in TH1. Thus, the combination of timer 1 input clock frequency and TH1 determine the baud rate.
The timer 1 input clock, relative to the external crystal clock, can be altered in two ways: 1) changing the system clock, or 2) chang-
ing the timer input clock divide ratio. Modifying the system clock is accomplished using the clock divide bits (CD1:0) found in the PMR
special function register. This procedure is discussed in Section 5. The timer 1 input clock divide ratio is configurable using the T1M
(CKCON.4) and T1MH (CKMOD.4) register bits. Setting the T1MH bit to a logic 1 results in the system clock being used to clock timer
1. When T1MH is clear ( = 0), setting the T1M bit to a logic 1 provides the system clock divided by 4 input to timer 1. When both T1M
and T1MH are logic 0, the Timer 1 input clock is fixed at the oscillator frequency divided by 12. When using power-management mode,
setting either T1MH or T1M to a logic 1 results in the system clock (OSC/1024) being used as the input clock to timer 1. While, if both
bits are clear ( = 0) in power-management mode, the system clock divided by 3 (OSC/3072) are provided to timer 1. The following
table summarizes the relationship between the external crystal frequency and the timer 1 input clock for the various configurations.
____________________________________________________________________________________________ 110
Table 12-5. Timer 1 Input Clock Frequency

TIMER 1
PMR REGISTER BITS INPUT CLOCK FREQUENCY
SYSTEM CLOCK MODE
4X/2X, CD1, CD0
T1MH,T1M = 00 T1MH,T1M = 01 T1MH,T1M = 1X
Divide-by-1 (default) X01, X10 OSC / 12 OSC / 4 OSC / 1
Power-management mode (/1024) X11 OSC / 3072 OSC / 1024 OSC / 1024
Using timer 1 in the 8-bit autoreload mode, serial port baud rates for mode 1 or 3 can be calculated using the formula below.
2 SMOD_x ✕ Timer 1 input clock frequency

Modes 1, 3 baud rate = 32 (256 - TH1)
Number of serial bits / Timer 1 rollover

Number of timer 1 rollovers frequency
Timer 1 input clock frequency can be found in the previous table, SMOD_x is the logic state of the baud-rate doubler bit for the asso-
ciated UART, and TH1 is the user assigned timer 1 reload value.
Often, users already know what baud rate is desired and only need to calculate the timer reload value. An equation to calculate the
timer reload value, TH1, is as follows:
2 SMOD_x ✕ timer 1 input clock frequency

TH1 = 256 - 32 ✕ baud rate
Note that the 8-bit, autoreload mode for timer 1 is the one most commonly used for serial port applications, but that it can actually be configured in any mode, even as a
counter.
Using Timer 2 for Baud-Rate Generation

To use timer 2 as baud-rate generator for serial port 0, the timer is configured in autoreload mode. Then, either the TCLK or RCLK bit
(or both) are set to a logic 1. TCLK = 1 selects timer 2 as the baud-rate generator for the transmitter and RCLK = 1 selects timer 2 for
the receiver. Thus, serial port 0 can have the transmitter and receiver operating at different baud rates by choosing timer 1 for one data
direction and timer 2 for the other. RCLK and TCLK reside in T2CON.4 and TCON.5, respectively.
Although the timer 2 input clock can be configured similarly to timer 1, it must be placed into a baud-rate generator mode in order to
be used by serial port 0. Setting either RCLK or TCLK to a logic 1 selects timer 2 for baud-rate generation. When this is done, the timer
2 input clock becomes fixed to the oscillator frequency divided by 2. This is compatible with the 80C32. The only exception is when
timer 2 is used for baud-rate generation within power-management mode. For PMM, the system clock (OSC/1024) is used as the input
clock for timer 2. The timer 2 interrupt is automatically disabled when either RCLK or TCLK is set. Also, the TF2 (TCON.7) flag is not
set on a timer rollover. The manual reload pin, T2EX (P1.1), does not cause a reload either. Table 12-6 illustrates this relationship.
Table 12-6. Timer 2 Baud-Rate Generation

TIMER 2 INPUT CLOCK FREQUENCY
PMR REGISTER BITS
SYSTEM CLOCK MODE BAUD-RATE GENERATOR MODE
4X/2X, CD1, CD0
(RCLK OR TCLK = 1)
Divide-by-1 (default) X01, X10 OSC / 2
Power-management mode (/1024) X11 OSC / 1024
111 ____________________________________________________________________________________________
When using timer 2 to generate baud rates, the formula is as follows. Note that the reload value is a 16-bit number, as compared with
timer 1, which uses only 8 bits. A second equation is provided so that the timer 2 reload value can be calculated for a given baud rate.
1 ✕
Timer 2 input clock frequency
Modes 1, 3 baud rate = 16 (65536–RCAP2H,RCAP2L)
Number of serial bits / Timer 2 rollover

Number of timer 2 rollovers frequency
Timer 2 input clock frequency

RCAP2H, RCAP2L = 65536 –
16 ✕ baud rate
Timer 2 input clock frequency can be found in Table 12-6, and RCAP2H, RCAP2L is the user assigned timer 2 reload value.
SERIAL I/O DESCRIPTION
A detailed description and block diagram of each serial mode is given below. Note that the baud clock input (to the serial I/O control
block) corresponding to the power-management mode has been omitted from each of the block diagrams. Reference the tables ear-
lier in this section for power-management mode baud clock rates. A description of framing-error detection and multiprocessor com-
munication follows this section.
Mode 0
Mode 0 is used to communicate in synchronous, half-duplex format with devices that accept the ultra-high-speed microcontroller as a
master. Figure 12-1 shows a functional block diagram and basic timing of this mode. As can be seen, there is one bidirectional data
line (RXD) and one shift clock line (TXD) used for communication. The shift clock is used to shift data into and out of the microcon-
troller and the remote device. Mode 0 requires that the microcontroller is the master, because the microcontroller generates the serial
shift clocks for both directions. As described earlier in the section, the shift clock frequency is a function of the system clock if the SM2
(SCON0.5 or SCON1.5) bit is set to a logic 1.
The RXD signal is used for both transmission and reception. TXD provides the shift clock. Data bits enter and exit least-significant bit
(LSb) first. The baud rate is equal to the shift clock frequency. The relevant UART begins transmitting when any instruction writes to
SBUF0 or SBUF1 (address 99h or C1h). The internal shift register then begins to shift data out. The clock is activated and transfers
data until the 8-bit value is complete. Data is presented just prior to the falling edge of the shift clock (TXD) so that an external device
can latch the data using the rising edge.
The UART begins to receive data when the REN bit in the SCON register (SCON0.4 or SCON1.4) is set to a logic 1 and the RI bit
(SCON0.0 or SCON1.0) is set to a logic 0. This condition tells the UART that there is data to be shifted in. The shift clock (TXD) acti-
vates, and the UART latches incoming data on the rising edge. The external device should therefore present data on the falling edge.
This process continues until 8 bits have been received. The RI bit is automatically set to a logic 1 immediately following the last rising
edge of the shift clock on TXD. This causes reception to stop until the SBUF has been read, and the RI bit cleared. When RI is cleared,
another byte can be shifted in.
____________________________________________________________________________________________ 112
SBUF
OUTPUT SHIFT REGISTER
SYSTEM CLOCK P3.0
CLOCK
RXD
S0
LOAD
LATCH PIN
D7
D6
D5
D4
D3
D2
D1
D0
DIVIDE- DIVIDE-
BY-12 BY-4
0 1
SM2= DATA BUS

SM2=
SCONx.5 LDSBUF
SCONx.5
RDSBUF
LOAD SHIFT
SERIAL READ
SERIAL I/O
CONTROL
BUFFER SERIAL RD RECEIVE DATA BUFFER WR

BUFFER
BAUD
CLOCK
RECEIVE
BUFFER
INTS
DATA LOAD
CLOCK
CLOCK
D7
D6
D5
D4
D3
D2
D1
D0
T1 R1
FLAG = FLAG =
SCONx.1 SCONx.0 SI
RECEIVE SHIFT REGISTER
SERIAL
INTERRUPT
TXD
PIN
TRANSMIT TIMING
LDSBUF WRITE TO SBUF
SHIFT
RXD
D0 D1 D2 D3 D4 D5 D6 D7
(DATA OUT)
TXD
(DATA CLOCK)
TI
RECEIVE TIMING
RDSBUF WRITE TO SCON (CLEAR RI)
SHIFT
RXD
(DATA IN) D0 D1 D2 D3 D4 D5 D6 D7
TXD
(DATA CLOCK)
RI
Figure 12-1. Serial Port Mode 0
113 ____________________________________________________________________________________________
Mode 1
Mode 1 is asynchronous and full duplex, using a total of 10 bits. The 10 bits consist of a start bit (logic 0), 8 data bits, and 1 stop bit
(logic 1) as illustrated in Figure 12-2. The data is transferred LSb first. As described above, the baud rates for mode 1 are generated
by either a divide-by-16 of timer 1 rollover, a divide-by-16 of the timer 2 rollover, or a divide-by-32 of timer 1 rollover. The UART begins
transmission after the first rollover of the divide-by-16 counter following a software write to SBUF. Transmission takes place on the TXD
pin. It begins by the start bit being placed on the pin. Data is then shifted out onto the pin, LSb first. The stop bit follows. The TI bit is
set by hardware after the stop bit is placed on the pin. All bits are shifted out at the rate determined by the baud-rate generator.
Once the baud-rate generator is active, reception can begin at any time. The REN bit (SCON0.4 or SCON1.4) must be set to a logic 1
to allow reception. The falling edge of a start bit on the RXD pin begins the reception process. Data is shifted in at the selected baud
rate. At the middle of the stop bit time, certain conditions must be met to load SBUF with the received data:
• RI must = 0, and either
• If SM2 = 0, the state of the stop bit does not matter, or
• If SM2 = 1, the state of the stop bit must = 1.
If these conditions are true, then SBUF (hex address 99h or C1h) is loaded with the received byte, the RB8 bit (SCON0.2 or SCON1.2)
is loaded with the stop bit, and the RI bit (SCON0.0 or SCON1.0) is set. If these conditions are false, then the received data is lost
(SBUF and RB8 not loaded) and RI is not set. Regardless of the receive word status, after the middle of the stop bit time, the receiver
goes back to looking for a 1 to 0 transition on the RXD pin.
Each data bit received is sampled on the 7th, 8th, and 9th clock used by the divide-by-16 counter. Using majority voting, two equal
samples out of the three determine the logic level for each received bit. If the start bit was determined to be invalid ( = 1), then the
receiver goes back to looking for a 1 to 0 transition on the RXD pin in order to start the reception of data.
Mode 2
Mode 2 uses a total of 11 bits in asynchronous full-duplex communication, as illustrated in Figure 12-3. The 11 bits consist of 1 start
bit (a logic 0), 8 data bits, 1 programmable 9th bit, and one stop bit (a logic 1). Like mode 1, the transmissions occur on the TXD sig-
nal pin and receptions on RXD. For transmission purposes, the 9th bit can be stuffed as a logic 0 or 1. A common use is to put the par-
ity bit in this location. The 9th bit is transferred from the TB8 bit position in the SCON register (SCON0.3 or SCON1.3) during the write
to SBUF. Baud rates are generated as a fixed function of the crystal frequency, as described earlier in this section. Like mode 1, mode
2’s transmission begins after the first rollover of the divide-by-16 counter following a software write to SBUF. It begins by the start bit
being placed on the TXD pin. The data is then shifted out onto the pin LSb first, followed by the 9th bit, and finally the stop bit. The TI
bit (SCON0.1 or SCON1.1) is set when the stop bit is placed on the pin.
Reception begins when a falling edge is detected as part of the incoming start bit on the RXD pin. The RXD pin is then sampled accord-
ing to the baud-rate speed. The 9th bit is placed in the RB8 bit location in SCON (SCON0.2 or SCON1.2). When a stop bit has been
received, the data value is transferred to the SBUF receive register (hex address 99 or C1). The RI bit (SCON0.0 or SCON1.0) is set to
indicate that a byte has been received. At this time, the UART can receive another byte.
Once the baud-rate generator is active, reception can begin at any time. The REN bit (SCON0.4 or SCON1.4) must be set to a logic 1
to allow reception. The falling edge of a start bit on the RXD pin begins the reception process. Data must be shifted in at the selected
baud rate. At the middle of the 9th bit time, certain conditions must be met to load SBUF with the received data.
• RI must = 0, and either
• If SM2 = 0, the state of the 9th bit does not matter, or
• If SM2 = 1, the state of the 9th bit must = 1.
If these conditions are true, then SBUF is loaded with the received byte, RB8 is loaded with the 9th bit, and RI is set. If these condi-
tions are false, then the received data is lost (SBUF and RB8 not loaded) and RI is set. Regardless of the receive word status, after the
middle of the stop bit time, the receiver goes back to looking for a 1 to 0 transition on RXD.
Data is sampled in a similar fashion to mode 1 with the majority voting on three consecutive samples. Mode 2 uses the sample divide-
by-16 counter with either the oscillator divided by 2 or 4.
____________________________________________________________________________________________ 114
SBUF
TRANSMIT SHIFT REGISTER
TIMER 2 P3.1 TXD
CLOCK
S0
START
TIMER 1 OVERFLOW LATCH PIN
LOAD
STOP
OVERFLOW
D7
D6
D5
D4
D3
D2
D1
D0
AVAILABLE TO SERIAL
1 0
DIVIDE-
PORT 0 ONLY
BY-2
SMOD_0 =
PCON.7 0 1
OR
SMOD_1 = DATA BUS
WDCON.7 LDSBUF
RDSBUF
0 1
TCLK = LOAD SHIFT
T2CON.4 SBUF
SERIAL
READ
SERIAL I/O
BUFFER CONTROL RD RECEIVE DATA BUFFER WR
SERIAL
DIVIDE- BUFFER
BAUD
RCLK = BY-16
CLOCK
T2CON.5 0 1 LOAD
RESET
RB8 =
INTS
SCONx.2
T1 R1
START
CLOCK
FLAG = FLAG = STOP
D7
D6
D5
D4
D3
D2
D1
D0
SCONx.1 SCONx.0
SI
SERIAL
INTERRUPT RECEIVE SHIFT REGISTER
DIVIDE- BIT RXD

BY-16 DETECTION PIN
TRANSMIT TIMING
LDSBUF
SHIFT
TXD
START D0 D1 D2 D3 D4 D5 D6 D7 STOP
TI
RECEIVE TIMING
RXD
START D0 D1 D2 D3 D4 D5 D6 D7 STOP
BIT DETECTOR
SAMPLING
SHIFT
RI
115 ____________________________________________________________________________________________
SBUF
P3.1 TXD
CLOCK
S0
START
OSC/2 = LATCH PIN
LOAD
STOP
CRYSTAL/2
D8
D7
D6
D5
D4
D3
D2
D1
D0
1 0
DIVIDE-
BY-2
SMOD_0 = TB8 =
PCON.7 0 1 SCONx.3
OR
SMOD_1 =
DATA BUS
WDCON.7 LDSBUF
RDSBUF
LOAD SHIFT
SBUF
SERIAL
READ
BUFFER RD RECEIVE DATA BUFFER WR
SERIAL
SERIAL I/O
CONTROL
DIVIDE- SHIFT BUFFER
BY-16 CLOCK
LOAD
RESET
RB8 =
INTS
SCONx.2
T1 R1
START
STOP
CLOCK
FLAG = FLAG =
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCONx.1 SCONx.0
SI
SERIAL
DIVIDE- BIT RXD

BY-16 DETECTION PIN
TRANSMIT TIMING
LDSBUF
SHIFT
TXD
START D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP
TI
RECEIVE TIMING
RXD
START D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP
BIT DETECTOR
SAMPLING
SHIFT
RI
____________________________________________________________________________________________ 116
Mode 3
Mode 3 has the same operation as mode 2, except for the baud-rate source. As shown in Figure 12-4, mode 3 can use timer 1 or 2 for
serial port 0 and timer 1 for serial port 1. The bit shifting and protocol are the same.
SBUF
TIMER 2 P3.1 TXD
CLOCK
S0
START
TIMER 1 OVERFLOW LATCH PIN
LOAD
STOP
OVERFLOW
D8
D7
D6
D5
D4
D3
D2
D1
D0
AVAILABLE TO SERIAL
1 0
DIVIDE-
PORT 0 ONLY
BY-2
TB8 =
SMOD_0 =
PCON.7 0 1 SCONx.3
OR
SMOD_1 =
DATA BUS
WDCON.7 LDSBUF
RDSBUF
0 1
TCLK = LOAD SHIFT
T2CON.4 SBUF
SERIAL
READ
SERIAL I/O
BUFFER
CONTROL
SERIAL RD RECEIVE DATA BUFFER WR

DIVIDE- BUFFER
BAUD
RCLK = BY-16
CLOCK
T2CON.5 0 1 LOAD
RESET
RB8 =
INTS
SCONx.3
T1 R1
START
CLOCK
STOP
FLAG = FLAG =
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCONx.1 SCONx.0
SI
SERIAL
DIVIDE- BIT RXD

BY-16 DETECTION PIN
TRANSMIT TIMING
LDSBUF
SHIFT
TXD
START D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP
TI
RECEIVE TIMING
RXD
START D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP
BIT DETECTOR
SAMPLING
SHIFT
RI
117 ____________________________________________________________________________________________
FRAMING ERROR DETECTION

A framing error occurs when a valid stop bit is not detected. This results in the possible improper reception of the serial word. The
UART can detect a framing error and notify the software. Typical causes of framing errors are noise and contention. The framing error
condition is reported in the SCON register for the corresponding UART.
The framing error bit, FE, is located in SCON0.7 or SCON1.7. Note that this bit normally serves as SM0 and is described as SM0/FE_0
or SM0/FE_1 in the register description. Framing error information is made accessible by the SMOD0 framing error detection enable
bit located at PCON.6. When SMOD0 is set to a logic 1, the framing error information is shown in SM0/FE (SCON0.7 or SCON1.7).
When SMOD0 is set to a logic 0, the SM0 function is accessible. The information for bits SM0 and FE is actually stored in different reg-
isters. Changing SMOD0 only modifies which register is accessed; not the contents of either.
The FE bit is set to a 1 when a framing error occurs. It must be cleared by software. Note that the SMOD0 state must be 1 while read-
ing or writing the FE bit. Also note that receiving a properly framed serial word does not clear the FE bit. This must be done in software.
MULTIPROCESSOR COMMUNICATION
The multiprocessor communication mode makes special use of the 9th data bit in modes 2 and 3. In the original 8051, the 9th bit was
restricted to a 0 or 1 condition, but had no special purpose. In the 80C32 and the ultra-high-speed microcontroller, it can be used to
signify that the incoming byte is an address. This allows the processor to be interrupted only if the correct address appears. If the mul-
tiprocessor mode has been enabled, the receive interrupt (signaled by the RI bit) only occurs when a recognized address is received.
When a serial word is received with the 9th bit set and the appropriate SM2 = 1, the byte is assumed to be an address. The address
is compared to an internally stored address. If it matches, a receive interrupt occurs. The internal address is derived from the contents
of two registers. The first register specifies an absolute address. This is the user-specified address of the device. The second register
is a bit-masking register that tells the comparator which address bit(s) to actually use in the comparison. This allows broadcast trans-
missions that reach groups of microcontrollers or all microcontrollers on a serial port. The user defines this protocol.
There are two special function registers that support multiprocessor communication for each UART. These are independent, so that dif-
ferent addresses can be used in each. The registers are SADDR0 or SADDR1 (hex address A9h or AAh) and SADEN0 or SADEN1 (hex
address B9h or BAh). The SADDR register specifies the individual processor’s address. The SADEN identifies address bits that should
be ignored in matching addresses.
Software writes an 8-bit address to the SADDR register. This is the microcontroller’s individual address. Any bit in SADEN that contains
a logic 0 causes the corresponding bit in SADDR to be ignored in comparison. Thus, logic 0 bits in SADEN create “don’t care” bit states
for address comparisons.
When an address is received, each address bit that is not masked by a “don’t care” is compared to the SADDR. The microcontroller
interrupts on any address that matches this comparison. Any address that meets this comparison is called a given address.
The following example shows how one address can be directed to an individual processor, or two out of three:
Micro 1
SADDR 11110000
SADEN 11111010
–––––––––––––––––––––––––
Given 11110x0x
Micro 2
SADDR 11110001
SADEN 11111001
–––––––––––––––––––––––––
Given 11110xx1
Micro 3
SADDR 11110010
SADEN 11111010
–––––––––––––––––––––––––
Given 11110x1x
Note that an address of 11110000 reaches only microcontroller 1. An address of 11110001 reaches both microcontroller 1 and micro-
controller 2. An address of 11110010 reaches only microcontroller 3.
____________________________________________________________________________________________ 118
The microcontroller also matches on any address that corresponds to the broadcast address. This is the logical OR of the SADDR and
SADEN registers, with any zeros defined as don’t cares. In most cases, the broadcast address is FFh.
The multiprocessor communication is always enabled. However, the SADEN registers default to 00h, which means all address bits are
“don’t care,” so all match. Thus, if no multiprocessor communication is used, these registers can be ignored.
SECTION 13: TIMED-ACCESS PROTECTION

The ultra-high-speed microcontroller uses a protection feature called timed access to prevent accidental writes to critical SFR bits.
These bits could cause a system failure or prevent the watchdog timer from doing its job if improperly written. The timed access
involves opening a timing window during which the protected bit can be modified. If the window is opened correctly, it remains open
long enough to alter one protected register. This section explains which bits are protected, why, and how to use the timed-access fea-
ture.
PROTECTED BITS
Bits that are protected by the timed-access feature are shown below. Only critical function bits unique to the ultra-high-speed micro-
controller are protected, ensuring code compatibility with the original 80C51 or 80C52. A full description of the function of each bit is
provided in Section 4:
WDCON.0 RWT Reset watchdog timer
WDCON.1 EWT Watchdog reset enable
WDCON.3 WDIF Watchdog interrupt flag
WDCON.6 POR Power-on reset flag
EXIF.0 BGS Bandgap select
ACON.5 PAGES0 Page mode select bit 0
ACON.6 PAGES1 Page mode select bit 1
ACON.7 PAGEE Page mode enable
ROMSIZE.0 RMS0 Program memory size select bit 0
ROMSIZE.3 RMS3 Program RAM enable
FCNTL.0 FC0 Flash command bit 0
PROTECTION SCHEME
Each bit mentioned above is protected against an accidental write by requiring the software to perform a procedure before writing the
bit. Timed access requires the software to write two specific values to the timed-access register during two consecutive instruction
cycles. The values AAh, then 55h, must be written in consecutive instructions to the TA register at SFR location C7h. If the writes are
performed correctly, the write-access window opens for three memory cycles. During this window, the software may modify a protect-
ed bit. The suggested code to open a timed-access window is:
MOV 0C7h, #0AAh
MOV 0C7h, #55h
The procedure to modify a timed-access-protected bit begins by writing the value AAh to the timed-access register (TA;C7h). The value
55h must then be written to the timed-access register within three memory cycles of writing AAh. This opens a three memory-cycle win-
dow, after the write of 55h, during which any timed-access protected bits may be modified. Failure to complete any of the required
steps also requires the procedure to begin again, starting with the write of AAh to the timed-access register. Attempts to modify timed-
access-protected bits after the window has closed are ignored. This is regardless of whether any bits were modified. Figure 13-1 illus-
trates a number of examples of correct and incorrect use of the timed-access procedure.
119 ____________________________________________________________________________________________
VALID TIMED-ACCESS PROCEDURES

Three Memory Cycles Three Memory Cycles Three Memory Cycles
MOV 0C7h, #0AAh MOV 0C7h, #55h SETB EWT
Three Memory Cycles Three Memory Cycles One Memory Cycle Two Memory Cycles
MOV 0C7h, #0AAh MOV 0C7h, #55h NOP SETB EWT
Three Memory Cycles Three Memory Cycles Three Memory Cycles

MOV 0C7h, #0AAh MOV 0C7h, #55h MOV WDCON, #02h
INVALID TIMED-ACCESS PROCEDURES

Three Memory Cycles One Memory Cycle Three Memory Cycles Two Memory Cycles
MOV 0C7h, #0AAh NOP MOV 0C7h, #55H SETB EWT
*Second write to TA register does not occur within 3 cycles of first write.
Three Memory Cycles Three Memory Cycles One Memory Cycle Three Memory Cycles
MOV 0C7h, #0AAh MOV 0C7h, #55H NOP MOV WDCON, #02h
*Modification of protected bit did not occur with 3 cycles of second write to TA register.
Three Memory Cycles Three Memory Cycles Two Memory Cycles Two Memory Cycles
MOV 0C7h, #0AAh MOV 0C7h, #55h SETB EWT SETB EWT
*Modification of second protected bit did not complete within 3 cycles of second write to
TA register.
Figure 13-1. Timed-Access Examples
TIMED-ACCESS PROTECTS WATCHDOG

Any microcontroller-based system can be faced with environmental conditions that are beyond its designed abilities. These include
external signal transients due to component failure, fluctuating power conditions, massive electrostatic discharge (ESD), and other
unexpected system events. When a microcontroller is exposed to such conditions, program execution can become corrupted. The
ultra-high-speed microcontroller incorporates a watchdog timer that can initiate a reset to recover from these conditions. The primary
function of the timed-access feature is to protect against accidental disabling of the watchdog timer by an “out-of-control” device. This
allows the watchdog timer to reset the system in the event of program execution failure.
The following hypothetical example demonstrates how a single bit change can corrupt program execution. The timed-access proce-
dure protects against an accidental write to the EWT bit by the errant code, allowing the watchdog timer reset function to reset the
device. While this is a purely fictitious example, it illustrates how the watchdog timer and timed-access feature allow the ultra-high-
speed microcontroller to minimize the effect of accidental code corruption. Note: Timed access is not optional and must be support-
ed if the protected bits are used. This example helps explain the category of problem that the timed access prevents.
EXAMPLE: A TRANSIENT CAUSES THE WATCHDOG TO BE DISABLED:
TABLE_READ:
C2D2 90 0A 00 MOV DPTR, 0A00H ;LOAD TABLE POINTER
C2D5 79 FF MOV R1, #0FFH ;LOAD COUNTER
C2D7 78 90 MOV R0, #90H ;DESTINATION POINTER
LOOP:
C2D9 E0 MOVX A, @DPTR ;READ DATA BYTE
C2DA F6 MOV @R0, A ;STORE IT IN RAM
C2DB 06 INC R0 ;NEXT TABLE LOCATION
C2DC A3 INC DPTR ;NEXT DATA VALUE
C2DD D9 C2 D9 DJNZ R1, LOOP ;NEXT BYTE OR DONE ?
____________________________________________________________________________________________ 120
A transient occurs while the op code is being fetched for the first instruction. The transient causes 1 bit of the op code in the first instruc-
tion to be read as a 0 instead of 1. The resulting program is what the microcontroller would actually execute:
TABLE_READ:
C2D2 80 0A 00 SJMP 0BH ;RELATIVE JUMP BY 10 LOCATIONS
C2D5 79 FF MOV R1, #0FFH ;LOAD COUNTER
C2D7 78 90 MOV R0, #90H ;DESTINATION POINTER
LOOP:
C2D9 E0 MOVX A, @DPTR ;READ DATA BYTE
C2DA F6 MOV @R0, A ;STORE IT IN RAM
C2DB 06 INC R0 ;NEXT TABLE LOCATION
C2DC A3 INC DPTR ;NEXT DATA VALUE
C2DD D9 C2 D9 DJNZ R1, LOOP ;NEXT BYTE OR DONE ?
The resulting jump is to address C2DE. This is not even a real op code, but would be treated as such. The resulting fetch is the value
C2 D9. This is the op code for CLR D9h. The bit-addressable location D9h corresponds to the EWT. If the timed-access procedure did
not prevent it, this errant instruction would disable the watchdog. Note that the program execution is completely lost now. Real op
codes are being replaced by operands, data, and garbage. In the ultra-high-speed microcontroller, the watchdog recovers from this
state as soon as it times out, since it could not have been disabled in this way.
In the ultra-high-speed microcontroller it is very hard to contrive a situation that accidentally disables the watchdog. Note, the timed
access prevents accidentally writing a bit. It can not prevent accidentally calling the correct code that writes a bit. This is much more
unlikely, however.
SECTION 14: INSTRUCTION SET DETAILS

Details of flags modified by each instruction are located in Section 4.
INSTRUCTION CODE
MNEMONIC D7 D6 D5 D4 D3 D2 D1 D0 HEX BYTE CYCLE EXPLANATION
ADD A, Rn 0 0 1 0 1 n2 n1 n0 28-2F 1 1 (A) = (A) + (Rn)
0 0 1 0 0 1 0 1 25
ADD A, direct 2 2 (A) = (A) + (direct)
a7 a6 a5 a4 a3 a2 a1 a0 Byte 2
ADD A, @Ri 0 0 1 0 0 1 1 i 26-27 1 2 (A) = (A) + ((Ri))
0 0 1 0 0 1 0 0 24
ADD A, #data 2 2 (A) = (A) + #data
d7 d6 d5 d4 d3 d2 d1 d0 Byte 2
ADDC A, Rn 0 0 1 1 1 n2 n1 n0 38-3F 1 1 (A) = (A) + (C) + (Rn)
ADDC A, 0 0 1 1 0 1 0 1 35
2 2 (A) = (A) + (C) + (direct)
direct a7 a6 a5 a4 a3 a2 a1 a0 Byte 2
ADDC A, @Ri 0 0 1 1 0 1 1 i 36-37 1 2 (A) = (A) + (C) + ((Ri))
0 0 1 1 0 1 0 0 34
ADDC A,#data 2 2 (A) = (A) + (C) + #data
ARITHMETIC OPERATION
SUBB A, Rn 1 0 0 1 1 n2 n1 n0 98-9F 1 1 (A) = (A) - (C) - (Rn)
1 0 0 1 0 1 0 1 95
SUBB A, direct 2 2 (A) = (A) - (C) - (direct)
SUBB A, @Ri 1 0 0 1 0 1 1 i 96-97 1 2 (A) = (A) - (C) - ((Ri))
1 0 0 1 0 1 0 0 94
SUBB A, #data 2 2 (A) = (A) - (C) - #data
INC A 0 0 0 0 0 1 0 0 04 1 1 (A) = (A) + 1
INC Rn 0 0 0 0 1 n2 n1 n0 08-0F 1 1 (Rn) = (Rn) + 1
0 0 0 0 0 1 0 1 05
INC direct 2 2* (direct) = (direct) + 1
INC @Ri 0 0 0 0 0 1 1 i 06-07 1 2 ((Ri)) = ((Ri)) + 1
INC DPTR 1 0 1 0 0 0 1 1 A3 1 1 (DPTR) = (DPTR) + 1
DEC A 0 0 0 1 0 1 0 0 14 1 1 (A) = (A) - 1
DEC Rn 0 0 0 1 1 n2 n1 n0 18-1F 1 1 (Rn) = (Rn) - 1
0 0 0 1 0 1 0 1 15
DEC direct 2 2* (direct) = (direct) -1
DEC @Ri 0 0 0 1 0 1 1 i 16-17 1 2 ((Ri)) = ((Ri)) - 1
MUL AB 1 0 1 0 0 1 0 0 A4 1 9 (B15–8 ), (A7–0 ) = (A) x (B)
DIV AB 1 0 0 0 0 1 0 0 84 1 10 (A15–8 ), (A7–0 ) = (A) / (B)
121 ____________________________________________________________________________________________
INSTRUCTION CODE
Contents of accumulator are BCD,
ARITHMETIC OPER
IF [[(A3-0 ) > 9] OR
[(AC) = 1]] THEN
(A3-0 ) = (A3-0 ) + 6
DA A
1 1 0 1 0 1 0 0 D4 1 2 AND
IF [[(A7-4 ) > 9] OR
[(C) = 1]] THEN
(A7-4 ) = (A7-4 ) + 6
ANL A, Rn 0 1 0 1 1 n2 n1 n0 58-5F 1 1 (A) = (A) AND (Rn)

0 1 0 1 0 1 0 i 55
ANL A, direct 2 2 (A) = (A) AND (direct)
ANL A, @Ri 0 1 0 1 0 1 1 i 56-57 1 2 (A) = (A) AND ((Ri))
0 1 0 1 0 1 0 0 54
ANL A, #data 2 2 (A) = (A) AND #data
0 1 0 1 0 0 1 0 52 (direct) =
ANL direct, A 2 2*
a7 a6 a5 a4 a3 a2 a1 a0 Byte 2 (direct) AND A
0 1 0 1 0 0 1 1 53
ANL direct, (direct) =
a7 a6 a5 a4 a3 a2 a1 a0 Byte 2 3 3
#data (direct) AND #data
ORL A, Rn 0 1 0 0 1 n2 n1 n0 48-4F 1 1 (A) = (A) OR (Rn)
0 1 0 0 0 1 1 I 45 (A) =
ORL A, direct 2 2
a7 a6 a5 a4 a3 a2 a1 a0 Byte 2 (A) OR (direct)
LOGICAL OPERATION
ORL A, @Ri 0 1 0 0 0 1 1 i 46-47 1 2 (A) = (A) OR ((Ri))

0 1 0 0 0 1 0 0 44
ORL A, #data 2 2 (A) = (A) OR #data
42 (direct) =
ORL direct, A 0 1 0 0 0 0 1 0 2 2*
Byte 2 (direct) OR (A)
0 1 0 0 0 0 1 1 43
(direct) =
ORL direct, #data a7 a6 a5 a4 a3 a2 a1 a0 Byte 2 3 3
(direct) OR #data
XRL A, Rn 0 1 1 0 1 n2 n1 n0 68-6F 1 1 (A) = (A) XOR (Rn)
0 1 1 0 0 1 0 1 65 (A) =
XRL A, direct 2 2
a7 a6 a5 a4 a3 a2 a1 a0 Byte 2 (A) XOR (direct)
XRL A, @ Ri 0 1 1 0 0 1 1 i 66-67 1 2 (A) = (A) XOR ((Ri))
64 (direct) =
XRL A, #data 0 1 1 0 0 1 0 0 2 2
Byte 2 (A) XOR #data
62 (direct) =
XRL direct, A 0 1 1 0 0 0 1 0 2 2*
Byte 2 (direct) XOR (A)
0 1 1 0 0 0 1 63
XRL direct, 1 (direct) =
a7 a6 a5 a4 a3 a2 a0 Byte 2 3 3
#data a1d1 (direct) XOR #data
d7 d6 d5 d4 d3 d2 d0 Byte 3
CLR A 1 1 1 0 0 1 0 0 E4 1 1 (A) = 0
CPL A 1 1 1 1 0 1 0 0 F4 1 1 (A) = (A)
____________________________________________________________________________________________ 122
INSTRUCTION CODE
RL A
0 0 1 0 0 0 1 1 23 1 1 A7 A6 A5 A4 A3 A2 A1 A0
The contents of the accumulator are
rotated left by 1 bit.
RLC A
0 0 1 1 0 0 1 1 33 1 1
C A7 A6 A5 A4 A3 A 2 A1 A0
LOGICAL OPERATION

rotated right by 1 bit.
RR A 0 0 0 0 0 0 1 1 03 1 1 A7 A6 A5 A4 A3 A 2 A0 A1
RRC A 0 0 0 1 0 0 1 1 13 1 1
C A7 A6 A5 A4 A3 A2 A0 A1

SWAP A 1 1 0 0 0 1 0 0 C4 1 1 (A3-0 ) _ (A7-4 )
MOV A, Rn 1 1 1 0 1 n2 n1 n0 E8-EF 1 1 (A) = (Rn)
1 1 1 0 0 1 0 1 E5
MOV A, direct 2 2 (A) = (direct)
MOV A, @Ri 1 1 1 0 0 1 1 i E6-E7 1 2 (A) = ((Ri))
0 1 1 1 0 1 0 0 74
MOV A, #data 2 2 (A) = #data
MOV Rn, A 1 1 1 1 1 n2 n1 n0 F8-FF 1 1 (Rn) = (A)
DATA TRANSFER
MOV Rn, 1 0 1 0 1 n2 n1 n0 A8-AF

2 2 (Rn) = (direct)
MOV Rn, 0 1 1 1 1 n2 n1 n0 78-7F
2 2 (Rn) = #data
#data d7 d6 d5 d4 d3 d2 d1 d0 Byte 2
1 1 1 1 0 1 0 1 F5
MOV direct, A 2 2* (direct) = (A)
MOV direct, 1 0 0 0 1 n2 n1 n0 88-8F
2 2* (direct) = (Rn)
Rn a7 a6 a5 a4 a3 a2 a1 a0 Byte 2
1 0 0 0 0 1 0 1 85 (direct1) = (direct2)
MOVdirect1,
a7 a6 a5 a4 a3 a2 a1 a0 Byte 2 3 3* (source)
direct2
a7 a6 a5 a4 a3 a2 a1 a0 Byte 3 (destination)
MOV direct, 1 0 0 0 0 1 1 i 86-87
2 2* (direct) = ((Ri))
@Ri a7 a6 a5 a4 a3 a2 a1 a0 Byte 2
123 ____________________________________________________________________________________________
INSTRUCTION CODE
0 1 1 1 0 1 0 1 75
MOV direct,
a7 a6 a5 a4 a3 a2 a1 a0 Byte 2 3 3 (direct) = #data
#data
MOV @Ri, A 1 1 1 1 0 1 1 i F6-F7 1 1 ((Ri)) = A
MOV @Ri, 1 0 1 0 0 1 1 i A6-A7
2 2 ((Ri)) = (direct)
MOV @Ri, 0 1 1 1 0 1 1 i 76-77
2 2 ((Ri)) = #data
#data d7 d6 d5 d4 d3 d2 d1 d0 Byte 2
1 0 0 1 0 0 0 0 90 (DPTR) = #data15-0
MOV DPTR,
d7 d6 d5 d4 d3 d2 d1 d0 Byte 2 3 3 (DPH) = #data15-8
#data16
d7 d6 d5 d4 d3 d2 d1 d0 Byte 3 (DPL) = #data7-0
MOVC A, @A +
DATA TRANSFER
1 0 0 1 0 0 1 1 93 1 3 (A) = ((A) + (DPTR))

DPTR
MOVC A, @A + PC 1 0 0 0 0 0 1 1 83 1 3 (A) = ((A) + (PC))
MOVX A, @Ri 1 1 1 0 0 0 1 i E2-E3 1 2 (A) = ((Ri))
MOVX
1 1 1 0 0 0 0 0 E0 1 2 (A) = ((DPTR))
@DPTR
MOVX @Ri, A 1 1 1 1 0 0 1 i F2-F3 1 2 ((Ri)) = (A)
MOVX
1 1 1 1 0 0 0 0 F0 1 2 ((DPTR)) = (A)
@DPTR,A
1 1 0 0 0 0 0 0 C0 (SP) = (SP) + 1
PUSH direct 2 2
a7 a6 a5 a4 a3 a2 a1 a0 Byte 2 ((SP)) = (direct)
1 1 0 1 0 0 0 0 D0 (direct) = ((SP))
POP direct 2 2*
a7 a6 a5 a4 a3 a2 a1 a0 Byte 2 (SP) = (SP) - 1
XCH A, Rn 1 1 0 0 1 n2 n1 n0 C8-CF 1 2 (A) = (Rn)
1 1 0 0 0 1 0 1 C5
XCH A, direct 2 3 (A) = (direct)
XCH A, @Ri 1 1 0 0 0 1 1 i C6-C7 1 3 (A) = ((Ri))
XCHD A, @Ri 1 1 0 1 0 1 1 i D6-D7 1 3 (A3-0) = ((Ri3-0 ))
INSTRUCTION CODE
CLR C 1 1 0 0 0 0 1 1 C3 1 1 (C) = 0
1 1 0 0 0 0 1 0 C2
CLR bit 2 2* (bit) = 0
b7 b6 b5 b4 b3 b2 b1 b0 Byte 2
BOOLEAN VARIABLE MANIPULATION
SETB C 1 1 0 1 0 0 1 1 D3 1 1 (C) = 1
1 1 0 1 0 0 1 0 D2
SETB bit 2 2* (bit) = 1
CPL C 1 0 1 1 0 0 1 1 B3 1 1 (C) = (C)
1 0 1 1 0 0 1 0 B2
CPL bit 2 2* (bit) = (bit)
1 0 0 0 0 0 1 0 82
ANL C, bit 2 2 (C) = (C) AND (bit)
1 0 1 1 0 0 0 0 B0
ANL C, bit 2 2 (C) = (C) AND (bit)
1 1 1 1 0 0 1 0 72
ORL C, bit 2 2 (C) = (C) OR (bit)
1 0 1 0 0 0 0 0 A0
ORL C, bit 2 2 (C) = (C) OR (bit)
1 0 1 0 0 0 1 0 A2
MOV C, bit 2 2 (C) = (bit)
1 0 0 1 0 0 1 0 92
MOV bit, C 2 2 (bit) = (C)
____________________________________________________________________________________________ 124
INSTRUCTION CODE
(PC) = (PC) + 2
(SP) = (SP) + 1
1
a10 a9 a8 0 0 0 1 Byte 1 ((SP)) = (PC7-0 )
ACALL addr 11 a8 2 2
a7 a6 a5 a3 a2 a1 a0 Byte 2 (SP) = (SP) + 1
((SP)) = (PC15-8 )
(PC) = page address
(PC) = (PC) + 3
0 0 (SP) = (SP) + 1
0 1 0 0 1 0 12
a15 a14 ((SP)) = (PC7-0 )
LCALL addr 16 a13 a12 a11 a10 a9 a8 Byte 2 3 3
a7 a6 (SP) = (SP) + 1
a5 a5 a3 a2 a1 a0 Byte 3
((SP)) = (PC15-8 )
(PC) = addr15-0
PROGRAM BRANCHING
(PC15-8 ) = ((SP))
(SP) = (SP) - 1
RET 0 0 1 0 0 0 1 0 22 1 3
(PC7-0 ) = ((SP))
(SP) = (SP) - 1
(PC15-8 ) = ((SP))
(SP) = (SP) - 1
RETI 0 0 1 1 0 0 1 0 32 1 3
(PC7-0 ) = ((SP))
(SP) = (SP) - 1
a10 a9 a8 0 0 0 0 1 Byte 1 (PC) = (PC) + 2
AJMP addr 11 2 2
a7 a6 a5 a4 a3 a2 a1 a0 Byte 2 (PC10-0 ) = page address
0 0 0 0 0 0 1 0 02
LJMP addr 16 a15 a14 a13 a12 a11 a10 a9 a8 Byte 2 3 3 (PC) = addr15-0
1 0 0 0 0 0 0 0 80 (PC) = (PC) + 2
SJMP rel 2 3
r7 r6 r5 r4 r3 r2 r1 r0 Byte 2 (PC) = (PC) + rel
JMP @A +
0 1 1 1 0 0 1 1 73 1 3 (PC) = (A) + (DPTR)
DPTR
(PC) = (PC) + 2
1 0 0 0 0 0 0 0 60
JZ rel 2 3 IF (A) = 0 THEN
r7 r6 r5 r4 r3 r2 r1 r0 Byte 2
(PC) = (PC) + rel
(PC) = (PC) + 2
1 0 0 0 0 0 0 0 70
JNZ rel 2 3 IF (A) ≠ 0 THEN
(PC) = (PC) + rel
125 ____________________________________________________________________________________________
INSTRUCTION CODE
(PC) = (PC) + 2
0 1 0 0 0 0 0 0 40
JC rel 2 3 IF (C) = 1 THEN
(PC) = (PC) + rel
(PC) = (PC) + 2
0 1 0 1 0 0 0 0 50
JNC rel 2 3 IF (C) ≠ 0 THEN
(PC) = (PC) + rel
0 0 1 0 0 0 0 0 20 (PC) = (PC) + 3
JB bit, rel b7 b6 b5 b4 b3 b2 b1 b0 Byte 2 3 4 IF (bit) = 1 THEN
0 0 0 1 0 0 0 0 30 (PC) = (PC) + 3
JNB bit, rel b7 b6 b5 b4 b3 b2 b1 b0 Byte 2 3 4 IF (bit) = 0 THEN
(PC) = (PC) + 3
0 0 0 1 0 0 0 0 10
IF (bit) = 1 THEN
JBC bit, rel b7 b6 b5 b4 b3 b2 b1 b0 Byte 2 3 4*
(bit) = 0 and (PC) =
(PC) + rel
(PC) = (PC) + 3
IF (direct) < (A)
THEN (PC) = (PC)
0 0 0 1 0 0 0 0 B5
+ rel and (C) = 0
CJNE A, direct, rel a7 a6 a5 a4 a3 a2 a1 a0 Byte 2 3 5
OR
IF (direct) > (A)
PROGRAM BRANCHING
THEN (PC) = (PC)

+ rel and (C) = 1
(PC) = (PC) + 3
IF #data < (A)
THEN (PC) = (PC)
1 0 1 1 0 1 0 0 B4
+ rel and (C) = 0
CJNE A, #data, rel d7 d6 d5 d4 d3 d2 d1 d0 Byte 2 3 4
OR
IF #data > (A)
THEN (PC) = (PC)
+ rel and (C) = 1
(PC) = (PC) + 3
IF #data < (Rn)
THEN (PC) = (PC)
1 0 1 1 1 n2 n1 n0 B8-BF
CJNE Rn, + rel and (C) = 0
d7 d6 d5 d4 d3 d2 d1 d0 Byte 2 3 4
#data, rel OR
IF #data > (Rn)
THEN (PC) = (PC)
+ rel and (C) = 1
(PC) = (PC) + 3
IF #data < ((Ri))
THEN (PC) = (PC)
1 0 1 1 0 1 1 i B6-B7
CJNE @Ri, + rel and (C) = 0
d7 d6 d5 d4 d3 d2 d1 d0 Byte 2 3 5
#data, rel OR
IF #data > ((Ri))
THEN (PC) = (PC)
+ rel and (C) = 1
(PC) = (PC) + 2
0
1 1 1 1 n2 n1 n0 D8-Df (Rn) = (Rn) - 1
DJNZ Rn, rel a5 3 4
r7 r6 r4 r3 r2 r1 r0 Byte 2 IF (Rn) ≠ 0 THEN
r5
(PC) = (PC) + rel
(PC) = (PC) + 3
1 1 1 1 0 1 0 1 D5
(direct) = (direct) - 1
DJNZ direct,rel a7 a6 d5 a4 a3 a2 a1 a0 Byte 2 3 5
IF (direct) ≠ 0 THEN
(PC) = (PC) + rel
NOP 0 0 0 0 0 0 0 0 00 1 1 (PC) = (PC) + 1
* Note: One additional clock cycle is required if the PSW, SP, DPS, IE, EIE, IP0, IP1, EIP0, or EIP1 register is accessed by certain direct
addressing instructions marked with an *. Additionally, the JBC bit instruction requires one additional clock cycle to clear a bit if the
jump is actually taken.
____________________________________________________________________________________________ 126
SECTION 15: PROGRAM LOADING

INTRODUCTION
The DS89C420 family has the ability to perform program loading or reloading in a number of ways. First, ROM loader mode can be
invoked to create a serial communication channel, which permits in-system program/erase of the internal and external program mem-
ory. Secondly, parallel programming mode allows programming and erasure of the internal flash memory using industry-standard
EPROM or flash parallel programmers. Finally, user code in-application programming allows the capability to in-application erase and
reprogram the upper 8kb block of flash memory through a special function register interface.
Note: The terms ROM loader, serial loader, and bootstrap loader are used interchangeably in this section and refer to the same func-
tional entity.
ROM LOADER MODE
The DS89C420 defaults to the normal operating (nonloader) mode without external hardware. ROM loader mode can be invoked at
any time, as described later in this section. Once the loader session is complete, the device performs a hardware reset and begin
operation. This is identical to an external reset, except that the ROM loader during the loader session may modify locations in scratch-
pad RAM in order to execute properly. The Table 15-1 shows which areas of scratchpad RAM are guaranteed preserved and which
ones are of indeterminate state after exiting the loader.
Table 15-1. Preserved and Indeterminate Scratchpad Memory
DS89C420
SCRATCHPAD MEMORY
Guaranteed Preserved 80h–FFh
Indeterminate 00h–7Fh
The guaranteed preserved locations are areas in scratchpad RAM that are be changed by the bootstrap loader. The indeterminate
area contains various stacks and buffers used by the loader, and a given byte in this area may or may not be modified by the loader.
As such, the user should not rely on the loader preserving any data in this area.
It should also be noted that the loader, upon being invoked, clears the EWT bit (WDCON.1) so that the watchdog timer is prevented
from generating an internal reset during the loader session.
Invoking the ROM Loader Mode
The ROM loader mode is invoked by simultaneously applying a logic 1 to the RST pin, a logic 0 to the EA pin, and driving the PSEN
pin to a logic 0 level. If power were to cycle while the required input stimuli were present, the loader would be invoked on power-up.
When the ROM loader mode is invoked, the device awaits an incoming <CR> character (0Dh) on serial port 0 at a baud rate that can
be detected by the autobaud routine. The autobaud routine is described later in this section. The autobaud routine receives and trans-
mits data only on serial port 0, ignoring activity on serial port 1. Upon successful baud-rate detection, the bootstrap loader transmits
a banner similar to the one shown below, signaling to the host that loader mode has successfully been invoked. The banner is followed
by a “>” prompt, which indicates the device is ready to receive a command. The command set recognizable by the ROM loader is also
detailed later in this section. The flow of these conditions is shown in Figure 15-1.
Exiting the Loader
In order to exit ROM loader mode on the DS89C420 device, first float the PSEN signal, and then float or drive the RST pin low. The RST
pin has an internal pulldown. The PSEN signal is an output and drives itself high. When the loader stimulus is removed, the processor
performs a hardware reset and begin execution at location 0000h. Note that both of these conditions must occur, or the loader is exit-
ed. The flow of these conditions is shown in Figure 15-1.
127 ____________________________________________________________________________________________
PROGRAM EXECUTION
INTERNAL MEMORY DISABLED EA\ =0
INTERNAL MEMORY ENABLED EA\ =1
N
RST = 1
N
DEVICE IN RESET
EA\ = 0 (INTERNAL MEMORY ENABLED)
N
DEVICE IN RESET
PSEN\ = 0 (INTERNAL MEMORY DISABLED)
AUTOBAUD ROUTINE
AWAITING <CR> CHARACTER ON RXD OF SERIAL PORT 0
Y
SERIAL COMMUNICATION WITH THE ROM LOADER CAN PSEN\
PROCEED AS ESTABLISHED ON SERIAL PORT 0 TOGGLED 0 1
N Y
POWER-ON
RESET
Figure 15-1. Invoking and Exiting the Loader on the DS89C420
____________________________________________________________________________________________ 128
Serial Program Load Operation

Program loading through a serial port is a convenient method of loading application software into the flash memory or external mem-
ory. Communication is performed over a standard, asynchronous serial communications port using a terminal emulator program with
8-N-1 (8 data bits, no parity, 1 stop bit) protocol settings. A typical application would use a simple RS-232 serial interface to in-system
program the device as part of a final production procedure.
The hardware configuration for the serial program load operation is illustrated in Figure 15-2. A variety of crystals can be used to pro-
duce standard baud rates. The serial loader is designed to operate across a 3-wire interface from a standard UART. The receive, trans-
mit, and ground wires are all that are necessary to establish communication with the device.
The serial loader implements an easy-to-use command line interface, which allows an Intel hex file to be loaded and read back from
the device. Intel hex is the standard format output by 8051 cross-assemblers.
TO PC
TD
ROIN ROOUT RXDO
RD
TOOUT DS232A TOIN TXDO
DTR
R1IN R1OUT
DS89C420
T1OUT T1IN VCC RST
EA
PSEN
HC/AC125
Figure 15-2. Serial Load Hardware Configuration
AUTOBAUD-RATE DETECTION
The serial bootstrap loader can automatically detect, within certain limits, the external baud rate and configure itself to that speed. The
loader controls serial port 0 in mode 1 (asynchronous, 1 start bit, 8 data bits, no parity, 1 stop bit, full duplex), using timer 1 in 8-bit
autoreload mode with the serial port 0 doubler bit (PCON.7) set. For these settings, an equation to calculate possible serial loader
baud rates is provided as a function of crystal frequency and timer reload value. Table 15-1 shows baud rates generated using the
equation:
Crystal Frequency
Serial Loader_Baud rate =
192 x ( 256-Timer Reload )
** Timer reload values attempted by the loader:
FF, FE, FD, FC, FB, FA, F8, F6, F5, F4, F3, F0, EC, EA, E8,
E6, E0, DD, D8, D4, D0, CC, C0, BA, B0, A8, A0, 98, 80, 60, 40
When communicating with a PC COM port having a standard 8250/16450 UART, attempt to match the loader baud rate and PC COM
port baud rate within 3% in order to maintain a reliable communication channel. If baud rates cannot be matched exactly, it is suggest-
ed configuring the loader to the faster baud rate to avoid the possibility of overflowing the DS89C420 serial input buffer.
129 ____________________________________________________________________________________________
Table 15-2. Serial Loader Baud Rates vs. Crystal Frequency

TIMER LOADER PC UART PC UART
CRYSTAL FREQUENCY (MHz) ERROR (%)
RELOAD BAUD RATE BAUD RATE RELOAD
32.0000 F6 16667 -1.3 16457 7
F3 12821 -0.2 12800 9
EC 8333 -1.3 8229 14
29.4912 FC 38400 0.0 38400 3
F8 19200 0.0 19200 6
F4 12800 0.0 12800 9
24.5760 F6 12800 0.0 12800 9
F5 11636 -1.0 11520 10
F4 10667 -1.8 10473 11
24.0000 F3 9615 -0.2 9600 12
F0 7812 -1.7 7680 15
E6 4808 -0.2 4800 24
22.1184 FF 115200 0.0 115200 1
FE 57600 0.0 57600 2
FD 38400 0.0 38400 3
20.0000 F8 13021 -1.7 12800 9
F0 6510 -1.7 6400 18
E8 4340 -1.7 4267 27
16.0000 FB 16667 -1.3 16457 7
F6 8333 -1.3 8229 14
F4 6944 -2.4 6776 17
11.0592 FF 57600 0.0 57600 2
FE 28800 0.0 28800 4
FD 19200 0.0 19200 6
1.84320 FF 9600 0.0 9600 12
FE 4800 0.0 4800 24
FD 3200 0.0 3200 36
Note: Only a few possible timer reload/PC UART reload values are shown per crystal frequency. This table, by no means, is an exhaustive list of acceptable configurations
for each crystal frequency, nor should it be considered a list of the allowable crystal frequencies.
COMMAND LINE INTERFACE

The serial bootstrap loader uses an easy-to-use command line interface that responds to alphabetic commands which are summa-
rized in Table 15-3. A detailed description of each command can be found in the following pages.
Table 15-3. Alphabetic Commands

COMMAND FUNCTION
B Self-CFC of internal ROM code.
C CRC-16 of flash memory range (inhibited if either LB2 or LB3 set).
CX CRC-16 of external RAM range.
D Dump Intel hex from internal flash memory range.
DX Dump Intel hex from external RAM range.
K Klear-Erase entire flash memory range.
L Load flash memory (Oh–3FFFh).
LB Load flash memory blindly (Oh–3FFFh)—no verify or precheck.
LE Load encryption vector (0–3Fh).
____________________________________________________________________________________________ 130
Table 15-3. Alphabetic Commands (continued)

COMMAND FUNCTION
LX Load external RAM (Oh–FFFFh).
R Read configuration.
V Verify flash memory against incoming hex.
VE Verify encryption vector against incoming hex.
VX Verify external RAM against incoming hex.
W Write register(s)
^C Reset loader.
Selected commands require arguments and some commands have optional arguments. In all cases, arguments are expected to be
hexadecimal numbers. In addition, an ASCII control-C character (^C) causes the serial loader to terminate any function currently being
executed and display the command line prompt. An incoming break character (defined as a received null character (00h) with the stop
bit = 0) causes the serial bootstrap loader to be restarted and the baud rate redetermined.
COMMAND LINE SYNTAX
Single-letter ASCII characters are recognized as commands by the bootstrap loader. Arguments are represented by hexadecimal num-
bers. A hexadecimal number is any sequence of hexadecimal characters. A hexadecimal character may be a digit, 0 through 9, or
one of the letters A through F. A byte is always the right-most two digits of a hexadecimal number. An address is always the right-most
four digits of a hexadecimal number.
BYTE CONVERSION ADDRESS CONVERSION

A → 000AH
A → 0AH
AB → 00ABH
AB → 0ABH
ABC → 0ABCH
ABC → 0BCH
ABCD → 0ABCDH
ABCD → 0CDH
ABCDE → 0BCDEH
The C, CX, D, and DX commands allow optional addresses to be entered. The syntax [begin-address [end-address]] is used to con-
vey the following meanings:
• No arguments: Begin-address is set to 0 and end-address is set to the range.
• One argument: Begin-address is set to the argument and end-address is set to the range.
• Two arguments: Begin-address is set to the first argument and end-address is set to the second argument. This second
address must not exceed the address value specified by the range.
In the second and third bullets above, an error message is generated if the end address is less than the begin address, either implic-
itly or explicitly. The 16kB flash memory can be addressed from 0 to 3FFFh, while the external RAM can be addressed from 0 to FFFFh.
Error messages are transmitted as soon as errors are detected. All messages are preceded by the two characters E:, and followed by
a mnemonic description.
Commands are not processed until an entire command line is entered and terminated with a <CR>. No command line may be greater
than 17 bytes. Since a command line is not processed until a <CR> is entered, the <delete> character can be used to make edits.
Lines longer than 17 characters return an error message and no action is taken for that command line.
Only legal characters are echoed back by the loader. The legal characters are: 0123456789, <:>, <space>, ABCDE-
FGHIJKLMNOPQRSTUVWXYZ, and <delete>. Backspace characters (<BS>) are converted to delete characters. The horizontal tab
character is converted to space. Lowercase alphabetic characters are converted to uppercase alphabetic.
The <delete> character is executed as a <BS> <space> <BS> when possible in command mode. This causes the character to be
overprinted on a hard-copy device. The <CR> character generates a <CR> <LF> pair.
131 ____________________________________________________________________________________________
COMMAND SUMMARIES
B
Return the CRC-16 (cyclic redundancy check) of the internal ROM code. This self-CRC computation should always return 0000h.
C [begin-address [end-address]]
Return the CRC-16 (cyclic redundancy check) of the flash memory. This computation is performed over the range unless option-
al start and end addresses are given. The CRC-16 algorithm is commonly used in data communications.
CX [begin-address [end-address]]
Return the CRC-16 (cyclic redundancy check) of the external RAM. This computation is performed over the range unless option-
al start and end addresses are given. The CRC-16 algorithm is commonly used in data communications.
D [begin-address [end-address]]
Dump flash memory in Intel hex format. An optional address range may be specified. Each record contains up to 32 data bytes.
The last line printed is the end-of-data record.
DX [begin-address [end-address]]
Dump external memory in Intel hex format. This command functions in the same manner as the D command with the exception
of the target memory being external.
K
Perform an erasure of the entire flash memory range, including security block, option control register, and bank-select bit.
L
Load standard ASCII Intel hex formatted data into flash memory. No lock bits may be set when attempting to load the internal flash
program memory. Only record types 00 and 01 are processed. Each record of the file is treated the same way. All characters are
discarded before the header character <:> is read. The rest of the record, defined by the length byte, is then processed. All char-
acters following the record checksum and prior to the next <:> are discarded. Control returns to the command prompt after an
Intel end record is encountered. Prior to programming each byte, the loader performs a preread of that flash memory location to
assess whether the new hex value can be written. After programming each byte, the loader reads the flash memory location again
to verify proper programming. The processing of each record is confirmed by an ACK/NAK response. New records should not be
transmitted until the ACK/NAK byte associated with the previous record has been received.
The ACK/NAK responses are as follows:
G–good record
A–hex record received, which contains an address not programmable by the L
command: address > 3FFFh (for flash); address > 3Fh (for encryption vector)
Example: record with address > 3FFFh, which would result in the NAK response <A>:
:07403000000012040080FEF5
F–flash write error
H–hex record received contained a nonhex character
L–record length > 20 bytes (type 0); record length > 0 bytes (type 1 EOF)
P–programming error—loader detected an attempt to write 1’s to 0’s
R–hex record contained a record type not supported by the DS89C420 loader
Example: record type other than 00 or 01, which would result in the NAK response <R>:
:020000040001F9
S – hex record contained an incorrect checksum
Example record with an incorrect checksum, which would result in the NAK response <S>:
:03000000024000BC
V–data read back does not match data that was written
____________________________________________________________________________________________ 132
LB
Load blind of internal flash memory—Loads standard Intel hex-formatted data into internal flash memory. This command functions
in the same manner as the L command, except that the preprogramming assessment and postprogramming verification of the
flash memory are not executed by the loader. When using this command, the P and V NAK responses are not returned by the
loader. All other ACK/NAK responses are still generated by the loader.
LE
Load encryption vector—Loads standard Intel hex-formatted data into flash security block. This command functions in the same
manner as the L command, except that it operates on the flash security block (0–3Fh).
LX
Load external memory—Loads standard Intel hex-formatted data into external memory. This command functions similar to the L
command, except that it operates on the external memory (0–FFFFh) and can write without restriction to any address location in
the range. If an external page mode or MOVX stretch cycle different from the default setting is desired, the ACON or CKCON reg-
isters should be modified prior to execution of the LX command.
R
Read—Displays the values of the lock bits, option control register, address control register, clock control register, power manage-
ment register, Ports 0, 1, 2, 3, and the flash control register in the following format:
LB:XX OCR:XX ACON:XX CKCON:XX PMR:XX P0:XX P1:XX P2:XX P3:XX FCNTL:XX
V
Verify current contents of flash memory vs. the received Intel hex. This command operates similar to the load command, except
that it does not write to the flash memory; it compares the data byte(s) in the flash memory to the byte(s) in the data stream. The
same ACK/NAK response scheme is used during verify operations as is used for load operations.
VE
Verify encryption vector—Verifies current contents of the flash security block vs. the received Intel hex. This command works in the
same manner as the V command, but operates on the flash security block (0–3Fh).
VX
Verify external memory—Verifies current contents of external memory versus the received Intel hex. This command works in the
same manner as the ‘V’ command, but operates on external memory (0–FFFFh).
W [LB | OCR | ACON | CKCON | PMR | P0 | P1 | P2 | P3] byte
Writes byte to the requested register. Valid entries for LB are 1 (enable LB1), 3 (enable LB1, LB2), and 7 (enable LB1, LB2, LB3).
ACON register writes modify only bits 7, 6, 5. CKCON register writes modify only bits 2,1, 0. PMR register writes modify only bit 0.
P3 register writes modify only P3.7–P3.2 (P3.1 and P3.0 are not altered).
^C
Interrupt whatever is going on, clear all the buffers, put up a prompt, and wait for the next command. Anything in the type-ahead
buffer is removed. All output is stopped.
ERROR MESSAGES
E:ARGREQ
An argument or arguments are required for this command.
E:BADCMD
An invalid command letter was entered.
E:BADREG
This message is printed if a register other than OCR, ACON, CKCON, PMR, P0, P1, P2, or P3 is used as the argument for the W com-
mand.
133 ____________________________________________________________________________________________
E:BADVAL
The requested value cannot be programmed into the OCR register because it contains 1’s in bit position(s) where 0’s have already
been programmed.
E:EXTARG
Extra data was encountered on the command line when it was not needed. Reenter the command.
E:ILLOPT
The optional parameters given were in error. If the start address is greater than the end address, either implicitly or explicitly, then an
error is printed. The range bit implicitly determines the maximum range.
E:LOCK BITS ENABLED
The requested operation cannot be performed due to the current lock bit settings.
E:LOCK BITS ALREADY SET
The requested lock bit setting cannot be programmed because a higher order lock bit has already been programmed.
E:NOTHEX
A nonhexadecimal character was found when expecting a hexadecimal character.
E:VALUE MUST BE 1, 3 OR 7
A value other than 1, 3, or 7 was entered when trying to write the lock bits.
PARALLEL PROGRAMMING MODE
The DS89C420 parallel program load mode is compatible with most industry-standard parallel programmers (Figure 15-3). The
DS89C420 data sheet contains the most comprehensive information relating to the parallel programming mode.
P1.0 DS89C420 P0.0

P1.1 P0.1
P1.2 P0.2
ADDRESS 7:0 P1.3 P0.3 DATA
P1.4 P0.4
P1.5 P0.5
P1.6 P0.6
P1.7 P0.7
DRIVE HIGH RST EA\ DRIVE HIGH

ALE/PROG\ CONTROL
ERROR P3.0 PSEN\ DRIVE LOW
P3.1
BUSY/READY P3.2 P2.7 CONTROL
P3.3 P2.6 CONTROL
P3.4 P2.5
P3.5 P2.4
CONTROL P3.6 P2.3
CONTROL P3.7 P2.2
P2.1
XTAL2 P2.0
4MHz TO 6MHz XTAL1
Figure 15-3. Parallel Load Hardware Configuration
____________________________________________________________________________________________ 134
USER CODE IN-APPLICATION PROGRAMMING MODE

The DS89C420 data sheet contains the most comprehensive information relating to the in-application programming mode. Additional
supporting information can be found in the SFR definitions of FCNTL (D5h) and FDATA (F6h) of this user’s guide.
INTEL HEX FILE FORMAT
Assemblers that are 8051-compatible assemblers produce an absolute output file in Intel hex format. These files are composed of a
series of records. Records in an Intel hex file have the following format:
<header><hex information><record terminator>
The specific record elements are detailed as follows:
: II aaaa tt dddddd ... dd xx
where:
: Indicates a record beginning
II Indicates the record length
aaaa Indicates the 16-bit load address
tt Indicates the record type
dd Indicates hex data
xx Indicates the checksum = (two’s complement (II+aa+a+tt+dd+dd+...dd)
Record type 00 indicates a data record and type 01 indicates an end record. An end record appears as :00 00000 01 FF. These are
the only valid record types for a NIL hex file. Spaces are provided for clarity.
The following is a short Intel hex file. The data bytes begin at 01 and count up to 2F. Notice the record’s length, beginning address,
and record type at the start of each line and the checksum at the end:
:200000000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F20D0
:0F0020002122232425262728292A2B2C2D2E2F79
:00000001FF
REVISION HISTORY
January 24, 2001 Original Issue
October 3, 2002 Revision 1
135 ____________________________________________________________________________________________

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Ultra-High-Speed Flash

Microcontroller User’s Guide

________________________________________________________________________ Maxim Integrated Products 1

SECTION 2: ORDERING INFORMATION

SECTION 4: PROGRAMMING MODEL

FFFFh 64k FFh 255 FFh

Figure 4-1. Memory Map Figure 4-2. Register Map

Figure 4-3. Scratchpad Register Addressing

The ultra-high-speed microcontroller supports eight addressing modes:

Program Status Flags

Table 4-1. Instructions that Affect Flag Settings

DS89C420 Special-Function Register Locations

DS89C420 Special-Function Register Reset Values

Data Pointer Low 0 (DPL)

Data Pointer High 0 (DPH)

Data Pointer Low 1 (DPL1)

Data Pointer High 1 (DPH1)

Power Control (PCON)

Timer/Counter Control (TCON)

Timer Mode Control (TMOD)

Timer 0 LSB (TL0)

Timer 1 LSB (TL1)

Timer 0 MSB (TH0)

Clock Control (CKCON)

Watchdog Interrupt Flag Timeout Periods (in Oscillator Clocks)

Serial Port Mode Functions

Serial Data Buffer 0 (SBUF0)

Address Control (ACON)

Bits 4–0 Reserved. Read data is 1.

Interrupt Enable (IE)

Slave Address Register 0 (SADDR0)

Slave Address Register 1 (SADDR1)

Interrupt Priority 0 (IP0)

Slave Address Mask Enable Register 0 (SADEN0)

Slave Address Mask Enable Register 1 (SADEN1)

Serial Port 1 Modes and Functions

Serial Data Buffer 1 (SBUF1)

Power Management Register (PMR)

Status Register (STATUS)

PIS2-0 INTERRUPT PRIORITY LEVEL

Bit 4 This bit is reserved and reads a logic 1.

Timer 2 Control (T2CON)

CP/RL2 EXEN2 DCEN RESULT

Timer 2 Mode (T2MOD)

DCEN T2EX DIRECTION

Timer 2 Capture LSB (RCAP2L)

Timer 2 LSB (TL2)

Timer 2 MSB (TH2)

Program Status Word (PSW)

Flash Memory Control (FCNTL)

Flash Command Bit Operations

Option Control Register

Definition of Lock Bits

Lock Bit Protection Modes

Flash Memory Data (FDATA)

Extended Interrupt Enable (EIE)

Bits 7–5 Reserved. Read data is 1.

Bits 7–5 Reserved. Read data is 1.

Extended Interrupt Priority 0 (EIP0)