ECE 538

VLSI System Testing

Krish Chakrabarty

Fault Modeling

Krish Chakrabarty 1

Fault Modeling
• Why model faults?
• Some real defects in VLSI and PCB
• Common fault models
• Stuck-at faults
• Single stuck-at faults
• Fault equivalence
• Fault dominance and checkpoint theorem
• Classes of stuck-at faults and multiple faults
• Transistor faults
• Summary

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 Why Model Faults?
• I/O function tests inadequate for manufacturing test
• Real defects (often mechanical) too numerous and
often not analyzable
• A fault model identifies targets for testing
• A fault model makes analysis possible
• Effectiveness measurable by experiments

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Some Real Defects in Chips

§ Processing defects
§ Missing contact windows
§ Parasitic transistors
§ Oxide breakdown
§ ...
§ Material defects
§ Bulk defects (cracks, crystal
imperfections)
§ Surface impurities (ion migration)
§ ...
§ Time-dependent failures
§ Dielectric breakdown
§ Electromigration
§ ...
§ Packaging failures
§ Contact degradation
§ Seal leaks
§ ...

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 Observed PCB Defects
Defect classes Occurrence frequency (%)

Shorts 51
Opens 1
Missing components 6
Wrong components 13
Reversed components 6
Bent leads 8
Analog specifications 5
Digital logic 5
Performance (timing) 5
Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

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Common Fault Models

• Single stuck-at faults
• Transistor open and short faults
• Memory faults
• PLA faults (stuck-at, cross-point, bridging)
• Functional faults (processors)
• Delay faults (transition, path)
• Analog faults
• For more examples, see Section 4.4 (p. 60-70) of the book.

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 Fault Models
• Faults must match level of abstraction in terms of
– Component types
– Signal values
– Time units
• Example: Logic (gate) level
– Component types: lines, gates, flip-flops
– Signal values: 0, 1
– Time units: gate delays
• Meaningless concepts at this level:
– Voltage, short-circuit, lost message

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Behavioral Fault Model

• Defined at highest-level of abstraction, i.e.
behavioral specification of system
• Inject various types of faults into Verilog/VHDL
descriptions, e.g.,
– Variable R assumed to be permanently at VL or VH
– A call to a function may be assumed to fail in such a
way that it always returns VL or VH.
– The “for (CC) {B}” clause fails: either the body {B} is
never executed, or always executed irrespective of
condition (CC)

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 Behavioral Faults
• The “switch (id)” clause may fail:
– All the specified cases are selected
– None of the specified cases are selected
• An “if (Y) then {B1} else {B2}” construct may fail, e.g.
– {B1} is never executed and {B2} is always executed
• The assignment “X := Y” may fail, e.g.
– The value of X remains unchanged
• Must provide adequate coverage of low-level faults

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Functional Fault Model

• Ad hoc, geared towards specific functional blocks,
e.g. multiplexers, adders, counters
• Faults for a multiplexer:
– A 0 or 1 cannot be selected on an input line
– Two inputs are selected simultaneously. Output = ?
• Useful if not too complex for test generation, and
provides good coverage of low-level faults

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 Functional Fault Models
• Example: truth table can change in any arbitrary way
– Needs exhaustive (verification) testing, all 2n inputs must
be applied
– Pseudoexhaustive testing possible
u << n
Testing time = m2u << 2n
x1
z1
x2 u z2
xn zm

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Single Cell Fault Model

x1 y1 x2 y2 x3 y3 x4 y4

c0 FA FA FA FA c4

z1 z2 z3 z4
• Cells can have any implementation
• All possible (combinational) cell faults are allowed; truth table can
change in any way
• C-testability: constant number of test patterns, independent of circuit size
(Ripple-carry adder needs only 8 test patterns for all single stuck-at faults)

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 Single Stuck-at Fault
• Three properties define a single stuck-at fault
• Only one line is faulty
• The faulty line is permanently set to 0 or 1
• The fault can be at an input or output of a gate
• Example: XOR circuit has 12 fault sites and 24 single stuck-at
faults
Faulty circuit value
Good circuit value
c j
0(1)
s-a-0
a d 1(0)
1 g h
z
0 1 i
b e 1

f k
Test vector for h s-a-0 fault
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Single Stuck-Line (SSL) Model

1 Any line in a logic
circuit can be permanently
stuck-at-1 (s-a-1, s/1) or
stuck-at-0 (s-a-0, s/0)

• Advantages: • Disadvantages:
– Also called stuck-at – Does not account for
– Matches circuit level, easy timing/delay faults
to use – Few physical defects
– Moderate number of faults behave like SSL
(2n for an n-line circuit) faults
– Tests for SSL faults provide
good defect coverage
(experiments)
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 Single Stuck-Line Faults
• A single node in the circuit is stuck-at 1 (s-a-1) or 0 (s-a-0)

A A
s-a-0 s-a-1
B B
z z
C C
D D

Fault-free function z = AB+CD Fault-free function z = AB+CD

Faulty function zf = AB Faulty function zf = AB+D

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SSL Fault Detection

• A test pattern for fault x s-a-d is an input combination that:
1) places d on x (activation), 2) propagates fault effect (D
or D) to primary output
D: 1/0, D: 0/1
Good circuit
Bad circuit

A
s-a-0
B
z
C
E

ABCE = 0011 is a test pattern for C s-a-0

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 Testing a Gate for SSL Faults
Fault
a/0 a/1 b/0 b/1 z/0 z/1
2-input OR gate
ab
a 00 x x x
z
b Test 01 x x
10 x x
11 x

2-input NAND gate Fault

a/0 a/1 b/0 b/1 z/0 z/1
a
z ab
b
00 x
Test 01 x x
10 x x
11 x x x

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Equivalence and Dominance

• Faults f1 and f2 are equivalent
if and only if (iff) every test pattern for f1 is
a test pattern for f2, and vice versa.
Fault
Example: {a/1, b/1, z/1} form an equivalence Test a/0 a/1 b/0 b/1 z/0 z/1
class. Equivalent faults give rise to identical ab
faulty functions 00 x x x
01 x x
• Fault f1 dominates fault f2 if and only if
10 x x
every test pattern for f1 is a test pattern for f2 11 x
(f2 is dominated by f1).
Example: a/0 dominates z/0, b/0 dominates z/0
Þ f1 and are f2 equivalent iff f1 dominates f2 and f2 dominates f1.
Þ Significant fault list collapsing is possible (drop dominated & equivalent
faults).
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 Fault Equivalence
• Number of fault sites in a Boolean gate circuit = #PI + #gates + #
(fanout branches).
• Fault equivalence: Two faults f1 and f2 are equivalent if all tests that
detect f1 also detect f2.
• If faults f1 and f2 are equivalent then the corresponding faulty functions
are identical.
• Fault collapsing: All single faults of a logic circuit can be divided into
disjoint equivalence subsets, where all faults in a subset are mutually
equivalent. A collapsed fault set contains one fault from each
equivalence subset.

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Equivalence Rules
sa0 sa0
sa1 sa1
sa0 sa1 sa0 sa1 WIRE
sa0 sa1 sa0 sa1
AND OR

sa0 sa1 sa0 sa1

sa0 sa1
NOT
sa1 sa0

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1 sa0
NAND NOR
sa1
sa0
sa0 sa1 sa0 sa1
sa1
sa0
FANOUT sa1

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 Equivalence Example
sa0 sa1 Faults in green
sa0 sa1 removed by
sa0 sa1 equivalence
collapsing
sa0 sa1 sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1
sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
20
Collapse ratio = ----- = 0.625
32

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Fault Equivalence

• Theorem: An n-input NAND, NOR, AND or OR gate has

n+2 equivalent classes:
{x1/c},{x2/c},…,{xn/c},{z/(cÅi)},{z/(cÅi},x1/c,x2/c,…}
• Local fault collapsing reduces number of faults by almost
50%

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 Fault Dominance
• If all tests of some fault F1 detect another fault F2, then
F2 is said to dominate F1.
• Dominance fault collapsing: If fault F2 dominates F1, then
F2 is removed from the fault list.
• When dominance fault collapsing is used, it is sufficient to
consider only the input faults of Boolean gates. See the
next example.
• In a tree circuit (without fanouts) PI faults form a
dominance collapsed fault set.
• If two faults dominate each other then they are equivalent.

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Dominance Example
All tests of F2
F1
s-a-1 001
F2
s-a-1 110 010
000
101 011
100

s-a-1 Only test of F1

s-a-1
s-a-1
s-a-0
A dominance collapsed fault set
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 Testing Simple Gates
1) N-input AND, NAND gate: 1) N-input OR, NOR gate:
n +1 patterns n +1 patterns
011…1 100…0
101…1 010…0
110…1 001…0

111…0 000…1
111…1 000…0

n-input XOR gate: 2 test patterns (n odd), 3 test patterns (n even)

Independent of n!

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Testing a Circuit
• Controllability problem: Apply test patterns to inputs of
the CUT that produces desired pattern at fault site (fault
activation)
• Observability problem: Propagate an error from fault site
to observable primary output

s-a-1
Observable
Controllable 0 1®0 (D)
primary
primary 1 z output
inputs
Circuit under test (CUT)

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Multiple Stuck-at (Stuck-Line)
Faults
• A multiple stuck-at fault means that any set of lines is
stuck-at some combination of (0,1) values.
• The total number of single and multiple stuck-at faults in
a circuit with k single fault sites is 3k-1.
• A single fault test can fail to detect the target fault if
another fault is also present, however, such masking of
one fault by another is rare.
• Statistically, single fault tests cover a very large number
of multiple faults.

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Switch-Level Fault Models

VDD
Stuck-open Faults
a
Fault-free circuit: z = a+b
b
Floating node Faulty circuit: zf = a+b + abz~
z
~z : Previous value of z
a b

Gnd Case 1: a = b = 1, z pulled down to 0

Case 2: a = 1, b =0, z retains previous state
A test for a stuck-open fault requires two patterns
{ab = 00, ab = 10}
initialization vector test vector

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 Stuck-Open Example
Vector 1: test for A s-a-0
(Initialization vector)
Vector 2 (test for A s-a-1)
pMOS VDD Two-vector s-op test
FETs
can be constructed by
A ordering two s-at tests
1 0
Stuck-
open
0 0
B
C
0 1(Z)

Good circuit states

nMOS
FETs Faulty circuit states
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Switch-Level Fault Models

Stuck-on Fault: Transistor permanently on
VDD
• T1 stuck-on: (1,1) possible test pattern
T1 Output for T2, T2, T3 turned on should be 1
a b
T2 z • T4 stuck-on: (1,0) possible test pattern
a Output for T2, T2, T3 turned on should be 0
T3
T4 b Þ Only one of these faults can be detected

Gnd • Limitation of voltage monitoring techniques

• Current monitoring techniques needed

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 Geometric Fault Models
Bridging faults: Derived from circuit layout
• Models short circuits, pairs of nodes considered
• Number of bridging faults?
• Feedback vs non-feedback bridging faults
bridge
A B z zf Wired-AND Wired-OR
A 0 0 0 0 0 0
z
B 0 1 0 ? 0 1
1 0 0 ? 0 1
1 1 1 1 1 1
zf = ?
What are the test patterns in this example?
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Bridging Fault Models

– Tests for resistive shorts between two normally
unconnected nets
– Closest fault-model to real defects
– Bridging-faults are caused by manufacturing defects
modeled as wired-AND, wired-OR
or resistive shorts

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 Bridging Faults
Wired-OR or WIRED-AND? VDD
Bridging VDD
a fault

b z
abc = 110 creates
intermediate voltage Gnd
at intermediate nodes
c

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Feedback vs Non-Feedback BF

Non-feedback bridging fault

Feedback bridging fault

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 Delay Faults
• Affect propagation delay of the circuit,
circuit fails at high speeds
• More important for high-speed circuits
• Gate delay fault (GDF): slow 1-to-0 or 0-
to-1 transition at a gate output
• Path delay fault (PDF): exists a path from
a primary input to primary output that is
slow to propagate a 0-to-1 or 1-to-0
transition

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Delay Faults
1 1
Gate delay fault
0
0
1

1 0
Path delay fault
0
1

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 Types of GDFs
• Gross GDFs (G-GDF): gate delay defect size is
greater than system clock period
– DFs in all paths going through faulty gate, hence
catastrophic
– Also called transition faults (TFs)
• Small GDFs (S-GDF): delay defect size is smaller
than system clock period
– Detectable if causes PDF in at least one path through
the gate

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Delay Fault Terminology

• Two-pattern tests
• Test is robust if independent of delays in the rest
of the circuit, else non-robust
• Robust test (RT) is a hazard-free robust test
(HFRT) if no hazards can occur on tested path,
irrespective of gate delays
• Non-hazard-free robust tests allow hazards on side
inputs

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 Summary
• Fault models are analyzable approximations of defects
and are essential for a test methodology.
• For digital logic single stuck-at fault model offers best
advantage of tools and experience.
• Many other faults (bridging, stuck-open and multiple
stuck-at) are largely covered by stuck-at fault tests.
• Stuck-short and delay faults and technology-dependent
faults require special tests.
• Memory and analog circuits need other specialized fault
models and tests.

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