Features Description: CMOS Octal Bus Transceiver

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82C86H

March 1997 CMOS Octal Bus Transceiver

Features Description
• Full Eight Bit Bi-Directional Bus Interface The Intersil 82C86H is a high performance CMOS Octal
Transceiver manufactured using a self-aligned silicon gate
• Industry Standard 8286 Compatible Pinout
CMOS process (Scaled SAJI IV). The 82C86H provides a full
• High Drive Capability eight-bit bi-directional bus interface in a 20 lead package. The
- B Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Transmit (T) control determines the data direction. The active
low output enable (OE) permits simple interface to the 80C86,
- A Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA
80C88 and other microprocessors. The 82C86H has gated
• Three-State Outputs inputs, eliminating the need for pull-up/pull-down resistors and
reducing overall system operating power dissipation.
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
• Gated Inputs
- Reduce Operating Power
Ordering Information
- Eliminate the Need for Pull-Up Resistors PART NUMBER
PACK- PKG.
• Single 5V Power Supply 5MHz 8MHz AGE TEMP. RANGE NO.

• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA CP82C86H-5 CP82C86H 20 Ld 0oC to +70oC E20.3
PDIP
• Operating Temperature Range IP82C86H-5 IP82C86H -40oC to +85oC E20.3
- C82C86H . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC CS82C86H-5 CS82C86H 20 Ld 0oC to +70oC N20.35
- I82C86H . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC IS82C86H-5 IS82C86H
PLCC
-40oC to +85oC N20.35
- M82C86H . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
CD82C86H-5 CD82C86H 20 Ld 0oC to +70oC F20.3
CERDIP

ID82C86H-5 ID82C86H -40oC to +85oC F20.3

MD82C86H-5/B - -55oC to F20.3


+125oC

5962- - SMD # F20.3


8757701RA

MR82C86H-5/B - 20 Pad -55oC to J20.A


CLCC +125oC
5962- - SMD # J20.A
87577012A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 2977.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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82C86H

Pinouts
82C86H (PDIP, CERDIP) 82C86H (PLCC, CLCC) TRUTH TABLE
TOP VIEW TOP VIEW
T OE A B
X H Hi-Z Hi-Z

VCC
A2

A1

A0

B0
A0 1 20 VCC H L I O
3 2 1 20 19
A1 2 19 B0 L L O I
A2 3 18 B1 H = Logic One
A3 4 17 B2 A3 4 18 B1 L = Logic Zero
I = Input Mode
A4 5 16 B3 A4 5 17 B2
O = Output Mode
A5 6 15 B4 A5 6 16 B3 X = Don’t Care
A6 7 14 B5 Hi-Z = High Impedance
A6 7 15 B4
A7 8 13 B6
A7 8 14 B5 PIN NAMES
OE 9 12 B7
PIN DESCRIPTION
GND 10 11 T
9 10 11 12 13 A0-A7 Local Bus Data I/O Pins

GND
OE

B7

B6
T
B0-B7 System Bus Data I/O Pins
T Transmit Control Input
OE Active Low Output Enable

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82C86H

Functional Diagram Decoupling Capacitors


The transient current required to charge and discharge the
A0 300pF load capacitance specified in the 82C86H/87H data
B0 sheet is determined by:

I = C L ( dv ⁄ dt ) (EQ. 1)
A1 B1

A2 B2
Assuming that all outputs change state at the same time and
A3 B3 that dv/dt is constant;
A4 B4 (V CC × 80% ) (EQ. 2)
I = C L -------------------------------------
A5 B5
tR ⁄ tF

A6 B6 where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight out-


puts.
A7 B7
– 12 –9
I = ( 80 × 300 × 10 ) × ( 5.0V × 0.8 ) ⁄ ( 20 × 10 ) (EQ. 3)
= 480mA

OE
T VCC VCC

P
Gated Inputs P

During normal system operation of a latch, signals on the N


STB
bus at the device inputs will become high impedance or P
make transitions unrelated to the operation of the latch. INTERNAL
DATA IN
These unrelated input transitions switch the input circuitry DATA
and typically cause an increase in power dissipation in N
CMOS devices by creating a low resistance path between
VCC and GND when the signal is at or near the input switch- N
ing threshold. Additionally, if the driving signal becomes high
impedance (“float” condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in FIGURE 1. 82C82/83H
device operation.
VCC
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
P
disabled (OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the VCC and OE
ground power supply pins by turning off the upper P-channel P
and lower N-channel (See Figures 1 and 2). No current flow INTERNAL
DATA IN DATA
from VCC to GND occurs during input transitions and invalid
VCC N
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device. P

D.C. input voltage levels can also cause an increase in ICC if N


these input levels approach the minimum VIH or maximum N
VIL conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi- FIGURE 2. 82C86H/87H GATED INPUTS
tion will occur only during the time the device is in the trans- This current spike may cause a large negative voltage spike
parent mode (STB = logic one). ICC remains below the on VCC which could cause improper operation of the device.
maximum ICC standby specification of 10µA during the time To filter out this noise, it is recommended that a 0.1µF
inputs are disabled, thereby greatly reducing the average ceramic disc capacitor be placed between VCC and GND at
power dissipation of the 82C8X series devices. each device, with placement being as near to the device as
possible.

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82C86H

Absolute Maximum Ratings Thermal Information


Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V CERDIP Package . . . . . . . . . . . . . . . . 70 16
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 CLCC Package . . . . . . . . . . . . . . . . . . 80 20
PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A
Operating Conditions PLCC Package . . . . . . . . . . . . . . . . . . 75 N/A
Maximum Storage Temperature Range . . . . . . . . . -65oC to +150oC
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Maximum Junction Temperature Hermetic Package . . . . . . . +175oC
Operating Temperature Range
Maximum Junction Temperature Plastic Package. . . . . . . . . +150oC
C82C86H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
I82C86H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
(PLCC - Lead Tips Only)
M82C86H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC

Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

DC Electrical Specifications VCC = 5.0V ± 10%; TA = 0oC to +70oC (C82C86H);


TA = -40oC to +85oC (I82C86H);
TA = -55oC to +125oC (M82C86H)

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical One 2.0 - V C82C86H, I82C86H

Input Voltage 2.2 V M82C86H (Note 1)

VIL Logical Zero Input Voltage - 0.8 V

VOH Logical One Output Voltage

B Outputs 3.0 V IOH = -8mA

A Outputs 3.0 V IOH = -4mA

A or B Outputs VCC -0.4 V IOH = -100µA

VOL Logical Zero Output Voltage

B Outputs 0.45 V IOL = 20mA

A Outputs 0.45 V IOL = 12mA

II Input Leakage Current -10.0 10.0 µA VIN = GND or VCC DIP Pins 9, 11

IO Output Leakage Current -10.0 10.0 µA VO = GND or VCC, OE ≥ VCC -0.5V


DIP Pins 1 - 8, 12 - 19

ICCSB Standby Power Supply - 10 µA VIN = VCC or GND, VCC = 5.5V, Outputs Open
Current

ICCOP Operating Power Supply - 1 mA/MHz TA = +25oC, Typical (See Note 2)


Current

NOTES:
1. VIH is measured by applying a pulse of magnitude = VIH(MIN) to one data input at a time and checking the corresponding device output for
a valid logical “1” during valid input high time. Control pins (T, OE) are tested separately with all device data input pins at VCC -0.4
2. Typical ICCOP = 1mA/MHz of read/ cycle time. (Example: 1.0µs read/write cycle time = 1mA).

Capacitance TA = +25oC

SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

CIN Input Capacitance

B Inputs 18 pF Freq = 1MHz, all measurements are


referenced to device GND
A Inputs 14 pF

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82C86H

AC Electrical Specifications VCC = 5.0V ± 10%; TA = 0oC to +70oC (C82C86H);


Freq = 1MHz TA = -40oC to +85oC (I82C86H);
TA = -55oC to +125oC (M82C86H)

NOTE 4

82C86H 82C86H-5
SYMBOL PARAMETER MIN MAX MAX UNITS TEST CONDITIONS

(1) TIVOV Input to Output Delay Notes 1, 2

Inverting 5 30 35 ns

Non-Inverting 5 32 35 ns

(2) TEHTV Transmit/Receive Hold Time 5 - - ns Notes 1, 2

(3) TTVEL Transmit/Receive Setup Time 10 - - ns Notes 1, 2

(4) TEHOZ Output Disable Time 5 30 35 ns Notes 1, 2

(5) TELOV Output Enable Time 10 50 65 ns Notes 1, 2

(6) TR, TF Input Rise/Fall Times - 20 20 ns Notes 1, 2

(7) TEHEL Minimum Output Enable High Time Note 3

82C86H 30 - - ns

82C86H-5 35 - - ns

NOTES:
1. All AC parameters tested as per test circuits and definitions in timing waveforms and test load circuits. Input rise and fall times are driven
at 1ns/V.
2. Input test signals must switch between VIL - 0.4V and VIH +0.4V.
3. A system limitation only when changing direction. Not a measured parameter.
4. 82C86H is available in commercial and industrial temperature ranges only. 82C86H-5 is available in commercial, industrial and military
temperature ranges.

Timing Waveform

TR, TF (6)

2.0V
INPUTS
0.8V

TEHEL (7)

OE

(1) (4)
TELOV (5)
TIVOV TEHOZ
VOH -0.1V 3.0V
OUTPUTS
VOL +0.1V 0.45V

TEHTV (2) TTVEL (3)

NOTE: All timing measurements are made at 1.5V unless otherwise noted.

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82C86H

Test Load Circuits


A SIDE OUTPUTS
TELOV OUTPUT HIGH TELOV OUTPUT LOW TEHOZ OUTPUT LOW/HIGH
TIVOV LOAD CIRCUIT ENABLE LOAD CIRCUIT ENABLE LOAD CIRCUIT DISABLE LOAD CIRCUIT

2.36V 1.5V 1.5V 2.36V

160Ω 375Ω 91Ω 160Ω

TEST TEST TEST TEST


OUTPUT OUTPUT OUTPUT OUTPUT
POINT POINT POINT POINT
100pF 100pF 100pF 50pF
(SEE NOTE) (SEE NOTE) (SEE NOTE) (SEE NOTE)

B SIDE OUTPUTS
TELOV OUTPUT HIGH TELOV OUTPUT LOW TEHOZ OUTPUT LOW/HIGH
TIVOV LOAD CIRCUIT ENABLE LOAD CIRCUIT ENABLE LOAD CIRCUIT DISABLE LOAD CIRCUIT

2.27V 1.5V 1.5V 2.27V

91Ω 180Ω 51Ω 91Ω

TEST TEST TEST TEST


OUTPUT OUTPUT OUTPUT OUTPUT
POINT POINT POINT POINT
300pF 300pF 300pF 50pF
(SEE NOTE) (SEE NOTE) (SEE NOTE) (SEE NOTE)

NOTE: Includes jig and stray capacitance.

Burn-In Circuits
MD82C86H CERDIP

VCC

R1 C1
F2 1 20
R1
F2 2 19 A
R1
F2 3 18 A
R1
F2 4 17 A
R1
F2 5 16 A
R1
F2 6 15 A VCC
R1
F2 7 14 A
R1 R2
F2 8 13 A
R1 A
9 12 A
R1 R3
10 11 VCC

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82C86H

Burn-In Circuits (Continued)


MR82C86H CLCC

VCC C1

F2 F2 F2 F3

R5 R5 R5 R5

3 2 1 20 19

R5 R5
F2 4 18 F3

R5 R5
F2 5 17 F3

R5 R5
F2 6 16 F3

R5 R5
F2 15 F3
7
R5 R5
F2 8 14 F3

9 10 11 12 13

R4 R4 R5 R5

F0 F1 F3 F3

NOTES:
1. VCC = 5.5V ± 0.5V, GND = 0V
2. VIH = 4.5V ± 10%
3. VIL = -0.2V to 0.4V
4. R1 = 47kΩ ± 5%
5. R2 = 2.4kΩ ± 5%
6. R3 = 1.5kΩ ± 5%
7. R4 = 1kΩ ± 5%
8. R5 = 5kΩ ± 5%
9. C1 = 0.01µF minimum
10. F0 = 100kHz ± 10%
11. F1 = F0/2, F2 = F1/2, F3 = F2/2

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82C86H

Die Characteristics
DIE DIMENSIONS: GLASSIVATION:
138.6 x 155.5 x 19 ± 1mils Type: SiO2
Thickness: 8kÅ ± 1kÅ
METALLIZATION:
Type: Si - Al WORST CASE CURRENT DENSITY:
Thickness: 11kÅ ± 1kÅ 1.47 x 105 A/cm2

Metallization Mask Layout


82C86H

A2 A1 A0 VCC B0 B1

B2

A3

B3
A4

B4

A5
B5

A6

A7 OE GND T B7 B6

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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