Features Description: CMOS Octal Bus Transceiver
Features Description: CMOS Octal Bus Transceiver
Features Description: CMOS Octal Bus Transceiver
Features Description
• Full Eight Bit Bi-Directional Bus Interface The Intersil 82C86H is a high performance CMOS Octal
Transceiver manufactured using a self-aligned silicon gate
• Industry Standard 8286 Compatible Pinout
CMOS process (Scaled SAJI IV). The 82C86H provides a full
• High Drive Capability eight-bit bi-directional bus interface in a 20 lead package. The
- B Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Transmit (T) control determines the data direction. The active
low output enable (OE) permits simple interface to the 80C86,
- A Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA
80C88 and other microprocessors. The 82C86H has gated
• Three-State Outputs inputs, eliminating the need for pull-up/pull-down resistors and
reducing overall system operating power dissipation.
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
• Gated Inputs
- Reduce Operating Power
Ordering Information
- Eliminate the Need for Pull-Up Resistors PART NUMBER
PACK- PKG.
• Single 5V Power Supply 5MHz 8MHz AGE TEMP. RANGE NO.
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA CP82C86H-5 CP82C86H 20 Ld 0oC to +70oC E20.3
PDIP
• Operating Temperature Range IP82C86H-5 IP82C86H -40oC to +85oC E20.3
- C82C86H . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC CS82C86H-5 CS82C86H 20 Ld 0oC to +70oC N20.35
- I82C86H . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC IS82C86H-5 IS82C86H
PLCC
-40oC to +85oC N20.35
- M82C86H . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
CD82C86H-5 CD82C86H 20 Ld 0oC to +70oC F20.3
CERDIP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 2977.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-317
82C86H
Pinouts
82C86H (PDIP, CERDIP) 82C86H (PLCC, CLCC) TRUTH TABLE
TOP VIEW TOP VIEW
T OE A B
X H Hi-Z Hi-Z
VCC
A2
A1
A0
B0
A0 1 20 VCC H L I O
3 2 1 20 19
A1 2 19 B0 L L O I
A2 3 18 B1 H = Logic One
A3 4 17 B2 A3 4 18 B1 L = Logic Zero
I = Input Mode
A4 5 16 B3 A4 5 17 B2
O = Output Mode
A5 6 15 B4 A5 6 16 B3 X = Don’t Care
A6 7 14 B5 Hi-Z = High Impedance
A6 7 15 B4
A7 8 13 B6
A7 8 14 B5 PIN NAMES
OE 9 12 B7
PIN DESCRIPTION
GND 10 11 T
9 10 11 12 13 A0-A7 Local Bus Data I/O Pins
GND
OE
B7
B6
T
B0-B7 System Bus Data I/O Pins
T Transmit Control Input
OE Active Low Output Enable
4-318
82C86H
I = C L ( dv ⁄ dt ) (EQ. 1)
A1 B1
A2 B2
Assuming that all outputs change state at the same time and
A3 B3 that dv/dt is constant;
A4 B4 (V CC × 80% ) (EQ. 2)
I = C L -------------------------------------
A5 B5
tR ⁄ tF
OE
T VCC VCC
P
Gated Inputs P
4-319
82C86H
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
II Input Leakage Current -10.0 10.0 µA VIN = GND or VCC DIP Pins 9, 11
ICCSB Standby Power Supply - 10 µA VIN = VCC or GND, VCC = 5.5V, Outputs Open
Current
NOTES:
1. VIH is measured by applying a pulse of magnitude = VIH(MIN) to one data input at a time and checking the corresponding device output for
a valid logical “1” during valid input high time. Control pins (T, OE) are tested separately with all device data input pins at VCC -0.4
2. Typical ICCOP = 1mA/MHz of read/ cycle time. (Example: 1.0µs read/write cycle time = 1mA).
Capacitance TA = +25oC
4-320
82C86H
NOTE 4
82C86H 82C86H-5
SYMBOL PARAMETER MIN MAX MAX UNITS TEST CONDITIONS
Inverting 5 30 35 ns
Non-Inverting 5 32 35 ns
82C86H 30 - - ns
82C86H-5 35 - - ns
NOTES:
1. All AC parameters tested as per test circuits and definitions in timing waveforms and test load circuits. Input rise and fall times are driven
at 1ns/V.
2. Input test signals must switch between VIL - 0.4V and VIH +0.4V.
3. A system limitation only when changing direction. Not a measured parameter.
4. 82C86H is available in commercial and industrial temperature ranges only. 82C86H-5 is available in commercial, industrial and military
temperature ranges.
Timing Waveform
TR, TF (6)
2.0V
INPUTS
0.8V
TEHEL (7)
OE
(1) (4)
TELOV (5)
TIVOV TEHOZ
VOH -0.1V 3.0V
OUTPUTS
VOL +0.1V 0.45V
NOTE: All timing measurements are made at 1.5V unless otherwise noted.
4-321
82C86H
B SIDE OUTPUTS
TELOV OUTPUT HIGH TELOV OUTPUT LOW TEHOZ OUTPUT LOW/HIGH
TIVOV LOAD CIRCUIT ENABLE LOAD CIRCUIT ENABLE LOAD CIRCUIT DISABLE LOAD CIRCUIT
Burn-In Circuits
MD82C86H CERDIP
VCC
R1 C1
F2 1 20
R1
F2 2 19 A
R1
F2 3 18 A
R1
F2 4 17 A
R1
F2 5 16 A
R1
F2 6 15 A VCC
R1
F2 7 14 A
R1 R2
F2 8 13 A
R1 A
9 12 A
R1 R3
10 11 VCC
4-322
82C86H
VCC C1
F2 F2 F2 F3
R5 R5 R5 R5
3 2 1 20 19
R5 R5
F2 4 18 F3
R5 R5
F2 5 17 F3
R5 R5
F2 6 16 F3
R5 R5
F2 15 F3
7
R5 R5
F2 8 14 F3
9 10 11 12 13
R4 R4 R5 R5
F0 F1 F3 F3
NOTES:
1. VCC = 5.5V ± 0.5V, GND = 0V
2. VIH = 4.5V ± 10%
3. VIL = -0.2V to 0.4V
4. R1 = 47kΩ ± 5%
5. R2 = 2.4kΩ ± 5%
6. R3 = 1.5kΩ ± 5%
7. R4 = 1kΩ ± 5%
8. R5 = 5kΩ ± 5%
9. C1 = 0.01µF minimum
10. F0 = 100kHz ± 10%
11. F1 = F0/2, F2 = F1/2, F3 = F2/2
4-323
82C86H
Die Characteristics
DIE DIMENSIONS: GLASSIVATION:
138.6 x 155.5 x 19 ± 1mils Type: SiO2
Thickness: 8kÅ ± 1kÅ
METALLIZATION:
Type: Si - Al WORST CASE CURRENT DENSITY:
Thickness: 11kÅ ± 1kÅ 1.47 x 105 A/cm2
A2 A1 A0 VCC B0 B1
B2
A3
B3
A4
B4
A5
B5
A6
A7 OE GND T B7 B6
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-324