www.DataSheet4U.

com

MAC8D, MAC8M, MAC8N

Preferred Device

Triacs
Silicon Bidirectional Thyristors
Designed for high performance full-wave ac control applications
where high noise immunity and high commutating di/dt are required.
http://onsemi.com
Features
• Blocking Voltage to 800 Volts TRIACS
• On-State Current Rating of 8.0 Amperes RMS at 100°C 8 AMPERES RMS
• Uniform Gate Trigger Currents in Three Quadrants 400 thru 800 VOLTS
• High Immunity to dv/dt − 250 V/ms minimum at 125°C
• Minimizes Snubber Networks for Protection
• Industry Standard TO-220AB Package MT2 MT1
• High Commutating di/dt − 6.5 A/ms minimum at 125°C G
• Pb−Free Packages are Available*

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) MARKING

DIAGRAM
Characteristic Symbol Value Unit
Peak Repetitive Off−State Voltage, (Note 1) VDRM, V
(TJ = −40 to 125°C, Sine Wave, VRRM
50 to 60 Hz, Gate Open)
MAC8D 400
MAC8M 600
MAC8N 800 MAC18xG
AYWW
On-State RMS Current, IT(RMS) 8.0 A TO−220AB
(Full Cycle Sine Wave, 60 Hz, TC = 100°C) 1 CASE 221A−09
2
3 STYLE 4
Peak Non-Repetitive Surge Current ITSM 80 A
(One Full Cycle Sine Wave,
60 Hz, TJ = 125°C)
Circuit Fusing Consideration (t = 8.3 ms) I2t 26 A2s x = D, M, or N
A = Assembly Location
Peak Gate Power PGM 16 W Y = Year
(Pulse Width ≤ 1.0 ms, TC = 80°C) WW = Work Week
G = Pb−Free Package
Average Gate Power PG(AV) 0.35 W
(t = 8.3 ms, TC = 80°C)

Operating Junction Temperature Range TJ −40 to +125 °C

ORDERING INFORMATION
Storage Temperature Range Tstg −40 to +150 °C
Device Package Shipping
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not MAC8D TO−220AB 50 Units / Rail
normal operating conditions) and are not valid simultaneously. If these limits are
MAC8DG TO−220AB 50 Units / Rail
exceeded, device functional operation is not implied, damage may occur and (Pb−Free)
reliability may be affected.
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking MAC8M TO−220AB 50 Units / Rail
voltages shall not be tested with a constant current source such that the MAC8MG TO−220AB 50 Units / Rail
voltage ratings of the devices are exceeded. (Pb−Free)
MAC8N TO−220AB 50 Units / Rail
MAC8NG TO−220AB 50 Units / Rail
(Pb−Free)

Preferred devices are recommended choices for future use

and best overall value.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2005 1 Publication Order Number:

December, 2005 − Rev. 5 MAC8D/D
 MAC8D, MAC8M, MAC8N

THERMAL CHARACTERISTICS
Characteristic Symbol Value Unit
Thermal Resistance, Junction−to−Case RqJC 2.2 °C/W
Thermal Resistance, Junction−to−Ambient RqJA 62.5 °C/W
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds TL 260 °C

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted; Electricals apply in both directions)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25°C IDRM, − − 0.01 mA
TJ = 125°C IRRM − − 2.0
ON CHARACTERISTICS
Peak On-State Voltage (Note 2), (ITM = ± 11 A Peak) VTM − 1.2 1.6 V
Gate Trigger Current (Continuous DC) (VD = 12 V, RL = 100 W) IGT mA
MT2(+), G(+) 5.0 13 35
MT2(+), G(−) 5.0 16 35
MT2(−), G(−) 5.0 18 35

Holding Current, (VD = 12 V, Gate Open, Initiating Current = ±150 mA) IH − 20 40 mA

Latching Current (VD = 24 V, IG = 35 mA), MT2(+), G(+); MT2(−), G(−) IL − 20 50 mA
MT2(+), G(−) − 30 80

Gate Trigger Voltage (VD = 12 V, RL = 100 W) VGT V

MT2(+), G(+) 0.5 0.69 1.5
MT2(+), G(−) 0.5 0.77 1.5
MT2(−), G(−) 0.5 0.72 1.5

Gate Non−Trigger Voltage (VD = 12 V, RL = 100 W, TJ = 125°C) VGD V

MT2(+), G(+); MT2(+), G(−); MT2(−), G(−) 0.2 − −
DYNAMIC CHARACTERISTICS
Rate of Change of Commutating Current See Figure 10.(VD = 400 V, ITM = 4.4 A, (di/dt)c 6.5 − − A/ms
Commutating dv/dt = 18 V/ms,Gate Open, TJ = 125°C, f = 250 Hz, No Snubber)
CL = 10 mF
LL = 40 mH
Critical Rate of Rise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform, dv/dt 250 − − V/ms
Gate Open, TJ = 125°C)
2. Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%.

http://onsemi.com
2
 MAC8D, MAC8M, MAC8N

Voltage Current Characteristic of Triacs

(Bidirectional Device)
+ Current

Quadrant 1
MainTerminal 2 +
Symbol Parameter VTM
VDRM Peak Repetitive Forward Off State Voltage
on state
IDRM Peak Forward Blocking Current IH
VRRM Peak Repetitive Reverse Off State Voltage IRRM at VRRM
IRRM Peak Reverse Blocking Current
VTM Maximum On State Voltage off state + Voltage
IH Holding Current IH IDRM at VDRM

Quadrant 3
VTM
MainTerminal 2 −

Quadrant Definitions for a Triac

MT2 POSITIVE
(Positive Half Cycle)
+

(+) MT2 (+) MT2

Quadrant II (−) IGT (+) IGT Quadrant I

GATE GATE

MT1 MT1

REF REF

IGT − + IGT

(−) MT2 (−) MT2

Quadrant III (−) IGT (+) IGT Quadrant IV

GATE GATE

MT1 MT1

REF REF

−
MT2 NEGATIVE
(Negative Half Cycle)

All polarities are referenced to MT1.

With in−phase signals (using standard AC lines) quadrants I and III are used.

http://onsemi.com
3
 MAC8D, MAC8M, MAC8N

125 12
DC

PAV, AVERAGE POWER (WATTS)

10
TC, CASE TEMPERATURE (°C)

120
180°
α = 120, 90, 60, 30°
8
115 120°

α = 180° 6
110
60°
4
DC 90°
105 α = 30°
2

100 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
IT(RMS), RMS ON-STATE CURRENT (AMP) IT(RMS), ON-STATE CURRENT (AMP)

Figure 1. RMS Current Derating Figure 2. On-State Power Dissipation

r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)

100 1

TYPICAL AT
TJ = 25°C

MAXIMUM @ TJ = 125°C
0.1
I T, INSTANTANEOUS ON-STATE CURRENT (AMP)

10
0.01
0.1 1 10 100 1000 1·10 4
t, TIME (ms)

Figure 4. Thermal Response

MAXIMUM @ TJ = 25°C 40
1
35
I H, HOLD CURRENT (mA)

30
MT2 POSITIVE
25

20

15
MT2 NEGATIVE
10

0.1 5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 −50 −30 −10 10 30 50 70 90 110 130
VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)

Figure 3. On-State Characteristics Figure 5. Hold Current Variation

http://onsemi.com
4
 MAC8D, MAC8M, MAC8N

100 1
Q2

VGT, GATE TRIGGER VOLTAGE (VOLT)

0.95
IGT, GATE TRIGGER CURRENT (mA)

Q2 0.9
Q3
0.85
Q3 0.8
Q1 075
10 0.7 Q1
0.65
0.6
0.55
0.5
0.45
1 0.4
−50 −30 −10 10 30 50 70 90 110 130 −50 −30 −10 10 30 50 70 90 110 130
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 6. Gate Trigger Current Variation Figure 7. Gate Trigger Voltage Variation
dv/dt , CRITICAL RATE OF RISE OF OFF-STATE VOLTAGE(V/μ s)

5000 100
4.5K

(dv/dt) c , CRITICAL RATE OF RISE OF

COMMUTATING VOLTAGE(V/μ s)
4K
3.5K
MT2 NEGATIVE
3K TJ = 125°C 100°C 75°C
2.5K 10
2K
1.5K 1
f=
tw 2 tw
1K
6f ITM
500 MT2 POSITIVE (di/dt)c =
VDRM 1000

0 1
1 10 100 1000 10 15 20 25 30 35 40 45 50 55 60
RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS) (di/dt)c, RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)

Figure 8. Critical Rate of Rise of Off-State Figure 9. Critical Rate of Rise of

Voltage (Exponential) Commutating Voltage

LL 1N4007
200 VRMS
ADJUST FOR MEASURE
ITM, 60 Hz VAC I
TRIGGER CONTROL

CHARGE
TRIGGER CONTROL −
CHARGE 200 V
+
MT2
1N914 51 W
NON-POLAR MT1
CL G

Note: Component values are for verification of rated (di/dt)c. See AN1048 for additional information.

Figure 10. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)

http://onsemi.com
5
 MAC8D, MAC8M, MAC8N

PACKAGE DIMENSIONS

TO−220AB
PLASTIC
CASE 221A−09
ISSUE AA

NOTES:
SEATING
−T− PLANE 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
B F C 2. CONTROLLING DIMENSION: INCH.
T 3. DIMENSION Z DEFINES A ZONE WHERE ALL
S BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4
INCHES MILLIMETERS
Q A DIM MIN MAX MIN MAX
A 0.570 0.620 14.48 15.75
1 2 3 B 0.380 0.405 9.66 10.28
U
C 0.160 0.190 4.07 4.82
H D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
K G 0.095 0.105 2.42 2.66
Z H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L R L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
V J Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
G S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
D U 0.000 0.050 0.00 1.27
N V 0.045 −−− 1.15 −−−
Z −−− 0.080 −−− 2.04

STYLE 4:
PIN 1. MAIN TERMINAL 1
2. MAIN TERMINAL 2
3. GATE
4. MAIN TERMINAL 2

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: http://onsemi.com
Literature Distribution Center for ON Semiconductor USA/Canada
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Order Literature: http://www.onsemi.com/litorder
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 For additional information, please contact your
Email: orderlit@onsemi.com Phone: 81−3−5773−3850 local Sales Representative.

http://onsemi.com MAC8D/D
6