SPC570S40E1, SPC570S40E3,

SPC570S50E1, SPC570S50E3
32-bit Power Architecture® microcontroller for automotive ASILD
applications
Datasheet - production data

– Boot time MBIST and LBIST for latent

faults
– Check of safety mechanisms availability
and error reaction path functionality by
eTQFP100 (14 x 14 x 1.0 mm) eTQFP64 (10 x 10 x 1.0 mm)
dedicated mechanisms
– Safety of the periphery by application-level
Features measures supported by replicated
• AEC-Q100 qualified peripheral bridges and by LBIST
• High performance e200z0h dual core – Further measures on dedicated peripherals
– 32-bit Power Architecture technology CPU (e.g. ADC supervisor)
– Core frequency as high as 80 MHz – Junction temperature sensor
– Single issue 4-stage pipeline in-order – 8-region system memory protection unit
execution core (SMPU) with process ID support (tasks
isolation)
– Variable Length Encoding (VLE)
– Enhanced SW watchdog
• Up to 544 KB (512 KB code + 32 KB data,
– Cyclic redundancy check (CRC) unit
suitable for EEPROM emulation) on-chip flash
memory: supports read during program and • Dual phase-locked loops with stable clock
erase operations, and multiple blocks allowing domain for peripherals and FM modulation
EEPROM emulation domain for computational shell
• Up to 48 KB on-chip general-purpose SRAM • Nexus Class 3 debug and trace interface
• Multi-channel direct memory access controller • Communication interfaces
(eDMA paired in lockstep) with 16 channels – 2 LINFlexD modules, 3 deserial serial
• Comprehensive new generation ASILD safety peripheral interface (DSPI) modules, and
concept Up to 2 FlexCAN interfaces with 32
message buffers each
– Safety of bus masters (core+INTC, DMA)
by delayed lockstep approach • On-chip CAN/UART Bootstrap loader with Boot
– Safety of storage (Flash, SRAM) by mainly Assisted Flash (BAF). Physical Interface (PHY)
ECC can be
– Safety of the data path to storage and – UART and CAN
periphery by mainly End-to-End EDC (E2E • 2 enhanced 12-bit SAR analog converters
EDC) – 1.5 µs conversion time (12 MHz)
– Clock and power, generation and – 16 physical channels (fully shared between
distribution, supervised by dedicated the 2 SARADC units)
monitors – Supervisor ADC concept
– Fault Collection and Control Unit (FCCU) – Programmable Cross Triggering Unit (CTU)
for collection and reaction to failure
• Single 3.3 V or 5 V voltage supply
notifications
• 4 general purpose eTimer units (6 channels
– Memory Error Management Unit (MEMU)
each)
for collection and reporting of error events
in memories • Junction temperature range -40 °C to 150 °C
(165 °C grade optional)

January 2018 DocID024492 Rev 7 1/75

This is information on a product in full production. www.st.com
Contents SPC570S40Ex, SPC570S50Ex

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Feature overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Package pads/pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 Electromagnetic compatibility (EMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.7.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.7.2 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.8 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.9 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.9.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.9.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.9.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.10 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.11 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 41
4.11.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 41
4.12 PMU monitor specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.12.1 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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SPC570S40Ex, SPC570S50Ex Contents

4.12.2 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.13 Platform Flash controller electrical characteristics . . . . . . . . . . . . . . . . . . 43
4.14 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.15 PLL0/PLL1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.16 External oscillator (XOSC) electrical characteristics . . . . . . . . . . . . . . . . 47
4.17 Internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . 50
4.18 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.18.2 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.19 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.20 JTAG interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.21 DSPI CMOS master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.21.1 Classic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.21.2 Modified timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.1 eTQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.2 eTQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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List of tables SPC570S40Ex, SPC570S50Ex

List of tables

Table 1. SPC570Sx device feature

summary (Family Superset Configuration)6
Table 2. SPC570S40Ex, SPC570S50Ex device configuration differences . . . . . . . . . . . . . . . . . . . . 8
Table 3. SPC570Sx series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. eTQFP64 and eTQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Radiated emissions testing specification, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. Device operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Thermal characteristics for eTQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. Thermal characteristics for eTQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. I/O pad specification descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 15. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Weak configuration I/O output characteristics, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 17. Medium configuration I/O output characteristics, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. Strong configuration I/O output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19. Very Strong configuration I/O output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20. I/O output characteristics for pads 4, 9, 11, 55, 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 22. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 23. Trimmed (PVT) values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 24. RWSC settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 25. Flash memory program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 26. Flash memory Life Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 27. PLL1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 28. PLL0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 29. External Oscillator electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 30. Selectable load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 31. Internal RC oscillator electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 32. ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 33. ADC pin specification, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 34. ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 35. Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 36. JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 37. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0 . . . . . . . . . . 57
Table 38. DSPI CMOS master modified timing (full duplex and output only) –
MTFE = 160
Table 39. eTQFP64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 40. eTQFP100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 41. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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SPC570S40Ex, SPC570S50Ex List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. eTQFP 64-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. eTQFP 100-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 6. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 7. Recommended parasitics on board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 8. Crystal/Resonator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 9. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 10. ADC characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 11. Input equivalent circuit (12- bit SAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 12. JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 13. JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 14. JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 15. DSPI CMOS master mode – classic timing, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 16. DSPI CMOS master mode – classic timing, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 17. DSPI PCS strobe (PCSS) timing (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 18. DSPI CMOS master mode – modified timing, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 19. DSPI CMOS master mode – modified timing, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 20. DSPI PCS strobe (PCSS) timing (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 21. eTQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 22. eTQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 23. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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Introduction SPC570S40Ex, SPC570S50Ex

1 Introduction

1.1 Document overview

This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the device. To
ensure a complete understanding of the device functionality, refer also to the device
reference manual and errata sheet.

1.2 Description
The SPC570Sx is a family of next generation microcontrollers built on the Power
Architecture embedded category.
The SPC570Sx family of 32-bit microcontrollers is the latest achievement in integrated
automotive application controllers. It belongs to an expanding family of automotive-focused
products designed to address the next wave of Chassis and Safety electronics applications
within the vehicle. The advanced and cost-efficient host processor core of this automotive
controller family complies with the Power Architecture embedded category and only
implements the VLE (variable-length encoding) APU, providing improved code density. It
operates at speeds of up to 80 MHz and offers high performance processing optimized for
low power consumption. It capitalizes on the available development infrastructure of current
Power Architecture devices and is supported with software drivers, operating systems and
configuration code to assist with users implementations.

Table 1. SPC570Sx device feature

summary (Family Superset Configuration)
Feature Description

Process 55 nm
Core e200z0h
Number of main cores 1
Main processor Number of checker cores 1
VLE Yes
Main processor frequency 80 MHz(1)
Interrupt controllers (including interrupt controller checker) 1
Software watchdog timer 1
1 AUTOSAR® STM
System timers
1 PIT with four 32-bit channels
DMA (including DMA checker) 1
DMA channels 16
SMPU Yes (8 regions)(2)
System SRAM Up to 48 KB
Code flash memory Up to 512 KB

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SPC570S40Ex, SPC570S50Ex Introduction

Table 1. SPC570Sx device feature

summary (Family Superset Configuration) (continued)
Feature Description

Data flash memory (suitable for EEPROM emulation) 32 KB

UTEST flash memory 8 KB
Boot assist flash (BAF) 8 KB
CRC 1
LINFlexD Up to 2
FlexCAN Up to 2
DSPI 3
eTimer 4 x 6 channels
ADC (SAR) 2(3)
CTU (Cross Triggering Unit) 1
Temperature sensor 1
Self-test control unit (memory and logic BIST) 1
FCCU 1
MEMU 1
PLL Dual PLL with FM
Nexus 3(4)
Sequence processing unit (SPU) 1
5 V(5)
External power supplies
3.3 V(5)
−40 to 150 °C
Junction temperature
165 °C grade optional (6)
Device SPC570SxxE3 eTQFP100
Packages
Device SPC570SxxE1 eTQFP64
1. Includes user programmable CPU core and one safety core. The two e200z0h processors in the lockstep
pair run at 80 MHz. The e200z0h is compatible with the Power Architecture embedded specification.
2. SMPU with process ID support extension
3. One ADC can be used as supervisor ADC
4. Including trace for the crossbar masters (data & instruction trace on core and data trace on eDMA). 4 MDO
pin Nexus trace port.
5. All I/Os can be supplied at 3.3 V or 5 V (mutually exclusive)
6. Refer to technical note "SPC570S family - High Temperature "D" Grade (DocID031416 - TN1262)" for
associated specification limitation.

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Introduction SPC570S40Ex, SPC570S50Ex

Table 2. SPC570S40Ex, SPC570S50Ex device configuration differences

SPC570S40 SPC570S50
(full option configuration) (full option configuration)

Flash 256 KB(1) 512 KB

RAM 32 KB(2) 48 KB
CAN 1(3) 2
Others aligned to the SPC570Sx device feature summary (Family Superset Configuration) described in Table 1
1. Flash blocks excluded on SPC570S40:
128K Block 0 [0x0100_0000 … 0x0101_FFFF]
128K Block 1 [0x0102_0000 … 0x0103_FFFF]
2. SRAM area excluded on SPC570S40
[0x4000_8000…0x4000_BFFF]
3. FlexCAN1 excluded on SPC570S40

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SPC570S40Ex, SPC570S50Ex Introduction

1.3 Feature overview

On-chip modules within the SPC570Sx include the following features:
• 2 main CPUs, single-issue, 32-bit CPU core complexes (e200z0h), running in lockstep
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length encoding (VLE), encoding a
mix of 16-bit and 32-bit instructions, for code size footprint reduction
• Up to 544 KB (512 KB code + 32 KB data, suitable for EEPROM emulation) on-chip
flash memory: supports read during program and erase operations, and multiple blocks
allowing EEPROM emulation
• Up to 48 KB on-chip general-purpose SRAM
• Multi-channel direct memory access controller (eDMA paired in lockstep)
– 16 channels per eDMA
• Interrupt controller (INTC) with dedicated interrupt source channels, including software
interrupts and 32 priority levels
• Dual phase-locked loops with stable clock domain for peripherals and frequency
modulation domain for computational shell
• Crossbar switch architecture for concurrent access to peripherals, flash memory, or
SRAM from multiple bus masters with end-to-end ECC
• System integration unit lite (SIUL2)
• Boot Assist Flash (BAF) supports factory programming using serial bootload through
‘UART Serial Boot Mode Protocol’. Physical Interface (PHY) can be
– UART / LIN
– CAN
• Enhanced analog-to-digital converter system
– 2 separate 12-bit SAR analog converters
– 1.5 µs conversion time (at 12 MHz)
– 16 physical channels
• Temperature sensor
– Range −40 to +150 °C
– Sensitivity approximately 5.14 mV/°C
• STCU2
– Support for Logic BIST and Memory BIST at power on
– ASIL D
• 3 deserial serial peripheral interface (DSPI) modules
• 2 LIN and UART communication interface (LINFlexD) modules
– LINFlexD_0 (master/slave)
– LINFlexD_1 (master)
• Up to 2 FlexCAN modules
• Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with partial
support for 2010 standard
• Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1)
• On-chip voltage regulator controller manages the supply voltage down to 1.2 V for core
logic

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Block diagram SPC570S40Ex, SPC570S50Ex

2 Block diagram

Figure 1 shows the top-level block diagram.

Figure 1. Block diagram

Nexus3 JTAGM JTAGC DCI SPU

Nexus 2+ RCCU Nexus 2+

DMACHMUX
DMACHMUX RCCU
(lockstep)
INTC Power PC
Power PC RCCU
INTC e200z0h
e200z0h (lockstep)
DMA (lockstep)
DMA RCCU
(lockstep)

RCCU

e2eEDC e2eEDC e2eEDC

XBAR
XBIC

RAM
Flash controller
controller

PBRIDGE_1 AIC1 AIC0 PBRIDGE_0

RAM Flash

eTimer_2 DSPI_2 CMU_1 XBAR SMPU XBIC SRAM PFLASHC INTC_0

eTimer_3 FCCU CMU_2 SWT STM DMA_0 eTimer_0 eTimer_1 CTU

FlexCAN_1 LINFlexD_1 CMU_3

SARADC_0 SARADC_B FlexCAN_0 STCU JTAGM PMCDIG

DSPI_0 DSPI_1 LINFlexD_0 MEMU CRC MC_CGM

DMA
MC_RGM MC_ME CHMUX_0 PIT MC_PCU SSCM

PLL_DIG_0 CMU_0 SIUL JDC IRCOSC_DIG XOSC_DIG

CFLASH_INF WKPU

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SPC570S40Ex, SPC570S50Ex Block diagram

Table 3 summarizes the functions of all blocks present in the SPC570Sx series of
microcontrollers. Please note that the presence and number of blocks vary by device and
package.

Table 3. SPC570Sx series block summary

Block Function

e200z0 CPU Allows single clock instruction execution

Analog-to-digital converter (ADC) Multi-channel, 12-bit analog-to-digital converter
Enables synchronization of ADC conversions with a timer event from the
Cross triggering unit (CTU)
eMIOS or from the PIT
Deserial serial peripheral Provides a synchronous serial interface for communication with external
interface (DSPI) devices
Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host
(eDMA) processor via 16 programmable channels.
Allows to route a defined number of DMA peripheral sources to the DMA
DMACHMUX
channels
Flash memory Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area
Supports the standard CAN communications protocol
network)
PLL0 Output independent of core clock frequency
Frequency-modulated phase- Generates high-speed system clocks and supports programmable frequency
locked loop (PLL1) modulation
Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests
AIPS System bus to peripheral bus interface
RAM controller Acts as an interface between the system bus and the integrated system RAM
System RAM Supports read/write accesses mapped to the SRAM memory from any master
Flash memory controller Acts as an interface between the system bus and the Flash memory module
Up to 512 KB of programmable, non-volatile Flash memory for code and 32 KB
Flash memory
for data
IRCOSC Controls the internal 16 MHz RC oscillator system
Controls the on-chip oscillator (XOSC) and provides the register interface for
XOSC
the programmable features
JTAG Master Provides software the option to write data for driving JTAG
JTAG Data Communication Provides the capability to move register data between the IPS and JTAG
Module domains
Programs a set of Flash memory access protections, based on user
PASS
programmable passwords
Provides an on-device trigger functions similar to those found on a logic
Sequence Processing Unit
analyzer
Manages a high number of LIN (Local Interconnect Network protocol)
LINFlex controller
messages efficiently with a minimum of CPU load

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Block diagram SPC570S40Ex, SPC570S50Ex

Table 3. SPC570Sx series block summary (continued)

Block Function

Clock generation module Provides logic and control required for the generation of system and peripheral
(MC_CGM) clocks
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
Mode entry module (MC_ME)
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
MC_PMC Contains registers that enable/disable the various voltage monitors
Reset generation module Centralizes reset sources and manages the device reset sequence of the
(MC_RGM) device
Provides hardware access control for all memory references generated in a
Memory protection unit (MPU)
device
Has six 16-bit general purpose counter, where each counter can be used as
eTimer
input capture or output compare function
Collects fault event notification from the rest of the system and translates them
FCCU
into internal and/or external system reactions
RCCU Compares input signals and issues an alarm in the case of a mismatch
Collects and reports error events associated with ECC (Error Correction Code)
MEMU
logic used on SRAM, DMA RAM and Flash memory
Verifies the integrity of the attribute information for crossbar transfers and
XBIC
signals the Fault Collection and Control Unit (FCCU) when an error is detected
STCU2 Handles the BIST procedure
CRC Controls the computation of CRC, off-loading this work from the CPU
Protects several registers against accidental writing, locking their value till the
RegProt
next reset phase
Temperature sensor Monitors the device temperature
Debug Control Interface Provides debug features for the MCU
Monitor a variety of signals including addresses, data, control signals, status
Nexus Port Controller
signals, etc.
Monitors the system bus and provides real-time trace information to debug or
Nexus Multimaster Trace Client
development tools
Periodic interrupt timer (PIT) Produces periodic interrupts and triggers
Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integration unit (SIUL) of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
Provides system configuration and status data (such as memory size and
System status configuration
status, device mode and security status), device identification data, debug
module (SSCM)
status port enable and selection, and bus and peripheral abort enable/disable
Provides a set of output compare events to support AUTOSAR and operating
System timer module (STM)
system tasks
System watchdog timer (SWT) Provides protection from runaway code

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SPC570S40Ex, SPC570S50Ex Block diagram

Table 3. SPC570Sx series block summary (continued)

Block Function

The wakeup unit supports up to 18 external sources that can generate

Wakeup unit (WKPU) interrupts or wakeup events, of which 1 can cause non-maskable interrupt
requests or wakeup events.
Supports simultaneous connections between two master ports and three slave
Crossbar (XBAR) switch ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.

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Package pinouts and signal descriptions SPC570S40Ex, SPC570S50Ex

3 Package pinouts and signal descriptions

3.1 Package pinouts

The available eTQFP pinouts are provided in the following figures. For pin signal
descriptions, please refer to the device reference manual.

Figure 2. eTQFP 64-pin configuration(a)

VDD_HV_IO

VDD_HV_IO
PD[15]
PD[14]

PD[10]
PE[15]
PE[14]

PD[11]
PE[11]

PD[9]
PE[8]
PE[7]
PE[6]
PE[5]
PE[3]
PE[2]
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
FCCU_F0 1 48 PD[8]
PA[0] 2 47 PD[7]
PA[3] 3 46 VDD_HV_IO
PA[4] 4 45 VDD_LV
PA[7] 5 44 PORST
PA[8] 6 43 TESTMODE
PA[9] 7 42 TCK
PA[11] 8 41 PC[15]
PA[12] 9 eTQFP64 Top view 40 TDO
PA[13] 10 39 TMS
PA[14] 11 38 TDI
VDD_LV 12 37 VDD_HV_OSC_PMC
VDD_HV_IO 13 36 XTAL
PB[3] 14 35 EXTAL
PB[4] 15 34 VDD_LV
PB[5] 16 33 VDD_HV_IO
17
18
19
20
21
22
23
24
25

32
26
27
28
29
30
31
PB[6]
PB[7]

PB[10]
PB[11]
PB[14]
PB[15]
PC[1]

PC[2]
PC[3]
PC[4]
PC[7]
PC[8]
PC[11]
FCCU_F1
VREFH_ADC

VDD_HV_ADC_TSENS

Note:
Availability of port pin alternate functions depends on product selection.

a. All eTQFP64 information is indicative and must be confirmed during silicon validation.

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SPC570S40Ex, SPC570S50Ex Package pinouts and signal descriptions

Figure 3. eTQFP 100-pin configuration

VDD_HV_IO

VDD_HV_IO

PD[15]
PD[14]
PD[13]
PD[12]

PD[10]
PE[15]
PE[14]
PE[13]
PE[12]

PE[10]

PD[11]
PE[11]

PD[9]
PE[9]
PE[8]
PE[7]
PE[6]
PE[5]
PE[4]
PE[3]
PE[2]

PE[1]
PE[0]
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
FCCU_F0 1 75 PD[8]
PA[0] 2 74 PD[7]
PA[1] 3 73 PD[6]
PA[2] 4 72 PD[5]
PA[3] 5 71 PD[4]
PA[4] 6 70 PD[3]
PA[5] 7 69 PD[2]
PA[6] 8 68 VDD_LV
PA[7] 9 67 PD[1]
PA[8] 10 66 PORST
PA[9] 11 65 PD[0]
PA[10] 12 64 TESTMODE
PA[11] 13 63 TCK
PA[12] 14 eTQFP100 62 PC[15]
PA[13] 15 61 TDO
PA[14] 16 Top view 60 TMS
PA[15] 17 59 TDI
PB[0] 18 58 PC[14]
VDD_LV 19 57 PC[13]
VDD_HV_IO 20 56 PC[12]
PB[1] 21 55 VDD_HV_OSC_PMC
PB[2] 22 54 XTAL
PB[3] 23 53 EXTAL
PB[4] 24 52 VDD_LV
PB[5] 25 51 VDD_HV_IO
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PB[6]
PB[7]
PB[8]

PB[9]
PB[10]
PB[11]
PB[12]
PB[13]
PB[14]
PB[15]
PC[0]
PC[1]

PC[2]
PC[3]
PC[4]
PC[5]
PC[6]
PC[7]
PC[8]
PC[9]
PC[10]
PC[11]
FCCU_F1
VREFH_ADC

VDD_HV_ADC_TSENS

Note:
Availability of port pin alternate functions depends on product selection.

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3.2 Pin descriptions

The following sections provide signal descriptions and related information about the
functionality and configuration of the SPC570Sx devices.
For information on the signal descriptions and related information about the functionality and
configuration of the SPC570Sx devices, refer to the "Signal description” chapter in the
devices’ reference manual.

3.3 Package pads/pins

Table 4 shows the eTQFP64 and eTQFP100 pinouts. The default reset state for all the pins
associated with a programmable alternate function is GPIO.
Note: Nexus pins can be enabled via JTAG during the reset phase

Table 4. eTQFP64 and eTQFP100 pinout

Pin No. Alternate functions
eTQFP100
eTQFP64

Port
Pad Type AF1 AF2 AF3 AF4
pin

— FCCU_F0 1 1 IO FCCU_F0(1)
DSPI 0 - DSPI 1 - Timer 0 -
PA[0] PAD[0] 2 2 IO Ext. INT 0
CS 0 CS 1 ch. 0
DSPI 1 - Timer 0 - Nexus Timer 1 -
PA[1] PAD[1] — 3 IO
CS 1 ch. 0 EVTI ch. 0
DSPI 2 - DSPI 0 - Nexus Timer 1 -
PA[2] PAD[2] — 4 IO
CS 1 CS 4 EVTO ch. 1
DSPI 0 - Timer 0 - DSPI 1 -
PA[3] PAD[3] 3 5 IO Ext. INT 1
CLK ch. 0 CLK
DSPI 0 - Timer 0 - DSPI 1 -
PA[4] PAD[4] 4 6 IO NMI
Serial Data ch. 1 Serial Data
LINFlex 1 - Timer 0 - Nexus Timer 1 -
PA[5] PAD[5] — 7 IO
TX ch. 1 MCK 0 ch. 2
LINFlex 1 - Timer 0 - Nexus Timer 1 -
PA[6] PAD[6] — 8 IO
RX ch. 2 MDO 0 ch. 3
DSPI 0 - Timer 0 - DSPI 1 -
PA[7] PAD[7] 5 9 IO —
Serial Data ch. 2 Serial Data
DSPI 0 - DSPI 2 - LINFlex 1 - Timer 0 -
PA[8] PAD[8] 6 10 IO
CS 1 CS 0 TX ch. 1
DSPI 0 - DSPI 0 - LINFlex 1 - Timer 0 -
PA[9] PAD[9] 7 11 IO
CS 2 CS 7 RX ch. 2
DSPI 1 - Nexus
PA[10] PAD[10] — 12 IO — Ext. INT 3
CS 1 MDO 1

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Table 4. eTQFP64 and eTQFP100 pinout (continued)

Pin No. Alternate functions

eTQFP100
eTQFP64
Port
Pad Type AF1 AF2 AF3 AF4
pin

DSPI 0 - DSPI 0 - Timer 0 -

PA[11] PAD[11] 8 13 IO Ext. INT 4
CS 3 CS 5 ch. 3
LINFlex 0 - FlexCAN 1 - LINFlex 1 - Timer 0 -
PA[12] PAD[12] 9 14 IO
RX RX RX ch. 3
LINFlex 0 - FlexCAN 1 - LINFlex 1 - Timer 0 -
PA[13] PAD[13] 10 15 IO
TX TX TX ch. 4
Timer 0 - DSPI 1 - Timer 0 -
PA[14] PAD[14] 11 16 IO Ext. INT 3
ch. 4 CS 1 ch. 5
FlexCAN 1 - Timer 1 - Nexus Timer 1 -
PA[15] PAD[15] — 17 IO
RX ch. 0 MDO 2 ch. 4
FlexCAN 1 - Timer 1 - Nexus Timer 1 -
PB[0] PAD[16] — 18 IO
TX ch. 1 MDO 3 ch. 5
— VDD_LV 12 19 PW —
— VDD_HV_IO 13 20 PWB20 —
Timer 1 - DSPI 0 - Nexus DSPI 1 -
PB[1] PAD[17] — 21 IO
ch. 5 CS 6 MSEO 0 CS 0
Timer 0 - FlexCAN 0 -
PB[2] PAD[18] — 22 IN/ANA ADC ch. 15 Ext. INT 3
ch. 4 RX
Timer 0 - Timer 1 - DSPI 0 -
PB[3] PAD[19] 14 23 IN/ANA ADC ch. 9
ch. 0 ch. 0 Serial Data
Timer 0 - Timer 1 - DSPI 1 -
PB[4] PAD[20] 15 24 IN/ANA ADC ch. 8
ch. 1 ch. 1 Serial Data
Timer 0 - Timer 1 - DSPI 2 -
PB[5] PAD[21] 16 25 IN/ANA ADC ch. 7
ch. 2 ch. 2 Serial Data
Timer 0 - Timer 1 -
PB[6] PAD[22] 17 26 IN/ANA ADC ch. 6 —
ch. 3 ch. 3
Timer 0 - Timer 1 -
PB[7] PAD[23] 18 27 IN/ANA Ext. INT 0 ADC ch. 5
ch. 4 ch. 4
Timer 0 - FlexCAN 1 -
PB[8] PAD[24] — 28 IN/ANA ADC ch.14 Ext. INT 4
ch. 5 RX
— VREFH_ADC 19 29 REF —
Timer 2 - LINFlex 0 -
PB[9] PAD[25] — 30 IN/ANA ADC ch. 13 Ext. INT 5
ch. 3 RX
Timer 0 - Timer 1 -
PB[10] PAD[26] 20 31 IN/ANA Ext. INT 1 ADC ch. 4
ch. 5 ch. 5
Timer 1 - Timer 0 -
PB[11] PAD[27] 21 32 IN/ANA Ext. INT 2 ADC ch. 3
ch. 4 ch. 4

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Table 4. eTQFP64 and eTQFP100 pinout (continued)

Pin No. Alternate functions

eTQFP100
eTQFP64
Port
Pad Type AF1 AF2 AF3 AF4
pin

Timer 2 - Timer 1 - LINFlex 1 -

PB[12] PAD[28] — 33 IN/ANA ADC ch. 12
ch. 4 ch. 5 RX
Timer 2 - Timer 3 -
PB[13] PAD[29] — 34 IN/ANA ADC ch. 11 NMI
ch. 5 ch. 0
Timer 2 - Timer 3 - Timer 2 -
PB[14] PAD[30] 22 35 IN/ANA ADC ch. 2
ch. 0 ch. 1 ch. 1
Timer 2 - Timer 3 - Timer 2 -
PB[15] PAD[31] 23 36 IN/ANA ADC ch. 1
ch. 1 ch. 2 ch. 2
Timer 1 - Timer 3 -
PC[0] PAD[32] — 37 IN/ANA ADC ch. 10 Ext. INT 0
ch. 0 ch. 3
Timer 2 - Timer 3 - Timer 2 -
PC[1] PAD[33] 24 38 IN/ANA ADC ch. 0
ch. 2 ch. 4 ch. 4
— VDD_HV_ADC_TSENS 25 39 PW —
Timer 0 - DSPI 2 - FlexCAN 1 - FlexCAN 0 -
PC[2] PAD[34] 26 40 IO
ch. 5 CS 1 RX RX
Timer 1 - DSPI 2 - FlexCAN 1 - FlexCAN 0 -
PC[3] PAD[35] 27 41 IO
ch. 0 CS 2 TX TX
Timer 1 - DSPI 1 - FlexCAN 1 -
PC[4] PAD[36] 28 42 IO Ext. INT 1
ch. 1 CS 0 RX
DSPI 1 - Timer 1 - FlexCAN 1 -
PC[5] PAD[37] — 43 IO Nexus RDY
CS 0 ch. 2 TX
DSPI 1 - Timer 1 - DSPI 2 - DSPI 0 -
PC[6] PAD[38] — 44 IO
Serial Data ch. 3 CS 4 Serial Data
Timer 1 - DSPI 1 - DSPI 2 - DSPI 0 -
PC[7] PAD[39] 29 45 IO
ch. 2 Serial Data CS 5 CS 0
Timer 1 - DSPI 1 - DSPI 2 - DSPI 0 -
PC[8] PAD[40] 30 46 IO
ch. 3 Serial Data CS 6 CS 1
DSPI 1 - Timer 1 - DSPI 2 - DSPI 0 -
PC[9] PAD[41] — 47 IO
Serial Data ch. 4 CS 7 Serial Data
DSPI 1 - Timer 1 - DSPI 0 -
PC[10] PAD[42] — 48 IO —
CLK ch. 5 CLK
Timer 1 - DSPI 1 - DSPI 0 -
PC[11] PAD[43] 31 49 IO —
ch. 4 CLK CS 2
— FCCU_F1 32 50 IO FCCU_F1
— VDD_HV_IO 33 51 PWB51 —
— VDD_LV 34 52 PW —
— EXTAL 35 53 ANA —

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Table 4. eTQFP64 and eTQFP100 pinout (continued)

Pin No. Alternate functions

eTQFP100
eTQFP64
Port
Pad Type AF1 AF2 AF3 AF4
pin

— XTAL 36 54 ANA —
— VDD_HV_OSC_PMC 37 55 PW —
Timer 0 - DSPI 1 - LINFlex 0 -
PC[12] PAD[44] — 56 IO —
ch. 0 CS 3 RX
Timer 0 - DSPI 1 - LINFlex 0 -
PC[13] PAD[45] — 57 IO —
ch. 1 CS 4 TX
Timer 0 - DSPI 1 - DSPI 0 -
PC[14] PAD[46] — 58 IO —
ch. 2 CS 5 CS 3
— TDI 38 59 IO —
— TMS 39 60 IO —
— TDO 40 61 IO —
DSPI 1 - Timer 2 -
PC[15] PAD[47] 41 62 IO NMI Ext. INT 4
CS 2 ch. 0
— TCK 42 63 IO —
— TESTMODE 43 64 IO —
DSPI 1 - Timer 2 -
PD[0] PAD[48] — 65 IO Ext. INT 0 —
CS 6 ch. 1
— PORST 44 66 IO —
Timer 0 - DSPI 1 - DSPI 0 -
PD[1] PAD[49] — 67 IO —
ch. 3 CS 7 CS 4
— VDD_LV 45 68 PW —
Timer 2 - DSPI 2 - DSPI 1 - Timer 3 -
PD[2] PAD[50] — 69 IO
ch. 0 CS 1 CS 6 ch. 0
Timer 2 - DSPI 2 - DSPI 1 - Timer 3 -
PD[3] PAD[51] — 70 IO
ch. 1 CS 2 CS 4 ch. 1
Timer 2 - DSPI 2 - DSPI 1 - Timer 3 -
PD[4] PAD[52] — 71 IO
ch. 2 CS 3 CS 7 ch. 2
— VDD_HV_IO 46 — PWB51 —
DSPI 2 - Timer 2 - DSPI 1 - Timer 3 -
PD[5] PAD[53] — 72 IO
CS 0 ch. 1 CS 6 ch. 3
DSPI 2 - Timer 2 - DSPI 1 - DSPI 0 -
PD[6] PAD[54] — 73 IO
Serial Data ch. 2 CS 5 CS 5
Timer 3 - CTU DSPI 1 - LINFlex 1 -
PD[7] PAD[55] 47 74 IO
ch. 0 trg_inp CS 2 RX
Timer 3 - CTU DSPI 1 - LINFlex 1 -
PD[8] PAD[56] 48 75 IO
ch. 1 trg_outp CS 6 TX

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Table 4. eTQFP64 and eTQFP100 pinout (continued)

Pin No. Alternate functions

eTQFP100
eTQFP64
Port
Pad Type AF1 AF2 AF3 AF4
pin

FlexCAN 0 - DSPI 2 - FlexCAN 1 - Timer 2 -

PD[9] PAD[57] 49 76 IO
RX CS 1 RX ch. 2
FlexCAN 0 - FlexCAN 1 - Timer 2 -
PD[10] PAD[58] 50 77 IO —
TX TX ch. 3
Timer 3 - DSPI 2 - DSPI 1 -
PD[11] PAD[59] 51 78 IO —
ch. 2 CLK CS 7
DSPI 2 - Timer 2 - DSPI 2 -
PD[12] PAD[60] — 79 IO —
Serial Data ch. 3 CS 2
DSPI 2 - Timer 2 - DSPI 2 -
PD[13] PAD[61] — 80 IO —
CLK ch. 4 CS 3
Timer 2 - DSPI 2 - Timer 3 -
PD[14] PAD[62] 52 81 IO —
ch. 3 Serial Data ch. 3
Timer 2 - DSPI 2 - Timer 3 -
PD[15] PAD[63] 53 82 IO —
ch. 4 Serial Data ch. 4
Timer 3 - Timer 2 -
PE[0] PAD[64] — 83 IO Ext. INT 2 —
ch. 3 ch. 4
Timer 3 - Timer 2 -
PE[1] PAD[65] — 84 IO — —
ch. 4 ch. 5
— VDD_HV_IO 54 85 PWB85 —
Timer 2 - DSPI 2 - DSPI 0 -
PE[2] PAD[66] 55 86 IO —
ch. 5 CS 0 CS 3
Nexus DSPI 0 - DSPI 2 -
PE[3] PAD[67] 56 87 IO —
MSEO(2) CS 4 CLK
Timer 3 - DSPI 2 - Timer 2 -
PE[4] PAD[68] — 88 IO —
ch. 5 CS 2 ch. 4
Nexus DSPI 2 -
PE[5] PAD[69] 57 89 IO — CLOCKOUT
MDO 3(2) Serial Data
Nexus DSPI 0 - DSPI 2 -
PE[6] PAD[70] 58 90 IO —
MDO 2(2) CS 6 Serial Data
Nexus DSPI 0 - Timer 3 -
PE[7] PAD[71] 59 91 IO —
MDO 1(2) CS 7 ch. 4
Nexus DSPI 0 - Timer 3 -
PE[8] PAD[72] 60 92 IO Ext. INT 3
MDO 0(2) CS 0 ch. 5
Timer 3 - DSPI 2 -
PE[9] PAD[73] — 93 IO — Ext. INT 4
ch. 2 CS 1
Timer 3 - DSPI 0 - DSPI 2 -
PE[10] PAD[74] — 94 IO —
ch. 3 CS 5 CS 2
— VDD_HV_IO 61 95 PW —

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Table 4. eTQFP64 and eTQFP100 pinout (continued)

Pin No. Alternate functions

eTQFP100
eTQFP64
Port
Pad Type AF1 AF2 AF3 AF4
pin

Nexus DSPI 0 - DSPI 0 - DSPI 1 -

PE[11] PAD[75] 62 96 IO
MCK0(2) CLK CS 1 CS 3
Timer 3 - DSPI 2 - DSPI 1 -
PE[12] PAD[76] — 97 IO —
ch. 4 CS 0 CS 2
Timer 3 - DSPI 2 - DSPI 1 -
PE[13] PAD[77] — 98 IO —
ch. 5 CS 1 CS 1
Nexus DSPI 0 - DSPI 0 - DSPI 2 -
PE[14] PAD[78] 63 99 IO
EVTO (2) Serial Data CS 2 CS 3
Nexus DSPI 0 - DSPI 1 -
PE[15] PAD[79] 64 100 IO —
EVTI(2) Serial Data CS 3
1. Cannot be changed
2. Can be enabled via JTAG during the reset phase

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Electrical characteristics SPC570S40Ex, SPC570S50Ex

4 Electrical characteristics

4.1 Introduction
This section contains electrical characteristics of the device as well as temperature and
power considerations.
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take precautions to avoid applying any voltage higher
than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD
or VSS). This could be done by the internal pull-up and pull-down, which is provided by the
product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and
its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.

4.2 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 5 are used and
the parameters are tagged accordingly in the tables where appropriate.

Table 5. Parameter classifications

Classification tag Tag description

P Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
C
relevant sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from
T typical devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
D Those parameters are derived mainly from simulations.

Note: The classification is shown in the column labeled “C” in the parameter tables where
appropriate.

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4.3 Absolute maximum ratings

Table 6. Absolute maximum ratings (1)
Value
Symbol Parameter Conditions Unit
Min Max

Cycle T Lifetime power cycles — — 1000k —

VSS C Ground voltage — — — —
VDD_LV C 1.2 V core supply voltage — -0.3 1.5 V
(2)
VDD_HV_IO C I/O supply voltage — -0.3 6.0 V
Power management unit and
VDD_HV_OSC_PMC C — -0.3 6.0 V
OSC power supply
VDD_HV_ADC_TSENS C ADC & TSENS power supply — -0.3 6.0 V
VREFH_ADC C ADC reference supply — 0 VDD_HV_ADC_TSENS V
— -0.3 6.0
VIN C I/O input voltage range(3) Relative to VSS -0.3 — V
Relative to VDD_HV_IO — 0.3
Maximum DC injection
Per pin, applies to all
IINJD T current for digital pad during -3 3 mA
digital pins
overload condition
Maximum DC injection
Per pin, applies to all
IINJA T current for analog pad during -3 3 mA
analog pins
overload condition
Medium -7 8
Maximum output DC current
IMAXD SR Strong -10 10 mA
when driven
Very strong -11 11
Maximum current per power
IMAXSEG SR — -90 90 mA
segment(4)
Storage temperature range
TSTG SR — -55 175 °C
and non-operating times
Maximum storage time, No supply; storage
STORAGE SR assembled part programmed temperature in range — 20 years
in ECU -40 °C to 85 °C
Maximum solder
(5)
TSDR SR temperature — — 260 °C
Pb-free package
MSL SR Moisture sensitivity level(6) — — 3 —
Range for x-rays
Maximum cumulated dose source during
X-rays dose T — 1 Grey
allowable inspection:
80÷130 KV; 20÷50 µA

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1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability or cause permanent damage to the device. During overload conditions (VIN >
VDD_HV_IO or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values.
2. Allowed 5.5–6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset,
TJ = 150 °C remaining time at or below 5.5 V.
3. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current
condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin
to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3V can be used for nominal
calculations.
4. A VDD_HV_IO power segment is defined as one or more GPIO pins located between two VDD_HV_IO supply pins.
5. Solder profile per IPC/JEDEC J-STD-020D
6. Moisture sensitivity per JEDEC test method A112

4.4 Electromagnetic compatibility (EMC)

Table 7 describes the EMC characteristics of the device.

Table 7. Radiated emissions testing specification(1),(2)

Functional BISS radiated
Coupling structure Test setup Function
configuration emissions limit

Reference test C1-S3 18 dBµV

Reference test with SSCG C1-S3 18 dBµV
Entire IC (G) TEM
Memory copy C4-S2 18 dBµV
Memory copy with SSCG C4-S2 18 dBµV
1. Reference “BISS Generic IC EMC Test Specification”, version 1.2, section 9.3, “Emission test configuration for ICs with
CPU”.
2. The EMC parameters are classified as “T”, validated on testbench.

4.5 Electrostatic discharge (ESD)

The following table describes the ESD ratings of the device.

Table 8. ESD ratings(1),(2)

Parameter C Conditions Value Unit

ESD for Human Body Model (HBM)(3) T All pins 2000 V

(4)
ESD for field induced Charged Device Model (CDM) T All pins 500 V
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature.
Maximum DC parametrics variation within 10% of maximum specification”
3. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing
4. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level

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4.6 Operating conditions

Table 9. Device operating conditions(1)
Value
Symbol C Parameter Conditions Unit
Min Typ Max

Frequency
Device operating
fSYS SR -40 °C < TJ < 150 °C — — 80 MHz
frequency(2)
Temperature
Operating
temperature — -40.0 — 150.0 °C
range - junction
TJ SR P
Operating
temperature — 165.0 (3) °C
— —
range - junction
Ambient operating
TA (TL to TH) SR P temperature — -40.0 — 125.0 °C
range
Voltage
LVD290/HVD400
P 2.97 — 3.63
enabled
VDD_HV_IO SR I/O supply voltage LVD290 enabled V
C HVD400 disabled 2.97 — 5.5
(4),(5)

LVD290/HVD400
P 2.97 — 3.63
PMC and OSC enabled
VDD_HV_OSC_PMC SR V
supply voltage LVD290 enabled
C 2.97 — 5.5
HVD400 disabled
D LVD400 enabled 4.5 — 5.5
SAR ADC supply
VDD_HV_ADC_TSENS SR LVD400 V
C voltage 3.0 — 3.6
disabled(4),(6)
SAR ADC
VREFH_ADC SR P — 2.0 — VDD_HV_ADC_TSENS V
reference voltage
SAR ADC
VREFH_ADC -
SR D reference — — — 25 mV
VDD_HV_ADC_TSENS
differential voltage
Slew rate on
VRAMP SR D — — — 0.5 V/µs
power supply pins
I/O input voltage
VIN SR C — 0 — 5.5 V
range

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Table 9. Device operating conditions(1) (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Injection current
DC injection
Digital pins and
IIC SR T current (per -3 — 3 mA
analog pins
pin)(7),(8),(9)
Maximum current
IMAXSEG SR D per power — -80 — 80 mA
segment(10)
1. The ranges in this table are design targets and actual data may vary in the given range.
2. Maximum operating frequency is applicable to the computational cores and platform for the device. See the Clocking
chapter in the SPC570Sx Microcontroller Reference Manual for more information on the clock limitations for the various IP
blocks on the device.
3. Refer to technical note "SPC570S family - High Temperature "D" Grade (DocID031416 - TN1262)" for associated specific
limitation.
4. Maximum voltage is not permitted for entire product life. See Absolute maximum ratings.
5. Reduced output/input capabilities below 4.2 V. See performance derating values in I/O pad electrical characteristics.
6. This LVD/HVD disabled supply voltage condition only applies after LVD/HVD are disabled by the application during the
reset sequence, and the LVD/HVD are active until that point.
7. Full device lifetime without performance degradation
8. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See Table 6:
Absolute maximum ratings for maximum input current for reliability requirements.
9. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is
above the supply rail, current will be injected through the clamp diode to the supply rail. For external RC network
calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature. For more
information, see the device characterization report.
10. A VDD_HV_IO power segment is defined as one or more GPIO pins located between two VDD_HV_IO supply pins.

4.7 Thermal characteristics

4.7.1 Package thermal characteristics

Table 10. Thermal characteristics for eTQFP64

Symbol C Parameter Conditions Value Unit

RθJA CC D Junction to ambient, natural convection(1) Four layer board - 2s2p board 32.3 °C/W
Junction to ambient in forced air @ 200 ft/min
RθJMA CC D Four layer board - 2s2p board 26.5 °C/W
(1 m/s)(1)
RθJB CC D Junction to board(2) — 12.1 °C/W
RθJCtop CC D Junction to top case(3) — 19.0 °C/W
RθJCbotttom CC D Junction to bottom case thermal resistance(4) — 1.9 °C/W
Junction to package top, natural
ΨJT CC D — 0.6 °C/W
convection(5)
1. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
2. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.

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3. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1021.1).
4. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any
interface resistance.
5. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.

Table 11. Thermal characteristics for eTQFP100(1)

Symbol C Parameter Conditions Value Unit

RθJA CC D Junction-to-ambient, natural Four layer board—2s2p 30.7 °C/W

convection(2)
RθJMA CC D Junction-to-moving-air, ambient(2) At 200 ft./min., four layer 24.3 °C/W
board—2s2p
RθJB CC D Junction-to-board(3) Ring cold plate 11.3 °C/W
RθJCtop CC D Junction-to-case top(4) Cold plate 16.0 °C/W
RθJCbotttom CC D Junction-to-case bottom(5) Cold plate 1.5 °C/W
ΨJT CC D Junction-to-package top(6) Natural convection 0.5 °C/W
1. The values are based on simulation; actual data may vary in the given range. The specified characteristics are subject to
change per final device design and characterization. Junction temperature is a function of die size, on-chip power
dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power
dissipation of other components on the board, and board thermal resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.

4.7.2 Power considerations

An estimation of the chip junction temperature, TJ can be obtained from the equation:

Equation 1: TJ = TA + (RθJA * PD)

where:
TA = ambient temperature for the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards
to provide consistent values for estimations and comparisons. The differences between the
values determined for the single-layer (1s) board compared to a four-layer board that has

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two signal layers, a power and a ground plane (2s2p), demonstrate that the effective
thermal resistance is not a constant. The thermal resistance depends on the:
• Construction of the application board (number of planes)
• Effective size of the board which cools the component
• Quality of the thermal and electrical connections to the planes
• Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using
fewer vias to connect the package to the planes reduces the thermal performance. Thinner
planes also reduce the thermal performance. When the clearance between the vias leave
the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for
the tightly packed printed circuit board. The value obtained on a board with the internal
planes is usually within the normal range if the application board has:
• One oz. (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the
surrounding components. In addition, the ambient temperature varies widely within the
application. For many natural convection and especially closed box applications, the board
temperature at the perimeter (edge) of the package is approximately the same as the local
air temperature near the device. Specifying the local ambient conditions explicitly as the
board temperature provides a more precise description of the local ambient conditions that
determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following
equation:

Equation 2: TJ = TB + (RqJB * PD)

where:
TB = board temperature for the package perimeter (°C)
RqJB = junction-to-board thermal resistance (°C/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, the
junction temperature is predictable if the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance
plus a case-to-ambient thermal resistance:

Equation 3: RqJA = RqJC + RqCA

where:
RqJA = junction-to-ambient thermal resistance (°C/W)
RqJC = junction-to-case thermal resistance (°C/W)
RqCA = case to ambient thermal resistance (°C/W)
RqJC is device related and is not affected by other factors. The thermal environment can be
controlled to change the case-to-ambient thermal resistance, RqCA. For example, change
the air flow around the device, add a heat sink, change the mounting arrangement on the

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printed circuit board, or change the thermal dissipation on the printed circuit board
surrounding the device. This description is most useful for packages with heat sinks where
90% of the heat flow is through the case to heat sink to ambient. For most packages, a
better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board
thermal resistance and the junction-to-case thermal resistance. The junction-to-case
thermal resistance describes when using a heat sink or where a substantial amount of heat
is dissipated from the top of the package. The junction-to-board thermal resistance
describes the thermal performance when most of the heat is conducted to the printed circuit
board. This model can be used to generate simple estimations and for computational fluid
dynamics (CFD) thermal models. More accurate compact Flotherm models can be
generated upon request.
To determine the junction temperature of the device in the application on a prototype board,
use the thermal characterization parameter (YJT) to determine the junction temperature by
measuring the temperature at the top center of the package case using the following
equation:

Equation 4: TJ = TT + (ΨJT x PD)

where:
TT = thermocouple temperature on top of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured in compliance with the JESD51-2
specification using a 40-gauge type T thermocouple epoxied to the top center of the
package case. Position the thermocouple so that the thermocouple junction rests on the
package. Place a small amount of epoxy on the thermocouple junction and approximately 1
mm of wire extending from the junction. Place the thermocouple wire flat against the
package case to avoid measurement errors caused by the cooling effects of the
thermocouple wire.
When board temperature is perfectly defined below the device, it is possible to use the
thermal characterization parameter (ΨJPB) to determine the junction temperature by
measuring the temperature at the bottom center of the package case (exposed pad) using
the following equation:

Equation 5: TJ = TB + (ΨJPB x PD)

where:
TB = thermocouple temperature on bottom of the package (°C)
ΨJPB = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)

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4.8 Current consumption

The following table describes the consumption figures.

Table 12. Current consumption

Value
Symbol C Parameter Conditions Unit
Min Typ Max

P Fmax(1) — — 110(1) mA
Operating current all
IDD 0.75 *
T supply rails Tj = 150 °C(1) — — mA
fCPU(2) + 50
Stop P Stop mode consumption Device working on RC clock — — 40(3) mA
1. Values are based on typical application code executing from Flash memory, where the DMA is running in continuous mode,
the ADC is in continuous conversion, the timers are running to maximum counter values and communication IPs are in
loopback or transmitting mode. IOs are unloaded.
The maximum consumption can reach 110 mA during boot time M/LBIST (before reset).
2. fCPU is measured in MHz
3. ADC and XOSC disabled, Includes regulator consumption for VDD_LV generation. Includes static I/O current with no pins
toggling.

4.9 I/O pad electrical characteristics

4.9.1 I/O pad types

Table 13 describes the different pad type configurations.

Table 13. I/O pad specification descriptions

Pad type Description

Provides a good compromise between transition time and low electromagnetic

Weak configuration
emission. Pad impedance is centered around 800 Ω
Provides transition fast enough for the serial communication channels with controlled
Medium configuration
current to reduce electromagnetic emission. Pad impedance is centered around 200 Ω
Provides fast transition speed; used for fast interface. Pad impedance is centered
Strong configuration
around 50 Ω
Provides maximum speed and controlled symmetric behavior for rise and fall transition.
Very strong configuration Used for fast interfaces requiring fine control of rising/falling edge jitter. Pad impedance
is centered around 40 Ω
These pads are associated to ADC channels and the external 8-40 MHz crystal
Input only pads
oscillator (XOSC) providing low input leakage

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4.9.2 I/O input DC characteristics

Table 14 provides input DC electrical characteristics as described in Figure 4.

Figure 4. I/O input DC electrical characteristics definition

VIN
VDD

VIH

VHYS

VIL

PDIx = ‘1’
(GPDI register of SIUL)

PDIx = ‘0’

Table 14. I/O input DC electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

TTL

3.0 V < VDD_HV_IO < 3.6 V

Input high level VDD_HV_IO
VIH SR P and 2.0 —
TTL + 0.3
4.5 V < VDD_HV_IO < 5.5 V
3.0 V < VDD_HV_IO < 3.6 V
VIL SR P Input low level TTL and -0.3 — 0.8 V
4.5 V < VDD_HV_IO < 5.5 V
3.0 V < VDD_HV_IO < 3.6 V
Input hysteresis
VHYST — C and 0.3(1) — —
TTL
4.5 V < VDD_HV_IO < 5.5 V

CMOS

Input high level 3.0 V < VDD_HV_IO < 3.6 V

0.65 * VDD_HV_IO
VIHCMOS_H(2) SR P CMOS and — V
VDD_HV_IO + 0.3
(with hysteresis) 4.5 V < VDD_HV_IO < 5.5 V
Input high level 3.0 V < VDD_HV_IO < 3.6 V
0.6 * VDD_HV_IO
VIHCMOS(2) SR P CMOS and — V
VDD_HV_IO + 0.3
(without hysteresis) 4.5 V < VDD_HV_IO < 5.5 V
Input low level 3.0 V < VDD_HV_IO < 3.6 V
0.35 *
VILCMOS_H(2) SR P CMOS and -0.3 — V
VDD_HV_IO
(with hysteresis) 4.5 V < VDD_HV_IO < 5.5 V

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Table 14. I/O input DC electrical characteristics (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Input low level 3.0 V < VDD_HV_IO < 3.6 V

0.4 *
VILCMOS(2) SR P CMOS and -0.3 — V
VDD_HV_IO
(without hysteresis) 4.5 V < VDD_HV_IO < 5.5 V
3.0 V < VDD_HV_IO < 3.6 V
Input hysteresis 0.1 *
VHYSCMOS — C and — — V
CMOS VDD_HV_IO
4.5 V < VDD_HV_IO < 5.5 V

Automotive

VDD_HV_IO
4.5 V < VDD_HV_IO < 5.5 V 3.8 —
Input high level + 0.3
VIH(3) SR P V
Automotive 0.75 * VDD_HV_IO
3.0 V < VDD_HV_IO < 3.6 V —
VDD_HV_IO + 0.3
4.5 V < VDD_HV_IO < 5.5 V -0.3 — 2.2
Input low level
VIL SR P 0.35 * V
Automotive 3.0 V < VDD_HV_IO < 3.6 V -0.3 —
VDD_HV_IO
4.5 V < VDD_HV_IO < 5.5 V 0.5 — —
Input hysteresis
VHYST — C 0.11 * V
Automotive 3.0 V < VDD_HV_IO < 3.6 V — —
VDD_HV_IO
Input Characteristics
Digital input
ILKG CC P — — — 1 µA
leakage
Digital input
CIN C D — — — 10 pF
capacitance
1. Minimum hysteresis at 4.0 V
2. VSIO[VSIO_xx] = 0 in the range 3.0 V < VDD_HV_IO < 4.0 V, VSIO[VSIO_xx] = 1 in the range 4.0 V < VDD_HV_IO < 5.9 V.
3. VSIO[VSIO_xx] = 0 in the range 3.0 V < VDD_HV_IO < 4.0 V, VSIO[VSIO_xx] = 1 in the range 4.0 V < VDD_HV_IO < 5.9 V.
Table 15 provides weak pull figures. Both pull-up and pull-down current specifications are provided.

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Table 15. I/O pull-up/pull-down DC electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

VIN = 0.69 * VDD_HV_IO

23 — —
4.5 V < VDD_HV_IO < 5.5 V
VIN = 0.49 * VDD_HV_IO
CC P — — 82
4.5 V < VDD_HV_IO < 5.5 V
VIN > VIL = 1.1 V (TTL)
— — 130
Weak pull-up/down 4.5 V < VDD_HV_IO < 5.5 V
|IWPU| µA
current absolute value(1) VIN = 0.75 * VDD_HV_IO
10 — —
3.0 V < VDD_HV_IO < 3.6 V
VIN = 0.35 * VDD_HV_IO
CC T — — 70
3.0 V < VDD_HV_IO < 3.6 V
VIN > VIL = 1.1 V (TTL)
— — 75
3.0 V < VDD_HV_IO < 3.6 V
VIN = 0.69 * VDD_HV_IO
— — 130
4.5 V < VDD_HV_IO < 5.5 V
VIN = 0.49 * VDD_HV_IO
CC P 40 — —
4.5 V < VDD_HV_IO < 5.5 V
VIN > VIL = 1.1 V (TTL)
16 — —
Weak pull-down current 4.5 V < VDD_HV_IO < 5.5 V
|IWPD| µA
absolute value VIN = 0.75 * VDD_HV_IO
— — 92
3.0 V < VDD_HV_IO < 3.6 V
VIN = 0.35 * VDD_HV_IO
CC T 19 — —
3.0 V < VDD_HV_IO < 3.6 V
VIN > VIL = 1.1 V (TTL)
16 — —
3.0 V < VDD_HV_IO < 3.6 V
1. Weak pull-up/down is enabled within tWK_PU = 1 µs after internal/external reset has been asserted. Output voltage will
depend on the amount of capacitance connected to the pin.

4.9.3 I/O output DC characteristics

Table 16: Weak configuration I/O output characteristics, provide DC characteristics for
bidirectional pads in the following configurations:
• Weak
• Medium
• Strong
• Very Strong

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Table 16. Weak configuration I/O output characteristics(1),(2)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

3.0 V < VDD_HV_IO < 3.6 V

— — 1040
C PMOS output impedance Push pull, IOH< 0.5 mA
ROH_W P Ω
C weak configuration 4.5 V < V < 5.5 V
DD_HV_IO
— — 1040
Push pull, IOH < 0.5 mA
3.0 V < VDD_HV_IO < 3.6 V
— — 1040
C NMOS output impedance Push pull, IOL < 0.5 mA
ROL_W P Ω
C weak configuration 4.5 V < V < 5.5 V
DD_HV_IO
— — 1040
Push pull, IOL < 0.5 mA

C Output frequency weak CL = 25 pF — — 2

fmax_W T MHz
C configuration CL = 50 pF — — 1
3.0 V < VDD_HV_IO < 3.6 V
— — 150
CL = 25 pF
3.0 V < VDD_HV_IO < 3.6 V
— — 300
C Transition time output pin C L = 50 pF
tTR_W D ns
C weak configuration 4.5 V < V < 5.5 V
DD_HV_IO
— — 100
CL = 25 pF
4.5 V < VDD_HV_IO < 5.5 V
— — 200
CL = 50 pF

C Difference between rise 3.0 V < VDD_HV_IO < 3.6 V — — 40

tSKEW_W T %
C time and fall time 4.5 V < VDD_HV_IO < 5.5 V — — 28
1. The above mentioned values are different for M/W (Medium/Weak) pads.
2. Please refer to Table 20: I/O output characteristics for pads 4, 9, 11, 55, 56

Table 17. Medium configuration I/O output characteristics(1),(2)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

3.0 V < VDD_HV_IO < 3.6 V

— — 270
C PMOS output impedance Push pull, IOH< 2 mA
ROH_M P Ω
C medium configuration 4.5 V < V < 5.5 V
DD_HV_IO
— — 270
Push pull, IOH < 2 mA
3.0 V < VDD_HV_IO < 3.6 V
— — 270
C NMOS output impedance Push pull, IOL < 2 mA
ROL_M P Ω
C medium configuration 4.5 V < V < 5.5 V
DD_HV_IO
— — 270
Push pull, IOL < 2 mA

C Output frequency medium CL = 25 pF — — 12

fmax_M T MHz
C configuration CL = 50 pF — — 6

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Table 17. Medium configuration I/O output characteristics(1),(2) (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

3.0 V < VDD_HV_IO < 3.6 V

— — 37
CL = 25 pF
3.0 V < VDD_HV_IO < 3.6 V
— — 72
C Transition time output pin C L = 50 pF
tTR_M D ns
C medium configuration 4.5 V < V < 5.5 V
DD_HV_IO
— — 25
CL = 25 pF
4.5 V < VDD_HV_IO < 5.5 V
— — 50
CL = 50 pF

C Difference between rise 3.0 V < VDD_HV_IO < 3.6 V — — 40

tSKEW_M T %
C time and fall time 4.5 V < VDD_HV_IO < 5.5 V — — 28
1. The above mentioned values are different for M/W (Medium/Weak) pads.
2. Please refer to Table 20: I/O output characteristics for pads 4, 9, 11, 55, 56

Table 18. Strong configuration I/O output characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

3.0 V < VDD_HV_IO < 3.6 V

— — 90
C PMOS output impedance Push pull, IOH< 6 mA
ROH_S P Ω
C strong configuration 4.5 V < V < 5.5 V
DD_HV_IO
— — 75
Push pull, IOH < 8 mA
3.0 V < VDD_HV_IO < 3.6 V
— — 90
C NMOS output impedance Push pull, IOL< 6 mA
ROL_S P Ω
C strong configuration 4.5 V < V < 5.5 V
DD_HV_IO
— — 75
Push pull, IOL < 8 mA
3.0 V < VDD_HV_IO < 3.6 V
— — 25
CL = 25 pF
3.0 V < VDD_HV_IO < 3.6 V
— — 12.5
C Output frequency strong CL = 50 pF
fmax_S T MHz
C configuration 4.5 V < VDD_HV_IO < 5.5 V
— — 50
CL = 25 pF
4.5 V < VDD_HV_IO < 5.5 V
— — 25
CL = 50 pF

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Table 18. Strong configuration I/O output characteristics (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

3.0 V < VDD_HV_IO < 3.6 V

— — 11
CL = 25 pF
3.0 V < VDD_HV_IO < 3.6 V
— — 22
C Transition time output pin C L = 50 pF
tTR_S D ns
C strong configuration 4.5 V < V < 5.5 V
DD_HV_IO
— — 8
CL = 25 pF
4.5 V < VDD_HV_IO < 5.5 V
— — 13
CL = 50 pF

C Difference between rise 3.0 V < VDD_HV_IO < 3.6 V — — 40

tSKEW_S T %
C time and fall time 4.5 V < VDD_HV_IO < 5.5 V — — 28

Table 19. Very Strong configuration I/O output characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

3.0 V < VDD_HV_IO < 3.6 V

— — 85
C PMOS output impedance Push pull, IOH < 7 mA
ROH_V P Ω
C very strong configuration 4.5 V < V < 5.5 V
DD_HV_IO
— — 65
Push pull, IOH < 8 mA
3.0 V < VDD_HV_IO < 3.6 V
— — 85
C NMOS output impedance Push pull, IOL < 7 mA
ROL_V P Ω
C very strong configuration 4.5 V < V < 5.5 V
DD_HV_IO
— — 65
Push pull, IOL < 8 mA
3.0 V < VDD_HV_IO < 3.6 V
— — 50
CL = 15 pF
3.0 V < VDD_HV_IO < 3.6 V
— — 30
CL = 25 pF
3.0 V < VDD_HV_IO < 3.6 V
— — 25
C Output frequency very Td = 0.6 ns, load = 10 pF
fmax_V T MHz
C strong configuration 4.5 V < VDD_HV_IO < 5.5 V
— — 50
CL = 25 pF
4.5 V < VDD_HV_IO < 5.5 V
— — 25
CL = 50 pF
4.5 V < VDD_HV_IO < 5.5 V
— — 25
Td = 1 ns, load = 10 pF

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Table 19. Very Strong configuration I/O output characteristics (continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

3.0 V < VDD_HV_IO < 3.6 V

— — 4.5
CL = 15 pF
3.0 V < VDD_HV_IO < 3.6 V
— — 5
CL = 25 pF
3.0 V < VDD_HV_IO < 3.6 V (4.5 * Tr)
— —
C Transition time output pin Td = 0.6 ns, load = 10 pF + Tf < 9
tTR_V D ns
C very strong configuration 4.5 V < V < 5.5 V
DD_HV_IO
— — 4
CL = 25 pF
4.5 V < VDD_HV_IO < 5.5 V
— — 8
CL = 50 pF
4.5 V < VDD_HV_IO < 5.5 V (4.5 * Tr)
— —
Td = 1 ns, load = 10 pF + Tf < 9

3.0 V < VDD_HV_IO < 3.6 V

0 — 1.2
tPHL- C Difference between delay C L = 15 pF
T ns
PLH_V C of rising and falling edges 4.5 V < V < 5.5 V
DD_HV_IO
0 — 1.2
CL = 25 pF

For W/M (Weak/Medium) pads the following values hold true.

Table 20. I/O output characteristics for pads 4, 9, 11, 55, 56

Value
Functionality Symbol Parameter Conditions Unit
Min Typ Max

PMOS output 3.0 V < VDD_HV_IO < 3.6 V

ROH_S impedance weak — — 1600 Ω
Push pull, IOH < 0.5 mA
configuration
NMOS output 3.0 V < VDD_HV_IO < 3.6 V
ROL_S impedance weak — — 1896 Ω
Push pull, IOL < 0.5 mA
configuration

Output frequency CL = 25 pF — — 2
Weak fmax_S MHz
weak configuration CL = 50 pF — — 1
Transition time CL = 25 pF — — 127
tTR_S output pin weak ns
configuration CL = 50 pF — — 2443

Difference between
tSKEW_S rise time and fall — — — 50 %
time

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Table 20. I/O output characteristics for pads 4, 9, 11, 55, 56 (continued)
Value
Functionality Symbol Parameter Conditions Unit
Min Typ Max

PMOS output 3.0 V < VDD_HV_IO < 3.6 V

ROH_M impedance medium — — 405 Ω
Push pull, IOH < 0.5 mA
configuration
NMOS output 3.0 V < VDD_HV_IO < 3.6 V
ROL_M impedance medium — — 495 Ω
Push pull, IOL < 0.5 mA
configuration
Output frequency CL = 25 pF — — 12
Medium fmax_M medium MHz
configuration CL = 50 pF — — 6

Transition time CL = 25 pF — — 34
tTR_M output pin medium ns
configuration CL = 50 pF — — 62

Difference between
tSKEW_M rise time and fall — — — 46 %
time

4.10 RESET electrical characteristics

The device implements a dedicated bidirectional reset pin (PORST).
Note: PORST pin does not require active control. It is possible to implement an external pull-up to
ensure correct reset exit sequence. Recommended value is 4.7 Kohm.

Figure 5. Start-up reset requirements

VDD

VDDMIN

RESET

VIH

VIL

device reset forced by RESET device start-up phase

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Figure 6 describes device behavior depending on supply signal on PORST:

1. PORST does not go low enough: it is filtered by input buffer hysteresis. The device
remains in the current state.
2. PORST goes low enough, but not for long enough: it is filtered by a low pass filter. The
device remains in the current state.
3. The PORST generates a reset:
a) PORST low but initially filtered during at least WFRST. Device remains initially in
current state.
b) PORST potentially filtered until WNFRST. Device state is unknown. It may either be
reset or remains in current state depending on extra conditions (PVT — process,
voltage, temperature).
c) PORST asserted for longer than WNFRST. The device is under hardware reset.

Figure 6. Noise filtering on reset signal

VPORST

VDD

VIH
VHYS

VIL

internal
reset

filtered by
filtered by filtered by unknown reset
hysteresis lowpass filter lowpass filter state device under hardware reset

WFRST WFRST
WNFRST

1 2 3a 3b 3c

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Table 21. Reset electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Input high level TTL VDD_HV_IO

VIH SR P — 2.0 — V
(Schmitt trigger) + 0.4

Input low level TTL 3.0 V < VDD_HV_IO < 3.6 V 0.4 — 0.6
VIL SR P V
(Schmitt trigger) 4.5 V < VDD_HV_IO < 5.5 V 0.4 — 0.8
Input hysteresis TTL
VHYS CC C — 275 — — mV
(Schmitt trigger)
Minimum supply for strong
VDD_POR CC C — — — 1.2 V
pull-down activation
Device under power-on reset
3.0 V < VDD_HV_IO < 5.5 V, 0.2 — — mA
IOL_R CC P Strong pull-down current VOL > 1.0 V
Device under power-on reset
12 — — mA
VDD_HV_IO = 4.0 V, VOL = VIL
ESR0 pin
23 — —
Weak pull-up current VIN = 0.69 * VDD_HV_IO
|IWPU| CC P µA
absolute value ESR0 pin
— — 82
VIN = 0.49 * VDD_HV_IO
PORST pin
— — 130
Weak pull-down current VIN = 0.69 * VDD_HV_IO
|IWPD| CC P µA
absolute value PORST pin
40 — —
VIN = 0.49 * VDD_HV_IO
PORST input filtered
WFRST SR P — — — 500 ns
pulse
PORST input not filtered
WNFRST SR P — 2000 — — ns
pulse

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4.11 Power management electrical characteristics

4.11.1 Voltage regulator electrical characteristics

The device implements an internal voltage regulator to generate the low voltage core supply
VDD_LV from the high voltage ballast supply VDD_HV_IO. The regulator itself is supplied by
VDD_HV_OSC_PMC.
Note: VDD_HV_OSC_PMC is to be shorted with VDD_HV_IO supply at package level.
The following supplies are involved:
• HV—High voltage external for voltage regulator module. This must be provided
externally through VDD_HV_OSC_PMC power pin.
• BV—High voltage external power supply for internal ballast module. This must be
provided externally through VDD_HV_IO power pins. Voltage values should be aligned
with VDD_HV_OSC_PMC.
• LV—Low voltage internal power supply for core, PLL and Flash digital logic. This is
generated by the internal voltage regulator but provided outside to connect stability
capacitor. It is split into three further domains to ensure noise isolation between critical
LV modules within the device:
– LV_COR—Low voltage supply for the core. It is also used to provide supply for
PLL1 through double bonding.
– LV_FLA—Low voltage supply for code Flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
– LV_PLL—Low voltage supply for PLL1. It is shorted to LV_COR through double
bonding.

Figure 7. Recommended parasitics on board

VDD_HV_OSC_PMC

VDD_HV_IO VDD_HV_IO (ballast supply) VDD_HV_IO VDD_HV_IO CDECBV

(ballast supply) (61, 95) (ballast supply) 2.2 µF
(ballast supply)
(54, 85) (46, 51)
VREF
VDD_LV
CREG
(45, 68)

VDD_LVn CV1V2 2.2 µF

Voltage
Regulator CV1V2 VDD_LV
(12, 19) VDD_HV_OSC_PMC
I DEVICE (37, 55)

VSS
DEVICE
VDD_LV CV1V2
(34, 52)
VDD_HV_IO (ballast supply)
(13, 20) 100 nF
VDD_HV_IO (ballast supply)
(33, 51)

Pin configuration: (x, y)

where x is the pin number in the 64-pin package
and y is the pin number in the 100-pin package

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Table 22. Voltage regulator electrical characteristics

Value(2)
(1)
Symbol Parameter Conditions Unit
Min Typ Max

Main internal voltage regulator

CREG SR — 1.1 2.2(3) 2.97 µF
stability external capacitance
Stability capacitor equivalent serial Total resistance including
RDECREGn SR 1 — 50 mΩ
resistance board track
EMC cap to be placed
CV1V2 SR VDD_LV/VSS pair 50 100 135 nF
on every 1.2V pin
CDECBV SR Decoupling capacitance ballast VDD_HV_IO/VSS_LV 1.1 2.2(4) 3 µF
1. VDD = 5.0 V ± 10%, TA = -40 / 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Recommended X7R or X5R ceramic -43% / +35% variation, 20% tolerance and 12.5% temperature.
4. Recommended X7R or X5R ceramic -43% / +35% variation, 20% tolerance and 12.5% temperature.
Note: All 1.2 V pins should be shorted externally on board with minimum resistance and minimum
inductance. It is recommended to use a 1.2 V plane on which all 1.2 V pins are shorted to
keep resistance and inductance negligible. Recommended capacitors should be placed
very close to the device pins such that parasitic resistance can be reduced. Connection from
VDD_LV pin to capacitor top plate should not exceed more than 5 mΩ in resistance and
0.5 nH in inductance. Similarly connection from bottom plate of capacitor to PCB ground
should not have more than 5mohm resistance and 0.5 nH inductance.

4.12 PMU monitor specifications

4.12.1 Nomenclature
• POR stands for Power On Reset. The POR circuit manages the reset from very low
voltage up to its threshold. Cannot be disabled.
• MVD stands for Minimum Voltage Detector. It cannot be disabled by the user and
generate a destructive Reset.
• LVD stands for Low Voltage Detector. It can be disabled by the user.
• HVD stands for High Voltage Detector. It can be disabled by the user.
• UVD stands for Upper Voltage Detector. It cannot be disabled by the user and generate
a destructive reset.

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Table 23. Trimmed (PVT) values

Domain monitor Voltage Name Segment Lower limit Upper limit

Power On Reset POR041 Core 0.39 V 0.95 V

Core 1.005 V 1.055 V
MVD098
Low Flash 1.005 V 1.055 V
1.2 V LVD108 Core 1.085 V 1.137 V
HVD140 Core 1.340 V 1.400 V
High Core 1.379 V 1.441 V
UVD145
Flash 1.379 V 1.441 V
Power On Reset POR200 Core 1.750 V 2.400 V
Core 2.694 V 2.826 V
MVD270
Flash 2.694 V 2.826 V
3.3 V Low Core 2.881 V 2.999 V
LVD290 Flash 2.881 V 2.999 V
ADC 2.881 V 2.999 V
High HVD400 Core 3.660 V 3.840 V
Low LVD400 ADC 4.128 V 4.332 V
5V
High UVD600 Core 5.684 V 5.920 V

4.12.2 Power up/down sequencing

For proper device functioning please adhere to following power sequence:
VDD_HV_OSC_PMC supply should always be greater than or equal to VDD_HV_IO supply (even
during ramping up).
VDD_HV_ADC_TSENS supply should always be greater than or equal to VREFH_ADC supply.

4.13 Platform Flash controller electrical characteristics

Table 24. RWSC settings(1)
Max Flash operating Frequency (MHz)(2) RWSC

20 0b000
40 0b001
64 0b010
80 0b011
1. RWSC is a field in the Flash memory of PFCR register used to specify the wait states for address pipelining and read/write
accesses.
2. Maximum frequencies (FM modulation up to 2% could be enabled additionally).

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4.14 Flash memory electrical characteristics

Table 25 shows the program and erase characteristics.

Table 25. Flash memory program and erase specifications

Value

Lifetime
Initial max
Symbol Characteristics (1) Typical max(4) Unit
Typ
(2) C end of C
All
25 °C life(3) < 1 K < 100 K
(5) temp C
(6) cycles cycles

Double Word (64 bits) program

tdwprogram 38 C 150 — — 94 500 C µs
time [Packaged part]
tpprogram Page (256 bits) program time 78 C 300 — — 214 1000 C µs
Page (256 bits) program time
tpprogrameep EEPROM (partition 1) 90 C 330 — — 250 1000 C µs
[Packaged part]
Quad Page (1024 bits) program
tqprogram 274 C 1000 1500 P 802 2000 C µs
time
Quad Page (1024 bits) program
tqprogrameep time EEPROM (partition 1) 315 C 1100 1650 P 925 2000 C µs
[Packaged part]
16 KB block pre-program and
t16kpperase 350 C 1000 1500 P 424 5000 — C ms
erase time
32 KB block pre-program and
t32kpperase 500 C 1000 1500 P 605 5000 — C ms
erase time
64 KB block pre-program and
t64kpperase 800 C 1000 1500 P 968 5000 — C ms
erase time
128 KB block pre-program and
t128kpperase 1000 C 2000 3000 P 1254 15000 — C ms
erase time
t16kprogram 16 KB block program time 42 C 54 80 P 51 1000 — C ms
t32kprogram 32 KB block program time 85 C 108 160 P 103 2000 — C ms
t64kprogram 64 KB block program time 169 C 216 320 P 204 4000 — C ms
t128kprogram 128 KB block program time 339 C 432 640 P 410 17000 — C ms
Program 8 KB EEPROM
t8kprogrameep 21 C 27 40 P 44 1000 C ms
(partition 1)
Erase 8KB EEPROM
t8keraseeep 300 C 1000 1500 P 660 5000 C ms
(partition 1)
ttr Program rate(7) 2.34 C 3.04 4.56 C 2.60 — C s/MB
tpr Erase rate(7) 7.2 C 14.4 28.8 C 7.92 — C s/MB
tffprogram Full Flash programming time(8) 4 C 16 24 P 5 26 — C s
(8)
tfferase Full Flash erasing time 12 C 24 30 P 15 40 — C s
tESRT Erase suspend request rate(9) 500 T — — — — — — µs

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Table 25. Flash memory program and erase specifications (continued)

Value

Lifetime
Initial max
Symbol Characteristics (1) Typical max(4) Unit
Typ
(2) C end of C
All
25 °C life(3) < 1 K < 100 K
(5) temp C
(6) cycles cycles

Program suspend request

tPSRT 30 T — — — — — — µs
rate(9)
tPSUS Program suspend latency(10) — — — — — — 15 T µs
tESUS Erase suspend latency(10) — — — — — — 30 T µs
Array Integrity Check Partition
tAIC0S 7.5 T — — — — — — — ms
0 (0.5 MB, sequential)(11)
Array Integrity Check
tAIC128K 1.9 T — — — — — — — ms
(128 KB, sequential)(11)
Array Integrity Check
tAIC0P 0.75 T — — — — — — — s
(0.5 MB, proprietary)(11)
Margin Read
tMR0S 25 T — — — — — — — ms
(0.5 MB, sequential)
Margin Read
tMR128KS 6.26 T — — — — — — — ms
(128 KB, sequential)
Array Integrity Check Abort
tAABT — — — — — — 10 — µs
Latency
tMABT Margin Read Abort Latency — — — — — — 10 — µs
1. Actual hardware programming times; this does not include software overhead.
2. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
3. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but
not tested.
4. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified
number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.
5. Initial factory condition: < 100 program/erase cycles, 20 °C < TJ < 30 °C junction temperature, and nominal (± 2%) supply
voltages. These values are verified at production testing.
6. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for
less than or equal to 100 program or erase cycles, -40 °C < TJ < 150 °C junction temperature, and nominal (± 2%) supply
voltages. These values are verified at production testing.
7. Rate computed based on 128K sectors.
8. Only code sectors, not including EEPROM.
9. Time between erase suspend resume and next erase suspend.
10. Timings guaranteed by design.
11. AIC is done using system clock, thus all timing is dependant on system frequency and number of wait states. Timing in the
table is calculated at 80 MHz.

All the Flash operations require the presence of the system clock for internal
synchronization. About 50 synchronization cycles are needed: this means that the timings of
the previous table can be longer if a low frequency system clock is used.

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Table 26. Flash memory Life Specification

Value
Symbol Characteristics(1) Unit
Min C Typ C

NCER16K 16 KB CODE Flash endurance 10 — 100 — Kcycles

NCER32K 32 KB CODE Flash endurance 10 — 100 — Kcycles
NCER64K 64 KB CODE Flash endurance 10 — 100 — Kcycles
NCER128K 128 KB CODE Flash endurance 1 — 100 — Kcycles
NDER8K 8 KB EEPROM Flash endurance 100 — — Kcycles
Minimum data retention Blocks with 0 - 1,000 P/E
tDR1k 25 — — Years
cycles
Minimum data retention Blocks with 1,001 - 10,000
tDR10k 15 — — Years
P/E cycles
Minimum data retention Blocks with 10,001 -
tDR100k 15 — — Years
100,000 P/E cycles
1. Program and erase cycles supported across specified temperature specs.

4.15 PLL0/PLL1 electrical characteristics

The device provides a phase-locked loop (PLL0) as well as a frequency-modulated phase-
locked loop (PLL1) module to generate a fast system clock from the main oscillator driver.

Table 27. PLL1 electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

fPLLIN SR — PLL1 reference clock(2) — 37.5 — 78.125 MHz

PLL1 reference clock duty
ΔPLLIN SR — — 35 — 65 %
cycle(2)
fPLLOUT CC D PLL1 output clock frequency — 4.762 — 625 MHz
(3)
fVCO CC P VCO frequency — 600 — 1250 MHz
tLOCK CC P PLL1 lock time Stable oscillator (fPLLIN = 16 MHz) — — 110 µs
fPLLIN = 16 MHz (resonator),
ΔtSTJIT CC T PLL1 short term jitter — — 1.8 ns
fPLLCLK @ 64 MHz
IPLL CC C PLL1 consumption TA = 25 °C — — 6 mA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional
mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN.
3. Frequency modulation is considered ±2%.

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Table 28. PLL0 electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

fPLLIN SR — PLL0 reference clock(2) — 8 — 56 MHz

PLL0 reference clock duty
ΔPLLIN SR — — 30 — 70 %
cycle(2)
fPLLOUT CC D PLL0 output clock frequency — 4.762 — 625 MHz
fVCO CC P VCO frequency — 600 — 1250 MHz
tLOCK CC P PLL0 lock time Stable oscillator (fPLLIN = 16 MHz) — — 110 µs
ΔtSTJIT CC T PLL0 short term jitter fsys maximum — — 300 ps
fPLLIN = 16 MHz (resonator),
ΔtLTJIT CC T PLL0 long term jitter -1 — 1 ns
fPLLCLK @ 64 MHz
IPLL CC C PLL0 consumption TA = 25 °C — — 5.5 mA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified.
2. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional
mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN.

4.16 External oscillator (XOSC) electrical characteristics

Table 29. External Oscillator electrical specifications(1)
Value
Symbol C Parameter Conditions Unit
Min Max

— 4 8
fXTAL CC D Crystal Frequency Range(2) — >8 20 MHz
— >20 40
[Covers: ADD12.017]Crystal
tcst CC T TJ = 150 °C — 5 ms
start-up time (3),(4)
trec CC — Crystal recovery time(5) — — 0.5 ms
EXTAL input high voltage VREF +
VIHEXT CC D VREF = 0.28 * VDD_HV_IO — V
(External Reference) 0.6
VILEXT CC D EXTAL input low voltage(6),(7) VREF = 0.28 * VDD_HV_IO — VREF - 0.6 V
Total on-chip stray capacitance
CS_EXTAL CC T QFP 6.0 8.0 pF
on EXTAL pin(8)
Total on-chip stray capacitance
CS_XTAL CC T QFP 6.0 8.0 pF
on XTAL pin8
P fXTAL ≤ 8 MHz 2.6 11.0
Oscillator Transconductance TJ = -40 °C
gm CC C fXTAL ≤ 20 MHz 7.9 26.0 mA/V
(5 V) to 150 °C
C fXTAL ≤ 40 MHz 10.4 34.0

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Table 29. External Oscillator electrical specifications(1) (continued)

Value
Symbol C Parameter Conditions Unit
Min Max

Oscillation Amplitude on
VEXTAL CC D TJ = –40 °C to 150 °C 0.5 1.6 V
the EXTAL pin after startup(9)
VHYS CC D Comparator Hysteresis TJ = 150 °C 0.1 1.0 V
IXTAL (10)
CC D XTAL current TJ = 150 °C — 14 mA
1. All oscillator specifications are valid for VDD_HV_IO = 3.0 V – 5.5 V.
2. The range is selectable by UTEST miscellaneous DCF clients XOSC_LF_EN and XOSC_EN_40 MHZ.
3. This value is determined by the crystal manufacturer and board design.
4. Proper PC board layout procedures must be followed to achieve specifications.
5. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load
capacitor value.
6. This parameter is guaranteed by design rather than 100% tested.
7. Applies to an external clock input and not to crystal mode.
8. See crystal manufacturer’s specification for recommended load capacitor (CL) values.The external oscillator requires
external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (CS_EXTAL/CS_XTAL)
and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load
capacitor value is selected via S/W to match the crystal manufacturer’s specification, while accounting for on-chip and PCB
capacitance.
9. Amplitude on the EXTAL pin after startup is determined by the ALC block, i.e., the Automatic Level Control Circuit. The
function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to
reduce power, distortion, and RFI, and to avoid over-driving the crystal. The operating point of the ALC is dependent on the
crystal value and loading conditions.
10. IXTAL is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum
current during startup of the oscillator. The current after oscillation is typically in the 2-3 mA range and is dependent on the
load and series resistance of the crystal. Test circuit is shown in Figure 9. The ALC block is the Automatic Level Control
Circuit. The function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation
in order to reduce power, distortion, and RFI, and to avoid overdriving the crystal.

Figure 8. Crystal/Resonator Connections

8-40 MHz EXTERNAL

OSCILLATOR (XOSC) DRIVER

On chip Cx Cy
vsssyn
Off chip

EXTAL XTAL

Crystal or Resonator

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Table 30. Selectable load capacitance

Capacitance offered on EXTAL/XTAL
load_cap_sel[4:0] from DCF record
(Cx and Cy)(1) (pF)

00000 1.032
00001 1.976
00010 2.898
00011 3.823
00100 4.751
00101 5.679
00110 6.605
00111 7.536
01000 8.460
01001 9.390
01010 10.317
01011 11.245
01100 12.173
01101 13.101
01110 14.029
01111 14.957
1. Values are determined from simulation with a tolerance of ±15%.

Figure 9. Test circuit

VDDOSC

Bias current
ALC

IXTAL XTAL
-
EXTAL
+ Comparator
A OFF
VSSOSC

V
VSS
Conditions
Z = R + jωL
VEXTAL = 0 V
VXTAL = 0 V
Tester
PCB GND ALC INACTIVE

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4.17 Internal RC oscillator (16 MHz) electrical characteristics

The device provides a 16 MHz internal RC oscillator. This is used as the default clock at the
power-up of the device.

Table 31. Internal RC oscillator electrical specifications

Value
Symbol C Parameter Conditions Unit
Min Typ Max

fTarget CC D IRC target frequency — — 16 — MHz

IRC frequency variation across temperature
δfvar_noT CC P — -6 — +6 %
and voltage
δfvar_SW — T IRC software trimming accuracy Trimming temperature -0.5 — +0.5 %
Factory trimming
tstart_noT CC T Startup time to reach within fvar_noT — — 5 µs
already applied

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4.18 ADC electrical characteristics

4.18.1 Introduction
The device provides a 12-bit Successive Approximation Register (SAR) analog-to-digital
converter.

Figure 10. ADC characteristic and error definitions

Offset error (EO) Gain error (EG)

4095

4094

4093

4092

4091

1 LSB ideal = VDD_ADC / 4096

4090

(2)

code out
7
(1)
6

5
(5) (1) Example of an actual transfer curve
(2) The ideal transfer curve
4
(3) Differential non-linearity error (DNL)
(4)
(4) Integral non-linearity error (INL)
3
(5) Center of a step of the actual transfer curve

2 (3)

1
1 LSB (ideal)

0
1 2 3 4 5 6 7 4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)

Offset error (EO)

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4.18.2 ADC electrical characteristics

Figure 11 shows the input equivalent circuit for 12-bit SAR channel.

Figure 11. Input equivalent circuit (12- bit SAR)

INTERNAL CIRCUIT SCHEME

VDD
Channel
Sampling
Selection

RSW1 RAD

CP1 CP2 CS

RCMSW Common mode

RSW1: Channel Selection Switch Impedance switch
RAD: Sampling Switch Impedance
CP : Pin Capacitance (two contributions, CP1 and CP2)
RCMRL Common mode
CS : Sampling Capacitance resistive ladder

RCMSW: Common mode switch

VCM
RCMRL: Common mode resistive ladder
VCM : Common mode voltage (~0.5 VDD)

The above figure can be used as approximation circuitry for external filtering definition.

Table 32. ADC input leakage current

Value
Symbol Parameter Conditions Unit
Min Max

Input leakage current, two ADC channels input Tj < 40 °C No current injection — 70
ILKG CC nA
with weak pull-up and weak pull-down Tj < 150 °C on adjacent pin — 220

Table 33. ADC pin specification(1),(2)

Value
Symbol C Parameter Conditions Unit
Min Max

ILKG CC — Input leakage current, two ADC See Table 14: I/O input —
channels on input-only pin. DC electrical
characteristics, parameter
ILKG
IINJ1,2 T — Maximum DC injection current for Per pin, applies to all -3 3 mA
analog pad during overload analog pins.
condition.
CP1 C D Digital input capacitance — — 10 pF
CP2 CC D Internal routing capacitance SAR12-bit channels — 1 pF

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Table 33. ADC pin specification(1),(2) (continued)

Value
Symbol C Parameter Conditions Unit
Min Max

CS CC D SAR ADC sampling capacitance SARn 12bit — 5 pF

RSWn CC D Analog switches resistance SAR 12-bit channels — 1.8 kΩ
RAD CC D ADC input analog switches SAR 12-bit — 0.8 kΩ
resistance
RCMSW CC D Common mode switch resistance sum of the two — 9 kΩ
resistances
RCMRL CC D Common mode resistive ladder kΩ
ABGAP CC D ADC digital bandgap accuracy -1.5 +1.5 %
1. Specifications in this table apply to both packaged parts and Known Good Die (KGD) parts, except where noted.
2. All specifications in this table valid for the full input voltage range for the analog inputs.

Table 34. ADC conversion characteristics

Value
Symbol C Parameter Conditions Unit
Min Max

VIN SR ADC input signal 0 < VIN < VDD_HV_IO VSS_HV_ADR(1) VREFH_ADC V
fADCK SR P Clock frequency — 7.5 12 MHz
tADCPRECH SR T ADC precharge time — 83 — ns
VPRECH SR D Precharge voltage — — 0.25 V
Applies to all internal reference
Internal reference points (VSS_HV_ADR,
ΔVINTREF CC P −0.20 0.20 V
voltage precision 1/3 * VREFH_ADC,
2/3 * VREFH_ADC, VREFH_ADC)
tADCSAMPLE SR P ADC sample time SAR – 12-bit configuration 0.5 — µs
12-bit configuration (12 clock
P 1.000 —
cycles)
tADCEVAL SR ADC evaluation time µs
10-bit configuration (10 clock
D 0.833
cycles)
ADC high reference
current (average Run mode — 15
IADCREFH(2) CC C across all codes) µA

Power Down mode — 1

VDD_HV_ADC_TSENS Run mode — 4.0
IADCVDD CC P power supply mA
current Power Down mode — 0.04

Total unadjusted VREFH_ADC > 3 V -6 6

LSB
TUE12 CC T error in 12-bit
configuration 3 V > VREFH_ADC > 2 V -9 9 (12b)

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Table 34. ADC conversion characteristics (continued)

Value
Symbol C Parameter Conditions Unit
Min Max

VIN < VDD_HV_ADC_TSENS

D VREFH_ADC − — ±1
VDD_HV_ADC_TSENS ∈
[0:25 mV]
VIN < VDD_HV_ADC_TSENS
VREFH_ADC −
D — ±2.0
VDD_HV_ADC_TSENS ∈
[25:50 mV]
VIN < VDD_HV_ADC_TSENS
D VREFH_ADC − — ±3.5
VDD_HV_ADC_TSENS ∈
[50:75 mV]
VIN < VDD_HV_ADC_TSENS
D VREFH_ADC − — ±6.0
VDD_HV_ADC_TSENS ∈
[75:100 mV]
TUE degradation VDD_HV_ADC_TSENS < VIN <
due to VREFH_ADC VREFH_ADC LSB
ΔTUE12 CC
D offset with respect to VREFH_ADC − — ±2.5 (12b)
VDD_HV_ADC_TSENS
VDD_HV_ADC_TSENS ∈
[0:25 mV]
VDD_HV_ADC_TSENS < VIN <
VREFH_ADC
D VREFH_ADC − — ±4.0
VDD_HV_ADC_TSENS ∈
[25:50 mV]
VDD_HV_ADC_TSENS < VIN <
VREFH_ADC
D VREFH_ADC − — ±7.0
VDD_HV_ADC_TSENS ∈
[50:75 mV]
VDD_HV_ADC_TSENS < VIN <
VREFH_ADC
D VREFH_ADC − — ±12.0
VDD_HV_ADC_TSENS ∈
[75:100 mV]
Differential non- LSB
DNL CC P VDD_HV_ADC_TSENS > 3.0 V -1 2
linearity (12b)

1. VSS_HV_ADR is connected to exposed pad for the device.

2. The consumption values are given after power-up when steady state is reached. Extra consumption of up to 2 mA can be
required during internal circuitry setup.

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4.19 Temperature sensor

The following table describes the temperature sensor electrical characteristics.

Table 35. Temperature sensor electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

— CC C Temperature monitoring range — -40 — 165 °C

TSENS CC P Sensitivity — — 5.18 — mV/°C
TACC CC C Accuracy TJ < 150 °C -3 — 3 °C
VDD_HV_ADC_TSENS power
ITEMP_SENS CC C — — — 700 µA
supply current

4.20 JTAG interface timings

Table 36. JTAG pin AC electrical characteristics
No. Symbol Parameter Conditions Min Max Unit

1 tJCYC D TCK cycle time — 100 — ns

2 tJDC D TCK clock pulse width (measured at VDDC/2) — 40 60 %
3 tTCKRISE D TCK rise and fall times (40% - 70%) — — 3 ns
4 tTMSS, tTDIS D TMS, TDI data setup time — 5 — ns
5 tTMSH, tTDIH D TMS, TDI data hold time — 5 — ns
6 tDOV D TCK low to TDO data valid — — 30 ns
7 tTDOI D TCK low to TDO data invalid — 0 — ns
8 tTDOHZ D TCK low to TDO high impedance — — 30 ns
9 tBSDV D TCK falling edge to output valid — — 50 ns
10 tBSDVZ D TCK falling edge to output valid out of high impedance — — 50 ns
11 tBSDHZ D TCK falling edge to output high impedance — — 50 ns
12 tBSDST D Boundary scan input valid to TCK rising edge — 50 — ns
13 tBSDHT D TCK rising edge to boundary scan input invalid — 50 — ns

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Figure 12. JTAG test clock input timing

TCK
2

3 2

1 3

Figure 13. JTAG test access port timing

TCK

TMS, TDI

6
7 8

TDO

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Figure 14. JTAG boundary scan timing

TCK

9 11

Output
Signals

10

Output
Signals

12
13

Input
Signals

4.21 DSPI CMOS master mode timing

4.21.1 Classic timing

Table 37. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0(1)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

SCK drive strength

1 tSCK CC D SCK cycle time
Very strong 25 pF 75 — ns
SCK and PCS drive strength
2 tCSC CC D PCS to SCK delay
Very strong 25 pF 50 — ns

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Table 37. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0(1)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

SCK and PCS drive strength

3 tASC CC D After SCK delay PCS = 0 pF
Very strong 53 — ns
SCK = 50 pF
SCK drive strength
4 tSDC CC D SCK duty cycle(4)
1 1
Very strong 0 pF /2tSCK - 2 /2tSCK + 2 ns
PCS strobe timing

PCSx to PCSS PCS and PCSS drive strength

5 tPCSC CC D
time(5) Very strong 25 pF 25 — ns

PCSS to PCSx PCS and PCSS drive strength

6 tPASC CC D
time(5) Very strong 25 pF 25 — ns
SIN setup time

SIN setup time to SCK drive strength

7 tSUI CC D
SCK(6) Very strong 25 pF 32 — ns
SIN hold time

SIN hold time from SCK drive strength

8 tHI CC D
SCK(6) Very strong 0 pF 0 — ns
SOUT data valid time (after SCK edge)

SOUT data valid SOUT and SCK drive strength

9 tSUO CC D
time from SCK(7) Very strong 25 pF — 5 ns
SOUT data hold time (after SCK edge)

SOUT data hold SOUT and SCK drive strength

10 tHO CC D
time after SCK(7) Very strong 25 pF 2 — ns
1. Protocol clock is 40 MHz and all pads are configured as very strong.
2. All timing values for output signals in this table are measured to 50% of the output voltage.
3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
4. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
5. PCSx and PCSS using same pad configuration.
6. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.
7. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

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Figure 15. DSPI CMOS master mode – classic timing, CPHA = 0

tCSC tASC

PCSx

tSDC tSCK

SCK Output
(CPOL = 0)
tSDC

SCK Output
(CPOL = 1)
tSUI
tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

Figure 16. DSPI CMOS master mode – classic timing, CPHA = 1

PCSx

SCK Output
(CPOL = 0)

SCK Output
(CPOL = 1)

tSUI tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

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Figure 17. DSPI PCS strobe (PCSS) timing (master mode)

tPCSC tPASC

PCSS

PCSx

4.21.2 Modified timing

Table 38. DSPI CMOS master modified timing (full duplex and output only) –
MTFE = 1(1)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

SCK drive strength

1 tSCK CC D SCK cycle time
Very strong 25 pF 50 — ns
SCK and PCS drive strength
2 tCSC CC D PCS to SCK delay
Very strong 25 pF 50 — ns
SCK and PCS drive strength
3 tASC CC D After SCK delay PCS = 0 pF
Very strong 53 — ns
SCK = 50 pF
SCK drive strength
4 tSDC CC D SCK duty cycle(4)
Very strong 0 pF 1/ t -2 1/
2 SCK 2tSCK +2 ns
PCS strobe timing

PCSx to PCSS PCS and PCSS drive strength

5 tPCSC CC D
time(5) Very strong 25 pF 25 — ns

PCSS to PCSx PCS and PCSS drive strength

6 tPASC CC D
time(5) Very strong 25 pF 25 — ns
SIN setup time

SIN setup time to SCK drive strength

7 tSUI CC D
SCK Very strong 25 pF 20 — ns
SIN hold time

SIN hold time from SCK drive strength

8 tHI CC D
SCK Very strong 0 pF 0 — ns
SOUT data valid time (after SCK edge)

SOUT data valid SOUT and SCK drive strength

9 tSUO CC D
time from SCK Very strong 25 pF — 6 ns

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Table 38. DSPI CMOS master modified timing (full duplex and output only) –
MTFE = 1(1) (continued)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

SOUT data hold time (after SCK edge)

SOUT data hold SOUT and SCK drive strength

10 tHO CC D
time after SCK Very strong 25 pF 2 — ns
1. Protocol clock is 40 MHz and all pads are configured as very strong.
2. All timing values for output signals in this table are measured to 50% of the output voltage.
3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
4. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
5. PCSx and PCSS using same pad configuration.

Figure 18. DSPI CMOS master mode – modified timing, CPHA = 0

tCSC tASC

PCSx

tSDC tSCK

SCK Output
(CPOL = 0)
tSDC

SCK Output
(CPOL = 1)
tSUI
tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

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Figure 19. DSPI CMOS master mode – modified timing, CPHA = 1

PCSx

SCK Output
(CPOL = 0)

SCK Output
(CPOL = 1)

tSUI tHI tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

Figure 20. DSPI PCS strobe (PCSS) timing (master mode)

tPCSC tPASC

PCSS

PCSx

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5 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

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5.1 eTQFP64 package information

Figure 21. eTQFP64 package outline

MECHANICAL PACKAGE DRAWINGS

eTQFP64 10x10x1.0 - 4.5x4.5 mm

FOOT PRINT 1.0 mm EXPOSED PAD DOWN
PACKAGE CODE :9I
JEDEC/EIAJ REFERENCE NUMBER : JEDEC MS-026-ACD-HD
REFERENCE : 7278840

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Table 39. eTQFP64 package mechanical data

Dimensions

Symbol Millimeters Inches(1)

Min. Typ. Max. Min. Typ. Max.

A(2) — — 1.2 — — 0.047

A1(3) 0.05 — 0.15 0.002 — 0.006
(2)
A2 0.95 1.00 1.05 0.037 0.039 0.041
b(4), (5) 0.17 0.22 0.27 0.007 0.009 0.0106
(5)
b1 0.17 0.2 0.23 0.007 0.0079 0.0091
c(5) 0.9 — 0.2 0.0354 — 0.0079
c1(5) 0.9 — 0.16 0.0354 — 0.0062
(6)
D 12 0.4724
D1(7), (8) 10 0.3937(2), (5)
D2(9) — — 4.98 — — 0.1961
(10)
D3 3.29 — — 0.1295 — —
e 0.5 0.0197
E(6) 12 0.4724
E1(7), (8) 10 0.3937
E2(9) — — 4.98 — — 0.1961
(10)
E3 3.29 — — 0.1295 — —
L 0.45 0.6 0.75 0.0177 0.0236 0.0295
L1 1 0.0394
N 64 2.5197
R1 0.08 — — 0.0031 — —
R2 0.08 — 0.2 0.0031 — 0.0079
S 0.2 — — 0.0079 — —
1. Values in inches are converted from mm and rounded to 3 decimal digits.
2. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude
beyond that surface.
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed
the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum
space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. To be determined at setting datum plane C.
7. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side.
D1 and E1 are Maximum plastic body size dimensions including mold mismatch.
8. The Top package body size may be smaller than the bottom package size by much as 0.15 mm.
9. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located.
It includes all metal protrusions from exposed pad itself.

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10. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to
be free from resin flashes/bleeds, bordered by internal edge of inner groove.

Note: TQFP stands for Thin Quad Flat Package.

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5.2 eTQFP100 package information

Figure 22. eTQFP100 package outline

MECHANICAL PACKAGE DRAWINGS

eTQFP100 BODY 14x14x1.0 - 5.4x5.4 mm

FOOT PRINT 1.0 mm EXPOSED PAD DOWN
PACKAGE CODE :YE
JEDEC/EIAJ REFERENCE NUMBER : JEDEC MS-026-AED-HD
REFERENCE : 7357321

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Table 40. eTQFP100 package mechanical data

Dimensions

Symbol Millimeters Inches(1)

Min. Typ. Max. Min. Typ. Max.

A(2) — — 1.2 — — 0.0472

A1(3) 0.05 — 0.15 0.019 — 0.0059
(2)
A2 0.95 1.00 1.05 0.0374 0.0394 0.0413
b(4), (5) 0.17 0.22 0.27 0.0067 0.0087 0.0106
(5)
b1 0.17 0.2 0.23 0.0067 0.0079 0.0091
c(5) 0.09 — 0.2 0.0035 — 0.0079
c1(5) 0.09 — 0.16 0.0035 — 0.0063
(6)
D 16 0.6299
D1(7), (8) 14 0.5512
D2(9) — — 5.67 — — 0.2232
(10)
D3 4.0 — — 0.1575 — —
E(6) 16 0.6299
(7), (8)
E1 14 0.5512
E2(9) — — 5.67 — — 0.2232
E3(10) 4.0 — — 0.1575 — —
e 0.5 0.0197
(11)
L 0.45 0.6 0.75 0.0178 0.0236 0.0295
L1 1 0.0394
aaa(12), (13) 0.2 0.0079
(12), (13)
bbb 0.2 0.0079
ccc(12), (13) 0.08 0.0031
1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
2. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude
beyond that surface.
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed
the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum
space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. To be determined at setting datum plane C.
7. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side.
D1 and E1 are maximum plastic body size dimensions including mold mismatch.
8. The Top package body size may be smaller than the bottom package size by much as 0.15 mm.
9. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located.
It includes all metal protrusions from exposed pad itself.
10. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to
be free from resin flashes/bleeds, bordered by internal edge of inner groove.

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11. L dimension is measured at gauge plane at 0.25 above the seating plane.
12. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
13. Tolerance.

Note: TQFP stands for Thin Quad Flat Package.

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Ordering information SPC570S40Ex, SPC570S50Ex

6 Ordering information

Figure 23. Ordering information scheme

Example code:
SPC57 0 S 50 E1 C XXX Y
Product identifier Core Family Memory Package Temperature Custom vers. Packing

Y = Tray
R = Tape and Reel

XXX = Options

B = -40 to 105°C
C = -40 to 125°C
D = -40 to 140°C (max 165°C
junction temperature)1

E1 = eTQFP64 exposed pad

E3 = eTQFP100 exposed pad

50 = 512 KB
40 = 256 KB

S = SPC57S family

0 = Single core e200z0h

functional core

SPC57 = Power Architecture in

55 nm

1. Refer to technical note "SPC570S family - High Temperature "D" Grade (DocID031416 - TN1262)" for
specification limitation applying for this temperature range to this specification.

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7 Revision history

Table 41. Document revision history

Date Revision Changes

08-Apr-2013 1 Initial release

21-Sep-2013 2 Updated Disclaimer
Updated the tables in Section 3.2.4: Pin multiplexing, Section 3.3: Package pads/pins
and Section 4.9.3: I/O output DC characteristics
03-Jun-2014 3
Updated Table 5: Parameter classifications
Updated Table 25: Flash memory program and erase specifications
Changed timing values in Table 25: Flash memory program and erase specifications
12-Jun-2014 4
Added Table 26: Flash memory Life Specification
Throughout the document:
– Editorial and formatting updates
– Changed device name from SPC570S40Ex to SPC570S
– Used slow/medium/fast/veryfast to describe pad strength
– Replaced all occurrences of PLL by PLL0 and FMPLL by PLL1
– Renamed VDD_HV_OSC as VDD_HV_OSC_PMC
– Renamed VDD_HV_ADV and VDD_ADC_TSENS as VDD_HV_ADC_TSENS
– Renamed VDD_HV_ADR as VREFH_ADC
– Renamed VDD_HV_IO_MAIN and VDD_HV_IO_JTAG as VDD_HV_IO
– Renamed VSS_HV_IO as VSS
Clarified descriptions of Figure 6: Noise filtering on reset signal
Removed subsections of Section 3.2: Pin descriptions with referral to the "Signal
description" chapter in the devices’ reference manual
Added Section 4.4: Electromagnetic compatibility (EMC)
26-Mar-2015 5 Added Section 4.5: Electrostatic discharge (ESD)
Added Section 4.8: Current consumption
Updated Section 4.11: Power management electrical characteristics
Added Section 4.12: PMU monitor specifications
Added Section 4.16: External oscillator (XOSC) electrical characteristics
Added Section 4.19: Temperature sensor
Added Section 4.20: JTAG interface timings
Added Section 4.21: DSPI CMOS master mode timing
Added Table 2: SPC570S40Ex, SPC570S50Ex device configuration differences
Table 6: Absolute maximum ratings
– Added: VDD_HV_OSC_PMC, VDD_HV_ADC_TSENS, VREFH_ADC, IMAXSEG
– Changed values for: Cycle, VIN, IMAXD
– Added condition for tXRAY
– Removed TJ
– Updated footnote 1. and parameter descriptions for IINJD and IINJA

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Table 41. Document revision history (continued)

Date Revision Changes

Table 9: Device operating conditions:

– Added: VDD_HV_OSC_PMC, VREFH_ADC - VDD_HV_ADC_TSENS, VIN,
IMAXSEG
– Changed values for: VDD_HV_IO
– Updated parameter descriptions for: VREFH_ADC, VREFH_ADC -
VDD_HV_ADC_TSENS
– Updated classification tags and footnotes for: VDD_HV_IO and VDD_HV_OSC_PMC
– Removed: VDD_LV
Table 14: I/O input DC electrical characteristics
– Added ILKG
– Changed conditions for: VIH, VIL, VHYST, VIHCMOS_H, VIHCMOS(2),
VILCMOS_H(2), VILCMOS(2), VHYSCMOS
– Changed values for: VIH, VIL, CIN
– Removed 4.0 V < VDD_HV_IO < 4.5 V conditions from the Automotive section
Updated Table 15: I/O pull-up/pull-down DC electrical characteristics
Removed “Min” values from tables: 16, 17, 18, 20
26-Mar-2015 5
Removed “Typ” values from tables: 16, 17, 18, 19, 20
Renamed Table 20: I/O output characteristics for pads 4, 9, 11, 55, 56 to include the
pad numbers
Table 21: Reset electrical characteristics changed conditions and values for: IOL_R,
|IWPU|, |IWPD|
Table 22: Voltage regulator electrical characteristics
– changed values and condition description for CDECBV
– removed IMREGINT
Table 25: Flash memory program and erase specifications changed values for: tPSUS,
tESUS
Table 31: Internal RC oscillator electrical specifications
– Removed condition and changed values for dfvar_noT
– Changed values for dfvar_SW
Table 34: ADC conversion characteristics
– Changed values for: IADCREFH, IADCVDD, DNL
– Added footnotes for VSS_HV_ADR and IADCREFH
Table 6: Absolute maximum ratings:
– Updated tXRAY
Table 12: Current consumption:
– Updated IDD information
– Added classification tag, Min Typ and Max columns
– Updated value of maximum consumption during boot time M/LBIST
23-Sep-2015 6 Tables 16, 17, 18, 19:
– Added classification tag, Min Typ and Max columns
Table 23: Trimmed (PVT) values:
– Updated POR200 lower limit
Removed “(pending silicon Qualification)” from the titles of Table 25 and Table 26
Corrected Section 4.12.2: Power up/down sequencing
Reverted to using weak/medium/strong/very strong to describe pad strength

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Table 41. Document revision history (continued)

Date Revision Changes

Throughout the document:

– Editorial and formatting updates
Updated Cover Page
– The following “feature” is added:
“AEC-Q100 qualified.”
– The following “feature” is updated: “Junction temperature range
-40 °C to 150 °C.” to “Junction temperature range -40 °C to 150 °C (165 °C grade
optional).”
Updated Table 1: SPC570Sx device feature summary (Family Superset Configuration)
– Added Junction Temperature value, “165 °C grade optional”.
– New footnote is added, “Refer to technical note "SPC570S family - High Temperature
"D".......specification limitation."
Figure 1: Block diagram
– Added blocks “CMU_3” and “WKPU”.
Table 6: Absolute maximum ratings:
– Updated tXRAY to X-rays dose.
Table 9: Device operating conditions
– Updated TJ by adding a new value, “165 °C grade optional”.
– New footnote is added, “Refer to technical note "SPC570S family - High Temperature
"D".........specification limitation.”
Figure 7: Recommended parasitics on board
31-Jan-2018 7 – Added VDD_HV_IO (ballast supply) (61, 95)
Section 4.7: Thermal characteristics
– Added Table 11: Thermal characteristics for eTQFP100
Section 4.11.1: Voltage regulator electrical characteristics
– Added a note “All 1.2 V pins should be shorted externally on board with minimum
resistance and minimum inductance....... more than 5 mohm resistance and 0.5 nH
inductance.”
Table 26: Flash memory Life Specification
– Updated all the parameters of “NDER16K” to “NDER8K”
Updated Section 4.18.2: ADC electrical characteristics
– Added Figure 11: Input equivalent circuit (12- bit SAR)
– Added Table 33: ADC pin specification,
Table 40: eTQFP100 package mechanical data
– Updated the values of D2 and E2.
Updated Section 4.18: ADC electrical characteristics
– Added Figure 11: Input equivalent circuit (12- bit SAR)
– Added Figure 33: ADC pin specification,
Figure 23: Ordering information scheme
– Updated the value of E1 (Package), “D= -40 to 140 °C” to “D= -40 to 140 °C” (165 °C
junction temperature maximum)
– Added a figure footnote “Refer to technical note "SPC570S family - High Temperature
“D” .........for specification”.

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Table 41. Document revision history (continued)

Date Revision Changes

Updated Section 5.1: eTQFP64 package information

– Figure 21: eTQFP64 package outline updated.
– Figure 39: eTQFP64 package mechanical data updated.
31-Jan-2018 7 (contd.)
Updated Section 5.2: eTQFP100 package information
– Figure 22: eTQFP100 package outline updated.
Table 40: eTQFP100 package mechanical data updated.

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