SAMPLE Paper
SAMPLE Paper
SAMPLE Paper
(1)
The low noise figure is particularly important for the LNA and
mixer, as it directly affects the receiver's sensitivity.
where F is the total noise factor G is power gain.
Additionally, the high linearity is crucial for minimizing the
It is clear that the system noise figure is in fact dominated by distortion and intermodulation products in the output signal,
the noise performance of the first few gain stages. which can degrade the receiver's performance.
(2)
(3)
Fig. 5. Proposed Receiver were integrated with three stage LNA, Gilbert Mixer, and Low-Pass Filter
RESULT
The work describes the design and optimization of an RF [1]Mugadhanam, R., & Uppara, E. Design and Analysis of
receiver front-end using UMC 40nm CMOS technology. The Improved 3-Stage LNA Architecture for CMOS RF Front End
front-end comprises an LNA, a mixer, a current amplifier, and Receiver Systems.
a filter, which were integrated to achieve optimal
performance. To enhance the output current of the LNA and [2]Verma, A., Yadav, P.K., Goswami, M. et al. A Differential
improve the conversion gain and noise performance of the LNA Architecture with Improved Figure of Merit Using 40 nm
receiver front-end, a current amplifier was introduced in the UMC CMOS Technology for mmWave Band Receiver
low IF receiver architecture. Moreover, the performance of Applications. Wireless Pers Commun
the receiver with single-ended LNA and differential LNA was
[3]P. K. Yadav, P. Kumar, A. Verma, S. Ambulker and P. K.
optimized and compared under the same power consumption
Misra, "A 60 GHz, 50 mW, 3dB Noise Figure Receiver
of 50mW. The designed RF receiver is to be simulated and the
Frontend Using UMC 40 nm CMOS technology," 2020 IEEE
obtained results are to be compared with the results of
International Symposium on Smart Electronic Systems
recently reported papers. Cadence Virtuoso ADE is being used
(iSES) (Formerly iNiS), Chennai, India, 2020
to design and simulate the receiver design in UMC 40nm
CMOS technology. The experimental results validate the [4]Verma, A., Yadav, P.K., Ambulker, S. et al. A 36.7 mW, 28
effectiveness of the proposed design in achieving high GHz receiver frontend using 40 nm RFCMOS technology with
performance with low power consumption. The proposed improved Figure of Merit. Analog Integr Circ Sig Process
design can be used as a reference for future RF receiver front-
end designs using UMC 40 nm CMOS technology. [5]A. Pandey, A. Verma and P. K. Misra, "A 3.3dB Noise
Figure,60-mW CMOS Receiver Front End for 865-867 MHz
Band," 2018 Conference on Information and Communication
Technology (CICT), Jabalpur, India, 2018