EE303: Digital System Design

Programmable Logic

Kyeongha Kwon
School of EE, KAIST

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Review: Programmable Read-Only Memory (PROM)
 Example: 32 x 8 PROM (32 words, 8 bit each)
32 X 8 = 256 interconnections
Each intersection could be
programmable if there’s a
switch (connected or not)

Address decoder

8 x 32-input OR

Combinational programmable logic device (PLD)! 2

 Programmable Logic Device (PLD)
 Integrated circuits (ICs) : logic gates with a fixed function

 PLD : programmable gates (AND array + OR array) with undefined function (at the time of manufacture)
− Must be programmed (reconfigured) before use To provide an AND–OR SoP
− Build reconfigurable digital circuits AND array OR array

- 3 kinds of PLD:
- PROM : fixed AND, programmable OR
- PAL : programmable AND, fixed OR
- PLA : programmable AND , OR

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 Programmable Logic Array (PLA)
 PROM’s decoder is replaced with AND array
- Does not provide full decoding of variables and
does not generate all minterms
- Programmable AND array:
- Programmed to generate any product term of input
variable
- Programmable OR array:
- The product terms are connected to OR gates to
generate sum of products

F1 = AB’ + AC + A’BC’
F2 = (AC + BC)’
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 Programmable Logic Array (PLA)
 Fuse map (programming table)
1: Connect to the input line
0: Connect to the input’s complement line
F1 = AB’ + AC + A’BC’ Dash: No connection
F2 = (AC + BC)’
(PLA on slide #4)

1: Connection between AND and OR gates

Dash: No connection
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 Programmable Array Logic (PAL)
 Programmable ANDs + Fixed ORs
- Easier to program, less flexible compared to PLA
- Implements sum-of-products expression

 Fixed outputs
- Each output consists of 3 programmable ANDs and
a fixed 3-input OR  Handles a SOP up to 3 products
Each section
(3 products)
 Feedback path from output F1
- Expand functionality a little bit (check next slide!)

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 Programmable Array Logic (PAL)
 Example

Simplify

(∵AA’=0)

For each 1 or 0

For dash(-)

Using w, z can be represented by a sum of 3 products 7

 Sequential Programmable Devices
 Digital systems = FFs + Logic gates
- Combinational PLD (PLA, PAL) includes only logic gates
- Need to add external flip-flops to PLD
- 3 major types
• SPLD: Sequential (or simple) programmable logic device (PLD)
• CPLD: Complex PLD
• FPGA: Field-programmable gate array

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 Simple Programmable Logic Device (SPLD)
 SPLD: combinational PAL + D flip‐flops Options for FFs
- Bypass FF
− Registered PAL : a PAL that includes flip‐flops - Clock edge
− Macrocell: each section of an SPLD - Reset
- Complement out

 The logic of a basic macrocell

- AND-OR array (the same as combinational PAL)
- New CLK, OE (output enable) input line for FFs
- Output of the flip-flop is fed into inputs to provide
the present state

A basic macrocell 9
Complex Programmable Logic Device (CPLD)
 A collection of simple PLDs on a single integrated-circuit (IC) chip
- IO blocks are connected to IC chip pins CPLD
IC Chip
- Switch matrix allows macrocells to connect each other / I/O pins
- Each PLD usually consists of 8-16 macrocells (<1000 macrocells per CPLD)

IC chip pins

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 Field Programmable Gate Array (FPGA)
 ICs that can be programmed following the user’s requirement
- An array of millions of programmable logic blocks + programmable IO blocks +
programmable interconnections
- Logic block = lookup tables, multiplexers, gates, and FFs
- Lookup table (LUT): a truth table stored in an SRAM (programmable unlike ROM)
- FPGA chips become more popular due to high IC fabrication costs / new applications (AI)

The two major FPGA companies, Altera and Xilinx, are acquired by Intel and AMD, respectively.
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 Field Programmable Gate Array (FPGA)
 Xilinx FPGA
− The first FPGA XC2000 (1985) consists of 600~1500 logic
gates.
− Recent Virtex UltraScale+ (2019) consists of 35B transistors,
which build 9 million logic cells.
− AMD acquired Xilinx on Feb. 2022, paid $49B. The biggest
acquisition in the history of the chip industry.

 Basic components of Xilinx FPGA

- Configurable logic block (CLB)
- Local/global routing wires
- Input-output block (IOB)
- SRAM-based configuration memory
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 State-of-the-Art Xilinx FPGA
 Virtex Ultrascale+
- Fabricated using TSMC 16nm process
- Offers 9M logic cells

 Targets
- Level of integration
- Amount of embedded memory
- Performance (speed)
- Subsystem interfaces

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 FPGA Implementation Flow
 Electronic design automation (EDA)
- Extensive computer-aided design (CAD) tools are required
- Synthesis: Converting high-level description of design into an optimized gate-level
representation
- Place & route (P&R): Decide where to place all logic components and how to connect
them efficiently

Verilog Gate-level Design Map to FPGA

(Behavioral) Synthesis P&R
A
.
+ C
B
.
C = A+B S = ABCi + A’B’Ci + AB’Ci’ + A’BCi’
. Co = ABCi + A’BCi + AB’Ci + ABCi’ 14
 Summary
 Programmable logic allows for designers to easily create custom designs
 PLAs and PALs contain AND-OR structure to implement SOP equations
 You can design sequential circuits with sequential PLDs
− This means general logic design is possible

 FPGAs contain a lot of logic blocks, small memories, and abundant wiring
resources for routing
 Designs described using Verilog
- Translated to the physical circuit via CAD tools

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 Notice
 The Last Homework
− HW#7 (for Chapter 7) will be posted this Friday – due: Next Friday

 Additional tutoring? Email to TA in charge of tutoring on Chapter 7

− Sara Kim (김사라, sara@kaist.ac.kr)

− Namhoon Kim (김남훈, namwide@kaist.ac.kr)

 Questions? CLASSUM, KLMS Q&A board, zoom

− https://kaist.zoom.us/j/7210364938 (PW: 22304) - by appointment

 A brief survey!
− https://forms.gle/4tuVLSffqbdJTPym8

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