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    DSD Lab 5

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    1) The document describes designing, simulating, and implementing a 4-bit ALU on an FPGA kit. It includes a truth table listing the ALU operations, Verilog code for the ALU module and testbench, and simulation and synthesis results. 2) The procedure involves writing Verilog code, simulating it, setting constraints, running synthesis and implementation, and generating a bitstream to download to the FPGA kit. 3) Results show the ALU performing OR and ADD operations as expected based on input test vectors and control signals. Implementation on the FPGA kit is successful.

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    DSD Lab 5

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    Thoughts
    35 views5 pages
    1) The document describes designing, simulating, and implementing a 4-bit ALU on an FPGA kit. It includes a truth table listing the ALU operations, Verilog code for the ALU module and testbench, and simulation and synthesis results. 2) The procedure involves writing Verilog code, simulating it, setting constraints, running synthesis and implementation, and generating a bitstream to download to the FPGA kit. 3) Results show the ALU performing OR and ADD operations as expected based on input test vectors and control signals. Implementation on the FPGA kit is successful.

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    DSD LAB 5

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    1) The document describes designing, simulating, and implementing a 4-bit ALU on an FPGA kit. It includes a truth table listing the ALU operations, Verilog code for the ALU module and testbench, and simulation and synthesis results. 2) The procedure involves writing Verilog code, simulating it, setting constraints, running synthesis and implementation, and generating a bitstream to download to the FPGA kit. 3) Results show the ALU performing OR and ADD operations as expected based on input test vectors and control signals. Implementation on the FPGA kit is successful.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    35 views5 pages

    DSD Lab 5

    Uploaded by

    Thoughts
    1) The document describes designing, simulating, and implementing a 4-bit ALU on an FPGA kit. It includes a truth table listing the ALU operations, Verilog code for the ALU module and testbench, and simulation and synthesis results. 2) The procedure involves writing Verilog code, simulating it, setting constraints, running synthesis and implementation, and generating a bitstream to download to the FPGA kit. 3) Results show the ALU performing OR and ADD operations as expected based on input test vectors and control signals. Implementation on the FPGA kit is successful.

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    University of Engineering
    &
           Technology, Taxila
     

      

    DSD  
    Lab Manual# 05
     
    GROUP NO 3
     
    6 SEMESTER
    TH

     
    OMEGA SECTION
     
    SUBMITTED TO: ENGR.ASGHAR ISMAIL
     
     
    Dated;
    18/07/2023
     
    Objective: Designing, Simulating and Implementing the HDL code for 4-bit ALU with following Inputs
    and Outputs. A: 4-bit input • B: 4-bit input • Cin: 1-bit input • Control: 3-bit control input • Output: 4-bit output

    Procedure:
    Following is Procedure for Implementation on FPGA kit
    1. Writing the Source Code of module and simulating it
    2. Opening Elaborated Design
    3. Setting Constraints
    4. Running Synthesis
    5. After Successful Synthesis Running Implementation
    6. After Successful Implementation Generating Bit Stream
    7. Downloading Bit Stream to FPGA kit using Hardware Manager

    Apparatus List:
    Board: Arty A7-100 Part: xc7a100tcsg324-1
    Product & Family: Artix-7 Nexys4 FPGA Kit Software: Vivado 2019.1

    TASK 1:

    4-Bit ALU Simulation and Implementation on FPGA Kit

    Truth Table

    S[2:0] Out[7:0]
    000 A+B
    001 ~B
    010 A.B
    011 A|B
    100 A>>>1
    101 A<<<1
    110 A==B
    111 A!=B
    Verilog Code:
    Source code Testbench
    module BIT_ALU4(alu_out, alu_op, module ALU();
    alu_in1,alu_in2); input[3:0]alu_in1; reg[3:0]alu_in1;
    input[3:0]alu_in2; input[2:0]alu_op; reg [3:0] alu_in2;
    output reg[3:0]alu_out; reg [2:0]alu_op;
    always@(alu_in1 or alu_in2 or wire
    alu_op) begin case(alu_op) [3:0]alu_out;
    3'b000: alu_out <= alu_in1+alu_in2; BIT_ALU4 DUT (.alu_in1(alu_in1),
    3'b001: alu_out <= ~alu_in2; .alu_in2(alu_in2), .alu_op(alu_op),
    .alu_out(alu_out));
    3'b010: alu_out <= alu_in1&alu_in2;
    initial begin
    3'b011: alu_out <= alu_in1|alu_in2; alu_in1= 4'b0100;
    3'b100: alu_out <= alu_in1>>>alu_in2; alu_in2= 4'b1001;
    3'b101: alu_out <= alu_in1<<<alu_in2; alu_op= 3'b011; #10
    alu_op=3'b000; end
    3'b110: alu_out <= alu_in1==alu_in2;
    endmodule
    3'b111: alu_out <= alu_in1!=alu_in2;
    default: alu_out <=0;
    endcase
    end endmodule

    RESULTS:
    Simulation:
    Schematic Diagram:
    FPGA Implementation:

    1) a3a2a1a0=1011 , b3b2b1b0=1001 op= 011 2) a3a2a1a0=1011 , b3b2b1b0=1001


    op= 000

    Conclusion:
    We observe from this experiment that 4-bit ALU will take 2 inputs of 4 bit each and a 3-bit opcode.
    This opcode decides which operation must be performed. Results are verified through implementation
    on FPGA Kit

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