Lab 06

Laboratory Report Cover Sheet
UET ABBOTABAD CAMPUS

Faculty of Department of Electronics Engineering
ELE-408
FPGA BASED SYSTEM DESIGN
7th Semester fall 2020
Name:
Register No./C.NO :
Venue: Computer Laboratory # 1
Lab No. : 6
Lab Tile : clock division using Internal Clock Of Spartan 3 Board And Blinking An
External Connected Led At Different Frequency.
Date of Conduction:
Date of Submission:
Particulars Maximum Marks Marks Obtained
Pre –lab 20
Post lab Codes/simulation 30
Data analysis 30
Punctuality 20
Total 100
REPORT VERIFICATION
Date:
Instructor Name: Engr. Mehmoona Gul
Signature:
LAB #6
CLOCK DIVISION USING INTERNAL CLOCK OF SPARTAN 3
BOARD AND BLINKING AN EXTERNAL CONNECTED LED AT
DIFFERENT FREQUENCY
6.1 AIM
The aim of this lab is to introduce the student how to use the expansion connector to connect FPGA to
external environment. And this will be done by writing a Verilog code that blinks an led connected to A1
port of development board at different frequency. The blinking frequencies will be set by accessing the
internal clock oscillator.
6.2 OBJECTIVE
After completing this lab, you will be able to:
 Blink an led at different frequency

 Use expansion connector for little project to take input and send output to external design
circuits
 use internal oscillator to drive different frequencies of interest
6.3 THEORY
6.3.1 INTRODUCTION
The Spartan-3 Starter Kit board has three 40-pin expansion connectors labeled A1, A2, and B1.
The A1 and A2 connectors, indicated as and, respectively, in Figure 6-1, are on the top edge of
the board. Connector A1 is on the top left, and A2 is on the top right. The B1 connector,
indicated as in Figure 6-1, is along the right edge of the board.
Each port offers some ability to program the FPGA on the Spartan-3 Starter Kit Board. For example, port
A1 provides additional logic to drive the FPGA and Platform Flash JTAG chain. Similarly, ports A2 and B1
provide connections for Master or Slave Serial mode configuration. Finally, port B1 also offers Master or
Slave Parallel configuration mode. Each 40-pin expansion header, shown in Figure 13-2, uses 0.1-inch
(100 mil) DIP spacing. Pin 1 on each connector is always GND. Similarly, pin 2 is always the +5V DC
output from the switching power supply. Pin 3 is always the output from the +3.3V DC regulator.
The pinout information for each connector appears below
6.3.2 A1 CONNECTOR PINOUT

The A1 expansion connector is located along the top edge of the board, on the left, as indicated by in
Figure 6-1 . Table 6-2 provides the pinout for the A1 connector. The FPGA connections are specified.
The A1 expansion connector shares connections with the 256Kx16 SRAM devices, specifically the SRAM
address lines, the OE# and WE# control signals, and the eight least significant data lines to SRAM IC10
only. Similarly, the JTAG chain is available on pins 36 through 40. Pin 20 is the FPGA DOUT/BUSY
configuration signal and toggles during the FPGA configuration process.
6.3.3 A2 CONNECTOR PINOUT

The A2 expansion connector is located along the top edge of the board, on the right, as indicated by in
Figure6-1. Table 6-2 provides the pinout for the A2 connector. The FPGA connections are specified in
parentheses. Most of the A2 expansion connector pins connect only with the FPGA and are not shared.
Pin 35 connects to the auxiliary clock socket, if an oscillator is installed in the socket. Pins 36 through 40
include the signals required to configure the FPGA in Master or Slave Serial mode.
6.3.4 B1 CONNECTOR PINOUT
The B1 expansion connector is located on the right edge of the board, as indicated by in Figure 6-1.
Table 6-3 provides the pinout for the B1 connector. The FPGA connections are specified in parentheses.
Most of the B1 expansion connector pins connect only with the FPGA and are not shared. Pins 36
through 40 include the signals required to configure the FPGA in Master or Slave Serial mode. These
same pins plus pins 5, 7, 9, 11, 13, 15, 17, 19, and 20 provide the signals required to configure the FPGA
in Master or Slave Parallel mode.
6.3.5 ON BOARD CLOCK
The board is also provided with an oscillator of 50MHz at the back side as shown in Figure 6-2.
The Spartan-3 Starter Kit board has a dedicated 50 MHz Epson SG-8002JF series clock oscillator source
and an optional socket for another clock oscillator source. Anyone can Use the 50 MHz clock frequency
as it is or derive other frequencies using the FPGAs Digital Clock Managers (DCMs). The pin configuration
to access the clock and socket is shown in the table.
6.4 PRE-LAB:
1. Calculate the bit size of the register to count 50MHz of clock signal.
2. write a Verilog code for a simple up-counter that count up to 50000000.

6.5 SOFTWARE TOOLS REQUIREMENT
Equipment:
Computer with ISE Software
Specifications:
 HP Computer i7 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk
 Software: ISE
6.6 HARDWARE SETUP

 Make a simple circuit on the breadboard by connecting an led with 1k ohm resistor
 Make the connection between A1- Connector of the fpga board and the external
light circuit.
6.7 VERILOG CODE

6.7.1 FOR LED BLINKING
module blinking ( CLOCK_50, LEDG);
input CLOCK_50;
output LEDG
reg [32:0] counter;
reg stateled ;
assign LEDG = stateled;
always @ (posedge CLOCK_50)
begin
counter <= counter + 1;
stateled <= counter[26];
end
endmodule
6.7.2 FOR CLOCK DIVISION/DIFFERENT FREQUENCY

GENERATION CODE
module freqqqq(
input clk,
output reg freqled
);
reg[26:0] counter=27'd0;
parameter dividingfactor = 27'd4;

always @(posedge clk)
begin
counter <= counter + 27'd1;
if(counter>=(dividingfactor-1))
counter <= 27'd0;
freqled <= (counter<dividingfactor/2)?1'b1:1'b0;
end
endmodule
6.8 PROCEDURE:
1. Double click the project navigator and select the option File-New project.
2. Give the project name.
3. Select Verilog module.
4. Type your Verilog coding.(described in sec 4.6 )
5. Check for syntax.
6. Choose behavioral simulation and simulate it by Xilinx ISE simulator.
7. Define UCF file.
8. Synthesize your design.
9. Implement your design
10. Generate programming file
11. Using JTAG cable configure your target device with .bit file
12. Verify the output on the fpga by watching the status of led.
6.9 IN LAB-TASK
1. Write a code for slow blinking of led.
2. Simulate the code and verify the results .
3. Create different frequencies using the above clock division method
Result
POST-LAB TASK
Write a code fo 10-sec watch. And display result on seven segment.

RESULT

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Laboratory Report Cover Sheet

UET ABBOTABAD CAMPUS

Post lab Codes/simulation 30

Instructor Name: Engr. Mehmoona Gul

 Blink an led at different frequency

The pinout information for each connector appears below

6.3.2 A1 CONNECTOR PINOUT

6.3.3 A2 CONNECTOR PINOUT

2. write a Verilog code for a simple up-counter that count up to 50000000.

6.6 HARDWARE SETUP

6.7 VERILOG CODE

module blinking ( CLOCK_50, LEDG);

reg [32:0] counter;

assign LEDG = stateled;

always @ (posedge CLOCK_50)

counter <= counter + 1;

stateled <= counter[26];

6.7.2 FOR CLOCK DIVISION/DIFFERENT FREQUENCY

output reg freqled

parameter dividingfactor = 27'd4;

counter <= counter + 27'd1;

counter <= 27'd0;

freqled <= (counter<dividingfactor/2)?1'b1:1'b0;

Write a code fo 10-sec watch. And display result on seven segment.

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