LaPlace Transforms in Design and

Analysis of Circuits
Part 5: Active Circuit Design & Analysis

Course No: E05-004

Credit: 5 PDH

Thomas G. Bertenshaw, Ed.D., P.E.

Continuing Education and Development, Inc.

22 Stonewall Court
Woodcliff Lake, NJ 07677

P: (877) 322-5800
info@cedengineering.com
 LaPlace Transforms in Design and Analysis of Circuits©
Part 5
by Tom Bertenshaw

Active Circuit Design and Analysis

A Generic Device

For the present we will restrict active circuits to be designed around a class of amplifiers
and filters implemented using Operational Amplifiers (OpAmps) for two reasons: a) they
possess a very high input impedance (an FET input), and b) their input circuitry contains
a differential amplifier that, when coupled with external feedback, drives the difference
between its two inputs to be zero. There are certainly other attributes to OpAmps, but for
now we will use just these two in developing an ensemble of basic building block
circuits. We will assume the gain-bandwidth product, source and sink currents, slew rate,
etc. of the OpAmp are sufficient for our purposes. In other words, we are leaving the
study of OpAmps themselves to another course.

Further, since the necessary DC power circuitry seldom impacts the response of active
amplifiers and filters beyond setting upper and lower bounds on voltage excursions, we
will also forgo those considerations in this module. Suffice it to say that we will work
with a generic device limited to excursions of  15V . If other values are necessary at any
point, they will be identified.

At this juncture, just keep in mind the salient feature of very high input impedance 1; so
high that when compared to external circuitry current flow values, any current flow into
the OpAmp can be ignored (nano amps). This is another of those For-All-Practical-
Purposes events). Also, keep in mind that external feedback causes the difference in
input values to be driven to zero (there will always be external feedback as the open loop
gain of an OpAmp is at, or over, a factor of 10 5 ). So, the characteristics to keep in mind
are a) no input current; and b) input A is driven to be the same voltage potential as input
B.

A
Vout
B

The OpAmp is basically a voltage driven voltage device, and gains are usually taken to
mean voltage gain. The OpAmp will sink and source current to the external circuitry
however, and the manufacturer’s data sheet for the particular device under consideration
will detail those and all other relevant parameters necessary to successfully use the
device.
1
a few megohms, or less, for PN junction devices to tens or even hundreds of megohms for FET's

1
Our generic OpAmp looks like (schematically):

Circuit #1

Inverting
Input
Vout
Noninverting
Input

When a positive going signal is applied to the inverting input it appears at the output as a
negative going signal, i.e., it is inverted. When a positive going signal is applied to the
non-inverting input, it appears at the output as positive going signal, i.e., its polarity is
preserved. Because of transit times there will be a small phase shift in the output, but that
effect is also assumed to be trivial for our purposes.

Basic Amplifiers

Inverting Amplifier

Circuit #2

i2 Ro

Ri
Vin
Vout
i1
A

Pt. A
Point A is at the same potential as the non-inverting input; it is a virtual ground at zero
volts potential (in actual design practice there is a small output offset caused by a trivial
input current, but FAPP (For All Practical Purposes2) the potential is caused to be zero
through a DC offset input (not shown) on the OpAmp).

Since no current flows into the OpAmp, i1  i 2 , using that fact:

V in  0 0 V
 out

Ri Ro

Re-arranging:

2
John S. Bell, 1928-1990, Physicist Extraordinaire

2
 V out Ro
 
V in Ri

Ro Ro
Since    180 , the minus sign simply means that there is a phase inversion.
Ri Ri

For example:

10

1
Vin
Vout
A

Assume V in  sin 5 t  , then the transform is:

 50
V out   10 sin 5 t  or V out ( s ) 
s  25
2

For convenience:

10

1
Vin
Vout
A

may be represented by the shorthand schematic:

-10

The second symbol is understood to be identical to the first as far as circuit behavior in
all parameters is concerned. It is merely shorthand. Bear in mind that the first, or upper,
schematic symbol is also a shorthand version of the detailed engineering drawing used
for production. Those details will not be addressed in this series of modules, but are
reserved for a course dealing in OpAmp fundamentals.

3
An example of use:

Low Pass Circuit

-10

For the above circuit, assume RC=.1, and bear in mind that the minus sign represents a
180o phase change at the output, but the absolute value of the amplification is 10. Then,
the transfer function is:
V out 100 180

V in s  10

and the plotting equations are:

 
2 
Mag .  20 log( 10 )  20 log  1 
 100 
 

1  
Phase   180  tan  
 10 

Lo-Pass with a Gain of 10

25.0
20.0
15.0
10.0
Magnitude db

5.0
0.0
-5.0
-10.0
-15.0
-20.0
-25.0
0.1 1 10 100 1000
Freq.

4
 Phase

-180.0
Phase (degrees w/respect to

-190.0
-200.0
-210.0
Input)

-220.0
-230.0
-240.0
-250.0
-260.0
-270.0
0.1 1 10 100 1000
Freq.

Let's extend this exercise to include a driver of sin(100t). Than the transfer function is:

 10000 . 9   180 . 995 100  95 . 7 o

V out ( s )   
 s  10 s 2  10
4
 s  10 s  100
2 2

Because it was known that the output phase with respect to the input varied between -180
and -270 (+90) minus what was chosen as the operator on the angle. Be careful when
using arctan in your calculator or software program; some devices only return answers
for quadrants I & IV and its left to you to keep track of the quadrant you are in.
Question: Why in the above example is the output magnitude less than 10?

The Bode plot predicts an output of 1*input @ -265o for an input at 100 rads/s. That
prediction closely approximates the calculated result. There is a small amount of error in
the calculations for both the plots and the calculated result due to round off (which is an
arbitrary choice).

Completing the analysis for the above circuit, using a FAPP approach:

 10 t
V out ( t )  sin( 100 t  264 )  . 9 e
o

Non-inverting Amplifier

The non-inverting amplifier schematic (non-detailed) looks like:

5
 Vin
Vout
Pt. A

Rf

Ri

The voltage at point A is:

 Ri 
V Pt . A   V
 R  R  out
 i f 

But the voltage at point A must also equal V in because of the external feedback network
of R i & R f , so re-arranging:

V out Rf
1
V in Ri

Its shorthand version is:

+X

where X is the numerical value of the gain. So, an amplifier with a gain of 10 would look
like:

6
 Vin
Vout

+10

A note of caution is warranted here. In these modules values are chosen to illustrate a
point. In practice resistances of 1  & 9  may not be practical because of current draw
and I2R heating in the OpAmp; but it should be clear that Rf must be 9X the value of Ri to
achieve a gain of +10. Choose Ri and Rf with a view to limiting the current draw from
the OpAmp; 100 & 900 ohms would limit the current draw to 15ma when the supply
is  15V .

Repeating the exercise for the inverting OpAmp, but as a non-inverting amplifier with
RC=.1:

+10

The transfer function is:

V out 100

V in s  10

The plotting equations unsurprisingly are:

 2 
   
Magnitude  20 log( 10 )  20 log 1  
  10  
 
and

7
 1  
Phase  0  tan  
 10 

The magnitude plot is identical to the plot for the -10 voltage gain lo-pass.

Lo-Pass with a Gain of 10

25.0
20.0
15.0
10.0
Magnitude db

5.0
0.0
-5.0
-10.0
-15.0
-20.0
-25.0
0.1 1 10 100 1000
Freq.

But the phase plot has different values on the Y axis.

Gain 10 Lo-Pass

0.0
-10.0
-20.0
Phase (degrees)

-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
-100.0
0.10 1.00 10.00 100.00 1000.00
Freq.

This time, we will drive the system with sin(10t). The transfer function is now:

( 7 . 07 ) 10   45
o
1000 .1
V out   
( s  10 )( s  10 )
2 2
( s  10 ) s 2
 10
2

The steady state amplitude of 7.07 is nicely consistent as the -3db point is .707 of max.
Since max is 10 in this case, our answer checks.

8
The net result of combining a voltage gain amplifier with a lo-pass filter is merely to
change the operating amplitude from a 0db floor. Of course an attenuator will also
function in a similar fashion. Notice that in the impulse response transfer function the
amplifier affects the magnitude of N(s) and does nothing to D(s). Ideally that is what we
are after; but in practice the OpAmp will not be ignored and it will impress its gain-
bandwidth product (GBW) on the output. We generally ignore that troublesome fact in
pedagogic treatises as the assumption is that the GBW is many times the bandwidth
needed. Sadly, in real life as we deal with frequencies tending into the microwave
region, consideration of the actual operating parameters of the OpAmp cannot be ignored,
and models such as S parameters become convenient. But, that tale is left for another
time. For now assume the GBW of the OpAmp is sufficient to pass undiminished any
signal within the bandwidth of our pedagogic interest.

An attenuator with a gain of . 1 looks like:

10
Vin
Vout
A

This attenuator is preferred over a simple voltage divider as any circuitry to the right of
Vout is invisible to the driver (Vin). These are great devices for isolating one circuit from
another and bypassing the loading problem.

The Summer

The summer is a utility workhorse circuit. Its function is to sum N inputs into a single
output. Simultaneously with summing, this circuit can be used to apply tailored gains to
each of its N inputs. Its schematic looks like:

R1
V1 Rf

Rk
Vk
Vout
Rn
Vn A

There are some rules to be observed when using a summer; it is required to operate in its
linear region of amplification so that superposition applies. Non-linear operation of any
input destroys information as the output is forced to a voltage rail (i.e., DC power supply

9
voltage); voltage rail outputs can not distinguish between input variations, i.e., input
information is lost as the sum of input excursions causes a collision with the rail.
Secondly, the input to the inverting input must be a virtual ground; this is accomplished
by causing the non-inverting input to be at 0 volts potential (you will know that it is
adjusted correctly if all inputs are grounded and V out  0 ).

Beginning the analysis:

R1
V out (V 1 )   V1
Rf
:
:
Rk
V out (V k )   V k
Rf
:
:
:
Rn
V out (V n )   Vn
Rf

Summing them all:

 R R R 
V out    1 V 1  .......... .  k V k  .......... ....  n V n 
R Rf Rf 
 f 

Bear in mind that it is prudent to require V out to maintain a small potential below the
positive rail and a small amount above the negative rail as a margin of safety; usually 1v
is sufficient.

The shorthand symbol for a summer is:

v1

v2 Σ vout
vn

The Buffer

We have one more elementary circuit to consider before we begin the discussion of the
more complex basic circuits; and that elementary circuit is the buffer. Its schematic is:

10
 Vout
Vin

The transfer function is:

V in  V out  0 or re-arranging V out  V in

And for this one:

Vin -
Vout
+

V in  V out  0 or V out  V in

The utility of this circuit is two fold; a) it has a sufficiently high input impedance that it
does not load the circuit providing V in and b) its output impedance is very low to the
circuit that the buffer is providing V out to; i.e., it looks like an ordinary low impedance
voltage supply. It provides major design advantages in that it isolates one circuit stage
from another, minimizing loading effects and maximizing voltage transfer from stage to
stage. Its shorthand schematic is:

±1

An illustration of use:

-10 1 Ckt. 2

The buffer prevents input impedance of Ckt. 2 from appearing in parallel with the lo-pass
filter. This arrangement preserves the filter's transfer function by not allowing the input
impedance of Ckt. 2 to alter the impedance and/or voltage division ratio of the filter. For
example, if the buffer were not there, then the filter impedance is altered in this way:

11
 -10

Zin
Ckt. 2

The lo-pass transfer function with the buffer is:

 1 
 10  
V out  RC 

V in 1
s
RC

Without the buffer the transfer function becomes:

 1 
 10  
V out  RC 

V in 1 1
s 
Z in C RC

Clearly the break frequency has shifted and the shift is dependent on Zin. But if Z in is
complex, then in turn, it is a function of frequency; this is a nasty loading problem. Use a
buffer to obviate that un-necessary complication. Task: Derive the above equation by
considering that the current through the resistor must equal the current through the
parallel combination of Z in & 1 .
sC

One last point: with the buffer in the circuit, the parallel combination of Z in (of the
buffer) and the capacitor is:

Z in X C
Zp 
Z in  X C

Because Z in  X c , Z p  X C and the loading problem vanishes towards zero. Older

engineers can recognize the similes between the solid state buffer and a vacuum tube
triode amp with unity gain.

12
 Mathematical Function Circuits

The Integrator

Consider the following circuit:

1/sC

Ri
Vin
-1 Vo
A

The transfer function is:

Vo 1 
 
V in sRC s

when V in is a unit step, then:


Vo  2
s

The time response, as a function of  is:

Vo (t )  t

Time Response

10

8
Magnitude

0
0 1 2 3 4 5 6 7 8 9 10
Time (sec)

a=.5 a=1 a=.1

13
This circuit presents a linear voltage rise as a function of time; as such, it has utility as a
timer that uses voltage comparisons as a trigger, or in any circuit that requires a linear
rise with respect to time. As a designer, you have control over the slope via choosing the
combination of RC that suits your purpose.

So, when the input is a unit step, this circuit integrates. But what if the input is a
sinusoid? In that case:

 
  90
a o o o
V0   

s s  o
2 2
 s s  o
2 2


Vo (t )  u ( t )  sin(  t  90 ) 
o

o
o


which is essentially a sinusoid riding a DC potential of . For the sake of illustration,
o
assume the usual RC=.1, and that  o  10 .

The plotting equation:

 2 
  
Magnitude  20 log( 100 )  20 log(  )  20 log  1   
  10  
 

The Integrator has now become a Lo-Pass filter with a controlled gain.

Lo-Pass w/Gain

40
20
Magnitude (db)

0
-20
-40

-60
-80
-100
0.1 1 10 100 1000
Freq.

As expected, there is -20db/decade roll-off until 10 rads/s. At that point the roll-off
increases to -40 dc/dec. Since we have established that with a step input this circuit

14
integrates, we should expect a gain in very low frequencies, and indeed there is a
significant gain.

Lo-Pass w/Gain

-90
-100
-110
Phase (degrees)

-120
-130
-140
-150
-160
-170
-180
0.1 1 10 100 1000
Freq.

Changing the Break Point: Integrator/Lo-Pass with Gain

Consider this circuit:

Rf

1/sC

Ri
Vin
-1 Vo
A

1
Step one is to develop a suitable expression for the parallel combination of & Rf .
sC

Rf 1
sC Rf C
 
1 sCR 1 1
Rf  f
s
sC RfC

The buffer may or may not be needed in an actual circuit; it is included here merely to
preserve polarity in the example.

15
We will keep this result in mind as it comes to play a frequent role in active circuits. In
general then, the impedance when R C (read "R is in parallel with C") is:

1
Cx
1
s
R xC x

then it follows that the complete transfer function becomes:

1
Vo RiC

f

Vi 1
s
RfC f

Notice that now the break frequency and the gain (as represented by N(s)) are now
decoupled and dependent upon two separate circuit parameters: R i & R f . Also that
Rf
when   0 , gain has devolved back to an expected , so the plotting equation is:
Ri

 2 
 Rf      
Magnitude  20 log    20 log
  1  


 
 Ri    o  
 

1
where  o  . And, of course:
RfC

1   
Phase  0  tan  
 
 o 

Rf
Assuming R f C  . 1 , and that  10 , then:
Ri

 
2 
Magnitude  20 log( 10 )  20 log  1  
 100 
 

16
 Computed Single Pole Lo-Pass

25.0
20.0
15.0
10.0
Msgnitude

5.0
0.0
-5.0
-10.0
-15.0
-20.0
1 10 100 1000
Freq

The above has the exact same response of the previous lo-pass with a gain of 10 circuit,
but with fewer components. Fewer components equal higher reliability and longer
MTBF3, resulting in a more compact circuit. While this case is trivial, it serves to open
the door to the design philosophy of component count minimization.

As an exercise, assume that a gain of 15 is needed and the circuit is to have a break
frequency at 100 rads/s. Further assume that a 1μf capacitor is chosen. Then since
ωo=100, the time constant is .01; further as C=1X10-6, Rf must equal 10KΩ. Gain is 15
which clamps Ri to 667Ω - a non-standard value.
10K

1μf
1K

Vin
-1 Vo

2K A

At this point the designer has the option of accepting a non-standard value for Ri or to
find some standard component mix of values for capacitance and resistance that will
simultaneously satisfy RfCf=.01 and Rf=15*Ri - it all depends upon what is acceptable
for the production line. A 2KΩ resistor in parallel with a 1KΩ would do the job; but it
adds to the component count. A standard value of 680Ω could be used, but the gain will
not equal 15. There seems to be no optimum solution; just choices that offer different
problematic aspects. Question: How could a change of requirement to a -40db/dec roll-

3
Mean Time Between Failures

17
off be handled? Again, in the above circuit, the buffer is included only to preserve
polarity in the example; in practice it may or may not be needed.

A Mythical Differentiator

This circuit deserves some serious discussion concerning the convenience of schematic
representation versus the realities of the component needs. The conventional schematic
is:

Rf
Ci
V1
Vout
A

First let's consider the transfer function:

V out  Rf
   sR f C i
V in 1
sC i
or, re-written:

V out   R f C i  sV in 
or, more compactly:

V out  K 1 sV in

Which says Vout equals the derivative of Vin scaled by the factor RfCi. Clearly this is a
very useful circuit. We now have a method of obtaining the derivative of an input, and
we retain control over the scale factor. Great! Or is it?

Consider the case when the op-amp has been properly offset such that V   V  =0, then
Vout also equals zero. The junction of the capacitor and Rf is now a virtual ground.
While that point is at a virtual zero volts potential, you cannot draw current into the op-
amp negative input from this virtual ground as no DC current can flow through the
capacitor. Bear in mind that in a real circuit, although the bias current is trivial, it is still
needed (biases the input gate of an FET). A physical ground is needed. As there is no
DC path to ground from the V  input, proper internal bias cannot be obtained, i.e., the
circuit cannot be depended on to work as intended. See appendix C for one work-around
for this problem.

18
 Differentiator and Gain

Consider the circuit below:

Ci Rf

Vin
Vout
Ri
A

The impedance of the input:

Ri 1
sC i Ri Ci
 
1 sC i R i  1 1
Ri  s
sC i RiC i

is the transfer function:

V out  1 
 R f C i  s    180

V in  RiC i 
leading to:

 Rf   
2 
Magnitude  20 log    20 log  1  2 
  o 
 Ri   

1
  
Phase  0  tan  
 
 o 

The re-arranged form of the transfer function:

V out  Rf   Rf 
   sR f C i     sR f C i 
 
 180

V in  R i   R i 

or
V out ( s )  K 1 sV in ( s )  K 2V in ( s )

Rf
is useful in developing a circuit that differentiates. Notice that when s=0, gain is ,
Ri
the common fixed gain inverting amplifier.

19
For the sake of an example, let ωo be 100 and a DC (ω=0) gain of 10.

Hi Pass w/Gain

70.0

60.0
50.0
Magnitue

40.0
30.0
20.0
10.0

0.0
1 10 100 1000 10000
Freq

This response is nothing new, but you as the designer have complete control over the gain
and break frequency. More importantly as we will shortly see, this circuit, as all the
others, is merely a building block. Eventually we will combine these circuits into a
transfer function that fits the needs of a design criterion.

Hi Pass w/Gain

0.0
-10.0
-20.0
-30.0
Phase

-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
1 10 100 1000 10000
Freq.

The last circuit we will consider in this module is a combination of the previous circuit
and the Integrator/Lo-Pass w/Gain circuit.

20
 Integrator/Lo-Pass w/Gain circuit

The following circuit has interesting and very useful properties. Being a combination of
the last two circuits discussed, you might expect that its performance would be a
combination of the performances of the previous two. Indeed it is.
Cf

Ci Rf

Vin
Vout
Ri
A

For all practical purposes this circuit reduces to:

Zf

Zi

where:
1
Ci
Zi 
1
s
RiC i
and:
1
Cf
Z f

1
s
RfC f
finally:
 1 
 s 
V out  C  RiC i 
  i 
V in C  1 
 f  s  
 RfC f 

21
 Rf 1
Notice that when s  0 the gain reverts to the expected  , and that when s 
Ri R xC x
1
sC i sC X Cf
the gain    
f
  also as expected. This yields:
sC f
1 X Ci
sC i

2 2
 C      
Mag .  20 log  i   20 log( 1     20 log
 1  
C   
 f   i   f 

Clearly if  i   f , it is a hi-pass; if  f   i , it is a lo-pass. If we assume that C i  C f we

have the ability to create either a lo- or a hi-pass by merely choosing resistor values
appropriate to the inequalities needed. For example, let the capacitors equal 1μf. If we
set the zero break frequency at 1 rad/s then the resistor value is 1x106 Ω. Then if we set
the pole break frequency at 10 rads/s, the resistor is 1x105 Ω; we now have a hi-pass.
Conversely if we set the pole frequency to 100 rads/s and the zero break frequency to
1000 rads/s with resistor values of 1x104 and 1x103 Ω, we have lo-pass. Notice that the
gain is for both plateaus and it does not perpetually increase or decrease.

hi/lo pass

25
20
15
10
Mag in db

5
0
-5
-10
-15
-20
-25
0.1 1 10 100 1000 10000
Freq

ωi<ωf ωf<ωi

Were we to cascade two of these circuits in series and choosing the zero frequencies to be
1 & 1000 rads/s and the pole frequencies to 10 & 100 rads/s, we get:

22
 Cf
Cf

Ci Rf
Ci Rf

Vin
Ri
A
Ri Vout
A
s

Bandpass

30

25

20
Freq

15

10

0
0.1 1 10 100 1000 10000
Mag db

Recognize that the slopes and amplitudes can be controlled and adjusted as necessary by
cascading additional modules of the same circuit. Footprint on the circuit board is
virtually unaffected by cascading when ASIC's are used. Were we to reverse the order of
the poles and zeros, i.e., poles at 1 and 1000 rads/s and zeros at 10 and 100 rads/s, we
obtain a "notch" filter.

23
 Notch

0.000

-5.000
Amplitude

-10.000

-15.000

-20.000
0.1 1 10 100 1000 10000
Freq

It is for certain that the circuit would have greater utility if the slope were on the order of
80db/dec or greater. In such a case the bandpass filter would look like this:

80db/dec Bandpass

80.000

70.000

60.000

50.000
Amplitude

40.000

30.000

20.000

10.000

0.000
0.1 1 10 100 1000 10000
Freq

Notice what happens to bandwidth as the order of the filter is increased from 1 to 4; the
bandwidth is decreased by approximately 63%. The salient points are that as the order of
the filter is increased, and discrimination and selectivity are enhanced.

The greatest utility is that the circuit whose Bode transfer function is as immediately
above, occurs when the base line is moved from 0db to  -76db. Its utility as a noise

24
suppression circuit then becomes self-evident. Ponder: What circuit would you use to
move the base line to   76 db (for simplicity use -80db)?

Other circuits will be developed as needed in subsequent modules as needed.

25
 Appendix A

A Look at the Op-Amp Output

There is a mix of error voltages that occur in practice that are not considered in the
elementary general development of op-amp circuit design. These voltages occur in the
output independently of the driver. The op-amp is a physical device consisting of
transistorized circuitry embedded in a substrate (a "chip") and is often implemented using
field effect transistors as the device of choice (in the slide rule days we used vacuum tube
triodes). There are solid considerations for choosing FET's, one of which is that the input
impedance is extremely high, and bias currents are miniscule. Nevertheless, there are
bias considerations that are inescapable in using the physical device.

As a rule, a DC path to ground must be provided for each input, even if it is a sneak path
such as the output stage of the driver. Bizarre effects will occur without those paths,
often rendering the device unresponsive or unpredictable. That being the case, the
assumption made during development that no current flows into the op-amp inputs is not
precisely correct. There is a current, often it is in the range of 10-6 of that of the external
circuit current. So while being imprecise, we can usually ignore the input current. But
precision requires that the designer be aware of it and its effects on the gross output.

V1
Vout
V2

The input stage of the op-amp produces an output that is proportional to V2-V1. That
stage is followed by conditioning and amplifying stages such that Vout=K1(V2-V1), where
K1 is the value of the open loop gain; a constant on the order of 105 or greater. The
expression Vout=K1(V2-V1) represents the output voltage due to the open loop gain of the
op-amp - it will be clamped to a rail.

Consider the following:

Rf

Ri
V1
Vout
Va V2
where V2 is at some small potential removed from actual circuit ground caused by bias
current, i.e. V2≠ 0. By extension then V a  V 2 . If the circuit is linear (and it better be if it
is to be useful as other than a binary device), then:

26
 V1  V a V a  V out

Ri Rf

doing some re-arranging:

Rf  Rf 
V1  V a  1    V out
Ri  R i 

To differentiate between the various values of Vout, assign Vo1 to the open-loop gain and
Vout to the closed loop gain. So:

Vo1=K1(V2-V1)=K1Va

where K1 is an intrinsically high value on the order of 105 or greater.

V 01
Va 
K1

Rf
Let  K2 , then:
Ri
V 
K 2V1   ol  1  K 2   V out
 K1 
K2 3
Assume  10 since K2 is of the order of 102 or less and K1 is of the order 105 or
K1
greater. Then:

K2 1 K2
  . 001
K1 K1

K 2V1  . 001 V ol  V out

V01 can be forced to closely approach 0 in a couple of ways. One is to supply the op-
amp's offset input (if it has one) a voltage sufficient to null out V01. Another is to use a
bias resistor at the positive input equal to the parallel combination of Rf and Ri.

27
 Rf

Ri
V1
Vout

RfRi/(Rf+Ri)

In the absence of the driver, the bias currents to each input are then the same (or nearly
so).

When V01 is forced to be 0 then by Vo1=K1Va, Va must be zero because K1 is not, leaving:

R V out
 
f

Ri V1

From the defining schematic above, the magnitude of V2 (the voltage appearing at the
junction of Ri & Rf) is:

 Ri R f 
V 2  i  


R  R 
 i f 

where i+ is the input current to the non-inverting input. That current is the bias current
into the gate of an FET; generally in the nano amp range which puts V2 about in the 10-4
volt range. So FAPP4 comes galloping to our salvation again (assumes that V2 is trivial
or nearly 0 for practical purposes) wherein the model assumes a zero volt potential at the
positive input; allowing the claim that:

Rf V out
 
Ri V1

In any event, the expression:

Vo Rf
 
V in Ri

is a close approximation of the actual gain, and as a working relationship, is sufficient for
almost all uses. But as in the Quantum world, there are little "ghosties" hanging around
that the designer must be aware of and account for when precision is necessary.
4
For All Practical Purposes

28
 Appendix B

Gain Bandwidth Product

The op-amp has internal poles that determine its response as a function of gain and
frequency. Fortunately, the response is linear or nearly so, and follows an algebraic
relationship.

As a rule, the open loop gain of an op-amp is very high; on the order of 105 or greater.
However there is a dominate low frequency pole at a very low value; between 2 and
30Hz. From that point, the response linearly falls off in a way such that:

gain*bandwidth=constant.

For example if the device has a bandwidth of 106 at a gain of 1, it will have a bandwidth
of 105 at a gain of 10, a bandwidth of 104 at a gain of 100, and so on. This device would
be identified as having a GBW (gain bandwidth product) of 106 (GBW being defined at a
gain of 1).

29
 Appendix C

Differentiator

Recall that this circuit has a transfer function of:

Ci Rf

Vin
Vout
Ri
A

V out Rf
 sR f C i 
V in Ri

Using block diagrams, this transfer function suggests to yield a differentiator:

sK1+K2
+

Vin Σ sK1 Vin

-
K2

While the component count exceeds that of the circuit consisting of an op-amp, a resistor
and a capacitor, its dependability to avoid the issue of an ungrounded (DC wise) input is
assured. Therefore its ability to deliver a dependable output is assured.

30
 Appendix D

Table of Transforms

Transform f (t ) F (s)
1 K K
s
t
2 Ke K
s
3 K sin(  t ) K
s 
2 2

4 K cos(  t ) Ks
s 
2 2

5 Ke
t
sin(  t ) K
 s   2   2
6 Ke
t
cos(  t ) K s   
 s   2   2 
7  (t ) 1
7a* K  (t ) K

8 Ku ( t  a ) Ke
 as

s
9 f ' (t ) sF ( s )  f ( 0 )
10
 f ( t ) dt F (s)

f (0)
s s
11 af ( t )  bg ( t ) aF ( s )  bG ( s )
12 t 1
2
s
 at
13 te 1
s  a 2

Table 1

31
(*) K is preserved for practical circuit reasons, not for theoretical reasons as K   is
approximately equal to  .

Table 1 is not all inclusive and other pairs will be examined and added when needed. But
for beginning analysis purposes, Table 1 is adequate.

It is very important to understand that to be able to transform any F ( s ) to an f (t ) , F ( s )

must be reduced to one of the forms so far developed. If it is not in one of these forms,
for the purposes of this course it cannot be operated on until it is. Study the right hand
side forms as they identify the left hand side.

Transforms 12 and 13 are found as follows:

f (t )  t
 1
 st
F (s)  0
te dt 
s
2

For transform 13, assume:

 at
f ( t )  te
 1
  s  a t
F (s)  
0
te dt 
s  a 2

Finding transforms 12 and 13 is a straight forward exercise using integration by parts.

32
 Appendix E

Convolution and LaPlace Domain Multiplication

Consider the following integral:

h (t )   f ( u ) g ( t  u ) du
0

For the sake of illustration, read the above integral this way: let f (u ) be a transfer
function in the time domain, and g ( t  u ) be a signal.

Begin by building the signal this way, g ( t )  e  t .

g(t)

2.500
2.000
1.500
1.000
0.500
0.000
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
t and/or u

Now "flip" the signal horizontally, so that as it progresses left-to-right, the leading edge is
g(0).

g(-t)

2.500
2.000
1.500
1.000
0.500
0.000
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
t and/or u

33
Now let g(-t) proceed left to right. Recognize that "u" is a dummy variable of integration
and that physically u  t for every u and t. Therefore g(t-u) always equals g(0) regardless
of where it is on the x axis.

Arbitrarily assume the limit on the integration is 8. At u  t  2 .1 , g(t-u) would be:

g(t-u) at t=2.1

2.500
2.000
1.500
1.000
0.500
0.000
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
t and/or u

At t=2.1, g(t-u)=g(2.1-2.1)=g(0); but when t=2.1 what does g(t-1) look like? Well
g((2.1-1)-2.1)=g(-1.1). And if you check the value of g(-1.1) on the graph of g(-t), you
will see that they agree with the value on the graph on the previous page at t=-1.

Therefore the argument (t-u) is interpreted to mean that the signal is flipped 180o
horizontally, allowing g(0) to be the leading edge of the signal passing through the
transfer function. This is the convolution integral and it expresses mathematically the
physical property that a signal passes through a transfer function as the right-to-left
mirror image of that seen on an oscilloscope. Note that it is irrelevant whether we
consider the signal passing through the transfer function or the transfer function passing
through the signal; our view has no effect on the outcome.

That being the agreed case, the following pair is defined:


 st
 h (t ) e dt  f ( s ) g ( s )
0

where:
h (t )  f (t ) g (t  u )

tying the physical property of passing a signal through some hardware to the LaPlace
transform of that process.

Suppose f ( t )  u ( t )  u ( t  1) and that g ( t )  u ( t )  u ( t  1) , then the transform would be:

34
 f (s) g (s) 
1
1  e   1 1  e  
s s 1
2
1  2 e s
e
2s

s s s
The time result would be:

h ( t )  t  u ( t )  2 u ( t  1)  u ( t  2 ) 

Simple Convolution

1
0.8
0.6
0.4
0.2
0
-3 -2 -1 0 1 2 3
time

f(t) g(-t)

f(t)g(t-u)

1
0.8
0.6
0.4
0.2
0
-3 -2 -1 0 1 2 3
time

f(t) g(t-u)

h(t) is the integral of the area where f(t) intersects g(t-u). After g(t-u) completely passes
through f(t), the results of the integral are:

35
 h(t)

1
0.8
0.6
0.4
0.2
0
-4 -3 -2 -1 0 1 2 3 4
time

h(t)

This result agrees with the results of the time domain inversion of f(s)g(s). You may
verify that this result is indeed the solution in the time domain by visiting
http://jhu.edu/signals/convolve/index.html; courtesy of Johns Hopkins University, or by
obtaining h(t) on the interval 0-2 using the convolution integral.

Reverting to g ( t )  2 e  t and using f ( t )  u ( t )  u ( t  1) ; then in the Laplace domain:

s
1 e  2   
f ( s ) g ( s )    
2

 s  1    s  s  1   1  e
s

s s    

Taking the inverse transform and plotting:

t t
h ( t )  2 (1  e ) u ( t )  2 (1  e ) u ( t  1)

exp(-t) convolve w/unit square

1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
0 1 2 3 4 5 6 7 8
time

Again, you may verify that this result is indeed the solution in the time domain by
visiting http://jhu.edu/signals/convolve/index.html; courtesy of Johns Hopkins
University, or by obtaining h(t) using the convolution integral.

36