This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2956323, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE POWER ELECTRONICS REGULAR PAPER

An Optimized Hybrid Modulation Scheme for

Reducing Conduction Losses in Dual Active Bridge
Converters
Bochen Liu, Student Member, IEEE, Pooya Davari, Senior Member, IEEE, Frede Blaabjerg, Fellow, IEEE

Abstract—A linearized hybrid modulation scheme for the DAB [12]–[14]. In order to overcome this drawback, many im-
converter is proposed in this paper. For the purpose of minimizing proved modulation methods are introduced to extend the DAB
the conduction losses dissipated on the transformer and the soft-switching operating range, such as extended phase-shift
power transistors, an optimal relationship function between the
two control variables employed in extended phase shift (EPS) (EPS) modulation [15], dual phase-shift (DPS) modulation
modulation can be derived. However, the obtained relationship [16], [17] and triple phase-shift (TPS) modulation [18]–[21].
function is a complex expression, which is not good for simple on- Other than only one phase shift in SPS, these improved
line control. Hence, a linearized modulation scheme is proposed modulation schemes try to introduce more control variables.
in this paper. This modulation scheme can achieve a quasi- In the simple SPS modulation, only the outer phase shift
minimum RMS value of the leakage inductance current for
the same output power. Meanwhile, the zero voltage switching between the primary and the secondary full bridge is regulated,
(ZVS) of the power transistors can be achieved over the whole leading to a two-level primary and secondary winding voltage.
power range. The power transfer capability is also kept same If varying inner phase shift (as defined in Section II-B) is
as the optimal EPS scheme. Finally, experiments are conducted considered, the winding voltages turn to three-level because
on a laboratory prototype to validate the effect of the linearized the diagonal switches in each full bridge are not turned on
modulation scheme on the reduction of conduction losses. The
experimental results present an improved converter efficiency or off synchronously any more. Taking [21] as an example,
and the realization of ZVS. a comprehensive searching of operation modes with TPS is
implemented, and the corresponding soft-switching boundaries
for each operation mode are derived. However, the analysis of
I. I NTRODUCTION power transfer range is absent, which is important for selecting
Firstly proposed in 1988 [1], the dual active bridge (DAB) proper operation mode due to the varying given powers.
converter is now widely used in many applications such Alternatively, applying multiple control variables makes it
as distributed power systems and energy storage [2], [3]. possible to realize a more ambitious target, such as current
Due to its advantages of galvanic isolation and bidirectional stress optimization [22]–[26], backflow power reduction [27]
power flow, DAB converters are applied among multiple and non-active power loss minimization [28]. Actually, these
dc energy sources such as battery packs, ultra-capacitors optimization targets are based on optimizing different parts of
and photovoltaic submodules to match various voltage levels the leakage inductance current, e.g. current stress optimization
[4]–[7]. Moreover, since the DAB converter can naturally usually refers to reducing the peak value of the leakage
achieve zero voltage switching (ZVS) without any auxiliary inductance current, backflow power is often related to the
components and has a simple and symmetrical structure, it is intervals when the current direction is reversed into the power
also a potential candidate for high efficiency and high power source.
density applications such as electric vehicles and aerospace Besides, many optimized control schemes are focusing on
[8]–[11]. For the same reason, the DAB is also an ideal dc- reducing the root mean square (RMS) value of the leakage
dc conversion choice for applications where modular design inductance current [29]–[32], which is closely related to the
is often needed such as energy storage systems and power conduction losses of the power semiconductors and high-
electronic transformers. frequency transformer. Notably, hybrid modulation methods
A conventional way to control the DAB converter is could be adopted in order to extend the converter performance
using single phase shift (SPS) modulation to fulfill the over a wide operation range [33], [34]. Furthermore, the
power/voltage/current requirements. SPS is simple and easy switching frequency can also be varied aiming at specific
for real time control. However, utilizing this simple modulation optimization objects. In [35], the switching frequency is varied
scheme can not guarantee ZVS if the voltage ratio deviates to modulate the DAB in a specific single-stage ac-dc converter.
far from one, which results in poor efficiency at partial load In [36], the circulating current is minimized over a wide power
conditions. Notably, under this situation, even the switches range using variable frequency modulation.
might be broken with excessive dv/dt caused by ZVS failure Among the aforementioned modulation methods, some of
them are complicated and not easy to implement. One usual
This paper is an extension of the conference paper with the title of “An situation is that in order to make the DAB converter work
Optimized Control Scheme for Reducing Conduction and Switching Losses in
Dual Active Bridge Converters”, which was presented in Proc. IEEE Energy at the optimal operation point, massive calculations are often
Conversion Congress and Exposition (ECCE), 2018. conducted to handle those complex relationships among the

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2956323, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE POWER ELECTRONICS REGULAR PAPER

control variables. The reason is that at least three limitations i1 HB1 HB2 i2 io
should be taken into account during the operation, i.e. the
ZVS range, the power transfer capability and the optimization S1 S2 S5 S6
L ip is
targets. Of course, there exist other factors depending on + +
different requirements, such as the voltage variation range, V1 _ C1 vp vs C2 _ V2
the transient response or the effect of the passive components.
One way to solve the complexity is to adopt a look-up table S3 n : 1S S8
S4 7
in the control process, where the optimal operation points
are calculated in advance and input into a table prior to the
converter operation. But the performance of this method is Fig. 1. Topology of the dual active bridge (DAB) converter.
adversely affected by the components mismatched parameters
due to their tolerances, temperature dependency and lifetime. ni1 HB1 2
nip L/n is HB2 i2
Moreover, a large memory is needed to guarantee the accuracy DC AC
if the converter has to work in a wide operation range. In + +
V1/n _ vp/n vs _ V2
terms of the variable switching frequency modulation, one AC DC
large challenge is the design of passive components and the
electromagnetic interference filter. Fig. 2. Simplified DAB model by referring the converter to the secondary side
In order to make the DAB converter more adaptive and of the transformer.
applicable, this paper proposes an optimized hybrid modu-
lation scheme to simplify the control process based on EPS
middle terminals of which are linked by a high-frequency
modulation. The main contributions of this paper are:
transformer and the side ends are paralleled with the input
• The comprehensive analysis of the power transfer range
and output dc voltage ports. In order to flexibly adjust the
for each operation mode, which is derived based on the leakage inductance, an auxiliary inductor is cascaded with the
ZVS conditions rather than operation mode boundary high-voltage primary winding so that a lower additional power
conditions as in some literature. loss is induced compared to the secondary low-voltage high-
• The analytical optimization expressions for each opera-
current winding.
tion mode are derived in order to minimize the RMS The magnetizing inductance is considered much larger than
value of the leakage inductance current. the leakage inductance, leading to negligible magnetizing
• Several simplified optimization methods are proposed
current compared with the load current. Therefore in the T-type
based on different voltage ratio requirements and pre- transformer equivalent circuit, the branch with magnetizing
ferred working conditions in various applications. inductor can be seen as an open circuit. On this basis, the
• Independent of the voltage ratio limitation and being
DAB model is obtained as shown in Fig. 2 after referring the
simpler than other methods, the linearized optimization circuit parameters to the secondary side.
method is applied to the available DAB setup in this paper
and validated by the experimental results.
B. Operation Modes
This paper is organized as follows. Firstly, the EPS based
operation modes for boost and buck scenarios under ZVS Due to the bidirectional power transfer ability and the
conditions are presented in Section II. Next, according to the symmetrical topology, the DAB converter has four operating
derived operation modes in Section II and selected components scenarios: forward/backward, buck/boost. Assuming the power
for the DAB setup, the losses distribution are calculated in flow is from the primary side to the secondary side, a factor
Section III. In Section IV, an optimal modulation scheme k is introduced as
(called ‘OMS1’ in the following) is firstly derived. In order V1
to simplify this scheme and considering different voltage k= (1)
nV2
ratio requirements, three approximated modulation schemes
are developed. With the aim of selecting the most suitable to signify the voltage ratio. k < 1 and k > 1 denote boost and
modulation method, a through comparison is presented among buck scenarios, respectively.
these four schemes at the end of Section IV. Therefore, In order to simplify the calculations, the base power Pb and
in Section V, the selected linear scheme is applied into a base current Ib defined in (2) are used to normalize the real
laboratory prototype to validate the feasibility on conduction values. Therein, V1 , V2 and fsw denote the input, output dc
losses reduction and ZVS realization. Finally, conclusions are voltage and the switching frequency, respectively. L is the total
given in Section VI. inductance consisting of the transformer leakage inductance
and the auxiliary inductance.
II. BASIC M ODULATION M ETHODS FOR D UAL ACTIVE (nV2 )2 n2 V 2
B RIDGE C ONVERTERS Pb = , Ib = (2)
8Lfsw 8Lfsw
A. DAB Model The power is mainly controlled by the outer phase shift
The topology of the DAB converter is shown in Fig. 1. ϕ, which is the displacement angle between the fundamental
It consists mainly of two full bridges HB1 and HB2 , the components of vp and vs . If Dϕ = ϕ/π is defined for

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2956323, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE POWER ELECTRONICS REGULAR PAPER

TABLE I
Po[pu] E XPRESSIONS OF THE N ORMALIZED L EAKAGE I NDUCTANCE C URRENT
vp φ DURING D IFFERENT I NTERVALS FOR E ACH EPS O PERATION M ODE

vs
Is,rms[pu] Mode I 99K Fig. 4(a)
is
t 8k
[t0 , t1 ] is (t)[pu] = t − 2k + 2Dα
t0 t1 t2 Tsw
8(k − 1)
(b) [t1 , t2 ] is (t)[pu] = t + 2 − 2k + 4Dϕ
(a) Tsw
8k
Fig. 3. (a) typical SPS working waveforms over one switching period, which [t2 , t3 ] is (t)[pu] = t − 2k − 2Dα
Tsw
is a special case of EPS by setting Dα = 1 in Mode II (b) the output power
Po and the RMS leakage inductance current I L,rms of the DAB converter with Mode II 99K Fig. 4(b)
repect to Dϕ , k = 0.75 in this case.
8(k + 1)
[t0 , t1 ] is (t)[pu] = t − 2k − 4Dϕ + 2
Tsw
8k
φ Mode Ⅰ φ Mode Ⅱ [t1 , t2 ] is (t)[pu] = t − 2k + 2Dα
Tsw
vp vp 8(k − 1)
[t2 , t3 ] is (t)[pu] = t − 2k + 2 + 4Dϕ
Tsw
vs α vs α
Mode III 99K Fig. 5(a)
is is 8
t t [t0 , t1 ] is (t)[pu] = t − (2k − 2)Dα − 4Dϕ
t0 t1 t2 t3 t0 t1 t2 t3 Tsw
8
(a) (b) [t1 , t2 ] is (t)[pu] = − t − (2k + 2)Dα + 4Dϕ + 4
Tsw
Fig. 4. In boost scenario, typical EPS working waveforms in one switching 8(k − 1)
[t2 , t3 ] is (t)[pu] = t + (2k − 2)Dα + 4Dϕ + 4 − 4k
period (a) Mode I, Dϕ < (1 − Dα )/2 (b) Mode II, Dϕ > (1 − Dα )/2 . Tsw
Mode IV 99K Fig. 5(b)
α Mode Ⅲ α Mode Ⅳ 8
[t0 , t1 ] is (t)[pu] = t − (2k − 2)Dα − 4Dϕ
vp φ vp φ Tsw
8(k + 1)
[t1 , t2 ] is (t)[pu] = t + (2k + 2)Dα − 4Dϕ − 4k
vs vs Tsw
8(k − 1)
is [t2 , t3 ] is (t)[pu] = t + (2k − 2)Dα + 4Dϕ + 4 − 4k
is Tsw
t t
t0 t1 t2 t3 t0 t1 t2 t3
(a)
TABLE II
(b) C OMBINED L IMITATIONS BY ZVS AND O PERATIONAL C ONSTRAINTS
Fig. 5. In buck scenario, typical EPS working waveforms in one switching
period (a) Mode III, Dϕ < (1 − Dα )/2 (b) Mode IV, Dϕ > (1 − Dα )/2 .
Mode I 2k/(1 − k)Dϕ < Dα < k, 0 < Dϕ < (1 − k)/2

Mode II Dα > 2k(1 − Dϕ )/(1 + k), (1 − k)/2 < Dϕ < 1/2

simplification, Dϕ ∈ [0, 1] stands for forward power flow from
V 1 to V 2 and Dϕ ∈ [−1, 0] for the reverse direction. In fact, Mode III 2Dϕ /(k − 1) < Dα < 1/k, 0 < Dϕ < (k − 1)/(2k)
Dϕ is often limited in [−0.5, 0.5] to lower the RMS value Mode IV Dα > 2(1 − Dϕ )/(1 + k), (k − 1)/(2k) < Dϕ < 1/2
of the leakage inductance current while maintaining the same
power transfer capability, which can be explained by Fig. 3.
Given the SPS working waveforms in Fig. 3(a) and
with Tsw = 1/fsw , the normalized average output power or buck scenario, as shown in Fig. 4 and Fig. 5, respectively. If
RT
Po [pu] = 1/Pb · 1/Tsw · 0 sw [vs (t) · is (t)]dt and the nor- the inner phase shift is denoted by Dα = α/π, then α ∈ [0, π]
malized RMS leakage inductance current Is,rms [pu] = 1/Ib · corresponds to Dα ∈ [0, 1]. Clearly, if Dα = 1, EPS is fallen
into SPS. In this regard, SPS can be seen as a special case of
q RT
1/Tsw · 0 sw i2s (t)dt are derived as
EPS.
Po [pu] = 4kDϕ (1 − Dϕ ) (3) The current waveform is shaped by the voltage drop on the
√ q leakage inductor.
2 3
Is,rms [pu] = · (12Dϕ2 − 8Dϕ3 − 2)k + k 2 + 1 (4) L dis (t) vp (t)
3 = − vs (t) (5)
which can be represented by the black curve and red curve in n2 dt n
Fig. 3(b), respectively. It can be seen that there are always two Considering is (t0 ) = is (t3 ) in half switching period (t3 =
points in the ranges of [0, 0.5] and [0.5, 1] for the same power, Tsw /2), the segmented current can be calculated, as listed in
but the leakage inductance current is smaller in [0, 0.5]. This Table I.
conclusion is also applicable to other phase-shift modulation In order to achieve zero-voltage switching for all switches,
schemes including EPS. the parasitic capacitor of each off-state transistor should be
In EPS, considering the voltage-second balance of the fully discharged at first, which happens through the resonance
leakage inductor, two operation modes can be found for boost of the parasitic capacitor Coss and the leakage inductance

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2956323, IEEE Journal
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basis, the limited power transfer range by considering the ZVS

constraints in Table II can be derived as
  )
2
 0, 2k (1 − k) → Mode I
k<1


Mode Ⅱ

 2k 2 (1 − k), k → Mode II


Po [pu] ∈  ) (7)
Mode I 
 0, 2(k − 1)/k → Mode III
 2(k − 1)/k, k  → Mode IV k > 1




and shown by the gray area in Fig. 6(b). For comparison,

in SPS, due to the ZVS conditions Dϕ > (1 − k)/2 and
Dϕ > (k − 1)/(2k), the power range limited by
( 
k − k3 , k → k < 1
Po [pu] ∈   (8)
k − 1/k, k → k > 1
(a)
is also plotted in Fig. 6(b). The boundary conditions in (8) are
denoted by the dashed lines in Fig. 6(b) . Varying with the
Po[pu]= k voltage ratio k, the ZVS can be theoretically achieved from
zero to the maximum power in EPS, while this is applicable
to SPS only when k = 1. In other words, the ZVS range
Po[pu]= k - k3 Mode Ⅳ Po[pu]= k – 1/k is considerably extended in EPS because of the introduced
control variable Dα .
Mode Ⅱ
Mode Ⅲ
Mode Ⅰ III. L OSSES D ISTRIBUTION
A. Transformer and Auxiliary Inductor
The losses of the magnetical components include copper
(b) losses and core losses. For the given transformer and inductor
in Table III, the copper losses can be calculated with
Fig. 6. (a) Output power in terms of Dα and Dϕ with the blue curve as
the operational constraint. (b) ZVS-limited power transfer range in terms of RL + RT rp 2
k: gray area is the ZVS range for EPS and it is divided into 4 parts (i.e. 4 Pcond,T r = ( + RT rs ) · Is,rms (9)
modes) by solid curves. The area encircled by dashed lines is ZVS range for
n2
SPS. where RL is the auxiliary inductor resistance, and RT rp , RT rs
are the primary and secondary winding resistances of the
transformer, respectively.
L. Afterwards, the body diode will be naturally conducted, For simplification, assuming the transformer and inductor
resulting in a near-zero source-to-drain voltage VDS (the actual are fed by the fundamental sinusoidal components, this allows
value is equal to the voltage drop on the body diode). Thus for calculating core losses with the Steinmetz equation [39]
zero-voltage switching can be achieved if the transistor is α
pv = Cm fsw B̂ β (10)
turned on at this moment, indicating that the direction of the
current flow is from source to drain at the switching-on instants and the core volume VT r and VL , respectively. The
for S1 ∼ S8 . According to this constraint, the polarity of the peak magnetic flux density B̂ is estimated with B̂T r ≈
leakage current at switching instants can be confirmed and 2V1 /(π 2 fsw NT rp AT r ) (Ntrp : primary winding turns, AT r :
the ZVS conditions can be further derived with the current effective magnetic cross section) and B̂L ≈ µef f µ0 NL IˆL /lL
expressions in Table I. Then associating with the operational (µef f : equivalent relative permeability of a gapped core, NL :
constraints for each mode, the combined limitations on the winding turns, IˆL : peak inductor current, lL : effective mag-
control variables are attained in Table II. netic path length) for the transformer and auxiliary inductor,
respectively. Detailed information is listed in Table IV.
C. ZVS-limited Power Transfer Range
B. Power Switches
Using the current expressions in Table I, the average output The losses caused by the power semiconductors mainly
power in one switching period can be calculated with consist of conduction and switching losses. For the calculation
of the conduction losses, the RMS switch currents can be

4kDα Dϕ Mode I,III
Po [pu] = easily derived from the RMS transformer current Is,rms due to

−k[4Dϕ2 − 4Dϕ + (1 − Dα )2 ] Mode II,IV that every switch conducts current during half of the switching
(6) period. Therefore, given the switch parameters in Table III, he
Since Dϕ in I, III is smaller, the power transmission ability conduction losses of the power switches can be calculated with
is weaker compared to II, IV, as shown in Fig. 6(a). In other RDSonp Is,rms 2 RDSons  Is,rms 2
words, Mode I and Mode III are suitable for lower power Pcond,sw = 4 · · √ +4· · √
Nswp 2n Nsws 2
transmission while Mode II and Mode IV for higher. On this (11)

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TABLE III
100
C OMPONENTS PARAMETERS OF THE I MPLEMENTED P ROTOTYPE

Percentage (%)
80
Components Parameters 60
40
Primary winding of the DAB HF RT rp =607.9 mΩ
transformer: 35 turns copper foil @Ta =25 o C 20

Secondary winding of the DAB HF RT rs =16.5 mΩ 0

transformer: 10 turns copper foil @Ta =25 o C 75 150 250 350 450 550 650 750 800
Output power (W)
Auxiliary inductor: RL =27.9 mΩ
10 turns Litz wire, 20 strands, 0.355 mm @Ta =25 o C Turning off losses Conduction Losses Core Losses Cap Losses

MOSFETs S1 ∼ S4 : RDSonp =72 mΩ Fig. 7. Calculated losses distribution percentages.

IPW65R080CFD @Tj =25 o C
MOSFETs S5 ∼ S8 : RDSons =9.6 mΩ
2 x IPP110N20N3 in parallel @Tj =25 o C
with further specifications:
TABLE IV
M AGNETIC C ORE PARAMETERS Psw = Psw,S1 ∼S4 + Psw,S5 ∼S8
Pcond = Pcond,T r + Pcond,sw
Transformer (core type: ETD59/31/22 material: N97) (15)
Pcore = Pcore,T r + Pcore,L
VT r AT r NT rp Cm α β
Pcap = Pcap,in + Pcap,out
51.2 cm2 368 mm2 35 8.21 1.28 2.2

Auxiliary Inductor (core type: ETD44/22/15 material: N87) Operating the converter under ZVS conditions, the cal-
culated losses percentages of different dissipation parts are
VL lL µef f Cm α β
shown in Fig. 7. It can be seen that for the given setup,
17.8 cm2 10.3 cm 120 10 1.26 2.15 the conduction losses are the dominating part over the whole
power range, although the switching losses are almost equal
to the conduction losses in light load. Besides, the conduction
RDSonp /Nswp and RDSons /Nsws are the equivalent switch losses portion increases a lot in the heavy load. therefore,
on-state resistance if each switch consists of Nswp and Nsws reducing conduction losses is of high importance to improve
paralleled semiconductors in the primary and secondary full- the system performance.
bridges, respectively.
On the basis of ZVS turn-on, only turn-off losses are
considered for calculating switching losses for each transistor, IV. O PTIMIZED M ODULATION S CHEMES FOR R EDUCING
which can be estimated by [40] C ONDUCTION L OSSES
tru + tf i
psw = UDS · Iof f · · fsw (12) As shown in Fig. 7, conduction losses are the major loss
2 source for the given converter setup, which are determined
where UDS denotes the turn-off voltage and Iof f is the current by the RMS value of the leakage inductance current Is,rms
at switching-off instants. tru and tf i are the voltage rise time seen from (9) and (11). It is also shown in (6) that there are
and current fall time during switching-off transients. infinite combinations of Dα and Dϕ for the same average
output power, which provides the possibility to reduce the
C. Capacitors conduction losses without sacrificing other performances. Fig.
8 illustrates an example of operating waveforms with different
The losses dissipated on the input and output capacitors are
values of Dα and Dϕ but with the same output power. Clearly,
calculated with the equivalent series resistance (ESR), which
the RMS current in Fig. 8(b) is smaller than Fig. 8(a).
can be obtained from the datasheet, leading to
As proved in the following, for different output power levels,
RESR 2 there exist an optimal operating point at which the leakage
pcap = I (13)
Ncap c inductance current is minimized and simultaneously the ZVS
where Ncap is the number of parallel capacitors. The selected can be guaranteed. But the derived analytical solutions are
capacitors are one B43544A6397M000 (C1 =0.39 mF ) on the too complex for practical control. Therefore, a linearized
input side and five EETEE2D301HJ in parallel (C2 =1.5 mF ) modulation scheme is proposed to simplify the control process.
on the output side.

A. Conventional Current Minimization (OMS1)

D. Losses Distribution
The total losses are the sum of all discussed power losses The normalized RMS currents Is,rms [pu] for each operation
and can be categorized as switching losses Psw , conduction mode are firstly derived based on the working waveforms in
losses Pcond , core losses Pcore and capacitor losses Pcap , Fig. 4 ∼ 5, and the results are listed in Table V. In order to
namely minimize the leakage inductance current and satisfy the output
power requirements at the same time, the power expression of
Ptotal = Psw + Pcond + Pcore + Pcap (14) Mode I in (6) is rewritten as Dϕ = Po [pu]/(4kDα ) and then

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of Emerging and Selected Topics in Power Electronics
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TABLE VI
vp vp O PTIMAL VARIABLES R ELATIONSHIP WITH M INIMIZED L EAKAGE I NDUC -
TANCE C URRENT IN E ACH O PERATION M ODE (OMS1)
t t
vs vs
Mode I 99K Fig. 4(a)
is is q
1− (1 − k)2 − 4k(2 − k)Dϕ
2
t t Dα,opt1 = , 0 < Dϕ ≤
1−k
2−k 2

(a) (b) Mode II 99K Fig. 4(b)

p
Fig. 8. Simulated working waveforms with different combinations of Dα and 2Dϕ + k − 1 + (1 − k − 2Dϕ )2 + [k(1 − 2Dϕ )]2
Dϕ (a) Dα =0.35, Dϕ =0.053 (b) Dα =0.73, Dϕ =0.026 for the same output Dα,opt1 = ,
k √
power. 1−k k − 1 + 1 − k2
f or < Dϕ <
2 2k
TABLE V √
E XPRESSIONS OF THE N ORMALIZED L EAKAGE I NDUCTANCE C URRENT k − 1 + 1 − k2 1
Dα,opt1 = 1, f or ≤ Dϕ <
FOR E ACH O PERATION M ODE 2k 2
Mode III 99K Fig. 5(a)
Operation Mode RMS leakage inductance current Is,rms [pu] q
k − (k − 1)2 − 4(2k − 1)Dϕ 2
k−1
2 h Dα,opt1 = , 0 < Dϕ ≤
· sqrt 3(k − 2)Dα3 2
+ 9Dα 2k − 1 2k
Mode I 3
2
i Mode IV 99K Fig. 5(b)
+ (36Dϕ − 9)kDα + 3k2
p
Dα,opt1 = kDϕ − k + 1 + [(1 − 2Dϕ )k − 1]2 + (1 − 2Dϕ )2 ,
2 √
1 − k + k2 − 1
h
3
· sqrt − 6Dα 2
+ (−18kDϕ + 9k + 9)Dα k−1
Mode II 3 f or < Dϕ <
i 2k 2
+ (36Dϕ − 18)kDα + 3k2 + 3k(1 − 2Dϕ )3 √
1−k+ k −1 2 1
Dα,opt1 = 1, f or ≤ Dϕ <
2 h 2 2
Mode III · sqrt 3 − (6k2 − 3k)Dα
3
+ 9k2 Dα
2
3 i
2
− 3kDα (3 − 12Dϕ ) q
2
1+ (1 − k) − 4k (2 − k) Dϕ2
2 h Dα2 = (20)
Mode IV · sqrt − 6k2 Dα3
+ (9k2 − 18kDϕ + 9k)Dα2
2−k
3
In order to select the correct solution from (19) and (20),
i
− (18 − 36Dϕ )kDα + 3 − 3(1 − 2Dϕ )3 k
the derived ZVS conditions for Mode I (in Table II) are
considered. Substituting Dϕ < (1 − k)/2 into (19) and (20),
the resulted
it is substituted into the expression of Is,rms [pu] in Table V, Dα1 < k (21)
resulting in
Dα2 > (2 − 2k + k 2 )/(2 − k) ≥ k (22)
Is,rms [pu] =
s indicate that Dα1 satisfies the ZVS condition Dα < k while
2  9P [pu]2  Dα2 does not. Therefore, the correct analytical solution of (18)
o
· 3(k − 2)Dα3 + 9Dα2 + − 9 kDα + 3k 2 should be Dα1 . In other words, if (19) is satisfied, the leakage
3 4k 2 Dα2
(16) inductance current in Mode I for a certain output power will be
located at the extreme value point. However, extreme values
For achieving the extreme value of Is,rms [pu] for a certain do not always mean the minimum values.
output power Po [pu], the differential of (16) with respect to In order to verify whether Dα1 is a proper solution of
Dα is set to be 0, namely ∂Is,rms [pu]/∂Dα = 0, solving minimal Is,rms , the relationships among Is,rms -Dα -Dϕ (ref.
which will lead to Table V) are depicted in Fig. 9. As shown in Fig. 9(a), only
the red-colored area is related to Mode I, limited by the
(12k 2 − 24k)Dα4 + 24kDα3 − 12k 2 Dα2 − 3Po [pu]2 = 0 (17) operational condition Dα < 1 − 2Dϕ . It can be seen that
It is difficult to directly solve for the analytical solution of for a certain output power, the black intersection points are
(17) due to the high order of Dα . So Po [pu] in (17) is replaced the minimum Is,rms [pu] at different power levels. Thus it can
by 4kDα Dϕ , and the simplified result is be concluded that Dα1 is the correct solution for achieving the
minimum Is,rms , which is exactly the Dα,opt1 in Table VI.
(k − 2)Dα2 + 2Dα − k(4Dϕ2 + 1) = 0 (18) Applying similar deriving process to Mode II, the resulting
Is,rms [pu] surface with respect to Dα and Dϕ is shown in Fig.
Then it becomes easy to obtain the solutions of (18), which 9(b). As for Mode III and Mode IV, the optimized results are
are q directly given in Table VI, from which it can be seen that
2
1 − (1 − k) − 4k (2 − k) Dϕ2 the analytical solution of Dα is segmented depending on the
Dα1 = (19) operation range of Dϕ in Mode II and Mode IV. Especially,
2−k

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Dα,opt1 curve for Mode Ⅰ

Is,rms surface for
Po[pu] = 0.03 Mode Ⅰ
Po[pu] = 0.08
Po[pu] = 0.14
Po[pu] = 0.20

(a)

(a)
Po[pu] = 0.42
Po[pu] = 0.33
Po[pu] = 0.23
Po[pu] = 0.14
Po[pu] = 0.047
Is,rms surface
for Mode Ⅱ

(b)
Fig. 10. The relationship function Dα = f (Dϕ ) in OMS1 (denoted by the
Dα,opt1 curve blue curve) including the gray ZVS range and colored power curves in: (a)
for Mode Ⅱ Boost scenarios (k = 0.75 in this case). (b) Buck scenarios ( k = 1.5 in this
case).

(b)
Fig. 9. 3D plot of the RMS leakage inductance current as the function of Dα relationship Dα = f (Dϕ ) for minimum Is,rms is represented
and Dϕ in boost scenario (k = 0.75 in this case) for (a) Mode I (b) Mode by the blue curve. Either in buck scenario (Fig. 10(a)) or boost
II. The expressions of Dα,opt1 for achieving minimum Is,rms at different
power levels can be found in Table VI. scenario (Fig. 10(b)), there are four key intersections induced
by the segmented optimal function, which are shown by the
red points. From left to right, the coordinates of these four
if Dϕ is close to 0.5, the optimal Dα is equal to 1, meaning √ points are derived as [0, k/(2 − k)], [(1 − k)/2, k], [(k −
cross
that the DAB converter transfers to the SPS modulation. 1+ 1 − k 2 )/(2k), 1], [0.5, 1]in√Fig. 10(a), and [0, 1/(2k−1)],
The modulation scheme for achieving minimum Is,rms is [(k − 1)/(2k), 1/k], [(1 − k + k 2 − 1)/2, 1], [0.5, 1] in Fig.
termed as Optimized Modulation Scheme 1 (OMS1). Although 10(b). Since the power is increased with Dϕ and Dα , three
the RMS leakage inductance current can be theoretically different load situations are divided by the four intersections,
minimized by adopting Dα,opt1 , it is difficult to realize OMS1 i.e. light load, medium load and heavy load. Based on different
in practical control due to the complex relationship between voltage ratio requirements and load situations, the Dα,opt1
Dα and Dϕ , as shown in Table VI. expression can be simplified in various ways.
Thus it is important to simplify the relationship expression 1) Unified Modulation Scheme (OMS2): A unified modula-
between Dα and Dϕ . Besides Dα and Dϕ , the RMS leakage tion scheme can be derived by applying curve fitting technique
inductance current is also determined by the voltage ratio k among the three points [0, 1/(2k −1)], [(k −1)/(2k), 1/k] and
(ref. Table V). For different applications, the input and output [0.5, 1], resulting in
voltage may change broadly, implying various voltage ratio 4 (3k − 2) 2 2 (2k − 1) k
requirements. On this basis, the following simplifying schemes Dα.opt2 = Dϕ + Dϕ + (23)
k (k − 2) k 2−k
are optimized considering both conduction losses reduction
and different voltage ratio ranges. which is as proposed in [41]. In this scheme, only one
B. Simplified Optimal Modulation Schemes expression is needed over the three load conditions.
Similarly, the unified modulation expression in buck scenar-
Due to the fact that the OMS1 is hard to realize, it is ios also can be derived as follows.
necessary to simplify the modulation scheme and meanwhile
4k(2k − 3) 2 1
keep Is,rms as close to the minimum value as possible for Dα,opt2 = Dϕ + (4 − 2k)Dϕ + (24)
reducing the conduction losses. As shown in Fig. 10, the 2k − 1 2k − 1
gray areas are limited by ZVS conditions and the colored The relation expressions denoted by (23) and (24) are
curves denote different output powers. The derived optimal plotted as the red curves in Fig. 11. Nevertheless, depending

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(a) (a)

(b) (b)
Fig. 11. The relationship function of (a) (23) for Boost scenarios (k = 0.75 Fig. 12. Two ZVS failure cases for Dα,opt2 in boost scenarios (a) k = 0.85
in this case). (b) (24) for Buck scenarios ( k = 1.5 in this case) in unified (b) k = 0.4 in unified modulation scheme (OMS2)
modulation scheme (OMS2), denoted by the red curves.

√
on the varying voltage ratio k, the red curve could exceed kept at 1 in the range of Dϕ ∈ [(k − 1 + 1 − k 2 )/(2k), 0.5].
the gray ZVS range. For example, two failed cases caused The simplified result will be
by too large or too small k in boost scenarios are shown in
Fig. 12, where part of the red curve is beyond the ZVS region. 
Therefore, there is a limited range of k for unified modulation. Ak · Dϕ2 + Bk · Dϕ + Ck ,
√



k + 1 − k2 − 1

In order to satisfy Dα,opt2 ≤ 1 for any value of Dϕ in 
Dα,opt3 = 0 < Dϕ < (27)
[0, 0.5], the symmetry axis of (23) should be larger than 0.5, √ 2k
k + 1 − k2 − 1

then the maximum value of k can be solved, which is

 1
1, ≤ Dϕ ≤

2k 2
(2k − 1)(2 − k) 1
≥ −→ kmax = 0.78 (25)
4(3k − 2) 2
with
On the other hand, in order to avoid the situation shown
in Fig. 12(b), Dα,opt2 in (23) should be larger than the ZVS 
√
 8 − 8k − 4k 2 1 − k 2 + 8k 3 − 8k 2 − 8k + 8
border 2kDϕ /(1 − k) for any Dϕ ∈ [0, (1 − k)/2], leading to A
 k
 =

 (2 − k) (1 − k 2 )

k√
2
1 − k 2 + 2k 3 − 6k 2 − 4k + 4

4 − 4k − 2k
k2 1−k Bk =
2
≥ −→ kmin = 0.45 (26)  k (k + 1) (k − 2)
2(3k − 5k + 2) 2




Ck =
 k
2−k
Similarly, the k range for (24) can be obtained in the same (28)
way, which is within [1.28, 2.23] in buck scenarios for unified
Applying a similar change into the buck scenarios, the curve
modulation scheme.
fitting results are as follows.
2) Partially Unified Modulation Scheme (OMS3): Seen
from Table VI, EPS transfers into SPS (Dα,opt1 = 1) in heavy
load. If the SPS is kept for easy control, the complex optimal

Ak · Dϕ2 + Bk · Dϕ + Ck ,
√

expressions in light and medium load can be unified with


1 − k + k2 − 1


one expression. In this regard, another group√ of three points Dα,opt3 = 0 < Dϕ < (29)
[0, k/(2 − k)], [(1 − k)/2, k] and [(k − 1 + 1 − k 2 )/(2k), 1] √ 2
1 − k + k2 − 1


 1
in boost scenarios are used for curve fitting, and the Dα is 1, ≤ Dϕ ≤

2 2

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in boost scenarios and


2 1 k−1
2k−1 Dϕ + 2k−1 , Dϕ ∈ [0, 2k ]




√
 2k√k2 −1+2k2 −2 D − (k−1) k2 −1+k2 −k−2 ,



k+1 ϕ k+1 √
Dα,opt4 = k−1 1−k+ k2 −1


 D ϕ ∈ [ 2k , 2 ]

√

 2
D ∈ [ 1−k+ k −1 , 0.5]

1,
ϕ 2
(32)
in buck scenarios.
Fig. 13 gives two cases derived from (31) and (32), re-
(a)
spectively. It can be clearly seen that no matter how the
voltage ratio changes, the linearized red curves will always
locate within the gray ZVS area. Accordingly, the linerized
modulation scheme (OMS4) is set free from the voltage ratio
limitation.

C. Comparison of Different Optimized Schemes

Based on different voltage ratio requirements and the pre-
ferred working conditions of the converter, the approximation
principles of OMS2 ∼ OMS4 have been explained in Section
IV-B. Compared to the original OMS1 in Section IV, the
three simplified schemes have their own pros and cons. In
(b) the following, a detailed comparison will be performed from
Fig. 13. The linearized relationship function of (a) (31) for Boost scenarios different perspectives.
(k = 0.75 in this case). (b) (32) for Buck scenarios ( k = 1.5 in this case) Firstly, with regard to the unification (depending on Dϕ ), it
in linear modulation scheme (OMS4), denoted by the red curves.
can be evaluated by the number of segments in the relationship
functions between Dα and Dϕ , which is represented by
the stars number in the second column of Table VII. More
with segments means poorer unification performance. Although
both OMS1 and OMS4 have the same three segments, the
 √ OMS4 is easier to implement due to the linear approximation.
4k[(2k 2 − 2k − 1) k 2 − 1 + 2(k + 1)(k − 1)2 ] Then the voltage ratio limitations (i.e. k range) are com-
Ak =


√3 − k 2 − 2k + 1


 2k pared for different schemes. As shown in last section, OMS1
(4k + 2 − 4k 2 ) k 2 − 1 − 4k 3 + 4k 2 + 6k − 2

Bk = and OMS4 can theoretically guarantee ZVS for any value of k,

 2k 2 + k − 1 whereas a limited range should be considered for OMS2 and


Ck =
 1
OMS3 to avoid ZVS failure over the whole power transfer
2k − 1
(30) range. In this regard, OMS1, OMS4 are better than OMS2,
Similar to the unified modulation scheme (OMS1), the OMS3.
voltage ratio in (27) and (29) needs to be limited within From the point of calculation burden, two conditions of
[0.56, 0.91] and [1.10, 1.80], respectively. the voltage ratio are considered, i.e. a fixed or a varying
k. If V1 and V2 are fixed, the voltage ratio can be seen as
3) Linearized Modulation Scheme (OMS4): One common a constant and thereby the k−depending coefficients (e.g.
drawback of OMS2 and OMS3 is the limited range of voltage Ak , Bk , Ck ) of Dα,opti (i = 1, 2, 3, 4) expressions are also
ratio k. In order to overcome this, a piecewise linear approx- constants. On this basis, Dα,opt4 has the simplest form due to
imation scheme can be derived by considering the three load the lower number of mathematical multiplications and square
situations individually. Therefore, the four key points are all roots, which also means faster processing speed for the digital
taken into account to linearize the complex exressions in Table processor. This advantage will become further clear when
VI, resulting in multiple DAB modules are working at the same time. On the
other hand, if V1 and V2 are varying, the sampling speed of V1 ,

2k k 1−k V2 and the calculation burden of the k−depending coefficients


 2−k Dϕ + 2−k , Dϕ ∈ [0, 2 ] should be taken into account. Regarding this, it can be found

 √ √ that OMS2 surpasses the other schemes, represented by four
 (2−2k2 +2 1−k2 )
 2 +1−k−2k 2
Dϕ − (1−k) 1−k

k(1+k) k(1+k) , stars in Table VII.
Dα,opt4 = √
2
1−k k−1+ 1−k At last, assuming the converter works in steady sate, the in-


 Dϕ ∈ [ 2 , 2k ]


 √ put and output voltages are stabilized with a fixed k. In respect
2

1, Dϕ ∈ [ k−1+2k 1−k , 0.5] of this, the complexity of different schemes are evaluated by

(31) adding the star numbers from the second to fourth column in

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TABLE VII
C OMPARISON OF OMS1, OMS2, OMS3 AND OMS4 Start the proposed hybrid OMS4 by applying below
procedure; given: V1, L, n, Po,ref and fsw
Voltage
Unification limita- Calculation burden Complexity Calculate k, Pb, Pmin, Pmax
tion
fixed k varying k No
If Po,ref/Pb ϵ [Pmin, Pmax] Stop
OMS1 F FF F F 4·F
OMS2 FFF F FF FFFF 6·F Yes
OMS3 FF F FFF FF 6·F
OMS4 F FF FFFF FFF 7·F k >1 or k <1 Po,act = V2 •󠄥 Io, Po,err = Po,ref - Po,act

Mode selection PI controller

Dφ
Dα is selected by (31) or (32) for OMS4

Modulation module

V2
Dual active bridge DC-DC converter
io

Fig. 15. Procedure of applying linearized modulation scheme (OMS4) to the

DAB converter

P5 , P10 and P15 are the k−related output powers

√ at the three
boundary points (i.e. [(1−k)/2, k], [(k−1+ 1 − k 2 )/(2k), 1],
[0.5, 1] that define the three segments in OMS4 in boost
Fig. 14. Relative errors defined by (33) varying with voltage ratios and output scenarios). Then the various other power levels Pi (i = 1..15)
powers
can be expressed by

0.2 · i · P5 , i = 1..5

Table VII, and the summations are shown in the last column.
Pi = P5 + 0.2 · (i − 5) · (P10 − P5 ), i = 6..10
It can be seen that OMS has the highest 7 stars, and thus will 
P10 + 0.2 · (i − 10) · (P15 − P10 ), i = 11..15

be selected as the focus to further evaluate the effectiveness
on reducing conduction losses. (35)
with
√
V. R ESULTS AND D ISCUSSION 2(k 2 − 1 + 1 − k 2 )
P5 = 2k 2 (1 − k), P10 = , P15 = k
As illustrated in IV-C, the linearized modulation scheme k
(36)
(OMS4) overtakes other schemes with a simpler form of
From Fig. 14, it can be seen that ierr,sps is larger than
modulation expression. However, OMS4 is essentially an ap-
ierr,OM S4 , especially in light load and medium load. When
proximating method, and this means that the effectiveness on
the voltage ratio k is 0.6, the maximum ierr,sps even exceeds
conduction losses reduction is not as good as OMS1 which can
100%. Consequently, it can be obtained that OMS4 is more
achieve minimum leakage inductance current Is,rms . Hence
applicable to the DAB converter, especially when the converter
the relative error calculated by (33) is used to measure the
works in light load and the voltage ratio deviates far from
deviation from the minimum Is,rms .
unity. On the other hand, comparing Is,rms,OM S4 with the
|Is,rms,OM S4 − Is,rms,OM S1 | optimal Is,rms,OM S1 , the relatives errors ierr are very small
ierr = · 100% (33)
Is,rms,OM S1 (less than 2%) for various voltage ratios and output power
levels, especially in medium and high power load (P5 ∼ P15 ,
For comparison, the values of Is,rms under SPS modulation
less than 0.5%), which proves the effectiveness of linearized
is also calculated, and the following relative error between
modulation scheme on reducing the conduction losses. The
Is,rms,sps and the minimum Is,rms,OM S1 is used to compare
process of applying OMS4 to the DAB converter is illustrated
with (33).
in Fig. 15.
|Is,rms,sps − Is,rms,OM S1 | An experimental platform for the DAB converter is built to
ierr,sps = · 100% (34)
Is,rms,OM S1 validate the linearized modulation scheme OMS4, as shown in
Fig. 16. The main circuit parameters are listed in Table VIII.
The calculated results varying with different voltage ratios In order to fully evaluate the performance improvement
and normalized output powers are shown in Fig. 14. Therein, caused by linearized modulation scheme, two groups of com-

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@ Po=190 W, Is.rms=9.08 A, η=92.5 %

Oscilloscope vs (100 V/div)
Main circuit board
Auxiliary power supply
Power analyzer
Power source vp (250 V/div) ip (10 A/div)
Differential
voltage probes
Current transducer
Control board
is (25 A/div) 5 μs/div
Electronic load
(a)
Front view of the
main circuit board @ Po=190 W, Is.rms=8.06 A, η=95.0 %
vs (100V/div)

Fig. 16. Test platform for the DAB converter

vp (250 V/div) ip (10 A/div)

TABLE VIII
S YSTEM S PECIFICATIONS

Parameters Description Value

P Rating power 1.5 kW
is (25 A/div)
5 μs/div
n:1 Turns ratio of the transformer 3.5 : 1
(b)
fsw Switching frequency 60 kHz
Tdead Dead time 400 ns vs (100 V/div)
Ls Series inductor 36.2 µH
Ltrp Primary-side leakage inductance 4.5 µH
Ltrs Secondary-side leakage inductance 372.5 nH
is (25 A/div)
C1 Primary DC capacitor 0.78 mF
C2 Secondary DC capacitor 1.5 mF ZVS vGS,S7 (10 V/div)
vDS,S7 (100 V/div)

parative experiments are conducted for each mode: group one 2 μs/div
(G1) adopts the optimized linear modulation (OMS4) and the (c)
other group (G2) does not use any optimized scheme (but still vs (100 V/div)
modulated by EPS). Moreover, for the purpose of highlighting
the effect of the conduction losses, the operating points of
two groups are both located within the ZVS range. As shown is (25 A/div)
in IV-B3, the piecewise linear scheme has three segments.
Therefore, for either boost or buck scenarios, the measured ZVS vGS,S7 (10 V/div)
working waveforms with three different output power levels vDS,S7 (100 V/div)
are shown in the following.
In Mode I, the steady state waveforms of the DAB con- 2 μs/div
verter are illustrated in Fig. 17, where vp and vs are voltage
Fig. 17. Experimental waveforms of DAB converter in Mode I where V1 =120
waveforms generated by HB1 and HB2 , and ip , is are the V, V2 =46 V (k = 0.75) (a) working waveforms without optimized modulation
primary and secondary transformer current, respectively. Fig. (b) working waveforms with linearized modulation scheme (c) ZVS realization
17(a) shows the measured waveforms when the DAB converter without optimized modulation (d) ZVS realization with linearized modulation
scheme.
works without adopting any optimized modulation (belongs
to G2). Fig. 17(b) shows the working waveforms when the
converter is modulated by linearized scheme (belongs to G1).
The output power for both situations is given at 190 W. As 17(d), corresponding to the working conditions in Fig. 17(a)
marked in the figure, the value of Is.rms in Fig. 17(b) is lower and Fig. 17(b), respectively. It can be seen that the switching-
than that in Fig. 17(a), indicating the effectiveness of OMS4 on signal (i.e. rising edge) of vGS,S7 comes after the drain-
in reducing the conduction losses of the DAB converter. As a source voltage vDS,S7 becoming zero, which implies that the
result, the overall system efficiency is improved from 92.5% to transistor S7 has achieved zero-voltage turn-on.
95 %. Besides, in order to directly see if the ZVS is achieved, In Mode II, the converter is operated at two power levels
the drain-source voltage and the gate signal of S7 (turned on (i.e. 430 W and 700 W) and the working waveforms are
at the rising edge of vs ) are illustrated in Fig. 17(c) and Fig. shown in Fig. 18 and Fig. 19, respectively. Although there

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@ Po=430 W, Is.rms=15.62 A, η=93.2 % @ Po=700 W, Is.rms=25.07 A, η=90.8 %

vs (100V/div) vs (100V/div)

vp (250 V/div) ip (10 A/div) vp (250 V/div) ip (10 A/div)

is (25 A/div)
5 μs/div is (25 A/div) 5 μs/div

(a) (a)

@ Po=430 W, Is.rms=13.87 A, η=94.0 % @ Po=700 W, Is.rms=23.21 A, η=91.3 %

vs (100V/div) vs (100V/div)

ip (10 A/div) vp (250 V/div) ip (10 A/div)

vp (250 V/div)

is (25 A/div) is (25 A/div) 5 μs/div

5 μs/div
(b) (b)

vs (100 V/div) vs (100 V/div)

is (25 A/div)
is (25 A/div)

ZVS vGS,S7 (10 V/div) ZVS vGS,S7 (10 V/div)

vDS,S7 (100 V/div) vDS,S7 (100 V/div)

2 μs/div
2 μs/div
(c) (c)
vs (100 V/div)
vs (100 V/div)

is (25 A/div)
is (25 A/div)

ZVS vGS,S7 (10 V/div) ZVS vGS,S7 (10 V/div)

vDS,S7 (100 V/div)
vDS,S7 (100 V/div)
2 μs/div
2 μs/div
Fig. 18. Experimental waveforms of DAB converter in Mode II where V1 =120 Fig. 19. Experimental waveforms of DAB converter in Mode II where V1 =120
V, V2 =46 V (k = 0.75) (a) working waveforms without optimized modulation V, V2 =46 V (k = 0.75) (a) working waveforms without optimized modulation
(b) working waveforms with linearized modulation scheme (c) ZVS realization (b) working waveforms with linearized modulation scheme (c) ZVS realization
without optimized modulation (d) ZVS realization with linearized modulation without optimized modulation (d) ZVS realization with linearized modulation
scheme. scheme.

the corresponding waveforms for Mode III and Mode IV,

are some oscillations at the switching-on instants of S7 , the respectively. Similar conclusions can be achieved with reduced
voltage across S7 is kept at zero when the gate signal reaches conduction losses and improved efficiency. Also, the ZVS is
high level, thus ZVS is still guaranteed in these two higher realized at different output power levels.
power situations. On the other hand, compared to Fig. 18(a) Besides, the linear OMS4 is essentially a hybrid modulation
and Fig. 19(a), the converter efficiency is improved when the scheme, consisting of EPS in light, medium load and SPS in
optimized linear modulation scheme is utilized in Fig. 18(b) heavy load. This can be seen from the expressions (31) and
and Fig. 19(b), respectively. (32) and the working waveforms in Fig. 19 and Fig. 22. By
In terms of buck scenarios, Fig. 20 ∼ Fig. 22 present switching the converter between light load and heavy load with

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2956323, IEEE Journal
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@ Po=150 W, Is.rms=8.44 A, η=93.1 % @ Po=1100 W, Is.rms=32.85 A, η=88.8 %

vs (100V/div)

vp (250 V/div) ip (10 A/div)

is (25 A/div) 5 μs/div

(a) (a)
@ Po=150 W, Is.rms=7.57 A, η=94.0 % @ Po=1100 W, Is.rms=30.10 A, η=90.7 %
vs (100V/div) vs (100V/div)

vp (250 V/div) ip (10 A/div) vp (250 V/div) ip (10 A/div)

is (25 A/div) 5 μs/div is (25 A/div) 5 μs/div

(b) (b)

vs (100 V/div) vs (100 V/div)

is (25 A/div)
is (25 A/div)
ZVS vGS,S7 (10 V/div) ZVS vGS,S7 (10 V/div)
vDS,S7 (100 V/div)

2 μs/div vDS,S7 (100 V/div) 2 μs/div

(c) (c)

vs (100 V/div) vs (100 V/div)

is (25 A/div) is (25 A/div)

ZVS vGS,S7 (10 V/div) vGS,S7 (10 V/div) ZVS

vDS,S7 (100 V/div)

2 μs/div vDS,S7 (100 V/div) 2 μs/div

Fig. 20. Experimental waveforms of DAB converter in Mode III where Fig. 21. Experimental waveforms of DAB converter in Mode IV where
V1 =190 V, V2 =36 V (k = 1.5) (a) working waveforms without optimized V1 =190 V, V2 =36 V (k = 1.5) (a) working waveforms without optimized
modulation (b) working waveforms with linearized modulation scheme (c) modulation (b) working waveforms with linearized modulation scheme (c)
ZVS realization without optimized modulation (d) ZVS realization with ZVS realization without optimized modulation (d) ZVS realization with
linearized modulation scheme. linearized modulation scheme.

OMS4, the dynamic response is shown in Fig. 23, where V2

is the output dc voltage, io is the output current and is is the operate the converter with different voltage ratios, and the
leakage inductance current referred to the secondary side. The measured efficiency curves are shown in Fig. 24. Correspond-
power is increased from 150 W to 700 W in Fig. 23(a) and ing to boost and buck scenarios, Fig. 24(a) (k = 0.9) and
then decreased in Fig. 23(b). Part of is is amplified in green Fig. 24(b) (k = 1.2) plot the converter efficiency at different
frames for having a clear view on the current shape of is . It output powers. In the figure, three situations are illustrated: the
can be seen that the converter can smoothly changes from EPS red curve denotes the linearized modulation scheme (belongs
to SPS or reverse depending on the power condition. to G1), the blue curve represents the normal EPS modulation
Furthermore, the input and output voltage are changed to without any optimization (belongs to G2) and the black curve

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2956323, IEEE Journal
of Emerging and Selected Topics in Power Electronics
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@ Po=1200 W, Is.rms=34.26 A, η=88.6 %

V2 (100V/div)
vs (100V/div)
Po=150 W Po=700 W
io (10 A/div)
vp (250 V/div) ip (10 A/div)

is (25 A/div) is (30 A/div)

1 ms/div
5 μs/div

(a) V2 (100V/div)
Po=700 W Po=150 W
@ Po=1200 W, Is.rms=32.40 A, η=89.5 % io (10 A/div)
vs (100V/div)
is (30 A/div)

vp (250 V/div) ip (10 A/div)

1 ms/div

Fig. 23. Dynamic response with the output power (a) increased from 150 W
to 700 W (b) decreased from 700 W to 150 W in boost scenario (V1 =120 V,
is (25 A/div) 5 μs/div
V2 =46 V).

(b)

vs (100 V/div)
OMS4
is (25 A/div)
EPS
vGS,S7 (10 V/div) ZVS

SPS
vDS,S7 (100 V/div) 2 μs/div

(c)

vs (100 V/div)
(a)
is (25 A/div)

vGS,S7 (10 V/div) ZVS OMS4

EPS
vDS,S7 (100 V/div) 2 μs/div

Fig. 22. Experimental waveforms of DAB converter in Mode III where

V1 =190 V, V2 =36 V (k = 1.5) (a) working waveforms without optimized SPS
modulation (b) working waveforms with linearized modulation scheme (c)
ZVS realization without optimized modulation (d) ZVS realization with
linearized modulation scheme.

is the resulted efficiency by applying SPS over the whole (b)

power range. Among the three situations, the linearized mod- Fig. 24. Measured efficiency curves of the DAB converter for different
ulation scheme has a better efficiency performance in either output power levels, where the red curve, blue curve and black curve denote
the converter efficiencies with linear modulation scheme (G1), without any
boost or buck scenarios. In light load, due to the ZVS failure optimization (G2) and with SPS, respectively. (a) Boost operation, V1 =190
in SPS (black curve), the induced switching losses result in V, V2 =60 V (k = 0.9) (b) Buck operation, V1 =190 V, V2 =45 V (k = 1.2).
lower efficiency compared to the other two situations (G1 and
G2). When the converter works with higher output power, the
linearized modulation transfer into SPS scheme and thus the red curve and the black curve are overlapped in heavy load

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2956323, IEEE Journal
of Emerging and Selected Topics in Power Electronics
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2956323, IEEE Journal
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