IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO.

12, DECEMBER 2016 8387

Combined Phase-Shift and Frequency Modulation of

a Dual-Active-Bridge AC–DC Converter With PFC
Felix Jauch, Student Member, IEEE, and Jürgen Biela, Member, IEEE

Abstract—This paper presents a combined phase-shift and fre- power quality ac–dc converters is given in [3], whereas [4] sum-
quency modulation scheme of a dual–active-bridge (DAB) ac– marizes single-phase nonisolated PFC topologies based on the
dc converter with power factor correction (PFC) to achieve zero boost converter approach.
voltage switching (ZVS) over the full range of the ac mains voltage.
The DAB consists of a half bridge with bidirectional switches on the A DAB converter topology with a rectified ac line voltage
ac side and a full bridge on the dc side of the isolation transformer to as input is presented in [5]–[7], where modulation schemes for
accomplish single-stage power conversion. The modulation scheme the ac–dc operation under zero voltage switching (ZVS) con-
is described by means of analytical formulas, which are used in an ditions are derived. Approaches where the DAB is connected
optimization procedure to determine the optimal control variables directly to the ac line voltage by applying bidirectional switches
for minimum switch commutation currents. Furthermore, an ac
current controller suitable for the proposed modulation scheme are given in [8]–[10]. In [10], a modulation scheme that guar-
is described. A loss model and measurements on a 3.3-kW elec- antees ac-side zero current switching (ZCS) and dc-side ZVS
tric vehicle battery charger to connect to the 230 Vrms / 50-Hz is presented. The main drawbacks of the modulation are the
mains considering a battery voltage range of 280–420 V validate the high transformer peak currents that substantially limit the effi-
theoretical analysis. ciency of the converter. The operation proposed in [9] allows a
Index Terms—AC–DC Converter, bidirectional, isolated, power three-level pulsewidth modulation on the ac side while achiev-
factor correction, zero voltage switching. ing either ZVS or ZCS conditions for all switching devices in
all points of operation. Nevertheless, through the applied com-
I. INTRODUCTION mutation control, the switching frequency and in turn the power
HE power conversion from ac to dc or vice versa has be- density of the converter is rather limited.
T come a fundamental part of the electricity infrastructure
since many applications demand either a dc source or a dc sink.
In general, several modulation methods like phase-shift mod-
ulation, triangular, and trapezoidal current mode modulation [1],
Even for electrical machines, ac frontend rectifiers are in place [11], [12] have been investigated for the operation of a DAB.
with subsequent inverters driving the machines. In some cases, Besides the commonly used control variables like phase-shifts
also galvanic isolation between ac and dc side is needed or and clamping intervals, also the switching frequency is consid-
even mandatory to be compliant with standards. Isolated ac–dc ered to control a DAB in [7] and [13] to boost the efficiency in
converters are used for instance for charging electric vehicles, light-load operation as well as to maintain ZVS conditions in
interfacing storage batteries for uninterruptible power supplies full ac–dc operation.
or supplying energy from photovoltaic systems to the grid. In This paper focuses on the DAB ac–dc converter presented in
order to keep the conducted electromagnetic interference low, [14], where bidirectional switches are applied on the ac side.
the harmonic content of the ac current has to be limited. Further- The discussed combined phase-shift and frequency modulation
more, to reduce losses in distribution grids, a converter equip- strategy is generalized in this paper so that the control variables
ment should draw mainly active power with a power factor (PF) are found by an optimization to achieve ZVS over the whole ac
close to unity. mains voltage for minimum commutation currents. Especially
For isolated power conversion from ac to dc, the conventional with the use of silicon power MOSFETs, hard switching con-
approach is a two-stage solution with a boost power factor cor- ditions in terms of forced body diode commutations lead to
rection (PFC) rectifier and a subsequent high-frequency isolated relatively high switching losses (high reverse recovery losses),
dc–dc converter such as a dual-active-bridge (DAB) [1] or a res- and therefore, to a reduced efficiency of the converter system.
onant dc–dc converter [2]. Besides this two-stage conversion, Furthermore, hard switching can lead in the worst case to the
several single-stage isolated ac–dc PFC converter topologies destruction of the semiconductor devices. For these reasons, this
have been proposed. A review of state-of-the-art single-phase paper focuses on developing a modulation scheme to allow ZVS
for all switches of the DAB at every time instant of the ac mains
voltage.
Manuscript received April 15, 2015; revised September 17, 2015 and Novem-
ber 25, 2015; accepted December 30, 2015. Date of publication January 08, First, in Section II, the DAB ac–dc converter topology is
2016; date of current version July 08, 2016. This paper was presented at the 15th explained. The operating principle in ac-to-dc and dc-to-ac op-
International Power Electronics and Motion Control Conference (EPE-PEMC eration including the mathematical analysis of the modulation
2012/ECCE Europe), Novi Sad, Serbia, September 4–6, 2012. Recommended
for publication by Associate Editor B. Wang. scheme is discussed in Section III. There, also the derivation of
The authors are with the Laboratory for High Power Electronic Systems, ETH the optimal control variables and the design of an ac input cur-
Zurich, Zurich 8092, Switzerland (e-mail: jauchf@ethz.ch; jbiela@ethz.ch). rent controller is given. Finally, Section IV shows a hardware
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. prototype system including a detailed loss model and experi-
Digital Object Identifier 10.1109/TPEL.2016.2515850 mental results for validating the theoretical analysis.
0885-8993 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
8388 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 12, DECEMBER 2016

the transformer leakage inductance current iL σ is shaped ac-

cording to the modulation scheme described in the following to
allow ZVS at every switching instant.

III. MODULATION AND CONTROL

The converter is operated with a combined phase-shift and
frequency modulation [14] based on a general trapezoidal cur-
rent mode modulation of the well-known DAB dc–dc converter
[12]. This modulation method is suitable for high power transfer
at relatively low peak currents and can be adjusted to achieve
ZVS in every switching point as shown later.
A simple equivalent circuit is given in Fig. 2(a), which con-
sists of the LC input filter stage and a parallel connected variable
Fig. 1. DAB ac–dc converter with PFC, which applies a combined phase-shift
and frequency modulation to guarantee ZVS over the whole ac line period. impedance load Zl . The impedance load represents the behavior
of the DAB seen from the mains.
By adjusting the control variables of the modulation, and
therefore, controlling the power drawn from the mains the
impedance load is changing. The converter is operated in such a
way, that the reactive power consumed by the filter capacitors is
compensated by the variable impedance load in order to achieve
PFC.
Fig. 2(b) shows a simplified representation of the converter
for phase-shift control. The magnetizing inductance Lm of the
transformer is assumed to be much larger than the leakage in-
ductance Lσ and is, therefore, neglected in the following.
Fig. 2. Equivalent circuits of the DAB converter: (a) with variable impedance The ac-side half bridge is switched with a constant duty cycle
load Z l for representing the behavior of the DAB seen from the mains and
(b) for representing phase-shift modulation for controlling the power transfer of 50%, which leads to equally distributed capacitor voltages
from the ac to the dc side and vice versa. vC 1 and vC 2 . Neglecting the input inductor L1 , the average
value over one switching cycle of vC 1 , vC 2 follows the ac line
II. DAB AC–DC CONVERTER voltage according to
The schematic of the DAB ac–dc converter is shown in Fig. 1 V̂1
and has been introduced in [14]. Due to the alternating line vC 1 (t) = vC 2 (t) = sin (ωt) . (2)
2
voltage, bidirectional switches on the ac side have to be used. Assuming further a negligible small capacitor voltage ripple,
These can be realized by an antiserial connection of two MOS- the dc-link voltage is vC 3 = V2 (see Fig. 1) for the following
FETs/IGBTs as shown in Fig. 1 or by reverse blocking IGBTs. mathematical considerations.
Compared to the conventional boost PFC approach, the pro- During one half cycle of the ac line voltage, only two of
posed converter filters high-frequency harmonic distortions on the ac-side switches are switched at high frequency. These are
the mains due to the inherently integrated LC input filter stage. S1a and S2a for the positive and S1b and S2b for the negative
The capacitors C1 and C2 absorb the high-frequency switched half wave. The switches switched at low frequency are turned
currents. Nevertheless, the remaining ac voltage ripple on the ON/OFF at nearly zero voltage and zero current at the zero
capacitors leads to a certain degree of high-frequency input- crossing of the ac voltage.
current distortions. As indicated in Fig. 2(b), on the primary side of the trans-
In either power flow direction, the converter can operate in former, a square-wave voltage vp with the time-dependent am-
buck or boost mode depending on the transformer turns ratio. plitude |v1 (t)| /2 is applied. The voltage vs on the transformer
For the considered ac-to-dc operation in boost mode in the secondary side consists of positive and negative voltage pulses
following, the turns ratio n is chosen such that the primary including a clamping interval with an amplitude of V2 , which
referred dc voltage V2 = nV2 is higher than half of the maximum allows shaping the transformer leakage inductance current iL σ
peak voltage of the ac line voltage in every operating point to transfer the desired instantaneous power and to achieve ZVS.
according to The voltage amplitudes of vp and vs are assumed to be constant
V̂1 over one switching cycle because the switching frequency is
nV2 > . (1) chosen to be well above the mains frequency.
2
The boost mode condition has to be fulfilled for the whole A. AC-to-DC Operation
battery voltage range and leads to a minimal turns ratio n at In ac-to-dc operation, power flows from the mains to the dc
the lowest battery voltage V2 . Based on the induced relation of side. To describe the combined phase-shift and frequency mod-
the winding voltages referred to the ac side of the transformer, ulation analytically, the control variables g and w normalized to
JAUCH AND BIELA: COMBINED PHASE-SHIFT AND FREQUENCY MODULATION OF A DUAL-ACTIVE-BRIDGE 8389

are assumed to be changing instantaneously (step function) at

the end of the interlocking interval and the leakage inductance
current is simplified to a linear waveform during that interval.
With the points in time τ0 up to τ8 defined according to
Fig. 3, the transformer leakage inductance current iL σ in ac-to-
dc operation is in general modeled by
⎧ |v 1 |
⎪
⎪ 2 +n V 2
(τ − τ0 ) + iL σ (τ0 ) τ 0 ≤ τ ≤ τ1
⎪
⎪ Lσ
⎪
⎪
⎪
⎪ |v 1 |
⎪
⎪ 2 +n V 2
(τ − τ1 ) + iL σ (τ1 ) τ 1 ≤ τ ≤ τ2
⎪
⎪ Lσ
⎪
⎪
⎪
⎪
|v 1 |
⎪
⎪ L σ (τ − τ2 ) + iL σ (τ2 )
2
τ 2 ≤ τ ≤ τ3
⎪
⎪
⎪
⎪ 21 −n V 2
⎪
⎨
|v |
(τ − τ3 ) + iL σ (τ3 ) τ 3 ≤ τ ≤ τ4
Lσ
iL σ (τ ) =
⎪
⎪
|v 1 |
− 2 −n V 2
⎪
⎪ (τ − τ4 ) + iL σ (τ4 ) τ4 ≤ τ ≤ τ5
⎪
⎪ Lσ
⎪
⎪ − 1 −n V 2
⎪
⎪
|v |

⎪
⎪
2
(τ − τ5 ) + iL σ (τ5 ) τ5 ≤ τ ≤ τ6
⎪
⎪
Lσ
⎪
⎪ |v |
⎪
⎪ − 2 1
⎪
⎪ L σ (τ − τ6 ) + iL σ (τ6 ) τ 6 ≤ τ ≤ τ7
⎪
⎪
⎪
⎩ − |v21 | +n V 2
Lσ (τ − τ7 ) + iL σ (τ7 ) τ7 ≤ τ ≤ τ8
(3)
with the values at the points in time
1
|v1 | + (4g + 2w − 1)nV2
iL σ (τ0 ) = − 2 (4)
4fs Lσ
Fig. 3. Primary and secondary transformer voltages v p , v s and transformer
leakage inductance current iL σ over one switching period T s in ac-to-dc opera-
(2g − 2si − 12 ) |v1 | − (2w + 4si − 1)nV2
iL σ (τ1 ) = (5)
tion. The gate signals of the ac-side switches differ for a positive and a negative 4fs Lσ
ac line voltage.
(2g − 12 ) |v1 | − (2w − 1)nV2
iL σ (τ2 ) = (6)
4fs Lσ
the switching period Ts = 1/fs are introduced. g is the phase
shift between the ac side applied square-wave voltage vp and (2g + 2w − 12 ) |v1 | − (2w − 1)nV2
iL σ (τ3 ) = (7)
the dc side applied square-wave voltage vs as shown in Fig. 3. 4fs Lσ
w represents the length of the dc-side clamping interval. More- 1
|v1 | + (4g + 2w − 1)nV2
2
over, the interlocking interval ti = si Ts is considered, which iL σ (τ4 ) = (8)
4fs Lσ
corresponds to the dead time between the turn-off and the turn-
on of a switch in a half bridge. This time interval is taken into (2g − 2si − 12 ) |v1 | − (2w + 4si − 1)nV2
account since it leads to a substantial contribution to the power iL σ (τ5 ) = − (9)
4fs Lσ
transfer especially at high switching frequencies. In a state
machine realization for generating the gate signals for the (2g − 12 ) |v1 | − (2w − 1)nV2
iL σ (τ6 ) = − (10)
switches, this interval is usually kept constant so that no external 4fs Lσ
control possibilities exist to adjust it. Therefore, the derivation (2g + 2w − 12 ) |v1 | − (2w − 1)nV2
of the power flow equation incorporates the dead time to im- iL σ (τ7 ) = − . (11)
4fs Lσ
prove the converter model from which the control variables g
and w are derived for a given reference power. The points in time τ1 and τ5 are not necessary for the ana-
It is assumed that the resonant transition for a minimum com- lytical determination of the power-flow equation. Nevertheless,
mutation current takes place rather slowly. This means that the they are required for calculating the turn-off currents for stating
voltage change on the transformer winding occurs near the end the ZVS conditions as shown later. The allowed intervals of the
of the interlocking interval. The assumption coincides with the control variables g and w are given by
measurements shown in [15], where the charging behavior of a 1
MOSFETs output capacitance is observed to be not time recip- si ≤ g ≤ (12)
2
rocal to its discharging behavior.
1
In Fig. 3, the resulting transformer leakage inductance cur- 0≤w≤ − g. (13)
rent iL σ and the gate signals of the switches for a positive and a 2
negative mains voltage are given. For the following mathemat- The boundaries for the control variables g and w arise from
ical analysis, the voltages applied to the transformer windings the applied general trapezoidal current mode modulation [12]
8390 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 12, DECEMBER 2016

determines the size of the passive components and in turn limits

the power density of the converter system. The required core
cross section of the transformer is given by the flux excitation at
the lowest switching frequency. Moreover, the ac- and dc-side
capacitors as well as the filter inductors have to be designed for
fs,min since the current and voltage ripples become substantially
greater compared to the operation at fs,max .
The power transferred over one switching cycle Ts from the
T
ac to the dc side can be calculated with the integral T1s 0 s vp (τ )
iL σ (τ )dτ and is given by
 
|v1 | nV2 2g − 4g 2 + w − 2w2 − 4gw
pt = . (15)
4fs Lσ
Setting the derivatives of pt with respect to g and w to zero,
leads to the maximum transferrable power of
|v1 | nV2
pt,max = (16)
16fs Lσ
at g = 1/4 and w = 0.
During the intervals [τ0 , τ1 ] and [τ4 , τ5 ], only reactive power
is transferred in the shaded areas shown in Fig. 3, which is re-
quired for the resonant transition to achieve ZVS. For a positive
voltage vp and as well for a negative voltage vp , the shaded areas
highlight two time intervals where the leakage inductance cur-
rent iL σ exhibits once a negative and once a positive polarity so
1
Fig. 4. Primary and secondary transformer voltages v p , v s and transformer
that the power derived by the integral T 1 +T 2
v p (τ )iL σ (τ )dτ
leakage inductance current iL σ over one switching period T s in dc-to-ac opera- over these two time intervals T1 , T2 gets zero. This means that
tion. The gate signals of the ac-side switches differ for a positive and a negative no active power is transferred during these intervals. The deriva-
ac line voltage.
tion of the control variables by keeping these areas small will
be shown later.
and the defined time intervals between the points in time τ0 up
to τ8 depicted in Fig. 3. With the aforementioned assumption B. DC-to-AC Operation
that the applied voltages to the transformer windings change at In dc-to-ac operation, power flows from the dc side to the ac
the near end of the interlocking interval, the lower limit of the side of the transformer, which demands an unequal sign of the
phase shift g is given by the constant interval si . This limit is applied transformer voltages vp , vs and the transformer leakage
reached for τ1 = τ0 . The upper limit for g is reached at 1/2 inductance current iL σ . Fig. 4 shows the transformer voltages
when the clamping interval w gets zero. This means that the vp , vs , the leakage inductance current iL σ and the gate signals
intervals [τ2 , τ3 ] and [τ3 , τ4 ] become zero with τ4 = τ3 = τ2 . of the switches for a positive and a negative mains voltage.
Depending on the phase shift g, the length of the clamping The analytical expression of the transformer leakage induc-
interval w reaches its upper limit where the time interval [τ3 , τ4 ] tance current iL σ in dc-to-ac operation can be determined the
becomes zero with τ4 = τ3 . same way as in the ac-to-dc operation considering the switching
Besides the phase shift g and the clamping interval w, also instants from Fig. 4. The power transferred from the dc to the
the switching period Ts is considered as a control variable with ac side is given by (15) by setting −pt . The same holds for
its limits the maximum transferrable power, which is defined by (16) by
Ts,min ≤ Ts ≤ Ts,max . (14) means of −pt,max .
Again, only reactive power is transferred during the intervals
Varying the switching frequency fs = 1/Ts can lead to sub- [τ2 , τ3 ] and [τ6 , τ7 ] in the shaded areas given in Fig. 4 that is
stantial improvements of the efficiency of a DAB converter in required for ZVS.
light-load operation [13]. From a practical point of view, the
control variable Ts should be limited within reasonable bound- C. ZVS Conditions
aries. The lower limit of the switching period Ts,min (upper limit To achieve ZVS for all switching devices during one half cy-
of the switching frequency fs,max ) is mainly restricted by the cle of the mains, the turn-off currents have to be large enough to
switching speed and the switching losses under ZVS conditions charge/discharge the drain–source capacitances of the switching
of the applied MOSFET device. The upper limit of the switch- devices in a bridge leg. The ZVS conditions for the general trape-
ing period Ts,max (lower limit of the switching frequency fs,min ) zoidal modulation scheme described previously and depicted in
JAUCH AND BIELA: COMBINED PHASE-SHIFT AND FREQUENCY MODULATION OF A DUAL-ACTIVE-BRIDGE 8391

Fig. 6. Converter efficiencies for the prototype system depending on the trans-
former leakage inductance peak current iL σ (τ 2 ) for different parameterizations
with the switching frequency fs and the power p t . The efficiencies are given at
the ac voltage amplitude v 1 = 325 V and the dc voltage V 2 = 350 V at a given
dc power operating point p t .
Fig. 5. Flow chart of the optimization algorithm to derive optimal control
variables g, w, T s for ZVS conditions for a given set of converter parameters
n, L σ , V 2 and a reference current amplitude Iˆ1∗ . in Figs. 3 and 4) that is required for ZVS is kept minimal what
in turn results in minimal transformer leakage inductance peak
Fig. 3 for ac-to-dc operation are given by currents.
The minimization of the peak current in every switching cycle
iL σ (τ0 ) < −Is (17) leads to the maximum converter efficiency as shown in Fig. 6 for
iL σ (τ1 ) > Is (18) different parameterizations with the switching frequency fs and
the power pt . There, the efficiencies at the ac voltage amplitude
iL σ (τ4 ) > Is (19) v1 = 325 V and the dc voltage V2 = 350 V are evaluated by
iL σ (τ5 ) < −Is (20) iterating over the phase shift g ∈ [si , 1/2] for a constant switch-
ing frequency fs and a given dc power operating point pt for the
where Is is the minimum commutation current required for the prototype system described later. With increasing phase shift g
resonant transition during the interlocking interval. With these the clamping interval w is decreased to keep the power pt con-
conditions, ZVS is inherently guaranteed also for the switching stant. As the phase shift increases also the leakage inductance
instants τ2 , τ3 , τ6 , τ7 in Fig. 3. In the same way, the ZVS condi- peak current iL σ (τ2 ) (see Fig. 3) increases and the converter
tions in dc-to-ac operation can be derived. Introducing energy efficiency drops. The starting point of the phase shift where the
equivalent capacitances Ceq,p , Ceq,s for the parallel connection efficiency exhibits its maximum guarantees that iL σ (τ0 ) < 0 as
of the drain–source capacitances of the ac-/dc-side bridge leg, well as iL σ (τ1 ) > 0.
the minimum commutation current can be determined as The optimization problem is formulated as
⎧ ⎫
⎨ v V ⎬ min (|iL σ (τ0 , x)| , |iL σ (τ1 , x)|) (22)
1 2
Is = max , . (21) x
⎩ Lσ Lσ ⎭
C eq, p C eq, s with respect to
⎡ ⎤ ⎡ ⎤ ⎡ 1 ⎤
Compared to [14], where the current points have been fixed to g si 2
⎢ ⎥
the minimum commutation current, a general approach to derive x = ⎣ w ⎦ with xlb = ⎣ 0 ⎦, xub = ⎣ 21 − g ⎦ (23)
the control variables for ZVS conditions using an optimization Ts Ts,min Ts,max
is described. This is presented in the next section.
where x denotes the vector of control variables, which is re-
D. Optimal Control Variables stricted to lower and upper bounds xlb , xub respectively. The
first constraint is given by the power equality constraint
For the combined phase-shift and frequency modulation,
there are three degrees of freedom in the modulation scheme. pt (t, x) = p∗t (t) (24)
These are the phase shift g, the length of the clamping interval
w, and the switching period Ts . At each point of the ac mains with the reference of the instantaneous power p∗t (t) for a given
voltage, these control variables are derived by minimizing the input current amplitude Iˆ1∗
absolute value of the transformer leakage inductance current iL σ ω (C1 + C2 ) 2
at the time instants τ0 and τ1 for a minimal commutation current p∗t (t) = V̂1 Iˆ1∗ sin2 (ωt) − V̂1 sin(ωt) cos(ωt).
4
as shown in Fig. 5. In this way, the reactive power (shaded areas (25)
8392 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 12, DECEMBER 2016

TABLE I
PARAMETERS OF THE HARDWARE PROTOTYPE SYSTEM

Mains voltage V1 230 Vrms ± 10 %

Mains frequency f g = 1/T g 50 Hz
Battery voltage V2 280 V...420 V
Output power P2 3.3 kW
Switching frequency fs 20 kHz...120 kHz
Fig. 8. Overview of the DAB converter control including the mains PLL to
Transformer turns ratio n 10/13
determine the mains angle , a lookup table to store the optimal control variables
Transformer leakage inductance Lσ 20 μH
g, w, T s as well as a PI controller for adjusting the switching period T s to shape
Transformer magnetizing inductance Lm 11 mH
the ac input current i1 .
Inductors L1 , L2 100 μH
Capacitors C1 , C2 10 μF
Capacitor C3 20 μF
1) Mains PLL: The mains PLL includes an orthogonal sys-
tem generator (OSG) implemented with a second-order gen-
eralized integrator (SOGI) structure as proposed in [16], [17].
With the OSG–SOGI structure, two clean orthogonal voltage
waveforms vα , vβ are constructed. These are then transformed
into rotating dq-coordinates and vd is controlled to zero (syn-
chronization to a sinusoidal waveform) to derive the mains
angle .
2) Lookup Table: The lookup table stores the optimal control
variables g, w, Ts for an ac mains half-wave dependent on the
mains angle  and parameterized with the dc output voltage
V2 and the reference current amplitude Iˆ1∗ . The output of the
switching period Ts serves as feed-forward value for the PI
controller that adds a ΔTs to it as shown in Fig. 8. The resulting
Fig. 7. Optimal control variables g(t), w(t), and fs (t) = 1/T s (t) over a half Ts∗ gets then multiplied by g and w. The switching signals state
cycle of the mains period in ac-to-dc operation for a mains voltage of 230 Vrms ,
an input current of 16 Arms , and an output voltage of 350 V. The control variables machine finally generates the gate signals for the switches from
are derived by using the optimization algorithm depicted in Fig. 5 and stored in gTs∗ , wTs∗ , Ts∗ according to Figs. 3 and 4, respectively.
the lookup table shown in Fig. 8. 3) PI Controller: For the PI controller design, the small-
signal transfer function from ΔTs to Δi1 is derived from (15)
There, also the compensation of the reactive power of the input and given as
capacitors C1 , C2 is taken into account. Further constraints are  
given by the minimum commutation current Is for ZVS as Δi1 nV2 2g − 4g 2 + w − 2w2 − 4gw
Gp = = . (28)
ΔTs 4Lσ
|iL σ (τ0 , x)| ≥ Is (26)
Since the DAB converter is not operated near the resonant fre-
|iL σ (τ1 , x)| ≥ Is . (27) quency of the resonant tank formed by C1 , C2 , C3 , and Lσ , the
dynamics of these passive elements can be neglected what has
The optimization results for a mains voltage of 230 Vrms , an
been also a prerequisite previously for describing iL σ with linear
input current of 16 Arms , and an output voltage of 350 V by
equations. The transfer function Gp is mainly dependent on the
using the parameters from Table I is shown in Fig. 7. Around
mains angle  (indirectly via the control variables g(), w())
the zero crossing of the mains voltage, the switching frequency
and the output voltage V2 . To compensate the voltage depen-
fs (t) is increased to lower the output power and reaches its
dences, the proportional and integral gain of the PI controller
maximum that is set to 120 kHz. Similar, the phase shift g(t) is
are scaled by
increased with lower output power that guarantees a triangular-
like transformer leakage inductance current that is required to 1 4Lσ
maintain ZVS also around the zero crossing of the mains voltage. K= = (29)
Gp nV2 (2g − 4g 2 + w − 2w2 − 4gw)
For high power transfer at t = 2 ms up to t = 8 ms (see Fig. 7),
w(t) stays rather constant and the power is controlled mainly such that
by the phase shift g(t) and the switching frequency fs (t). P
KP = K K (30)
E. Converter Control I
KI = K K (31)
The control of the DAB converter is based on a phase-locked where K  I are the constant gains and KP , KI the effective
P , K
loop (PLL) for synchronization to the ac mains voltage v1 , a and adaptive ones. The closed-loop transfer function can be
lookup table to store the optimal control variables g, w, Ts as written as
well as a PI controller for adjusting the switching period Ts
to shape the ac input current i1 . An overview of the control is GPI Gp KI + K
P s
Gcl = = (32)
depicted in Fig. 8. 1 + GPI Gp  I + (1 + K
K  P )s
JAUCH AND BIELA: COMBINED PHASE-SHIFT AND FREQUENCY MODULATION OF A DUAL-ACTIVE-BRIDGE 8393

TABLE II
COMPONENTS OF THE HARDWARE PROTOTYPE SYSTEM

MOSFETs S 1 a , S 1 b , S 2 a , S 2 b 2x STY139N65M5, 650 V, 14 mΩ

MOSFETs S 3 , S 4 , S 5 , S 6 2x STY139N65M5, 650 V, 14 mΩ
Transformer 2x 2x AMCC-4 VITROPERM 500
10 primary turns, 120 μm copper foil
13 secondary turns, 120 μm copper foil
Inductor L 1 2x Kool Mu E 4317 26u, 27 turns
Litz wire, 20 strands, 0.355 mm
Inductor L 2 2x Kool Mu E 4317 26u, 27 turns
Litz wire, 20 strands, 0.355 mm
Capacitors C 1 , C 2 18x Syfer 1825J500564KX, 560 nF
Capacitor C 3 36x Syfer 1825J500564KX, 560 nF

Fig. 9. Photograph of the hardware prototype system for experimental verifi-

cation of the proposed combined phase-shift and frequency modulation.

Fig. 11. Calculated efficiencies of the DAB ac–dc converter applying the pro-
posed combined phase-shift and frequency modulation over the output power
range for battery voltages 280, 350, and 420 V. Additionally, the calculated
efficiency curve for the converter operated with the standard phase-shift modu-
lation and the measured efficiency of the hardware prototype both at a battery
voltage of 350 V are shown.

Fig. 10. 2-D drawing of the transformer including its reluctance model con-
sisting of C-cores forming an E-core with the ac-side winding W p wound around IV. HARDWARE PROTOTYPE
the inner leg and the dc-side winding W s around the inner and the right-hand
sided stray leg. By inserting an air gap of length δσ in the stray leg, the leakage For validating the combined phase-shift and frequency mod-
inductance L σ can be set.
ulation, an electric vehicle battery charger for Lithium-ion bat-
teries with 3.3-kW output power to connect to the single-phase
with GPI being the transfer function of the PI controller ac mains has been built and is shown in Fig. 9. The parameters
  of the hardware prototype are given in Table I.
KI KI
GPI = KP + =K K P + . (33) A. Converter Components and Loss Model
s s
In the following, the converter components with their loss
 P = 0, the closed-loop transfer function can be models are presented for evaluating the converter efficiencies at
By setting K
different operating points. Table II summarizes the components
simplified to a first-order system
of the hardware prototype, whereas Fig. 11 shows the calculated
1 efficiencies over the output power range for battery voltages of
Gcl = 1 (34) 280, 350, and 420 V. For low output power, the efficiency curves
1+ I
K
s
diverge because of the high transformer leakage inductance peak
where the rise time from 10% to 90% of the steady-state value currents occurring at high output voltages. In low power mode,
in the step response is given by mainly a triangular-like leakage inductance current occurs at
the maximum switching frequency where the peak current is
2.2 directly proportional to the output voltage.
tr = . (35)
I
K Additionally, the efficiency of the converter applying the
standard phase-shift modulation without the use of the dc-side
Since the controller tracks a sinusoidal waveform, the rise time clamping interval (w = 0) is depicted in Fig. 11. The switching
should be kept small in the magnitude of a few switching periods frequency is fixed at 60 kHz, which corresponds to the average
Ts,max at the lowest switching frequency. With a rise time of of the control variable fs depicted in Fig. 7 for an input current
tr = 100 μs, the controller gains are determined to be KP = 0 of 16 Arms and an output voltage of 350 V. The leakage induc-

and KI = 22 000. tance of the transformer is slightly adjusted to 12 μH to allow
8394 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 12, DECEMBER 2016

with i = {1a, 1b, 2a, 2b, 3, 4, 5, 6}. The hardware prototype ap-
plies two MOSFETs in parallel for all switches (Ns = 2). For
conduction loss calculations, a worst-case junction temperature
of 100 ◦ C is assumed.
2) Transformer: For the proposed modulation to work prop-
erly, the transformer turns ratio has to guarantee vC 3 > V̂1 /2
(with vC 3 referred to the ac side of the transformer), also at
the lowest battery voltage of 280 V. Furthermore, the leakage
inductance Lσ is designed such that the peak of the instanta-
neous power P̂1 [neglecting the reactive power term in (25)] at
full input power of 3.68 kW can be transferred at the lowest
switching frequency of 20 kHz and the lowest battery voltage
Fig. 12. Calculated efficiencies of the DAB ac–dc converter over the out- of 280 V. This can be done by using (16) and solving for Lσ .
put power range for battery voltages 280 and 420 V applying two parallel The transformer is built of two AMCC-4 C-cores [20] made of
STY139N65M5 MOSFETs (R ds, on = 23.8 mΩ at T j = 100 ◦ C) from STMi- VITROPERM 500 [21] material forming an E-core. To increase
croelectronics [18] (solid lines) and three parallel IPW65R019C7 MOSFETs
(R ds, on = 32.5 mΩ at T j = 100 ◦ C) from Infineon [19] (dashed lines). the core area, two of them are stacked. The ac-side winding is
wound around the center leg and the dc-side winding around
the center and an outer stray leg [22]. Fig. 10 depicts a 2-D
drawing of the transformer including its reluctance model with
the flux sources Φp , Φs (driven by the applied winding voltages
vp , vs ) and the magnetic core reluctances Rm 1 , Rm 2 , Rm 3 . An
air gap δσ is inserted in the stray leg to get the desired leak-
age inductance which is modeled by the leakage reluctance
Rσ . In the loss model, the core losses per volume are calcu-
lated by applying the improved generalized Steinmetz equation
Fig. 13. Calculated loss distribution between the converter components at the
(iGSE) [23].
maximum output power of 3.56 kW and a battery voltage of 350 V. For the ac- and dc-side windings, copper foil is used where
the optimal foil thickness is calculated according to [24], which
gives a minimum value of effective ac resistance. These values
the maximum power to be transferred in case of the phase-shift
are 132 and 116 μm. For the hardware prototype, 120-μm copper
modulation. Especially the ac-side MOSFETs are operated un-
foil is chosen, with 10 primary and 13 secondary turns. The skin
der hard switching conditions in the region of low output power
and proximity effect losses per unit length in foil conductors
so that the efficiency drastically drops what in turn can lead in
for each current harmonic are then calculated according to [25].
the worst case to the destruction of the semiconductor devices.
The external magnetic field strength for calculating proximity
The loss distribution between the components at the maxi-
losses is derived by a 1-D approximation based on the Dowell
mum output power of 3.56 kW and a battery voltage of 350 V
method [26] as the air gap in the stray leg is relatively small and
is depicted in Fig. 13.
losses caused by the fringing field can be neglected.
Fig. 12 shows the calculated efficiencies of the DAB ac–dc
3) Inductors: For the ac- and dc-side inductors L1 , L2 two
converter for battery voltages 280 and 420 V for the consid-
stacked E-cores of type Kool Mu 4317 with material 26u from
ered prototype system applying two parallel STY139N65M5
Magnetics [27] are used. Powder cores are ideally suited for
MOSFETs from STMicroelectronics [18] (solid lines) and for a
the hardware prototype because they offer a distributed air gap
converter solution applying three parallel IPW65R019C7 MOS-
and a high saturation flux density. This is advantageous over a
FETs from Infineon [19] (dashed lines).
ferrite core with a large air gap exhibiting considerable fringing
1) Power MOSFETs: Since the proposed modulation
magnetic field. Both inductors are wound with the litz wire with
scheme guarantees ZVS at every switching instant, MOSFET
20 strands of diameter 0.355 mm and a turns number of 27 so
devices with a comparable low on-state resistance are chosen.
that a minimum inductance value of 100 μH is guaranteed at the
The used device is a 650-V MOSFET with an on-state resis-
highest peak current.
tance of 14 mΩ from STMicroelectronics [18]. The losses of the
Again, the core losses per volume are calculated by using the
power MOSFETs are mainly determined by conduction losses.
iGSE, the Steinmetz parameters are obtained from [27]. The
The switching loss energy ESi,sw per MOSFET depending on
skin and proximity effect losses per unit length in the litz wire
the drain–source current is approximated by the turn-off loss
for each current harmonic are calculated according to [25]. Also
curves given in the datasheet as well as measurement data and
for the inductors, the external magnetic field strength is derived
linearly scaled with the drain–source voltage vSi . To reduce con-
by a 1-D approximation [26].
duction losses, Ns number of MOSFETs are paralleled so that
4) Capacitors: For the ac- and dc-side capacitors C1 , C2 ,
the power loss per switch is then approximated by
C3 , paralleled 560-nF ceramic capacitors with dielectric X7R
Rds,on 2 vSi from Syfer [28] are used. For achieving high power densities,
PSi = ISi + Ns fs ESi,sw (36) multilayer ceramic capacitors are ideally suited because they
Ns 400 V
JAUCH AND BIELA: COMBINED PHASE-SHIFT AND FREQUENCY MODULATION OF A DUAL-ACTIVE-BRIDGE 8395

offer comparable high energy densities and allow high current

ripples. Since the voltage ripple on the capacitors is relatively
small at high switching frequencies, dielectric losses are not
accounted for in the loss model. Therefore, only the ohmic
losses according to
Resr 2
PCi = I i = {1, 2, 3} (37)
Nc Ci
where Resr denotes the equivalent series resistance obtained
from datasheet and Nc the number of parallel capacitors are
considered.
5) Auxiliary Losses: Besides the load-dependent losses
shown in the previous sections, a constant loss share for prechar-
ging relay, FPGA control board, sensing and fans of 6 W is con-
sidered. The gate drive losses per switch are approximated by
PGi = Ns Vgs Qg fs (38) Fig. 14. Measured ac√input current i1 and ac input voltage v 1 for an input
current reference Iˆ1∗ = 2 · 8 Arms and an output voltage of 350 V in ac-to-dc
with i = {1a, 1b, 2a, 2b, 3, 4, 5, 6}, Vgs the gate–source voltage, operation for a mains voltage of 230 Vrms .
and Qg the gate charge from the datasheet. Furthermore, losses
caused by an EMI filter are approximated by an equivalent
resistance of 4 mΩ.
6) Cooling System: The number of semiconductors basi-
cally defines the base plate size of the heat sink as 80 × 65 mm
for ac- and dc-side switching devices so that a double-sided
heat sink can be used. Two 40 × 40 mm fans of type San Ace
40 are applied for forced convection cooling. After optimizing
the cooling system as described in [29] considering a minimum
fin thickness of 1 mm and a minimum fin spacing of 2 mm, a
thermal heat sink to ambient resistance of Rth,s−a = 0.32 K/W
results which in turn leads to a cooling system performance
index of 9.86.
B. Experimental Verification
For validating the proposed modulation scheme on the hard-
ware prototype, the control shown in Fig. 8 is implemented in
VHDL on an FPGA device. The optimization of the control Fig. 15. Measured dc √ output current i2 and dc output voltage v C 3 for an input
variables is done offline with the results stored in lookup tables current reference Iˆ1∗ = 2 · 8 Arms and an output voltage of 350 V in ac-to-dc
operation for a mains voltage of 230 Vrms .
on the FPGA. The interlocking for the used switching devices is
set to 500 ns. For each parallel connection of two MOSFETs, a
10-nF ceramic capacitor is placed in parallel in order to limit the ac voltage, all MOSFETs are opened for a short time period
dids /dt, and therefore, the ringing of the drain–source voltage so that i1 starts to ring when the switching operation is started
vds at the end of the resonant transition. Under these circum- again. Oscillations can also be seen in the dc output current i2
stances, a minimum commutation current Is of 5 A per device when it touches the zero line.
is found to be sufficient for achieving ZVS over the whole ac The measurements of voltages and currents at the transformer
mains cycle. are given in Figs. 16 and 17. The transformer leakage inductance
The experiments are conducted by using an ac source capable current iL σ exhibits the typical envelope with twice the ac in-
of delivering 8 Arms at 230 Vrms connected to the input of the put voltage frequency. The transformer voltage vp+ measured
hardware prototype and a 10-kW dc source connected to the from point p+ to the negative ac input rail shows square-wave
output of the hardware prototype to simulate a battery voltage voltages with amplitudes following the ac input voltage. Dur-
of 350 V. Additionally, a resistive load draws 15 A from the dc ing the first half wave of the input voltage, the amplitudes are
source so that power can flow from the ac input of the converter positive, during the second half wave, they are negative. The
to the dc output. transformer voltages vs+ , vs− are measured from points s+, s−
For the measurements, the ac current controller described to the negative dc output rail and show square-wave voltages
earlier is enabled and its reference set to 8 Arms . Fig. 14 shows the with a constant amplitude of the dc output voltage.
measured ac input current i1 together with the ac input voltage Postprocessing of the waveforms i1 , v1 from Fig. 14 leads to
v1 , whereas Fig. 15 depicts the measured dc output current i2 a total harmonic distortion (THD) of 2.89% and a PF of 0.9992
and the dc output voltage vC 3 . During the zero crossing of the at the given operating point. The ac input current harmonics
8396 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 12, DECEMBER 2016

Fig. 18. Experimental ac input current harmonics compared √ to the IEC 61000-
3-2 class A standard for an input current reference Iˆ1∗ = 2 · 8 Arms and an
output voltage of 350 V in ac-to-dc operation for a mains voltage of 230 Vrms .

Fig. 16. Measured transformer leakage inductance current iL σ and trans-

former voltage v p + (transformer connection p+ to negative ac input rail) for at the switching instants in combination with a slow turn-off of
√
an input current reference Iˆ1∗ = 2 · 8 Arms and an output voltage of 350 V in the MOSFET has a substantial impact on the semiconductor
ac-to-dc operation for a mains voltage of 230 Vrms . losses. By using devices with an improved switching behav-
ior, the efficiency of the hardware prototype could be further
increased.
V. CONCLUSION
A combined phase-shift and frequency modulation for a DAB
ac–dc converter with PFC is presented to achieve ZVS over the
whole ac mains voltage period. The modulation is described
by analytical formulas and the control variables for minimum
switch commutation currents are derived by an optimization
procedure. A 3.3-kW electric vehicle battery charger with a
230-Vrms /50-Hz ac mains input for a battery voltage range of
280–420 V is built. The evaluation of the losses predict efficien-
cies of 96% up to 97% for an output power between 50% and
100% and a power density of 2.5 kW/L. The theoretical analysis
of the modulation is validated by measurements, which show a
THD of 2.89% and a PF of 0.9992 at 8 Arms ac input current.
Fig. 17. Measured transformer leakage inductance current iL σ and trans- Furthermore, the harmonic spectrum of the ac input current fully
former voltages v p + , v s + , v s − (transformer connection p+ to negative ac in-
put rail, transformer connections s+, s− to negative dc output rail) for an input complies with the IEC 61000-3-2 class A standard.
√
current reference Iˆ1∗ = 2 · 8 Arms and an output voltage of 350 V in ac-to-dc
operation for a mains voltage of 230 Vrms . ACKNOWLEDGMENT
The authors would like to thank Swisselectric Research and
compared to the IEC 61000-3-2 class A standard are given in the Competence Center Energy and Mobility (CCEM) very
Fig. 18. It can be seen, that the proposed modulation scheme of much for their strong financial support of the research work
the DAB ac–dc converter guarantees full compliance with the and Vacuumschmelze for providing the core material for the
IEC standard. transformer.
The measured efficiency is determined to be 95% for an ac
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