Sifang Csc-211eb V1.06

CSC-211
Multifunction Protection IED

Manual
CSC-211 系列数字式多功能保护装置
说明书
(英文)
编制：
杨帆
校核：
朱胜孟
标准化审查：
审刘晓丰
定：
孙娴
版本号：V1.06
文件代号：
V1.06
出版日期：2020
0000189069 年 10 月
2020年10月
Version：V1.06
Doc. Code：0000189069
Issued Date：2020.10
Copyright owner: Beijing Sifang Automation Co., Ltd
Note: the company keeps the right to perfect the instruction. If equipment
does not agree with the instruction at anywhere, please contact our
company in time. We will provide you with corresponding service.
®
is registered trademark of Beijing Sifang Automation Co., Ltd.
We reserve all rights to this document, even in the event that a patent is issued and a
different commercial proprietary right is registered. Improper use, in particular reproduction
and dissemination to third parties, is not permitted.
This document has been carefully checked. If the user nevertheless detects any errors, he
is asked to notify us as soon as possible.
The data contained in this manual is intended solely for the product description and is not to
be deemed to be a statement of guaranteed properties. In the interests of our customers,
we constantly seek to ensure that our products are developed to the latest technological
standards as a result; it is possible that there may be some differences between the
hardware/software product and this information product.
Manufacturer: Beijing Sifang Automation Co., Ltd.

Email: support@sf-auto.com
Website: http://www.sf-auto.com
Add: No.9, Shangdi 4th Street, Haidian District, Beijing, P.R.C.100085
Preface
Purpose of this manual
This manual describes the functions, operation, installation, and placing
into service of IED CSC-211. In particular, one will find:
 Information on how to configure the IED scope and a description of the
IED functions and setting options;
 Instructions for mounting and commissioning;
 Compilation of the technical specifications;
 A compilation of the most significant data for experienced users in the
Appendix.
Target audience
This manual mainly face to installation engineer, commissioning engineer
and operation engineer with perfessional electric and electrical knowledge,
rich experience in protection function, using protection IED, test IED,
responsible for the installation, commissioning, maintenance and taking
the protection IED in and out of normal service.
Applicability of this manual

This manual is valid for V1.00 CSC-211 multifunction protection IED.
Note: the password for this device is 8888.
Technical support
In case of further questions concerning the CSC-211 multifunction
protection IED, please contact SiFang company or your local SiFang
representative.
Safety information
Strictly follow the company and international safety regulations.

Working in a high voltage environment requires serious approch
to aviod human injuries and damage to equipment.
Do not touch any circuitry during operation. Potentially lethal

voltages and currents are present.
Avoid to touching the circuitry when covers are removed. The IED
contains electirc circuits which can be damaged if exposed to
static electricity. Lethal high voltage circuits are also exposed
when covers are removed.
I
Using the isolated test pins when measuring signals in open
circuitry. Potentially lethal voltages and currents are present.
Never connect or disconnect wire and/or linker to or from IED

during normal operation. Dangerous voltages and currents are
present. Operation may be interrupted and IED and measuring
circuitry may be damaged.
Always connect the IED to protective earth regardless of the

operating conditions. Operating the IED without proper earthing
may damage both IED and measuring circuitry and may cause
injuries in case of an accident.
Do not disconnect the secondary connection of current

transformer without short-circuiting the transformer’s secondary
winding. Operating a current transformer with the secondary
winding open will cause a high voltage that may damage the
transformer and may cause injuries to humans.
Do not remove the screw from a powered IED or from an IED

connected to power circuitry. Potentially lethal voltages and
currents are present.
Using the certified conductive bags to transport PCBs (modules).

Handling modules with a conductive wrist strap connected to
protective earth and on an antistatic surface. Electrostatic
discharge may cause damage to the module due to electronic
circuits are sensitive to this phenomenon.
Do not connect live wires to the IED, internal circuitry may be

damaged.
When replacing modules using a conductive wrist strap

connected to protective earth. Electrostatic discharge may
damage the modules and IED circuitry.
When installing and commissioning, take care to avoid electrical

shock if accessing wiring and connection IEDs.
Changing the setting value group will inevitably change the IEDs
operation. Be careful and check regulations before making the
change.
II
Contents
Chapter 1 Introduction................................................................................................................. 1
1 IED overview ...................................................................................................................... 2
2 IED characteristic ............................................................................................................... 2
3 Basic function..................................................................................................................... 3
3.1 Protection function...................................................................................................... 3
3.2 Monitoring function ..................................................................................................... 4
3.3 Measurement function ................................................................................................ 4
3.4 Control function .......................................................................................................... 5
3.5 Communication mode ................................................................................................ 5
Chapter 2 General functions ....................................................................................................... 7
1 Event record and analysis ................................................................................................. 8
1.1 Overview ........................................................................................................................ 8
1.2 Fault record .................................................................................................................... 8
1.3 Wave form record........................................................................................................... 8
1.4 Sequence of events (SOE) ............................................................................................ 8
1.5 Operation record ............................................................................................................ 9
2 Diagnostic function............................................................................................................. 9
2.1 Overview ........................................................................................................................ 9
2.2 Diagnostic principle ........................................................................................................ 9
3 Time synchronization function ........................................................................................... 9
3.1 Overview ........................................................................................................................ 9
3.2 Synchronization principle ............................................................................................. 10
3.3 IRIG-B code synchronization mode ............................................................................. 10
3.4 PPS synchronization mode .......................................................................................... 10
3.5 SNTP time synchronization mode................................................................................ 11
3.6 1588 synchronization mode ......................................................................................... 11
4 Authorization .................................................................................................................... 11
Chapter 3 Fault phase selection component ............................................................................ 13
1. Overview .......................................................................................................................... 14
2. Function module description ............................................................................................ 14
3. Detailed description ......................................................................................................... 14
3.1 Protection principle....................................................................................................... 14
3.1.1 Steady state component phase selector ........................................................................... 14
3.1.2 Undervoltage phase selection component ........................................................................ 15
3.1.3 Fault location ..................................................................................................................... 16
3.2 Setting list..................................................................................................................... 17
Chapter 4 Overcurrent Protection (50, 51, 67).......................................................................... 19
1 Overview .......................................................................................................................... 20
2 Function module description ............................................................................................ 20
III
3 Detailed description ......................................................................................................... 21
3.1 Protection principle ....................................................................................................... 21
3.1.1 Inrush blocking components .............................................................................................. 21
3.1.2 Compound voltage blocking unit ........................................................................................ 22
3.1.3 Directional component ....................................................................................................... 23
3.1.4 Definite time ....................................................................................................................... 24
3.1.5 Inverse time ....................................................................................................................... 24
3.1.6 Trip characteristic............................................................................................................... 25
3.1.7 Alarm characteristic ........................................................................................................... 26
3.1.8 Logic diagram .................................................................................................................... 26
3.2 Setting list ..................................................................................................................... 27
3.3 Report list ..................................................................................................................... 30
3.4 Technical data .............................................................................................................. 31
Chapter 5 Earth fault protection (50N, 51N, 67N) ..................................................................... 33
1 Overview .......................................................................................................................... 34
3.1.1 Inrush blocking components .............................................................................................. 35
3.1.3 Definite time ....................................................................................................................... 38
3.1.4 Inverse time ....................................................................................................................... 38
3.1.6 Alarm characteristic ........................................................................................................... 40
3.2 Setting list ..................................................................................................................... 41
3.3 Report list ..................................................................................................................... 45
3.4 Technical data .............................................................................................................. 45
Chapter 6 High sensitive earth fault protection (50Ns, 51Ns, 67Ns) ........................................ 47
1 Overview .......................................................................................................................... 48
3.1.2 Definite time ....................................................................................................................... 51
3.1.3 Inverse time ....................................................................................................................... 51
3.1 Setting list ..................................................................................................................... 53
3.2 Report list ..................................................................................................................... 56
3.3 Technical parameter .................................................................................................... 56
Chapter 7 Negative sequence current protection (46) .............................................................. 59
1 Overview .......................................................................................................................... 60
IV
3.1.1 Definite time ...................................................................................................................... 61
3.1.2 Inverse time ....................................................................................................................... 61
3.1.3 Trip characteristic .............................................................................................................. 62
3.2 Setting list..................................................................................................................... 64
3.3 Report list ..................................................................................................................... 65
Chapter 8 Undercurrent protection (37) .................................................................................... 67
1 Overview .......................................................................................................................... 68
3.2 Setting list..................................................................................................................... 69
3.3 Report list ..................................................................................................................... 69
Chapter 9 Overvoltage protection (59) ...................................................................................... 71
1 Overview .......................................................................................................................... 72
3.1.1 Definite time ...................................................................................................................... 73
3.1.2 Inverse time ....................................................................................................................... 73
3.1.4 Logic diagram .................................................................................................................... 74
3.2 Setting list..................................................................................................................... 75
3.3 Report list ..................................................................................................................... 77
Chapter 10 Zero sequence voltage protection (64) .................................................................... 79
1 Overview .......................................................................................................................... 80
3.1.1 Definite time ...................................................................................................................... 81
3.1.2 Inverse time ....................................................................................................................... 81
3.1.4 Fault phase selection ........................................................................................................ 82
3.1.5 Logic diagram .................................................................................................................... 83
3.2 Setting list..................................................................................................................... 83
3.3 Report list ..................................................................................................................... 85
V
Chapter 11 Negative sequence voltage protection (47).............................................................. 87
1 Overview .......................................................................................................................... 88
3.1.1 Definite time ....................................................................................................................... 88
3.1.2 Inverse time ....................................................................................................................... 89
3.2 Setting list ..................................................................................................................... 90
3.3 Report list ..................................................................................................................... 92
Chapter 12 Undervoltage protection (27) .................................................................................... 95
1 Overview .......................................................................................................................... 96
3.1.1 Blocking condition .............................................................................................................. 97
3.1.2 Definite time ....................................................................................................................... 97
3.1.3 Inverse time ....................................................................................................................... 98
3.1.5 Logic diagram .................................................................................................................... 99
3.2 Setting list ................................................................................................................... 100
3.3 Report list ................................................................................................................... 102
3.4 Technical parameter .................................................................................................. 103
Chapter 13 Unbalanced voltage protection (59NU59C) ........................................................... 105
1 Overview ........................................................................................................................ 106
2 Function module description .......................................................................................... 106
3 Detailed description ....................................................................................................... 106
3.1 Protection principle ..................................................................................................... 106
3.2 Setting list ................................................................................................................... 107
3.3 Report list ................................................................................................................... 107
Chapter 14 Unbalance current protection (60N-5051_RLC) ..................................................... 109
1 Overview ........................................................................................................................ 110
3.2 Setting list ................................................................................................................... 111
3.3 Report list ................................................................................................................... 111
VI
Chapter 15 Thermal overload protection (49) ........................................................................... 113
1 Overview ........................................................................................................................ 114
3.1 Protection principle..................................................................................................... 115
3.2 Setting list................................................................................................................... 116
3.3 Report list ................................................................................................................... 116
3.4 Technical data ............................................................................................................ 116
Chapter 16 Power protection (32F) ........................................................................................... 119
1 Overview ........................................................................................................................ 120
3.2 Setting list................................................................................................................... 121
3.3 Report list ................................................................................................................... 122
Chapter 17 Circuit breaker failure protection (50BF) ................................................................ 123
1 Overview ........................................................................................................................ 124
3.1 Protection function ..................................................................................................... 125
3.1.1 Current check .................................................................................................................. 125
3.1.2 Breaker auxiliary contact check ....................................................................................... 126
3.1.3 Circuit breaker failure protection trip logic diagram ......................................................... 127
3.2 Setting list................................................................................................................... 128
3.3 Report list ................................................................................................................... 128
Chapter 18 Dead zone protection (50DZ) ................................................................................. 131
1 Overview ........................................................................................................................ 132
3.2 Setting list................................................................................................................... 136
3.3 Report list ................................................................................................................... 136
Chapter 19 Stub protection (50STUB) ...................................................................................... 137
1 Overview ........................................................................................................................ 138
VII
3.2 Setting list ................................................................................................................... 139
3.3 Report list ................................................................................................................... 140
Chapter 20 Broken conductor protection (46BC) ...................................................................... 141
1 Overview ........................................................................................................................ 142
3.2 Setting list ................................................................................................................... 143
3.3 Report list ................................................................................................................... 144
Chapter 21 Overexcitation protection (24) ................................................................................ 145
1 Overview ........................................................................................................................ 146
3.2 Setting list ................................................................................................................... 149
3.3 Report list ................................................................................................................... 151
Chapter 22 Underfrequency protection (81UF) ......................................................................... 153
1 Overview ........................................................................................................................ 154
3.1.1 Protection function introduction ........................................................................................ 155
3.1.2 Logic diagram .................................................................................................................. 156
3.2 Setting list ................................................................................................................... 156
3.3 Report list ................................................................................................................... 157
Chapter 23 Overfrequency protection (81OF)........................................................................... 159
1 Overview ........................................................................................................................ 160
3.1.2 Logic diagram .................................................................................................................. 161
3.2 Setting list ................................................................................................................... 161
3.3 Report list ................................................................................................................... 162
VIII
Chapter 24 Frequency rate protection (81DF) .......................................................................... 163
1 Overview ........................................................................................................................ 164
3.1.1 Protection function introduction ....................................................................................... 164
3.1.2 Logic diagram .................................................................................................................. 165
3.2 Setting list ............................................................................................................... 166
3.3 Report list ............................................................................................................... 168
3.4 Technical parameter............................................................................................... 168
Chapter 25 Switch-on-to-fault protection .................................................................................. 169
1 Overview ........................................................................................................................ 170
3.1.2 Logic diagram .................................................................................................................. 172
3.2 Setting list................................................................................................................... 172
3.3 Report list ................................................................................................................... 173
Chapter 26 Non-electric protection ........................................................................................... 175
1 Overview ........................................................................................................................ 176
3.2 Setting list................................................................................................................... 177
3.3 Report list ................................................................................................................... 177
Chapter 27 Synchro-check and non-voltage check (25) ........................................................... 179
1 Overview ........................................................................................................................ 180
3.1.2 Synchronization check mode .......................................................................................... 182
3.1.3 Modes of non-voltage check ........................................................................................... 183
3.1.4 Non synchronization mode .............................................................................................. 183
3.1.5 Logic diagram .................................................................................................................. 184
3.2 Setting list................................................................................................................... 184
3.3 Report list ................................................................................................................... 186
IX
3.4 Technical data ............................................................................................................ 187
Chapter 28 Automatic reclosing (79)......................................................................................... 189
1 Overview ........................................................................................................................ 190
3.1.1 Auto-reclosing startup ...................................................................................................... 192
3.1.2 Auto-reclosing logic .......................................................................................................... 192
3.2 Setting list ................................................................................................................... 194
3.3 Report list ................................................................................................................... 195
Chapter 29 Blocking simple busbar differential protection ........................................................ 197
1 Protection principle ........................................................................................................ 198
2 Setting list....................................................................................................................... 198
3 Report list ....................................................................................................................... 199
Chapter 30 Simple busbar differential protection ...................................................................... 201
2 Setting list....................................................................................................................... 202
3 Report list ....................................................................................................................... 203
Chapter 31 Undervoltage load shedding protection.................................................................. 205
1 Overview ........................................................................................................................ 206
3.1.2 Logic diagram .................................................................................................................. 208
3.2 Setting list ................................................................................................................... 208
3.3 Report list ................................................................................................................... 209
Chapter 32 Overload load shedding protection ........................................................................ 211
1 Overview ........................................................................................................................ 212
3.1.2 Logic diagram .................................................................................................................. 213
3.2 Setting list ................................................................................................................... 214
3.3 Report list ................................................................................................................... 214
Chapter 33 Cooling load startup protection............................................................................... 215
X
2 Setting list ...................................................................................................................... 217
3 Report list ....................................................................................................................... 218
Chapter 34 Temperature protection .......................................................................................... 219
1 Overview ........................................................................................................................ 220
3 Setting list ...................................................................................................................... 221
4 Report list ....................................................................................................................... 222
Chapter 35 Frequency auto-reclosing protection ...................................................................... 223
1. Overview ........................................................................................................................ 224
2. Function module description .......................................................................................... 224
3. Detailed description ....................................................................................................... 225
3.1 Protection principle ................................................................................................. 225
3.2 Setting list ............................................................................................................... 225
3.3 Report list ............................................................................................................... 226
3.4 Technical parameter............................................................................................... 227
Chapter 36 Secondary circuit monitoring .................................................................................. 229
1 CT failure ....................................................................................................................... 230
1.1 Overview .................................................................................................................... 230
1.2 Function module description ...................................................................................... 230
1.3 Detailed description.................................................................................................... 230
1.3.1 Protection principle .......................................................................................................... 230
1.3.2 Setting list ........................................................................................................................ 231
1.3.3 Report list ........................................................................................................................ 231
2 VT failure ........................................................................................................................ 231
2.1 Overview .................................................................................................................... 231
2.2 Function module description ...................................................................................... 231
2.3 Detailed description.................................................................................................... 232
2.3.1 Protection principle .......................................................................................................... 232
2.3.2 Setting list ........................................................................................................................ 235
2.3.3 Report list ........................................................................................................................ 235
2.3.4 Technical parameter........................................................................................................ 236
Chapter 37 User-defined function ............................................................................................. 237
1 Overview ........................................................................................................................ 238
2 User-defined configuration ............................................................................................. 238
2.1 Open project............................................................................................................... 238
2.2 Binary input configuration .......................................................................................... 238
2.3 Binary output configuration ........................................................................................ 239
2.4 LED configuration....................................................................................................... 241
2.5 IO-Matrix configuration ............................................................................................... 241
XI
2.5.1 IO-Matrix channel configuration ....................................................................................... 241
2.5.2 IO-Matrix function configuration ....................................................................................... 242
2.6 Binary input switch setting group ............................................................................... 242
2.6.1 Function description ......................................................................................................... 242
2.6.2 Setting list ........................................................................................................................ 243
2.7 Configuration startup .................................................................................................. 243
2.8 Other configuration ..................................................................................................... 244
2.9 Defined logic............................................................................................................... 245
2.10 Connector attribute change ........................................................................................ 245
Chapter 38 Control function ...................................................................................................... 247
1 CB/Isolator control ......................................................................................................... 248
1.1 Introduction ............................................................................................................. 248
1.2 Function module description .................................................................................. 248
1.3 Detailed description ................................................................................................ 248
2 Direct control .................................................................................................................. 249
2.1 Introduction ............................................................................................................. 249
2.2 Function module description .................................................................................. 249
3 Tap control ..................................................................................................................... 249
3.1 Overview................................................................................................................. 249
3.2 Description of function module ............................................................................... 249
4 Report list ....................................................................................................................... 250
Chapter 39 Substation communication ..................................................................................... 251
1 Overview ........................................................................................................................ 252
1.1 Communication protocol ............................................................................................ 252
1.1.1 IEC61850-8 communication protocol ............................................................................... 252
1.1.2 IEC60870-5-103 communication protocol ........................................................................ 252
1.2 Communication port ................................................................................................... 252
1.2.1 Front plate communication port........................................................................................ 252
1.2.2 RS485 communication port .............................................................................................. 252
1.2.3 Time synchronization port ................................................................................................ 252
1.2.4 Ethernet communication port ........................................................................................... 252
1.3 Technical data ............................................................................................................ 253
1.4 Typical substation communication mode ................................................................... 254
1.5 Typical clock synchronization mode .......................................................................... 254
Chapter 40 Man-machine interface (MMI) and operation ......................................................... 255
1 Overview ........................................................................................................................ 256
2 Function description ....................................................................................................... 256
2.1 Liquid crystal display (LCD).................................................................................... 256
2.2 Man-machine interface (MMI) ................................................................................ 256
XII
2.3 Menu structure ....................................................................................................... 258
Chapter 41 IED hardware ......................................................................................................... 265
1 Overview ........................................................................................................................ 266
1.1 IED structure .............................................................................................................. 266
1.2 Module arrangement diagram .................................................................................... 267
2 Analog input module ...................................................................................................... 267
2.1 Overview .................................................................................................................... 267
2.2 Analog input module introduction............................................................................... 267
2.3 Technical data ............................................................................................................ 268
3 BIO module .................................................................................................................... 269
3.1 Overview .................................................................................................................... 269
3.2 BIO module introduction ............................................................................................ 269
3.3 Technical data ............................................................................................................ 271
4 CPU module................................................................................................................... 271
4.1 Overview .................................................................................................................... 271
4.2 CPU module introduction ........................................................................................... 272
4.3 Technical data ............................................................................................................ 273
5 Power supply module..................................................................................................... 274
5.1 Overview .................................................................................................................... 274
5.2 Power module introduction ........................................................................................ 274
5.3 Technical data ............................................................................................................ 276
6 TCS Module ................................................................................................................... 276
6.1 Overview .................................................................................................................... 276
6.2 TCS Module instructions ............................................................................................ 276
6.2.1 TCS trip monitoring circuit ............................................................................................... 278
6.2.2 Binary output circuit with large capacity .......................................................................... 279
6.2.3 Ordinary BO circuit .......................................................................................................... 279
6.3 Technical data ............................................................................................................ 280
7 Test ................................................................................................................................ 281
8 Structural design ............................................................................................................ 283
9 CE Certification .............................................................................................................. 283
10 Permissible environmental conditions ........................................................................... 283
Chapter 42 Appendix ................................................................................................................ 285
1 Setting list ...................................................................................................................... 286
2 Report list ....................................................................................................................... 286
2.1 Alarm report ............................................................................................................... 286
2.2 Operation report ......................................................................................................... 288
3 Typical wiring ................................................................................................................. 289
3.1 As to incoming and outlet line feeder protection and line backup protection............. 289
3.2 As for transformer backup protection IED .................................................................. 294
XIII
3.3 As for synchronization function .................................................................................. 296
3.4 As for capacitor protection ......................................................................................... 298
4 Inverse time characteristic ............................................................................................. 301
4.1 Twelve types of IEC and ANSI time inverse property curve ...................................... 301
4.2 User definable properties ........................................................................................... 301
5 CPU module upgrading introduction .............................................................................. 302
6 Connector list ................................................................................................................. 303
7 Explanation of abbreviations .......................................................................................... 304
7.1 Explanation of setting abbreviations .......................................................................... 304
7.2 Explanation of logic switch abbreviations .................................................................. 316
7.3 Explanation of trip report and alarm report ................................................................ 321
7.4 Explanation of operation report abbreviations ........................................................... 325
7.5 Explanation of device menu abbreviations ................................................................ 326
7.6 Explanation of Connector list ..................................................................................... 328
XIV
Chapter 1 Introduction
About this chapter

This chapter gives an overview of SIFANG Digital
multifunction protection IED.
1
1 IED overview
CSC-211 digital multifunction protection IED is used for factory power
system of 110kV or below power grid and power plant. It has perfect
protection, measurement, control and monitoring function. It provides an
integrated scheme for feeder, capacitor, circuit breaker, etc., at the same
time, it can be used as a backup protection device for a circuit and a
transformer.
Table 1 CSC-211 Application Description
Type Sub-type Description

Main and backup protection in one device, protection
measurement and control solution for feeder and
CSC-211 CSC-211-EB capacitor;
Main and backup protection are independent, backup
protection device for a circuit and a transformer solutions.
This series of IEDs use the new design concept, all the IEDs are
established in a general hardware and software platform. All functions are
modulized designed and at the same time diagnosis and debugging tools
are also provided. According to the actual needs of the field, through the
visual chart logic, users can customize all kinds of protection and control
logic. The equipment is highly reliable, flexible and maintainable and can
be adapted to the different site conditions.
CSC-211 digital multifunction protection IED has leading multiple features,
integrated protection, measurement and control, it supports the IEC61850
standard communication and achieves the interface with substation
automation system and protection information management system; it
provides the device description file(ICD file) that meets the requirements of
IEC61850 to support network services that IEC61850 defines. Fully
support the GOOSE function, and it can meet the needs of transformer
substation with various configuration. It can be installed in the panel at site.
2 IED characteristic
CSC-211 IED contains selectivity, reliability and speed, and the application
range is as bellow:
1) Integrated protection function and monitor and control function;
2) Meeting demands for three-phase tripping in transmission and
distribution grid;
3) Circuit breaker position status monitoring;
4) The device is equipped with module self-diagnosis function;
5) The device can provide complete report records, including operation
report, alarm report and tripping report. Up to 2000 reports can be
stored, and the reports can be saved, even there is a power outage;
6) It provides two electric/optical Ethernet ports, and communicates with
substation automation system by choosing protocol IEC 61850 or IEC
60870-5-103 (TCP103);
7) RS485 port are provided for communication with substation
automation system through IEC60870-5-103 protocol;
8) It supports PRP protocol based on IEC 62439-3, the device can be set
2
to PRP mode, and the dual network ports adopt redundant mode to
send and receive information in parallel;
9) Simple network time protocol (SNTP), pulse, IRIG-B or 1588
synchronizing modes can be selected to synchronize time;
10) A friendly MMI;
11) Can be centrally installed in the panel or be installed on the switch
panel indoors or outdoors.
3 Basic function
3.1 Protection function
Used in low voltage feeder, capacitor, transformer backup protection, etc.
Table 2 Typical configuration 1
IEC61850
Description ANSI code Logic node
name
Overcurrent protection (with inrush current,
50,51,67
direction, voltage)
Earth fault protection (with inrush current,
50N,51N,67N
direction)
High sensitive earth fault protection (with
50Ns,51Ns,67Ns
direction)
Negative sequence current protection 46 PPBR
Undercurrent protection 37 PUCP
Overvoltage protection 59 PTOV
Zero sequence voltage protection 64 PTOV
Negative sequence voltage protection 47 PPBV
Undervoltage protection 27 PTUV
Voltage unbalance protection 59NU59C
Current unbalance protection
Thermal overload protection 49 PTTR
Power protection 32F
CBF protection 50BF RBRF
Dead zone protection 50DZ
Stub protection 50STUB
Disconnection protection 46BC
Overexcitation protection 24
Underfrequency protection 81UF
Overfrequency protection 81OF
Frequency changing rate protection 81DF
3
IEC61850
Description ANSI code Logic node
name
Switch-onto-fault protection SOTF
Overload load shedding
Undervoltage load shedding
Non-electric protection 32
Synchro-check and non-voltage check 25 RSYN
Auto-reclosing 79 RREC
Simple busbar protection
Blocking simple busbar protection
Cooling load startup protection
CT failure
VT failure 97FF
3.2 Monitoring function

Table 3 Monitoring function
Description
Position of circuit breaker, disconnector and other switching devices monitoring
Position of circuit breaker monitoring
Auxiliary contacts of circuit breaker monitoring
Self-diagnosis function
Disturbance and fault record
3.3 Measurement function

Measurement is sampled through the dedicated measurement channels.
Table 4 Measurement function
Description
Current: Ia, Ib, Ic
Voltage: Ua, Ub, Uc, Uab, Ubc, Uca
Active power: P, Pa, Pb, Pc
Reactive power: Q, Qa, Qb, Qc
Power factor: COSφ
Frequency: F
4
3.4 Control function

Table 5 Control function
Description
Circuit breaker, disconnector and other switching devices control
3.5 Communication mode

Table 6 Communication mode
Communication port on the front plate
RJ45 Ethernet communication port

Communication port on the rear plate
Isolated RS485 communication port

Ethernet electrical/optical communication ports
Time synchronization port
Communication protocol
IEC61850 Protocol
IEC60870-5-103 Protocol
DNP3.0 (supported by Master above 4.0)
MODBUS (supported by Master above 4.0)
5
Chapter 2 General functions
About this chapter

The chapter describes the general IED functions
7
1 Event record and analysis

1.1 Overview
To get fast, complete and reliable information about fault current, voltage,
binary signal and other disturbances in the power system is very important.
Through record function of fault data, operators can make better analysis
about the related primary and secondary devices during and after the fault.
Operational personnel can acquire valuable information to explain the
cause of the fault and modify the IED configuration in accordance with the
conclusion to improve IED reliability.
Disturbance data includes devices samples and calculated analogs, BI
and BO signals.
1.2 Fault record

IED can save the latest 2000 fault records (which will not loss during power
failures). The records can be viewed through operation interface of device,
communication port or debugging software. The types of reports recorded
in failure records include startup report, trip report, alarm report, operation
report and BI change position report.
Main information of fault records includes:
1) Fault time: Date and time;
2) Time list: Trip component and time;
3) Operation data: Current, voltage, frequency and phase.
1.3 Wave form record

Recording function is used to capture the sampling data, analog data and
state data of predefined length before and after an event (analog data is
only applicable for the intermediate node, mid file), and replay the
protected equipment running track before and after the event. Any logic
component and BIO of the device can be used to trigger recording
function.
Recording contains analog channel, digital channel (BI, BO and protection
component states) as well as time standard sequence information.
IED makes data record according to each cycle. Each record can reach up
to 20s, and the latest 8 times of protection trips and 8 times startups, 16
records can be saved totally.
Waveform record file can be exported through the Ethernet debugging port
by using the debugging tool software (COMTRADE type), it can also be
uploaded to engineer station through the substation communication
network and used to analyze IED trip.
1.4 Sequence of events (SOE)

IED monitors and records a total of 2000 state change events of the
position change of binary input and output, state change of wave recording
and connector enable/disable tripping in real time; it also records event
time scale, reason and present state. These real-time data are transferred
to the station control center through communication port. Users can view
the protection SOE report through the local MMI or debugging software.
8
1.5 Operation record

IED records the latest 2000 important modification of operating parameters
and the operation object, operation time, data modifications or operational
reasons will be recorded, which can provide bases for accident tracing.
Operation information is saved in operation record of the IED. Users can
view the report information through the local MMI or debugging software.
2 Diagnostic function
2.1 Overview
The device realizes the hardware and software self-checking and
monitoring of the device by means of energizing self-diagnosis and
operation self-monitoring to ensure the high reliability of the operation of
the device. Self checking objects include key components of hardware
(such as analog sampling circuit, BIO output circuit, RAM and ROM) and
hardware accessories (such as backup battery, communication interface)
and important running parameters (such as settings, soft connectors), in
addition, the embedded two level software monitor can be used to monitor
the operation conditions of the software. When the device detects any
abnormal conditions, the device will record the abnormal events and drive
signal node and LED lights. For the key abnormal conditions, the device
will block the protection function and the important output circuit to prevent
the device from malfunctions.
The user can also check the important hardware circuit of the device
through the test command provided by the device, such as the AC circuit,
BI circuit and BO circuit, etc.
In order to cooperate with automation system engineering implementation,
the device provides remote point test function, so the local SCADA and
remote master database can be checked, so the complicated manual point
check operation between the SCADA operator and remote operator is
avoided. Mainly includes the telesignalisation point check, telemetry point
checkand so on.
2.2 Diagnostic principle

1) Measurement device power;
2) Check zero drift and zero drift out-of-limits;
3) Confirm alarm circuit;
4) Check setting and parameter.
3 Time synchronization function

3.1 Overview
The IED, as a part of the protection system, can be time synchronized by
time synchronization source. In the security automation intelligent system,
through the time synchronization, IED and other devices in the system
have the same clock source. When the system fault or abnormal, there is a
unified clock reference between the various devices.
9
3.2 Synchronization principle

Definition of time
The error of a clock is the difference between the actual time and the
synchronized clock. The rate accuracy of a clock is normally called the
clock accuracy. When the clock deviation is too large, the clock will
re-synchronize to ensure clock accuracy is within the set range.
Synchronization principle
Generally speaking, synchronization can be seen as a hierarchical
structure. A module is synchronized from a higher level and provides
synchronization to lower levels.
Figure 1 Synchronization principle diagram

A module of the system is synchronized when it receives synchronization
signal from a higher level and this module is time synchronization module.
The less the clock synchronization level, the higher the final time
synchronization accuracy is. The same module may have several options
of time synchronization sources with different errors, this module can
choose the best time source and adjust the internal clock, according to the
time synchronization source. The maximum error of a clock can be defined
as:
1) The maximum error of the last synchronization information;
2) The calculated time from last time synchronization information;
3) The rate accuracy of the internal clock in the module.
Time synchronization system provides three synchronization methods:
IRIG-B code, IEEE1588 and net synchronization and second pulse
synchronization.
3.3 IRIG-B code synchronization mode

The CPU module of the device supports IRIG-B (DC) time synchronization
at RS485 voltage level.
3.4 PPS synchronization mode

The CPU module supports PPS signal at RS485 voltage level. If the
substation time is not synchronized with the standard time, the present
time of the substation will be regarded as valid time and the IED time is
synchronized with it. After receiving the pulse signal, the CPU can
10
automatically adapt to the positive and negative pulses.
3.5 SNTP time synchronization mode

SNTP time synchronization adopts question and answer type. A time
synchronization message is sent from IED to SNTP-server, SNTP server
deals with the transmission delay, and then returns the time information to
the device. SNTP time synchronization mode is performed through
Ethernet. In order to ensure SNTP time synchronization is normal, one
SNTP server must be set, it is suggested that one server can be set at one
substation. The accuracy of binary input in SNTP synchronization mode is
1ms. The IED itself can be set as a SNTP time synchronization server.
3.6 1588 synchronization mode

It supports IEEE1588 high precision network synchronization.
4 Authorization
To safeguard the interests of customers, accesses to the IED and the
debugging software are restricted in terms of authorization. In practice,
attention should be paid to the following aspects in the use of the IED and
associated debugging software:
1) There are two types of access to the IED:
a) Local: debugging through the local MMI;
b) Remote: debugging through the communication ports.
2) Different users have different authority to access to or operate device
or debug the software.
11
Chapter 3 Fault phase selection component
Chapter 3 Fault phase selection

component
About this chapter

This chapter describes the basic protection element, fault
phase selection component.
13
1. Overview
The fault phase selector component can distinguish the fault phase, and
make use of various phase selection principles to judge the different fault
conditions, so as to meet the requirements of trip phase selection.
The fault uses steady-status sequence component to judge the phase, for
power supply, terminal fault small current or no current, the low voltage
phase selector is used to judge the phase.
Phase selection function can be blocked by external binary input, VT
failure and CT failure.
2. Function module description

The I/O signals described herein only reflect the visible engineering part.
The input and output signals of fault phase selection module function are
shown as follows:
Faulty Phase Selection

1 1
BIBlk FaultPhase
2 2
VTFailBlk FaultA
3 3
CTFailBlk FaultB
4
FaultC
Figure 2 Input and output signal diagram of fault phase selector component function
Table 7 Parameter description
Number Key Unit Type Description

Input:
1. BIBlk BOOL BI blocking BO
2. VTFailBlk BOOL VT failure blocking signs
3. CTFailBlk BOOL CT failure blocking sign
Output:
1. FaultPhase SINT Fault phase
2. FaultA BOOL Phase A fault
3. FaultB BOOL Fault of phase B
4. FaultC BOOL Phase C fault
3. Detailed description
3.1 Protection principle
3.1.1 Steady state component phase selector
The steady status component phase selector selects the phase through
the angle between zero sequence current component and negative
sequence current components, and the phase impedance is used to
14
confirm whether the phase selection is correct.

The analysis shows that the angle between the zero sequence current
component and negative sequence current component of the fault current
can be used to select the fault phase, the analysis is shown in the following
figure:
I0a
0 0
+30 AN,BCN -30
ABN BCN
0 0
+90 -90
CN,ABN BN,CAN
0 0
+150 CAN -150
Figure 3 Relationship diagram between zero sequence current component and

negative sequence current component angle of various faults
Table 8 Steady status component phase selector table
Phase area Angle range Phase selection results

1 +30°~-30° AN or BCN
2 +90°~+30° ABN
3 +150°~+90° CN or ABN
4 -150°~+150° CAN
5 -90°~-150° BN or CAN
6 -30°~-90° BCN
For example, the angle between the negative sequence component and
the zero sequence components is between -30 degrees and +30 degrees,
and the fault type is phase A grounding or fault between phase B and C or
grounding fault between phase B and C.
As shown in the table above, area 2, 4, and 6 directly reflect the relative
fault type, but area 1, 3, and 5 may reflect the existence of two types of
fault, at this point, it is distinguished through phase impedance calculation.
If the phase impedance is larger than that of the phase impedance setting
value, the possibility of phase fault is eliminated, and it is judged to the
corresponding single-phase grounding fault, or it is judged to the
corresponding phase fault.
3.1.2 Undervoltage phase selection component
The steady status component phase selector is not reliable in the weak
feedback system, and the low voltage phase selector is applied to the
weak feedback system.
Discriminant formula for single phase fault and interphase fault is as
follows:
15
Upe<k×Upe_Secondary
or
Upp <k×Upp_Secondary
Where:
1) Upe and Upp are phase-to-earth voltage and phase-to-phase voltage
respectively
2) U_Secondary is system secondary rated voltage value
3) k is internal coefficient
For example, if only A phase voltage is low, it is judged to be A phase fault;
if only the AB phase voltage is low, it is judged to be AB phase fault; if AB,
BC and CA phase voltage are all low, then it is judged to be three-phase
fault.
3.1.3 Fault location
Position location only supports metal fault location.
A separate measuring system has been provided for each of the six possible
impedance loops A-E, B-E, C-E, A-B, B-C, C-A. The impedance calculation
will be continued whether a fault has been detected.
Based on the following differential equations, measuring elements
calculates relevant loop impedances with real-time voltages and currents.
Measuring of the single phase impedance for a single phase fault is as
follows:
d(I∅ + K x × 3I0 )
U∅ = L∅ × + R ∅ × (I∅ + K r × 3I0 )
dt
∅：A, B, C
Measuring of the phase-phase impedance for multi-phase faults is as
follows:
dI∅∅
U∅∅ = L∅∅ × + R ∅∅ × I∅∅
dt
∅∅：AB, BC, CA
Where, K x and K r are residual compensation factors. Matching of the
earth to line impedance is an essential prerequisite for the accurate
measurement of the fault impedance (impedance protection, fault locater)
during earth faults. This compensation will be done by residual
compensation settings value:
X 0 − X1
Kx =
3X1
R 0 − R1
Kr =
3R1
Measuring resistance R and reactance X (ωL=2πfL) at IED location can be
obtained by solving above differential equations.
For example, solving above equations leads to the following relation for
phase-phase (A-B) short circuit which can be used to calculate the
phase-to-phase loop impedance.
16
Figure 4 Phase-to-phase (A-B) short circuit

𝐼𝐼𝐿1 × 𝑍𝑍𝐿 − 𝐼𝐼𝐿2 × 𝑍𝑍𝐿 = 𝑈𝑈𝐿1𝐸 -𝑈𝑈𝐿2𝐸
Where:
U, I: measuring voltage and measuring current
Z=R+jX: measured impedance
Line impedance can be calculated as follow:
𝑈𝑈𝐿1𝐸 − 𝑈𝑈𝐿2𝐸
𝑍𝑍𝐿 =
𝐼𝐼𝐿1 − 𝐼𝐼𝐿2
In addition, solving differential equation for single-phase (e.g. A-E) results:
Figure 5 Single phase earth (A-E) short circuit

𝑅𝑅𝐸 𝑋𝑋𝐸
𝑈𝑈𝐿1𝐸 = 𝐼𝐼𝐴 × (𝑅𝑅𝐿 + 𝑗𝑗𝑋𝑋𝐿 ) − 𝐼𝐼𝐸 × � 𝑅𝑅𝐿 + 𝑗𝑗 𝑋𝑋𝐿 �
𝑅𝑅𝐿 𝑋𝑋𝐿
= 𝐼𝐼𝐴 × (𝑅𝑅𝐿 + 𝑗𝑗𝑋𝑋𝐿 ) − 𝐼𝐼𝐸 × (Kr 𝑅𝑅𝐿 + 𝑗𝑗Kx 𝑋𝑋𝐿 )
This can be used for resistance and reactance calculation by separating it
to real and imaginary parts.
The impedances of the unfaulted phases are also influenced by the
short-circuit currents and voltages in the short-circuited phases. For
example, during an A-E fault, phase-to-phase impedance calculation of.A-B
and C-A is affected by I1 and the phase-to-earth impedance calculation of
phase B and C is affected by IE. In addition to the load currents which may
flow, the unfaulted phases will be affected by faulted loop current which
have nothing to do with the actual fault distance/ impedance.
Effect in the unfaulted loops is usually greater than the short-circuit
impedance of the faulted phases, because the unfaulted loop only carries
a part of the fault current and always has a larger voltage than the faulted
loop. As mentioned earlier, all impedance calculations start independently
when the impedance calculation is triggered by any of the starting
components. First, the symmetric component phase selector chooses the
fault phase, and then the IED compare the impedance of these phases to
remove the unfaulted phases.
3.2 Setting list
17
Table 9 Fault location setting

Default
NO. Setting name Range Step Unit Remark
value
Positive
1. WholeLinePositiveSeqX 0.05/In~600/In 120 0.01 Ω sequence
reactance in
Positive
2. WholeLinePositiveSeqR 0.05/In~600/In 120 0.01 Ω sequence
resistance in
3. LineLengthSet 0.1~999 999 0.01 km Line length
4. ZeroSeqXCompCoef -0.33~10 8 0.001
5. ZeroSeqRCompCoef -0.33~10 8 0.001
18
Chapter 4 Overcurrent protection (50, 51, 67)
Chapter 4 Overcurrent Protection

(50, 51, 67)
About this chapter

This chapter describes the overcurrent principle, the input
and output signals, setting value parameters, messages and
technical parameters.
19
1 Overview
When the power system fault occurs, the current of the system increases,
and the overcurrent protection can avoid the damage of the fault current to
the equipment. The device provides four-stage of overcurrent protection;
each stage provides options of overcurrent definite-time protection or
inverse time protection. Each stage of overcurrent protection has the same
logic criterion, and each stage can be enabled or disabled independently.
Each stage of the overcurrent protection can be selectively input harmonic
blocking element and directional element, and based on the phase
measurement of the current action. In addition, each stage of the
overcurrent definite-time protection can be selectively input the complex
pressure locking element.
Main characteristics of overcurrent protection:
1) The device provides four stages of overcurrent protection, each stage
adopts definite time-lag or 12 IEC and ANSI standard curve of inverse
time characteristic, and it adopts user-defined characteristic curve as
well;
2) The flow direction sensitive angle can be adjusted to meet different
application occasions;
3) Each section of the overcurrent protection can be respectively set
whether it inputs direction element, whether the action area is
"forward" or "reverse" action is set by the logic switch;
whether it’s through harmonic locking;
5) Harmonic blocking can lock across;
whether it’s through re-pressing locking;
7) The protection of the input direction component needs to detect
whether the VT secondary circuit disconnects. If VT is disconnected,
the protection of the input direction component can be set as VT
disconnection protection or VT disconnection protection blocking.
8) The protective function can be disabled through the function connector.
The connector properties can be configured as soft connector, hard
connector, soft-hard series, soft-hard parallel, and the default is
soft-hard parallel.
9) Overcurrent support of stage 4 can adopt root mean source calculated
current or fundamental current, and root mean source method does
not support blocking condition.
2 Function module description

The input and output signals of overcurrent protection function diagram are
shown below:
20
Directional / Non-directional Overcurrent Protection

1 1
BIBlk Start
2 2
ENA_OC Operation
3
Alarm
4
PhaseA 5
PhaseB 6
PhaseC
Figure 6 Diagram of input and output signals of overcurrent protection function

The left side is the input and the right is the output, parameter description
is shown in the following table.
Function Identifier Description

Input:
BIBlk BIBlk
Output:
Start IED startup
OC Alarm Protection alarm (only for the configuration of alarm stage)
Operation IED trip
PhaseA Phase A trip
PhaseB Phase B trip
PhaseC Phase C trip
Input:
ENA
The total connector of overcurrent protection，the corresponding
ENA_OC
hard connector is ENA_OC_5.
3 Detailed description
IED is equipped with four-stage overcurrent protection. Please refer to the
setting list for details. The overvoltage protection stage 1 will be taken as
an example below and the principle will be introduced.

3.1.1 Inrush blocking components
When "OC1BlkBy2ndH"=1, inrush check, the inrush criterion is shown as
below:
I∅2
> “OC2ndHI2/I1Ratio”, (∅ = 𝑎𝑎, 𝑏𝑏, 𝑐𝑐)
I∅
When it is detected that the ratio of second harmonic and fundamental
wave is larger than "OC2ndHI2/I1Ratio" and there is a current, then the
inrush condition is satisfied in the phase.
21
When inrush condition is detected, within the "HarmCrossBlkTime", one

phase inrush protection fails and three phase protection; after the
"HarmCrossBlkTime", one phase inrush protection fails and one phase
protection; when the inrush criterion returns, release each blocking.
When the maximum fundamental wave current of the three phases is
larger than "HarmUnblkOCCurr", release each blocking.
The output blocking state of each phase is caused by inrush blocking of
overcurrent stage 1 phase A, phase B and phase C. Schematic diagram is
shown below:
Phase A ratio of I2 to I1 >“OC2ndHI2/I1Ratio”
≥1
&
Phase B ratio of I2 to I1>“OC2ndHI2/I1Ratio”
Three-phase inrush blocking
Phase C ratio of I2 to I1>“OC2ndHI2/I1Ratio”
Time<“HarmCrossBlkTime”
Three-phase inrush blocking &

Overcurrent stage 1 three-phase inrush blocking
“OC1BlkBy2ndH”=1
“OCStage1RMSOn”=0
Phase A ratio of I2 to I1>“OC2ndHI2/I1Ratio” &

&
Overcurrent stage 1
Time>“HarmCrossBlkTime” phase A inrush blocking
Phase B ratio of I2 to I1>“OC2ndHI2/I1Ratio” &
Time>“HarmCrossBlkTime” &
Overcurrent stage 1
phase B inrush blocking
Phase C ratio of I2 to I1>“OC2ndHI2/I1Ratio” &

&
Overcurrent stage 1
Time>“HarmCrossBlkTime” phase C inrush blocking
Figure 7 Inrush blocking logic diagram
3.1.2 Compound voltage blocking unit

When “OCStage1BlkByVolt” =1, check the voltage. The voltage blocking
element is compound voltage element, including low voltage and negative
sequence voltage components, composite voltage criterion:
min(Uab, Ubc, Uca) < “PPVoltBlkSet”or U2 > “U2BlkSet”
When the "3PhVoltConnect" =1, the low voltage or negative sequence
voltage is detected; when the "3PhVoltConnect"=0, the negative sequence
22
voltage component exits.

&
min(Uab,Ubc,Uca)<“PPVoltBlkSet”
“3PhVoltConnect”=1
& ≥1
Multi-voltage component satisfied
Negative sequence voltage>“U2BlkSet”
“3PhVoltConnect”=0 &
max(Uab,Ubc,Uca)<“PPVoltBlkSet”
Multi-voltage component satisfied &

≥1
Overcurrent stage 1 multi-voltage
“OCStage1BlkByVolt”=1 component satisfied
“OCStage1BlkByVolt”=0
Figure 8 Logic diagram of the characteristics of multi-voltage element
3.1.3 Directional component

When "DirOCStage1"=1, direction check. Directional elements are
connected with a 90° angle, the fault phase direction is determined by the
fault phase current and the line voltage of the sound phase.
Table 11 The judgment of the fault phase direction
Phase Current Voltage

A Ia U bc
B Ib U ca
C Ic U ab
When the three-phase fault occurs, there is no sound phase voltage, which
is not enough to judge the fault current direction, so memory voltage is
adopted. Diagram forward and reverse direction characteristics of phase A
current:
FWD 90° IA 90° IA
Bisector Bisector
RVD
Φ Φ
0° 0°
U BC_Ref U BC_Ref
5°
-IA -IA 5°
23
Figure 9 Forward and reverse direction interval graph

Overcurrent direction sensitive angle Φ =Angle: Adjustable.
Positive direction overcurrent range: (-85°~ +85°), reverse direction
overcurrent range: (+95°~ +265°).
Direction discrimination logic diagram is shown below:
Phaseφ directional
component satisfied &
≥1
Overcurrent stage 1 directional
“DirOCStage1”=1 component satisfied
“DirOCStage1”=0
Φ=a,b,c
Figure 10 Logic diagram of direction discrimination

In the process of direction discrimination and voltage discrimination, the
VT disconnection may lead actions or alarms that are not consistent with
the flow direction discrimination or the voltage discrimination along
overcurrent protection stages. When VT fails, the action mode is decided
according to "VTFailProtOff"; if “VTFailProtOff” is set to 1, overcurrent
protection with voltage or directional element is blocked; if “VTFailProtOff”
is set to 0, voltage blocking element and directional element exit and act in
a pure overcurrent mode.
When the three-phase voltage connection is set 0, the direction is satisfied
automatically.
3.1.4 Definite time
When "OCStage1Curve"=0, overvoltage is the definite time characteristic,
inverse time function is disabled.
I∅ > “OCStage1CurrSet”, (∅ = 𝑎𝑎, 𝑏𝑏, 𝑐𝑐)
When the phase-to-earth current is greater than "OCStage1CurrSet", timing
component starts, overcurrent protection trips when "OCSatge1Time";
when the phase-to-earth current I∅ < Dropout × “OCStage1CurrSet” ,
Dropout is dropoff coefficient, timing component and overcurrent
protection return.
3.1.5 Inverse time
When "OCStage1Curve"=1~13, overvoltage is the definite time
characteristic, inverse time function is disabled.
 
 
A
=t  + B  ⋅T
  IΦ  P 
  − 1 
  Iset  
Where:
A: "InvTimeOCStage1CoefA"
P: "InvTimeOCStage1IndexP"
B: "InvTimeOCStage1TimeB"
24
T: "InvTimeOCStage1ConstT"
Iφ: Phase current value in the system
Iset: "OCStage1CurrSet"
If the phase-to-earth current exceeds "OCStage1CurrSet", the timing
element starts, inverse time characteristic curve is selected by curve. A, P,
B are determined when the value is from 1 to 12, see the curve definition
table. When the value is 13, it is user-defined, calculate tripping delay
according to the setting of A, P, B, T, when the time is up, overcurrent
protection trips. When the delay is less than the "InvTimeOCMinTime", the
component trips according to the "InvTimeOCMinTime"
Table 12 Curve definition
Curve Inverse time characteristic A P B
0 Definite time
1 IEC INV. 0.14 0.02 0

2 IEC VERY INV. 13.5 1.0 0
3 IEC EXTERMELY INV. 80.0 2.0 0
4 IEC SHORT TIME INV. 0.05 0.04 0
5 IEC LONG TIME INV. 120.0 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
9 ANSI MODERATELY INV. 0.0103 0.02 0.0228
10 ANSI VERY INV. 3.922 2.0 0.0982
11 ANSI EXTERMELY INV. 5.64 2.0 0.02434
12 ANSI DEFINITE INV. 0.4797 1.5625 0.21359
13 USER DEFINE
3.1.6 Trip characteristic

When overcurrent protection function is enabled (En=1) and no BI blocking,
if the "OCStage1On"=1, the overcurrent protection of the corresponding
stage is enabled.
If the action conditions are met, time component starts; take stage 1
protection for example, when time is over, "OCStage1Trip" is issued. While
IED trips, each phase trip state will be displayed at the same time. LED
and protection trip can be configured by AESP.
When "OC1BlkBy2ndH"=1, the harmonic locking component is put into
operation, when the action timer is time out, the inrush current is checked,
and if the current is not locked, unblock overcurrent trip, otherwise it will
output “InrushBlk” report.
When "OCStage1BlkByVolt"=1, the compound voltage locking element is
put into the device. When the protection is started, the device checks the
compound voltage locking condition, unblock overcurrent protection if it
25
meets the conditions, otherwise the protection is locked.

When “DirOCStage1"=1, overcurrent protection is with the directional
element, and choose the positive or negative direction characteristic
according to "OCStage1FwdDir", when the directional element is not
satisfied, overcurrent protection is blocked.
When the overcurrent component trips, at the same time, three-phase
current value of Ia, Ib and Ic will also be displayed.
3.1.7 Alarm characteristic
When overcurrent protection function is enabled (En=1) and no open
blocking, if the "OCStage1AlmOn"=1 of overcurrent stage 1, the
corresponding overcurrent protection stage is enabled. If phase current is
greater than the setting value "OCSatge1AlmTimeSet", the timer starts
and "OCStage1ProtAlarm" is issued. LED and protection trip can be
configured by AESP. When the phase
currentI∅ < Dropout × “OCStage1AlarmSet”, Dropout is dropoff coefficient,
timing component and overcurrent protection return.
Alarm only be blocked by BIBlk.Inrush,compound voltage,direction don’t
block alarm characteristic.
3.1.8 Logic diagram
Taking the stage 1 of the overurrent as an example, the logic diagram of
definite time is shown below:
Iφ>“OCStage1CurrSet”
InstantVTFail &
≥1
&
“VTFailProtOff”=1
Overcurrent stage 1 phaseφ startup
Overcurrent stage 1 directional component satisfied
Overcurrent stage 1 multi-voltage component satisfied
Overcurrent protection is on
Overcurrent stage 1 phaseφ startup &

T1 &
&
BI blocking Overcurrent stage 1 trips
Overcurrent stage 1 three-phase inrush blocking
“OCStage1On”=1
T1：“OCSatge1Time”
Φ=a,b,c
Figure 11 Logic diagram of the overcurrent definite time of Stage1
26
Overcurrent stage 1 phaseφ startup &

T1Alm &
OCStage1Alarm
BI blocking
“OCStage1AlarmOn”=1
T1Alm：“OCStage1TimeAlarmSet”
Φ=a,b,c
Figure 12 Logic diagram of overcurrent stage 1 alarm
3.2 Setting list

Table 13 Overcurrent protection setting
Default
value
1 OCStage1CurrSet 0.05In~40In 40 0.01 A
2 OCSatge1Time 0.00~300.00 100 0.01 s
3 OCStage1AlarmSet 0.05In~40In 40 0.01 A
4 OCStage1TimeAlarmSet 0.00~100.00 100 0.01 s
5 OCStage1Curve 0~13 0 1
6 InvTimeOCStage1CoefA 0.001~1000 10 0.001
7 InvTimeOCStage1IndexP 0.01~10.00 10 0.01
8 InvTimeOCStage1TimeB 0.000~100.00 100 0.01
9 InvTimeOCStage1ConstT 0.025~1.5 0.025 0.001
11 OCSatge2Time 0.00~300.00 100 0.01 s
18 OCStage3Time 0.00~300.00 100 0.01 s
25 OCStage4Time 0.00~300.00 100 0.01 s
27
Default
value
31 InvTimeOCMinTime 0.100~100.00 0.1 0.01 s
32 PPVoltBlkSet 1.00~120.0 30 0.01 V
0.01 One time
of
33 0.05~100.0 3 V negative
sequence
voltage
U2BlkSet
34 DirOCSensitiveAngle 0.00~90.00 30 0.01 degree
35 OCHarmUnblkCurr 0.05In~40In 40 0.01 A
36 OC2ndHI2/I1Ratio 0.07~0.50 0.07 0.01
37 HarmCrossBlkTime 0.000~100.00 100 0.01 s
Table 14 Overcurrent protection logic switch
Default
Number Logic switch name Set mode Remark
value
1-overcurrent stage 1 on,
1. OCStage1On 1/0 0
0-overcurrent stage 1 off
1-Overcurrent stage 1 alarm

2. OCStage1AlarmOn 1/0 0 on; 0-overcurrent stage 1
alarm off
1-overcurrent stage 1 Dir on,

3. DirOCStage1 1/0 0
0-Overcurrent stage 1 Dir off
1-overcurrent stage 1
forward direction,
4. OCStage1FwdDir 1/0 0
reverse direction
5. OCStage1BlkByVolt 1/0 0 voltage on, 0-Overcurrent
stage 1 voltage off
secondary harmonic on,
6. OC1BlkBy2ndH 1/0 0
0-Overcurrent stage 1
secondary harmonic off
0-adopt fundamental
component in stage 1 of
7. OCStage1RMSOn 1/0 0 overcurrent；
1-adopt root mean source in
stage 1 of overcurrent
8. OCStage2On 1/0 0
9. DirOCStage2 1/0 0 1-overcurrent stage 2 Dir on,
28
Default
value
forward direction,
reverse direction
stage 2 voltage off
0-adopt fundamental
13. OCStage2RMSOn 1/0 0 overcurrent;
14. OCStage3On 1/0 0
forward direction,
reverse direction
stage 3 voltage off
0-adopt fundamental
19. OCStage3RMSOn 1/0 0 overcurrent;
20. OCStage4On 1/0 0
forward direction,
reverse direction
stage 4 voltage off
25. OCStage4RMSOn 1/0 0 0-adopt fundamental

29
Default
value
overcurrent;
1-three-phase voltage
26. 3PhVoltConnect 1/0 1 connection, 0-Single-phase
voltage connection
1-VT failure protection off,
27. VTFailProtOff 1/0 0
0-VT failure protection on
3.3 Report list

Table 15 Report list
Number Report name Remark

Trip report:
1. OCStage1Trip /
2. OCStage2Trip /
3. OCStage3Trip /
4. OCStage4Trip /
5. OCStage1PhATrip /
6. OCStage1PhBTrip /
7. OCStage1PhCTrip /
Inrush conditions meet the requirements of blocking
17. InrushBlk
overcurrent protection
Alarm report:
1. OCStage1Alarm
30
3.4 Technical data

Table 16 Overcurrent protection technical data
Content Range and value Error
Definite time characteristic
Current 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
≤ ± 1% times of setting or
+40ms,
Time delay 0.00s～300.00s
At 2 times of operating
current
Inverse time characteristic
Normal inverse time
Very inverse time; IEC60255-151
IEC standard ≤ ±5% setting or +40ms,
Extreme inverse time
when 2<I/ISETTING<20
Long inverse time
Inverse time
Short inverse time
Long inverse time ANSI IEEEC37.112,
ANSI Medium inverse time ≤±5% setting or +40ms, when
Abnormal inverse time 2<I/ISETTING<20
Definite inverse time
 
  IEC60255-151
A
t   ⋅T
User-defined characteristic
= + B ≤±5% setting or +40ms, when
curve   IΦ  P  2<I/ISETTING<20
  −1 
  Iset  
Time coefficient of inverse
0.001～1000
time A
Time delay of inverse time
0.000～100.00
B
Inverse time index P 0.01～10.00
Inverse time constant T 0.025～1.5
Minimum trip time 20ms
Return mode Instantaneous return
Directional component
Action angle range 70° ≤ ±3°,
Sensitive Angle 0°～90° when line voltage >2V
Inrush blocking
Maximum current of open
magnetizing inrush current 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
blocking
The ratio of secondary
harmonic and fundamental 0.07～0.5
current
Crossing blocking
(IL1,IL2,IL3) ( time setting 0.00s～100.00s ≤ ±1% setting or +40ms
can be set)
31
Chapter 5 Earth fault protection (50N, 51N, 67N)
Chapter 5 Earth fault protection

(50N, 51N, 67N)
About this chapter

This chapter describes the zero sequence current principle,
the input and output signals, setting value parameters,
messages and technical parameters.
33
1 Overview
Under the condition of high resistance grounding fault in the neutral point
grounding system, the calculated impedance located out of the distance
impedance zone and the IED maloperation. Therefore, other protection
trips are needed to isolate the fault, earth fault protection can reliably
identify high resistance grounding fault. For example, in the double circuit
lines, the directional earth fault protection simultaneously distinguishes the
size and direction of fault current and cooperates with other protection
devices in the system.
The characteristics of earth fault protection are listed as follow:
1) Definite-time of 4 stages, inverse-time limit (including all IEC/ANSI
standard inverse-time characteristic);
2) The direction feature of each stage is Independently selectable;
3) Negative sequence directional component(selectable);
4) The inrush blocking feature of each stage is independently selectable;
5) Inrush locking is distinguished by secondary harmonic currents;
6) The maximum current of open magnetizing inrush blocking can be
adjusted;
7) Earth fault protection of VT breaking blocking direction.
soft-hard parallel.
9) Zero current external connection of stage 4 and self-produced zero
current support can adopt root mean source calculated current or
fundamental current, and root mean source method does not support
blocking condition.

The input and output signals of earth fault protection function are shown
below:
Directional / Non-directional Zero
Overcurrent Protection
1 1
BIBlk Start
2 2
ENA_EF Operation
3
Alarm
Figure 13 Diagram of input and output signals of earth fault protection function
The left is the input and the right is the output.

EF Input:
34

BIBlk BIBlk
Output:
Start IED startup
Operation IED trip
Alarm Protection alarm (only for the configuration of alarm stage)
Input:
ENA
The total connector of Earth fault protection ， the
ENA_EF
corresponding hard connector is ENA_EF_5.
IED is equipped with four-stage earth fault protection, please refer to the
setting list for details. The overcurrent protection stage 1 will be taken as
an example below and the principle will be introduced.

3.1.1 Inrush blocking components
When "3I0Stage1BlkBy2ndH"=1, inrush detects. There are two inrush
criteria:
Check phase current harmonics and external zero sequence current
harmonic.
1) Only when "3I0HarmonChkExtrI02/I01"=1, and "Extr3I0Stage1"=1,
zero-sequence current harmonic is detected. When it is detected that
the ratio of second harmonic and fundamental wave is larger than
"3I02ndHI02/I01" and there is zero sequence current, then the zero
sequence inrush condition is satisfied. When the maximum
fundamental wave of zero sequence current is larger than
"3I0UnblkHarmBlkCurr", release each blocking.
2) In addition to the first case, detect the phase current harmonic. When
it is detected that the ratio of second harmonic and fundamental wave
is larger than "OC2ndHI2/I1Ratio" and there is a current, then the
inrush condition is satisfied in the phase. When the maximum
fundamental wave of phase current is larger than "OC2ndHI2/I1Ratio",
release each blocking.
Output locking statue when any of the above two harmonic check method
is satisfied, the secondary harmonic current is high.
35
3I0>“3I0UnblkHarmBlkCurr” &
&
3I02/3I0>“3I02ndHI02/I01”
“Extr3I0Stage1”=0 & ≥1
Secondary harmonic current is great
“3I0HarmonChkExtrI02/I01”=1
&
Imax>“HarmUnblkPhCurr”
Ia2/Ia1>“OC2ndHI2/I1Ratio”
≥1
Ib2/Ib1>“OC2ndHI2/I1Ratio”
Ic2/Ic1>“OC2ndHI2/I1Ratio”
3I02/3I0: Zero sequence current second harmonic/Zero sequence current fundamental wave
Ia2/Ia1：Phase A current secondary harmonic/Phase A current fundamental wave
Ib2/Ib1：Phase B current secondary harmonic/Phase B current fundamental wave
Ic2/Ic1：Phase C current secondary harmonic/Phase C current fundamental wave
Figure 14 Logic diagram of the secondary harmonic blocking of earth fault protection

1) Zero sequence directional component
In order to meet the different operating conditions of power system, the
reference voltage can be clockwise rotate 0 to 90°according to the
"3I0DirectSensitiveAngle". This setting influences direction characteristics
of each stage. The reference voltage vector after rotation is closer to the
-3I0 of lag 3U0 angle Φd, which makes the direction distinguishing more
sensitive. Rotate reference voltage vector to define the forward direction
and reverse direction action zone. The direction range of the positive
direction is rotating voltage reference vector for the vertical bisector
between -80 degrees and +80 degrees. If the -3I0 vector is in this zone,
the device is considered to be in the forward direction.
An example is given to illustrate the direction discrimination of A phase
faults. In the figure, 3I0 exceeds 3U0, so the -3I0 lags 3U0, the reference
voltage 3U0 vector rotates "3I0DirectSensitiveAngle", in order to be closer
to the -3I0 vector. In addition, the yellow area in the diagram is a positive
direction.
3I 0 90° 90°
3I 0
Reverse
10°
10°
0° 0°
3 U 0_Ref 3U 0_Ref
Φ0 Φ0
Forward Bisector Bisector
-3 I 0 -3 I 0
36
Figure 15 Diagram of zero sequence directional element

Where:
Zero sequence directional sensitive angle: the angle is settable,
Ф0="Dir3I0SensitiveAngle";
Zero sequence positive direction overcurrent range: (-80°~ +80°), zero
sequence reverse direction overcurrent range: (+100°~ +260°).
2) Negative sequence directional component
When "ZeroSeqChkU2/I2DirOn"=1, and the zero sequence voltage is
small, then enable the negative sequence directional element. For
example, zero sequence current mutual coupling or uncertain zero
sequence directional impedance happen in the double circuit line. Here, it
is necessary to input the negative sequence directional component to
detect the fault current direction, the logic switch “ZeroSeqChkU2/I2DirOn”
is set to 1. Here, it is still the default input zero sequence direction
discrimination. However, when 3U0 is less than 1V and 3U2 is larger than
2V, it is converted into negative sequence direction discrimination; at this
point negative sequence component is used to discriminate the direction.
Negative sequence directional characteristics diagram:
3I 2 90° 90°
3I 2
Reverse
10°
10°
0° 0°
3 U 2-Ref 3U 2-Ref
Φ2 Φ2
Forward Bisector Bisector
-3 I 2 -3 I 2
Figure 16 Negative sequence directional characteristic diagram

Where:
Ф2: setting "3I0NSDSensitiveAngle".
Negative sequence positive direction overcurrent range: (-80°~ +80°),
negative sequence reverse direction overcurrent range: (+100°~ +260°).
In the process of direction discrimination, the VT disconnection may lead
actions or alarms that are not consistent with the flow direction
discrimination or the voltage discrimination along overcurrent protection
stages. When VT fails, the action mode is decided according to
"VTFailProtOff"; if “VTFailProtOff” is set to 1, earth fault protection with
voltage or directional element is blocked; if “VTFailProtOff” is set to 0,
voltage blocking element and directional element exit and act in a pure
overcurrent mode.
37
&
InstantVTFai
Zero sequence forward group & ≥1
Calculated zero sequence

voltage>1V
& &
“ZeroSeqChkU2/I2DirOn”=1
Negative sequence forward group
“3I0Stage1Extr3U0”=0
≥1
&
U4InstantVTFail Forward direction
≥1
&
Zero sequence forward group
&
External connected zero

sequence voltage>1V
“3I0Stage1Extr3U0”=1
Zero sequence forward group: calculated by adopting 90° wiring mode, zero sequence current is within direction group
Negative sequence forward group: calculated by adopting 90° wiring mode, negative sequence current is within direction group
Figure 17 Logic diagram of zero sequence current direction sensitive angle
3.1.3 Definite time

When "3I0Stage1Curve"=0, zero sequence current is the definite time
3I0 > “3I0Stage1CurrSet”
When the zero sequence current is greater than "ZSOCStage1Set",
timing component starts and until "3I0Stage1CurrSet“, earth fault
protection trips, when 3I0 < Dropout × “3I0Stage1CurrSet”, Dropout is
dropoff coefficient, timing component returns, earth fault protection
returns.
3.1.4 Inverse time
When "3I0Stage1Curve"=1~13, zero sequence current is the definite time
 
 
 A 
=t  P
+ B ⋅T
  3I 0  − 1 
  3I 0set  
Where:
A: "InvTimeOCStage1CoefA"
P: "InvTimeOCStage1IndexP"
B: "InvTimeOCStage1TimeB"
T: "InvTimeOCStage1ConstT"
3I 0 : Zero sequence current setting value
38
3I 0set Current: 3I0Stage1CurrSet

If the current exceeds "3I0Stage1CurrSet", the timing element starts,
inverse time characteristic curve is selected by "3I0Stage1Curve", A, P, B
are determined when the value is from 1 to 12, see the Table 17; when the
value is 13, it is user defined characteristics, calculate the trip delay
according to the setting of the A, P, B, T. While timing, earth fault
protection trips. When the calculated delay is less than the minimum trip
delay time "3I0InvTimeMinTripTime", the component trips according to the
"3I0InvTimeMinTripTime"
0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE

When earth fault protection function is enabled and no BI blocking, if the
"3I0Stage1On"=1, the earth fault protection of the corresponding stage is
enabled.
If the action conditions are met, time component starts; take stage 1
protection for example, when time is over, "3I0Stage1Trip" is issued. LED
and protection trip can be configured by AESP. While IED trips, each
phase trip states will be displayed at the same time.
When "3I0Stage1BlkBy2ndH"=1, the harmonic locking component is put
into operation, when the action timer is time out, the inrush current is
checked, and if the current is not blocked, unblock overcurrent trip,
otherwise it will output “InrushBlk” report.
39
When "Dir3I0Stage1”, protection is with the directional element, and

choose the positive or negative direction characteristic according to
"3I0Stage1FwdDir", when the directional element is not satisfied, earth
fault protection is blocked.
When "CTFailAlarmOn"=1, input “CTFailBlk3I0” logic switch, then the CT
failure blocking earth fault protection, otherwise unblocking earth fault
protection.
Element trip triggers action or alarm, meanwhile output analog quantity of
action time, when the element is based on the self-produce zero sequence
current judgment, self-produce zero sequence currents output; when it is
based on the external zero sequence current, external zero sequence
currents output.
3I0>“3I0Stage1CurrSet”
BI blocking
&
InstantVTFail
“VTFailProtOff”=1 &
& T1
“3I0Stg1RMSOn”=0
&
CTFailAlarm
“CTFailBlk3I0”=1
&
Forward direction
≥1 &
Zero sequence stage 1 tirps
“3I0Stage1FwdDir”=1
“Dir3I0Stage1”=1
&
Secondary harmonic current is great
“3I0Stage1BlkBy2ndH”=1
“3I0Stg1RMSOn”=0
“3I0Stage1On”=1
Zero sequence overcurrent stage 1 protection is on
T1：“3I0Satge1Time”
Figure 18 Logic diagram of earth fault protection function
3.1.6 Alarm characteristic

When earth fault protection function is enabled and no BI blocking, if
“3I0Stage1AlarmOn"=1, the earth fault protection alarm of stage 1 is
enabled. If the current exceeds the setting value "3I0Stage1AlarmSet", the
timer starts, when "3I0Stage1AlarmSet" is time out, "3I0Stage1Alarm" will
be issued. LED and protection trip can be configured by AESP. When3I0 <
Dropout × “3I0Stage1AlarmSet” , Dropout is dropoff coefficient, timing
component and overcurrent protection return.
Alarm only be blocked by BIBlk.Inrush,direction don’t block alarm
characteristic.
40
3I0>“3I0Stage1CurrSet” &
T1Alm &
Zero sequence stage 1
BI blocking protection alarm
“3I0Stage1AlarmOn”=1
T1Alm：“3I0Satge1TimeAlarmSet”
Figure 19 Logic diagram of earth fault protection alarm
3.2 Setting list

Table 19 Earth fault protection setting
Default
Number Setting name Range Step Unit Remark
value
3 times of zero
1. 3I0Stage1CurrSet 0.05~200 40 0.01 A sequence
current
2. 3I0Satge1Time 0.00~300.00 100 0.01 s
3 times of zero
3. 3I0Stage1AlarmSet 0.05~200 40 0.01 A sequence
current
4. 3I0Satge1TimeAlarmSet 0.00~100.00 100 0.01 s
0: Definite time
1: IECINV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
5. 3I0Stage1Curve 0~13 0 1 SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
6. InvTime3I0Stage1CoefA 0.001~1000 10 0.001
41
Default
value
7. InvTime3I0Stage1IndexP 0.01~10.00 10 0.01
8. InvTime3I0Stage1TimeB 0.000~100.00 100 0.01
9. InvTime3I0Stage1ConstT 0.025~1.5 0.025 0.001
3 times of zero
current
11. 3I0Satge2Time 0.00~300.00 100 0.01 s
12. 3I0Stage2Curve 0~13 0 1
3 times of zero
current
18. 3I0Satge3Time 0.00~300.00 100 0.01 s
3 times of zero
current
25. 3I0Satge4Time 0.00~300.00 100 0.01 s
31. 3I0InvTimeMinTripTime 0.100~100.00 0.1 0.01 s
42
Default
value
32. Dir3I0SensitiveAngle 0.00~90.00 30 0.01 degree
33. 3I0NSDSensitiveAngle 0.00~90.00 30 0.01 degree
34. HarmUnblkPhCurr 0.05In~40In 40 0.01 A
35. 3I0UnblkHarmBlkCurr 0.05In~40In 40 0.01 A
36. OC2ndHI2/I1Ratio 0.07~0.50 0.07 0.01
37. 3I02ndHI02/I01 0.07~0.50 0.07 0.01

Remark：If two earth fault channels are configured, the setting value of earth fault stage 2 is
the same as that in this table.
Table 20 Earth fault protection logic switch
Set Default
Number Logic switch name Remark
mode value
1-Zero sequence current stage 1
1. 3I0Stage1On 1/0 0 on, 0-Zero sequence current
stage 1 off
2. 3I0Stage1AlarmOn 1/0 0 alarm on; 0-Zero sequence
current stage 1 alarm off
1-zero sequence current stage 1
3. Dir3I0Stage1 1/0 0 Dir on, 0-zero sequence current
stage 1 Dir off
forward direction; 0-zero
4. 3I0Stage1FowardDir 1/0 0
sequence current stage 1 reverse
direction
secondary harmonic blocking on,
5. 3I0Stage1BlkBy2ndH 1/0 0
secondary harmonic blocking off
1-3I0 external connection; 0-3I0
6. Extr3I0Stage1 1/0 0
calculated
1-3U0 external connection; 0-3U0
7. 3I0Stage1Extr3U0 1/0 0
calculated
0-adopt fundamental component

in stage 1 of zero current;
8. 3I0Stg1RMSOn 1/0 0
stage 1 of zero current

stage 2 off
stage 2 Dir off
11. 3I0Stage2FowardDir 1/0 0 1-Zero sequence current stage 2
43
Set Default
mode value
direction
calculated
calculated


stage 3 off
stage 3 Dir off
direction
calculated
calculated


stage 4 off
stage 4 Dir off
direction
26. 3I0Stage4BlkBy2ndH 1/0 0 1-zero sequence current stage 4
44
Set Default
mode value
calculated
calculated

1: check negative sequence

30. ZeroSeqChkU2I2DirOn 1/0 1 direction; 0: don't check negative
sequence direction
1-Zero sequence current
harmonics check I02/I01; 0-Zero
31. 3I0HarmonChkI02/I01 1/0 0
sequence current harmonics
check I2/I1
32. CTFailBlk3I0 1/0 0 0-open; 1-lock.
33. VTFailProtOff 1/0 0 0-open; 1-lock.
voltage connection
3.3 Report list


Trip report:
1. 3I0Stage1Trip /
2. 3I0Stage2Trip /
3. 3I0Stage3Trip /
4. 3I0Stage4Trip /
Alarm report:
1. 3I0Stage1Alarm
2. 3I0Stage1BlkByInrush
Remark： If two earth fault channels are configured, the report of earth fault stage 2 is the
same as that in this table.
45
3.4 Technical data

Table 22 Earth fault protection technical data

≤ ±1% setting or +40ms, at 2
Time delay 0.00s～300.00s
times of operating current
Normal inverse time IEC60255-151
Very inverse time; ≤ ±5% times of setting or
IEC standard +40ms, in the case of
Long inverse time 2 < 3I 0 / 3I 0set<20
Inverse time
Short inverse time ANSI IEEEC37.112,
Long inverse time ≤ ±5% times of setting or
ANSI Medium inverse time +40ms, in the case of
Abnormal inverse time 2 < 3I 0 / 3I 0set<20
Definite inverse time
  IEC60255-151
 
User-defined characteristic  A  ≤ ±5% times of setting or
= t  P
+ B ⋅T +40ms, in the case of
curve
  3I 0  − 1  2 < 3I 0 / 3I 0set<20
  3I 0set  

0.001～1000
time A
Time delay of inverse time B 0.000～100.00
Directional component
Zero sequence direction
160°
element action angle range ≤±3, when 3U0≥1V
Directional sensitive angle 0°~90°
Negative sequence direction
160°
element action angle range ≤±3, when 3U2≥2V
Directional sensitive angle 0°~90°
46
Chapter 6 High sensitive earth fault protection (50Ns,
51Ns, 67Ns)
Chapter 6 High sensitive earth fault

protection (50Ns, 51Ns,
67Ns)
About this chapter

This chapter describes the high sensitive zero sequence
current principle, the input and output signals, setting value
parameters, messages and technical parameters.
47
51Ns, 67Ns)
1 Overview
Sensitive earth fault protection can be used to detect and give selective
trip of phase to earth faults in isolated or compensated networks. The
protection function also can be applied to detect high impedance earth
faults in solidly or low-resistance earthed networks.
Sensitive earth fault protection integrated in the IED provides following
features:
1) Sensitive overcurrent have four stages, definite or inverse time stage
is optional;
2) Sensitive earth fault directional element with U0/I0-Φ principle;
3) Sensitive earth fault directional element with Cos Φ principle;
4) Dedicated sensitive CT;
5) Direction component needs to detect whether the VT secondary circuit
disconnects.
soft-hard parallel.

The input and output signals of earth fault protection function diagram are
shown below:
Directional / Non-directional Sensitive Zero Overcurrent Protection
1 1
BIBlk Start
2 2
ENA_SEF Operation
Figure 20 Diagram of input and output signals of high sensitive earth fault protection
function
Input:
BIBlk BIBlk
SEF Output:
Start High sensitive earth fault protection start-up
Operation High sensitive earth fault protection trip
Input:
ENA
The total connector of High sensitive earth fault protection，
ENA_SEF
the corresponding hard connector is ENA_SEF_5.
48
51Ns, 67Ns)
IED is equipped with four-stage high sensitive earth fault protection,
please refer to the setting list for details. The SEF/REF overcurrent
protection stage 1 will be taken as an example below and the principle will
be introduced.

1) 3U0/3I0-Φmeasurement
In order to satisfy different network conditions and applications, the
reference voltage can be rotated by adjustable angle
“HVSide3I0DirSensitiveAngle” between 0° and 90° in anticlockwise
direction (positive sign). It should be noted that the settings affect all the
directional stages of sensitive earth fault element. In this way, the vector of
rotated reference voltage can be closely adjusted to the vector of fault
current -Is which leads the fault voltage 3U0 by the fault angle Φd. The
rotated reference voltage defines the forward and reverse area. The
forward area is in range of ±80° around the rotated reference voltage. If the
vector of the fault current -Is is in this area, the device detects forward
direction. The figure below shows an example of direction determination.
As can be seen from the figure, the rotated angle of the reference voltage
is the fault sensitive angle. The reference voltage is rotated by this angle to
be closely matched to -Is current. Furthermore, the forward area is
depicted in the figure.
90° 90°
Forward - I NS
- I NS �
10° � 10°
Bisector Bisector
Φd �
Φd � 0°
0°
� 3U0_Ref
3U0_Ref
Reverse
�
I NS
I NS
Figure 21 33U0/3I0-Φ Measurement of forward and reverse action area

Where:
Zero-sequence directional sensitive angle: the angle is settable;
Positive direction range of high sensitive zero sequence current: (-80° ~
+80°), negative direction range of high sensitive zero sequence current:
(+100° ~ +260°).
2) CosΦ measurement
Similar to 3U0/3I0-Φ method, the direction determination is performed in
cos Φ method by using the measured current at sensitive current input Is
49
51Ns, 67Ns)
together with the measured or calculated displacement voltage.
Direction determination is performed in Cos Φ method by using those
component of the residual current which is perpendicular to the directional
characteristic (axis of symmetry). As Figure 20 shows below. It shows how
the IED adopts complex vector diagram for direction determination. As can
be seen, displacement voltage 3V0 is the reference magnitude quantity.
The axis of symmetry is defined as a line perpendicular to this quantity.
The sensitive earth fault protection would issue a trip command or an
alarm signal if the active component of Is is in the opposite direction of the
reference voltage and has a magnitude exceeds setting
“HVSide3I0IsCosSet”.
IS 90° 90°
IS
Forward 0° Reverse 0°
3U0_Ref 3U0_Ref
- IS - IS
Figure 22 CosΦ Measurement of forward and reverse action area

&
VT failure blocking
3U0/3I0-ΦMeasurement & ≥1
forward group
Calculated zero sequence

voltage>2V
&
“Chk3U03I0Criterion”=1
&
CosΦMeasurement
forward group
“Extr3U0”=0
≥1
&
U4 failure blocking Forward direction
≥1
3U0/3I0-Φ Measurement &

forward group &
External connected zero

sequence voltage>2V
“Chk3U03I0Criterion”=1
&
CosΦ Measurement
forward group
“Extr3U0”=1
3U0/3I0-Φ Measurement forward group: calculate in accordance with 3U0/3I0-Φ mode, current is within the direction group.
CosΦ Measurement forward group: calculate in accordance with 3U0/CosΦ mode, negative sequence current is within the direction group.
Figure 23 Logic diagram of SEF/REF protection directional blocking
50
51Ns, 67Ns)
3.1.2 Definite time
When "SEF/REFStage1Curve"=0, high sensitive zero sequence current
trips as the definite time characteristic, inverse time function is disabled.
Is0 > “SEF/REFStage1CurrSet”
When the current is greater than "SEF/REFStage1CurrSet", timing
component starts, high sensitive earth fault protection trips when
"SEF/REFStage1Time" is up; when the current Is0 < Dropout × “SEF/
REFStage1Time”, Dropout is dropoff coefficient, timing component and high
sensitive earth fault protection return.
3.1.3 Inverse time
When "SEF/REFStage1Curve" =1~13, high sensitive zero sequence
current trips as the inverse time characteristic, definite time function is
disabled.
 
 
 A 
=t  P
+ B ⋅T
  Is0  −1 
  I s 0set  
If the current exceeds "SEF/REFStage1CurrSet", timing element starts,

inverse time characteristic curve is selected by curve, A, P and B are
determined when the value ranges 1~12; when the value is 13, it is
user-defined, calculate tripping delay according to the setting of A, P, B, T.
When time is up, high sensitive earth fault protection will trip.
Where:
A: "InvTimeSEF/REFStage1CoefA"
P: "InvTimeSEF/REFStage1IndexP"
B: "InvTimeSEF/REFStage1B"
T: "InvTimeSEF/REFStage1ConstT"
I s 0 : Zero sequence current setting value of high voltage side

I s 0 set : "SEF/REFStage1CurrSet"
When “SEF/REFStage1Curve” =14, high sensitive earth fault acts with
epatr curve characteristics. The ISE curve of primary current is:
0.5~6A,t=432*T/(ISEF0.655);
6~200A,t=800*T/ISEF;
Above 200A,t=4*T;
Where,
ISEF：Primary current value（A）
t：Inverse time trip time
T: “InvTimeSEF/REFStage1ConstT”
51
51Ns, 67Ns)
EPATR curve
Time（s）
Primary current value（A），CT ratio100:1
Figure 24 EPATR curve


0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE
14 EPATR curve

When high sensitive earth fault protection function is enabled and no BI
blocking, if "SEF/REFStage1On"=1, high sensitive earth fault protection of
the corresponding stage is enabled.
If high sensitive zero sequence current trip is enabled and the tripping
conditions are met, time component starts; take stage 1 protection as an
example, when time is over, "SEF/REFStage1Trip" is issued. LED and
protection trip can be configured by AESP.
When "DirSEF/REFStage1"=1, protection is with the directional element
and choose the positive or negative direction according to
"SEF/REFStage1FwdDir".
In the process of direction discrimination, the VT disconnection may lead
52
51Ns, 67Ns)
actions or alarms that are not consistent with the flow direction
discrimination along each overcurrent protection stage. When VT fails, the
action mode is decided according to "VTFailProtOff"; if “VTFailProtOff” is
set to 1, overcurrent protection with directional element is blocked; if
“VTFailProtOff” is set to 0, directional element exits and acts in a pure
overcurrent mode.
The element action triggers the protection action, and outputs the high
sensitive zero sequence current value at the same time of the action time.
&
VT failure blocking
Is0>“SEF/REFStage1CurrSet”
&
BI blocking T1
& &
Forward direction
≥1
SEF/REF stage 1 trips
“SEF/REFStage1FwdDir”=1
“DirSEF/REFStage1”=0
“SEF/REFStage1On”=1
SEF/REF stage 1 protection is on
T1：“SEF/REFStage1Time”
Figure 25 Logic diagram of SEF/REF protection function
3.1 Setting list

Table 25 High sensitive earth fault protection setting
Default
value
1. SEF/REFStage1CurrSet 0.005~1.00 1 0.001 A
2. SEF/REFStage1Time 0.00~300 100 0.01 s
0: Definite
time
1: IEC INV.
2: IEC
VERY INV.
3: IEC
EXTERMEL
Y INV.
4: IEC
SHORT
TIME INV.
3. SEF/REFStage1Curve 0~14 0 1 5: IEC
LONG TIME
INV.
6: ANSI INV.
7：ANSI
SHORT INV.
8: ANSI
LONG INV.
9: ANSI
MODERATE
LY INV.
10: ANSI
53
51Ns, 67Ns)
Default
value
VERY INV.
11: ANSI
EXTERMEL
Y INV.
12: ANSI
DEFINITE
INV.
13: User
defined
14:Apply
only to
EPATR
curve
InvTimeSEF/REFStage1
4. 0.001~1000 10 0.001
CoefA
InvTimeSEF/REFStage1I
5. 0.01~10.00 10 0.01
ndexP
6. 0.000~100.00 100 0.01
B
7. 0.025~1.5 0.025 0.001
ConstT
If using
1.2/3.53 AC
module, the
setting
range is
0.005~1.00；
If using
6/3.53 AC
module, the
setting
range is
0.005~5.00；
10. SEF/REFStage2Curve 0~14 0 1
11. 0.001~1000 10 0.001
CoefA
12. 0.01~10.00 10 0.01
ndexP
InvTimeSEF/REF2Const
13. 0.000~100.00 100 0.01
B
14. 0.025~1.5 0.025 0.001
ConstT
If using
1.2/3.53 AC
module, the
setting
range is
15. SEF/REFStage3CurrSet 0.005~1.00 1 0.001 A 0.005~1.00；
If using
6/3.53 AC
module, the
setting
range is
54
51Ns, 67Ns)
Default
value
0.005~5.00；
18. 0.001~1000 10 0.001
CoefA
19. 0.01~10.00 10 0.01
ndexP
20. 0.000~100.00 100 0.01
B
21. 0.025~1.5 0.025 0.001
ConstT
If using
1.2/3.53 AC
module, the
setting
range is
0.005~1.00；
If using
6/3.53 AC
module, the
setting
range is
0.005~5.00；
25. 0.001~1000 10 0.001
CoefA
26. 0.01~10.00 10 0.01
ndexP
27. 0.000~100.00 100 0.01
B
28. 0.025~1.5 0.025 0.001
ConstT
InvTimeSEF/REFMinTim
29. 0.100~100.00 0.1 0.01 s
e
SEF/REFDirSensitiveAn
30. 0.00~90.00 0 0.01 degree
gle
31. SEF/REF_IsCosSet 0.005~1.00 1 0.001 A
Remark:If two high sensitive earth fault channels are configured, the setting value of high
sensitive earth fault stage 2 is the same as that in this table.
Table 26 High sensitive earth fault protection logic switch
Setting Default
Mode value
1. SEF/REFStage1On 1/0 0
2. DirSEF/REFStage1 1/0 0
3. SEF/REFStage1Fwd 1/0 0
55
51Ns, 67Ns)
Setting Default
Mode value
13. Chk3U03I0Criterion 1/0 0
14. Extr3U0 1/0 0
1-VT failure protection off,
0-VT failure protection on
connection,
16. 3PhVoltConnect 1/0 1
0-Single-phase voltage
connection
Remark: If two high sensitive earth fault channels are configured, the logic switch of high
sensitive earth fault stage 2 is the same as that in this table.
3.2 Report list


Trip report:
1. SEF/REFStage1Trip /
Remark: If two high sensitive earth fault channels are configured, the report of high sensitive
earth fault stage 2 is the same as that in this table.
3.3 Technical parameter

Table 28 High sensitive earth fault protection technical data
Items Setting range Trip Value Error

High sensitive CT current
0.005A/5.000A ≤±2.5% setting value or 1mA
input settings
≤ ±1.5% setting or +40ms,
Time setting 0.00s～300.00s when trip current is set as
200% setting
When I/In≥0.5, it is about
DropoffCoef
0.95
Reset time Approx. 40 ms
High sensitive CT current
0.005A/1.000A ≤±2.5% setting value or 1mA
input settings
56
51Ns, 67Ns)
Normal inverse time; ≤ ±5% setting value or +40ms,
Very inverse time;
IEC standard curve
Extreme inverse time; when 2 < I s 0 / I s 0set<20 , it
Long inverse time; meets IEC60255-151 standard
Standard inverse time;
Short inverse time ≤ ±5% setting value or +40ms,
Long inverse time;
ANSI standard curve Normal inverse time; when 2 < I s 0 / I s 0set<20 , it
Very inverse time; meets ANSI/IEEEC37.112
Extreme inverse time; standard
User-defined inverse time;
 
  ≤ ±5% setting value or +40ms,
 A 
User defined curve =t  P
+ B ⋅T when 2 < I s 0 / I s 0set<20 , it
  Is0  −1 
  I s 0set 
meets IEC60255-151 standard

0.001～1000
time A
High sensitive earth fault protection directional element
Is0cosΦ;
Principle
Φ (V0 / I0)
high sensitive earth fault External 3U0 or
directional voltage self-produce 3U0
≤ ±3% setting, when zero
sequence directional voltage is
external connection
Directional voltage threshold 2.00～100.00V
≤ ±5% setting, when zero
sequence directional voltage is
calculated
High sensitive earth fault
0.0°~90.0° ≤ ±3°
direction sensitive angle
Angle trip range 160° ≤ ±3°
57
Chapter 7 Negative sequence current protection (46)
Chapter 7 Negative sequence

current protection (46)
About this chapter

This chapter describes the negative sequence current
principle, the input and output signals, setting value
59
1 Overview
Negative sequence current protection can detect the unbalance of power
system load. When the generator connect unbalanced load, negative
sequence current protection is particularly useful. Because the unbalanced
load will produce a reverse magnetic field in the three-phase induction
motor, resulting in overheating of the rotor end. Secondly, the negative
sequence current protection can also be used to detect the disconnection,
short circuit and polarity of current transformer. Besides, the negative
sequence current protection can also detect the single-phase or two-phase
faults in the system and the fault statue when the fault current is less than
the load current.
The main characteristics of the negative sequence current protection are:
offer four stages of negative sequence current protection, and definite time
or inverse time can be selected.
The protective function can be disabled through the function connector.
connector, soft-hard series, soft-hard parallel, and the default is soft-hard
parallel.

The input and output signals of negative sequence current protection
function are shown below:
Negative Sequence Over Current
Protection
1 1
BIBlk Start
2 2
ENA_NSOC Operation
Figure 26 Diagram of input and output signals of negative sequence current protection
function
Function identifier Description
Input:
BIBlk Binary input blocking
NSOC Output:
Start IED startup
Operation IED trip
Input:
ENA The total connector of Negative sequence current protection，
ENA_NSOC
the corresponding hard connector is ENA_NSOC_5.
60
IED is equipped with four-stage negative sequence current protection.

Please refer to the setting list for details. The negative sequence current
protection stage 1 will be taken as an example below and the principle will
be introduced.

3.1.1 Definite time
When "3I2Stage1Curve"=0, negative sequence current is the definite time
The negative sequence current protection action current is calculated by
the three-phase current as follow:
3İ 2 = İA + a2 İB + aİC
3I2 > “3I2Stage1CurrSet”
When the current is greater than "3I2Stage1CurrSet", timing component
starts and until "3I2Stage1CurrSet“, negative sequence current protection
trips, when current 3I2 < Dropout × “3I2Stage1CurrSet”, timing component
returns, negative sequence current protection returns.
Where:
I 2 : Negative sequence current;

I 2 set : "3I2Stage1CurrSet"
Dropoff: Return coefficient
3.1.2 Inverse time
When "3I2Stage1Curve"=1~13, negative sequence current is the inverse
time characteristic, definite time function is disabled.
 
 
 A 
=t  P
+ B ⋅T
  I2  −1 
  I 2set  
If the negative sequence current exceeds "3I2Stage1CurrSet", the timing

element starts, inverse time characteristic curve is selected by Curve, A, P,
B are determined when the value is from 1 to 12, see the Table 29; when
the value is 13, it is user defined characteristics, calculate the trip delay
according to the setting of the A, P, B, T. While timing, earth fault
protection trips. When the calculated delay time is shorter than
"InvTimeI2MinTime", the component trips in accordance with
"InvTimeI2MinTime".
Where:
A: "InvTime3I2Stage1CoefA"
P: "InvTime3I2Stage1IndexP"
B: "InvTime3I2Stage1TimeB"
T: "InvTime3I2Stage1ConstT"
61
I 2 : Negative sequence current

I 2set : "3I2Stage1CurrSet"
0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE

When negative sequence current protection function is enabled and there
is no binary input blocking, if "3I2Stage1On"=1, then the negative
sequence current protection of the corresponding stage is enabled.
Negative sequence current protection is tripped, after the starting of
protection trip, if the action conditions are met, timing component starts,
take stage 1 for example, when time is over, and “3I2Stage1Trip" is issued.
LED and protection trip can be configured by AESP. When the zero
sequence current component trips, at the same time, negative sequence
current value will also be displayed.
Negative sequence current
stage 1 protection is on
&
&
“3I2Stage1On”=1 T1 Negative sequence current
stage 1 trips
3I2>“3I2Stage1CurrSet”
BI blocking
T1：“3I2Stage1Time”
62
Figure 27 Logic diagram of negative sequence current protection function
63
3.2 Setting list

Table 31 Negative sequence current protection setting
Default
value
3 times of
negative
1. 3I2Stage1CurrSet 0.05In~40In 40 0.01 A
sequence
current
Negative
sequence
2. 3I2Stage1Time 0.00~100.00 100 0.01 s
current stage 1
time
0: Definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
3 times of
negative
sequence
current
9. 3I2Stage2Time 0.00~100.00 100 0.01 s
64
Default
value
3 times of
negative
sequence
current
16. 3I2Stage3Time 0.00~100.00 100 0.01 s
3 times of
negative
sequence
current
23. 3I2Stage4Time 0.00~100.00 100 0.01 s
29. InvTime3I2MinTime 0.100~100.00 0.1 0.01 s
Table 32 Negative sequence current protection logic switch

Setting
Number Logic switch name Default value Remark
Mode
1. 3I2Stage1On 1/0 0 1: On; 0: Off
2. 3I2Stage2On 1/0 0 1: On; 0: Off
3. 3I2Stage3On 1/0 0 1: On; 0: Off
4. 3I2Stage4On 1/0 0 1: On; 0: Off
3.3 Report list


Trip report:
1. 3I2Stage1Trip /
2. 3I2Stage2Trip /
3. 3I2Stage3Trip /
4. 3I2Stage4Trip /
65

Table 34 Negative sequence current protection technical data
≤ ±2.5% setting value or
Current setting 0.05In~40In
±0.02In
≤ ±1% setting or +40ms,
200% setting
Dropoff coefficient When I/In>0.5, it is about 0.95
≤ ±2.5% setting value or
Current setting 0.05In~40In
±0.02In
Normal inverse time; ≤ ±5% setting value or
IEC standard curve

Very inverse time; +40ms, when 2 < I 2 / I 2set<20 ,
Extreme inverse time; it meets IEC60255-151
Long inverse time; standard
Short inverse time ≤ ±5% setting value or
Long inverse time;
ANSI standard curve Normal inverse time; +40ms, when 2 < I 2 / I 2set<20 ,
Very inverse time; it meets ANSI/IEEEC37.112
Extreme inverse time; standard
  ≤ ±5% setting value or
 
User defined curve =

t 
A 
+ B ⋅T +40ms, when 2 < I 2 / I 2set<20 ,
P
  I2  −1  it meets IEC60255-151
  I 2set   standard
0.001～1000
time A
Time delay of inverse time
0.000～100.00
B
Reset time Approx. 40ms
66
Chapter 8 Undercurrent protection (37)
Chapter 8 Undercurrent protection

(37)
About this chapter

This chapter describes the low current protection principle,
67
1 Overview
Low current protection is to prevent when the voltage drops, the charging
capacitor bank supplies power to the power grid.
The device provides a stage of low current protection.
parallel.

The input and output signals of low current protection function diagram are
shown below:
Under Current protection

1 1
En Start
2 2
BIBlk Operation
3
ENA_UI
Figure 28 Diagram of input and output signals of low current protection function
Input:
BinaryInput
CBOpen Circuit breaker trip position
Input:
UI Output:
Start IED startup
Operation IED trip
Input:
ENA
The total connector of Undercurrent protection ， the
ENA_UI
corresponding hard connector is ENA_UI_5.
When undercurrent protection function is enabled and no BI blocking, if
"UCOn"=1, undercurrent protection is enabled.
68
When low current protection is input and the circuit breaker is in close
position, if the three-phase current is lower than the setting value of the
"UCSet", then the protection is started, and after the "UCTime" is delayed,
the protection trips.
Low current protection trip is enabled and the trip conditions are satisfied,
timing component starts, time up, IED issues "UCTrip". LED and protection
trip can be configured by AESP.
Ia<“UCSet”
&
Ib<“UCSet”
Ic<“UCSet”
&
Circuit breaker trip position &
T
Undercurrent trips
BI blocking
Undercurrent protection is on
“UCOn”=1
T：“UCTime”
Figure 29 Logic diagram of low current protection
3.2 Setting list

Table 36 Low current protection setting
Default
value
1. UCSet 0.05In~40In 0.25 0.01 A
2. UCTime 0~100 100 0.01 s
Table 37 Low current protection logic switch
Number Logic switch name Set mode Default value Remark
1. UCOn 1/0 0 1: On; 0: Off
3.3 Report list


Trip report:
1. UCTrip /

Table 39 Low current protection technical parameter

Current setting 0.05In～40.00In ≤ ±2.5% setting value or ±0.02In
≤ ±1% setting or +40ms, when the
Time setting 0.00s~100.00s
tripping value is below 0.5 times of
69
the current setting value
70
Chapter 9 Overvoltage protection (59)
Chapter 9 Overvoltage protection

(59)
About this chapter

This chapter describes the overvoltage principle, the input
and output signals, setting value parameters, reports and
technical parameters.
71
1 Overview
Overvoltage protection is used to prevent the impact of overvoltage on
electrical equipment. The abnormal overvoltage often occurs in low load,
long transmission line; generator voltage regulation fails in the islanded
system, or the load shedding of the generator in the system. Even if the
compensating capacitor can compensate line capacitance, lower the
overvoltage of the lines, when the compensating capacitor fails,
overvoltage will endanger the line insulation system, here the circuit must
be removed.
Overvoltage protection has the following characteristics:
1) Definite time and reverse time are selective on stage 4;
2) Measured voltage can be phase-to-earth voltage or phase-to-phase
voltage;
3) The protection dropoff coefficient of stage 4 can be adjusted
separately;
soft-hard parallel.

The input and output signals of overvoltage protection function diagram
are shown below:
Overvoltage Protection
1 1
BIBlk Start
2 2
ENA_OV Operation
Figure 30 Diagram of input and output signals of overvoltage protection function

Input:
OV Output:
Start IED startup
Operation IED trip
ENA Input:
72
The total connector of overvoltage protection，the corresponding

ENA_OV
hard connector is ENA_OV_5.
Overvoltage protection selects the phase voltage or line voltage through
the on-off logic switch "OVChkPEVolt". Logic switch "OVChkPEVolt" set 1,
select the phase voltage UA-N, UB-N, UC-N; Logic switch "OVChkPEVolt"
set 0, select the line voltage UA-B, UB-C, UC-A. The overovervoltage
protection of stage 1 will be taken as an example in below and the principle
will be introduced.
3.1.1 Definite time
When "OVStage1Curve"=0, overvoltage is the definite time characteristic,
inverse time function is disabled.
U∅ > “OVStage1VoltSet”, (∅ = 𝑎𝑎, 𝑏𝑏, 𝑐𝑐)
When "OVChkPEVolt"=1, use the phase-to-earth voltage; when
"OVChkPEVolt"=0, use the phase-to-phase voltage. When the
phase-to-earth (phase-to-phase) voltage setting is greater than
"OVStage1VoltSet", timing component starts and until timing to the
"OVStage1Time", overvoltage protection trips, when the phase-to-earth
(phase-to-phase) voltage U∅ < OVDropoffCoef × “OVStage1VoltSet” , timing
component returns, overvoltage protection returns.
3.1.2 Inverse time
When "OVStage1Curve"=1-13, overvoltage is the definite time
 
 
 A 
=t  P
+ B ⋅T
  UΦ  −1 
 U set  
Where:
A: "InvTimeOVStage1CoefA"
P: "InvTimeOVStage1IndexP"
B: "InvTimeOVStage1TimeB"
T: "InvTimeOVStage1ConstT"
U Φ : Phase-to-earth/phase-to-phase voltage
U set : OVStage1VoltSet
When "OVChkPEVolt"=1, use the phase-to-earth voltage; when
"OVChkPEVolt"=0, use the phase-to-phase voltage. If the phase-to-earth
(phase-to-phase) voltage exceeds "OVStage1VoltSet", the timing element
starts, inverse time characteristic curve is selected by Curve, A, P, B are
determined when the value is from 1 to 12, see Table 40, when the value is
13, it is user defined characteristics, calculate the trip delay according to
73
the setting of the A, P, B, T. When time is up, overvoltage protection will

trip. When the calculated delay time is shorter than "InvTimeOVMinTime",
the component will trip in accordance with "InvTimeOVMinTime".
0. Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
3. IEC EXTERMELY INV. 80.0 2.0 0
4. IEC SHORT INV 0.05 0.04 0
5. IEC LONG INV. 120.0 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
9. ANSI MODERATELY INV. 0.0103 0.02 0.0228
10. ANSI VERY INV. 3.922 2.0 0.0982
11. ANSI EXTERMELY INV. 5.64 2.0 0.02434
12. ANSI DEFINITE INV. 0.4797 1.5625 0.21359
13. User defined

When overvoltage protection is enabled and there is no binary input
blocking, if "OVStage1On"=1, then overvoltage protection of the
corresponding stage is enabled.
After the starting of protection trip, if the action conditions are met, timing
component starts, take stage 1 for example, when time is over,
"OVStage1Trip" is issued. LED and protection trip can be configured by
AESP.
The three-phase analog quantity U1, U2 and U3 of the trip time issued
when the overvoltage protection trips, the element is based on the
phase-to-earth voltage judgment, it issues three-phase phase-to-earth
voltage; when it is based on the phase-to-phase voltage judgment, it
issues three-phase phase-to-phase voltage.
3.1.4 Logic diagram
The logic diagram of overvoltage protection is shown in following figure.
74
max(Ua,Ub,Uc)>“OVStage1VoltSet” &
“OVChk1Ph”=1 ≥1
min(Ua,Ub,Uc)>“OVStage1VoltSet” &
“OVChk1Ph”=0
&
“OVChkPEVolt”=1
max(Uab,Ubc,Uca)>“OVStage1VoltSet” &
min(Uab,Ubc,Uca)>“OVStage1VoltSet” &
& &
T1
Overvoltage stage 1 trips
“OVChkPEVolt”=0
Overvoltage stage 1 protection is on
“OVStage1On”=1
T1：“OVStage1Time”
Figure 31 Logic diagram of overvoltage protection
3.2 Setting list

Table 42 Overvoltage protection setting
Default
value
1. OVStage1VoltSet 40.00~200.0 110 0.01 V
2. OVStage1Time 0.00~120.00 120 0.01 s

0: Definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7:ANSI
3. OVStage1Curve 0~13 0 1
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
75
Default
value
13: User
defined
Inverse time
4. InvTimeOVStage1CoefA 0.001~1000 10 0.001
characteristic
5. InvTimeOVStage1IndexP 0.01~10.00 10 0.01
6. InvTimeOVStage1TimeB 0.000~100.00 100 0.01
7. InvTimeOVStage1ConstT 0.025~1.5 0.025 0.001
9. OVStage2Time 0.00~120.00 120 0.01 S

Inverse time
characteristic
16. OVStage3Time 0.00~120.00 120 0.01 S

Inverse time
characteristic
23. OVStage4Time 0.00~120.00 120 0.01 S

Inverse time
characteristic
29. InvTimeOVMinTime 0.100~100.00 0.1 0.01 s
30. OVStage1DropoffCoef 0.95~1 1 0.01
76
Table 43 Overvoltage protection logic switch

Setting Default
Mode value
1-phase-to-earth voltage;
1. OverVoltChkPEVolt 1/0 0
0-phase-to-phase voltage
1-check phase 1; 0-check
phase 3
2. OVChk1Ph 1/0 0 When “3PhVoltConnect”
Connect is 0, only “OVChk1Ph”
is enabled
3. OVStage1On 1/0 0 /
3.3 Report list


Trip report:
1. OVStage1Trip /
2. OVStage2Trip /
3. OVStage3Trip /
4. OVStage4Trip /

Table 45 Overvoltage protection technical parameter
Voltage wiring type Line voltage or phase voltage ≤ ±2.5% setting or ±1V
Phase voltage setting value 40V～100V ≤ ±2.5% setting or ±1V
Line voltage setting 80V～200V ≤ ±2.5% setting or ±1V
Dropoff coefficient 0.95～1 ≤ ±3% setting
≤ ±1% setting or +60ms
Time delay setting 0.00s~120.00s
At 1.2 times of trip voltage
Reset time <40ms
Phase voltage setting value 40V～100V ≤ ±2.5% setting or ±1V
Line voltage setting 80V～200V ≤ ±2.5% setting or ±1V
Normal inverse time; In the case of
Very inverse time; 2 < U / Uset<20 , the
IEC standard curve
Extreme inverse time; allowable trip time error is:
Long inverse time; ±5% or +60ms;
77

Short inverse time
In the case of
Long inverse time;
2 < U / Uset<20 , the
ANSI standard curve Normal inverse time;
allowable trip time error is:
Very inverse time;
±5% or +60ms;
Extreme inverse time;
 
  In the case of
A
User defined curve =t  + B  ⋅T 2 < U / Uset<20 , it meets the
  U P 
  −1  IEC60255-151 standard
 Uset  
0.001～1000
time A
78
Chapter 10 Zero sequence voltage protection (64)
Chapter 10 Zero sequence voltage

protection (64)
About this chapter

This chapter describes the zero sequence voltage principle,
79
1 Overview
Zero sequence voltage protection is generally used in the power network
with small grounding fault current.
The main features of zero sequence voltage protection are as follows:
1) It provides 3 stages of definite and reverse time selective protection;
2) Fault phase selection function;
3) Zero sequence voltage 3U0 can be selected as self-produce zero
sequence voltage (the total of three phase measurement voltage), or
external zero sequence voltage (zero sequence residual voltage).
soft-hard parallel.

The input and output signals of zero sequence voltage protection function
are shown below:
Voltage Displacement Protection

1 1
BIBlk Start
2 2
ENA_ZSOV Operation
Figure 32 Diagram of input and output signals of zero sequence voltage protection
function
Input:
ZSOV Output:
Start IED startup
Operation IED trip
Input:
ENA
The total connector of zero sequence voltage protection，the
ENA_ZSOV
corresponding hard connector is ENA_ZSOV_5.
Zero sequence voltage protection is used for ground fault check. Zero
80
sequence voltage protection can be set as alarm or trip, definite and

reverse time are selective.
Compare the external or self-produce zero sequence voltage and the
corresponding setting value, if it is greater than the setting, trip timer starts.
Timer starts timed to the user defined time delay. The time delay setting
can be adjusted independently by settings. When time delay defined by
the users is over, the protection device sends out a trip command. The
zero sequence voltage protection stage 1 will be taken as an example
below and the principle will be introduced.
3.1.1 Definite time
When "3U0Stage1CurveSel" =0, zero sequence voltage is the definite time
characteristic.
3U0 > “3U0Stage1VoltSet”
If the zero sequence voltage exceeds the defined time startup setting
"3U0Stage1VoltSet", the start signal is triggered and timing component
starts, time to "3U0Stage1Time", zero sequence voltage protection trips.
3.1.2 Inverse time
When "3U0Stage1CurveSel" =1~13, zero sequence voltage trips as the
inverse time characteristic.
 
 
 A 
=t  P
+ B ⋅T
  3U 0  − 1 
  3U 0set  
Where:
A: "InvTime3U0Stage1CoefA"
P: "InvTime3U0Stage1IndexP"
B: "InvTime3U0Stage1TimeB"
T: "InvTime3U0Stage1ConstT"
3U 0 : Zero sequence voltage
3U 0set : 3U0Stage1VoltSet
If the zero sequence voltage exceeds "3U0Stage1VoltSet", Start signal is
triggered and the timing component starts, inverse time characteristic
curve is selected by curve, A, P, B are determined when the value is from
1 to 12, see the table 46; when the value is 13, it is the user defined
characteristic, calculate the trip delay in accordance with the setting of the
A, P, B, T. When time is over, zero sequence voltage protection will trip.
When the calculated delay time is less than the "InvTime3U0MinTime", the
component will trip according to the "InvTime3U0MinTime".
0. Definite time
81
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
3. IEC EXTERMELY INV. 80.0 2.0 0
4. IEC SHORT INV 0.05 0.04 0
5. IEC LONG INV. 120.0 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
9. ANSI MODERATELY INV. 0.0103 0.02 0.0228
10. ANSI VERY INV. 3.922 2.0 0.0982
11. ANSI EXTERMELY INV. 5.64 2.0 0.02434
12. ANSI DEFINITE INV. 0.4797 1.5625 0.21359
13. User defined

When zero sequence voltage protection is enabled and no binary input
blocking, if "3U0Stage1On"=1, then zero sequence voltage protection of
corresponding stage is enabled.
Zero sequence voltage protection is tripped, after the starting of protection
trip, if the action conditions are met, timing component starts, take stage 1
for example, when time is over, and “3U0Stage1Trip" is issued. LED and
Zero sequence voltage protection simultaneously outputs the trip value at
the corresponding time during operation.
If the "3PhVoltConnect" is 0, when "Extr3U0" is 1, it was considered to be
a setting error, output "3U0SetErr", and block the zero sequence voltage
protection function.
When VT fails, blocking zero voltage calculated protects; when UO fails,
blocking zero voltage external protects.
3.1.4 Fault phase selection
Fault phase selection logic shall be started when the zero sequence
voltage protection trips, fault phase selection function is enabled.
The three phase voltage is connected to the device with the star
connection mode, measure the three-phase voltage to ground, and
compare the measured values with the "DeadVoltSet" and "LiveVoltSet"
respectively. If the voltage of any phase of the three-phase voltage is lower
than the "DeadVoltSet" and the voltages of other two phases are higher
than the "LiveVoltSet", the ground fault of the low voltage phase is
82
determined.
When the "DeadVoltSet" is greater than the "LiveVoltSet", it is considered
as the error of the setting and output the report of "3U0SetErr", lock fault
phase selection function.
3.1.5 Logic diagram
Zero sequence voltage grounding fault logic diagram is shown below:
Fault phase selection is on
&
Ua>“LiveVoltSet”
Phase A fault
Ua<“DeadVoltSet”
&
Ub>“LiveVoltSet”
Phase B fault
Ub<“DeadVoltSet”
&
Uc>“LiveVoltSet”
Phase C fault
Uc<“DeadVoltSet”
Figure 33 Logic diagram of zero sequence voltage grounding fault
3.2 Setting list

Table 48 Zero sequence voltage protection setting
Default
value
1. 3U0Stage1VoltSet 2.00~100.0 100 0.01 V
2. 3U0Stage1Time 0.00~120.00 120 0.01 s

0: Definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
3. 3U0Stage1Curve 0~13 0 1
7:ANSI SHORT
INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI VERY
INV.
11: ANSI
EXTERMELY
INV.
83
Default
value
12: ANSI
DEFINITE INV.
13: User defined
InvTime3U0Stage1Co
4. 0.001~1000 10 0.001
efA
InvTime3U0Stage1Ind
5. 0.01~10.00 10 0.01
exP
InvTime3U0Stage1Tim
6. 0.000~100.00 100 0.01
eB
InvTime3U0Stage1Co
7. 0.025~1.5 0.025 0.001
nstT
8. 3U0Stage2VoltSet 2.00~100.0 100 0.01 V
9. 3U0Stage2Time 0.00~120.00 120 0.01 s
11. 3U0Stage2CoefA 0.001~1000 10 0.001
12. 3U0Stage2IndexP 0.01~10.00 10 0.01
13. 3U0Stage2TimeB 0.000~100.00 100 0.01
14. 3U0Stage2ConstT 0.025~1.5 0.025 0.001
15. 3U0Stage3VoltSet 2.00~100.0 100 0.01 V
16. 3U0Stage3Time 0.00~120.00 120 0.01 s
18. 3U0Stage3CoefA 0.001~1000 10 0.001
19. 3U0Stage3IndexP 0.01~10.00 10 0.01
20. 3U0Stage3TimeB 0.000~100.00 100 0.01
21. 3U0Stage3ConstT 0.025~1.5 0.025 0.001
22. InvTime3U0MinTime 0.100~100.00 0.1 0.01 s
23. DeadVoltSet 10.00~100.0 30 0.01 V
24. LiveVoltSet 40.00~100.0 80 0.01 V
Table 49 Zero sequence voltage protection binary setting

Logic switch Default
Number Range Remark
name value
1. 3U0Stage1On 1/0 0
Zero sequence voltage voltage
self-produce or external
4. Extr3U0 1/0 0 1-Zero sequence voltage voltage external;
0-zero sequence voltage
voltage-calculated
84
3.3 Report list


Trip report:
1. 3U0Stage1Trip /
2. 3U0Stage2Trip /
3. 3U0Stage3Trip /
4. PhAEarth /
5. PhBEarth /
6. PhCEarth /
Alarm report:
1. 3U0SetErr /

Table 51 Zero sequence voltage protection technical data
Operating voltage 3V0
2V/100V ≤ ±5% setting or 1V
(self-produced)
≤ ±1% setting or + +60ms,
Trip time 0.00s～120.00s when trip voltage is set as
120% of setting
Dropout ratio About 0.95
Operating voltage 3V0
2V～100V ≤ ±5% setting or 1V
(calculated)
Very inverse time; 2 < 3U 0 / 3U 0set<20 , the
IEC standard curve
Extreme inverse time; allowable trip time error is: ±
Long inverse time; 5% or +60 ms
Short inverse time In the case of
Long inverse time;
2 < 3U 0 / 3U 0set<20 , the
Very inverse time; allowable trip time error is: ±
Extreme inverse time; 5% or +60ms
 
  In the case of
 A 
User defined curve =t  P
+ B ⋅T 2 < 3U 0 / 3U 0set<20 , it meets
  3U 0  − 1  the IEC60255-151 standard
  3U 0set  
0.001～1000
time A
85
Chapter 11 Negative sequence voltage protection (47)
Chapter 11 Negative sequence

voltage protection (47)
About this chapter

This chapter describes the negative sequence voltage
principles, the input and output signals, setting parameters,
87
1 Overview
In normal operating three-phase system, the negative sequence voltage is
almost 0, and the negative sequence voltage will occur when there is
asymmetrical situation in the system. Negative sequence voltage
protection is operated by checking negative sequence voltage.
Main characteristics of the negative sequence voltage protection are as
follows: offer 4 stages of protection, definite time or inverse time can be
selected.
parallel.

The input and output signals of negative sequence voltage protection
Negative Sequence Over Voltage
Protection
1 1
BIBlk Start
2 2
ENA_NSOV Operation
Figure 34 Diagram of input and output signals of negative sequence voltage protection
function
Input:
NSOV Output:
Start IED startup
Operation IED trip
Input:
ENA
The total connector of negative sequence voltage protection，
ENA_NSOV
the corresponding hard connector is ENA_NSOV_5.
The negative sequence voltage protection stage 1 will be taken as an
example below and the principle will be introduced.
3.1.1 Definite time
88
When "3U2Stage1Curve"=0, negative sequence voltage is the definite

time characteristic, inverse time function is disabled.
The negative sequence voltage protection trip voltage is calculated by the
three-phase voltage as follow:
3U̇ 2 = U̇ A + a2 U̇ B + aU̇ C
3U2 > “3U2Stage1VoltSet”
If the voltage is exceeds "3U2Stage1VoltSet", timing component starts and
until timing to "3U2Stage1VoltSet", negative sequence voltage protection
trips.
Where:
U 2 : Negative sequence voltage
3.1.2 Inverse time

When "3U2Stage1Curve"=13, negative sequence voltage is the inverse
time characteristic, definite time function is disabled.
 
 
 A 
=t  P
+ B ⋅T
  U2  −1 
 U 2set  
If the voltage exceeds "3U2Stage1VoltSet", the timing component starts,

inverse time characteristic curve is selected by inverse time characteristic
curve, A, P, B are determined when the value is from 1 to 12, see Table 52;
when the value is 13, it is the user defined characteristics, calculate the trip
delay in accordance with the setting of the A, P, B, T. When time is up,
negative sequence voltage protection will trip. When the calculated delay
time is shorter than "InvTimeU2MinTime", the component will trip in
accordance with "InvTimeU2MinTime".
Where:
A: "InvTime3U2Stage1CoefA"
P: "InvTime3U2Stage1IndexP"
B: "InvTime3U2Stage1TimeB"
T: "InvTime3U2Stage1ConstT"
U 2 : Negative sequence voltage
U 2 set : 3U2Stage1VoltSet
0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
89
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE

When negative sequence voltage protection function is enabled and there
is no binary input blocking, if "3U2Stage1On"=1, then the negative
sequence voltage protection is enabled.
After the protection trip starts, if the trip conditions are satisfied, timing
component starts, and works till the IED issues "3U2Stage1Trip". LED and
3.2 Setting list

Table 54 Negative sequence voltage protection setting
Default
value
3 times of
negative
1. 3U2Stage1VoltSet 40~100.00 100 0.01 V
sequence
voltage
2. 3U2Stage1Time 0.00~100.00 100 0.01 s
0: Definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7:ANSI
SHORT INV.
8: ANSI LONG
INV.
90
Default
value
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
4. InvTime3U2Stage1CoefA 0.001~1000 10 0.001
5. InvTime3U2Stage1IndexP 0.01~10.00 10 0.01
6. InvTime3U2Stage1TimeB 0.000~100.00 100 0.01
7. InvTime3U2Stage1ConstT 0.025~1.5 0.025 0.001
3 times of
negative
8. 3U2Stage2VoltSet 40~100.00 100 0.01 V
sequence
voltage
9. 3U2Stage2Time 0.00~100.00 100 0.01 s
10. InvTime3U2Stage2Curve 0~13 0 1
15. InvTime3U2MinTime 0.100~100.00 0.1 0.01 s
3 times of
negative
16. 3U2Stage3VoltSet 40~100.00 100 0.01 V
sequence
voltage
17. 3U2Stage3Time 0.00~100.00 100 0.01 s
3 times of
negative
23. 3U2Stage4VoltSet 40~100.00 100 0.01 V
sequence
voltage
24. 3U2Stage4Time 0.00~100.00 100 0.01 s
91
Table 55 Negative sequence voltage protection logic switch

1. 3U2Stage1On 1/0 0 1: On; 0: Off
2. 3U2Stage2On 1/0 0 1: On; 0: Off
3. 3U2Stage3On 1/0 0 1: On; 0: Off
4. 3U2Stage4On 1/0 0 1: On; 0: Off
3.3 Report list


Trip report:
1. 3U2Stage1Trip /
2. 3U2Stage2Trip /
3. 3U2Stage3Trip /
4. 3U2Stage4Trip /

Table 57 Negative sequence voltage protection technical data

Trip voltage 3U2 (calculated) 40V～100V ≤ ±5% setting or 1V
≤ ±1% setting or + +60ms,
Time setting 0.00s～100.00s when trip voltage is set as
120% of setting
Dropout ratio About 0.95
Trip voltage 3U2 (calculated) 2V～100V ≤ ±5% setting or 1V

, the
IEC standard curve
Very inverse time; 2 < U 2 / U 2set<20
Extreme inverse time; allowable trip time error is: ±
Long inverse time; 5% or +60 ms

Short inverse time In the case of
Long inverse time; , the
2 < U 2 / U 2set<20
Very inverse time; allowable trip time error is: ±
Extreme inverse time; 5% or +60 ms
In the case of
A , it meets
User defined curve � i + B� k 2 < U 2 / U 2set<20
( )P -1
I_SET
the IEC60255-151 standard
0.001～1000
time A
92

93
Chapter 12 Undervoltage protection (27)
Chapter 12 Undervoltage protection

(27)
About this chapter

This chapter describes the principles of undervoltage
protection, the input and output signals, setting parameters,
95
1 Overview
Undervoltage protection can effectively protect the power equipment from
the impact of voltage drop.
The main features of undervoltage protection are as follows:
1) It provides 4 stages of protection, definite and inverse time can be
selected;
2) Undervoltage protection voltage can be selected as phase voltage or
line voltage;
3) Low voltage blocking current check;
4) State check of circuit breaker;
5) VT failure check, VT failure blocking undervoltage protection;
6) Dropoff coefficient is adjustable.
soft-hard parallel.

The input and output signals of undervoltage protection function are shown
below:
Undervoltage Protection
1 1
BIBlk Start
2 2
CBOpen Operation
3
ENA_UV
Figure 35 The input and output signal diagram of undervoltage protection function
Input:
BinaryInput
Input:
UV Output:
Start IED startup
Operation IED trip
ENA Input:
96
The total connector of Undervoltage protection ， the

ENA_UV
corresponding hard connector is ENA_UV_5.
Four-stage undervoltage protection of device configuration, phase
voltage/line voltage is available, definite/inverse time is available, see
details in setting value list. The undervoltage protection stage 1 will be
taken as an example below and the principle will be introduced.

Undervoltage protection can provide 4 stages of protection, with selectable
definite/inverse time. Take the undervoltage 1 stage as the example, it can
be enabled or disabled via the enabled/disabled platen "UVStage1On".
With the enabled logic switch "UVChkPEVolt", the undervoltage protection
operation voltage setting can choose phase-to-earth voltage UA-N, UB-N,
UC-N, otherwise, it chooses phase-to-phase voltage UA-B, UB-C, UC-A.
With the limit of field condition, the voltage transformer of the circuit
breaker may be connected to the power supply side or the load side. The
installation position of VT is different, and the operation characteristics of
undervoltage protection are different. As the undervoltage protection starts
tripping and the breaker is off, the voltage beside power supply stays
unchangeable but the voltage beside load drops to zero, now undervoltage
protection returns. If the voltage transformer is installed on the power
supply side, and does not want to protect the undervoltage detection
current, the setting of "UVChkCurrOn" can be set to 0. In addition, the
undervoltage protection can also be controlled by the word
"UVChkCBState" to choose whether the action logic is to detect the circuit
breaker status. When the undervoltage protection is required to check the
circuit breaker state, the undervoltage protection sends out the trip
command only when the circuit breaker is closed. If the voltage
transformer is installed on the power supply side, and does not want the
undervoltage protection to check circuit breaker status, the logic switch
"UVChkCBState" is set to 0.
3.1.1 Blocking condition
When "UVChkCBState"=1, circuit breaker will be checked at blocking
protection during the trip, with non-blocking protection starting and
blocking protection delaying.
When the maximum value of the three-phase current is less than
"UVCurrSet", the blocking is protected, the non-blocking protection starts,
and the blocking is delayed.
As VT failure blocking is 1, the blocking is protected, the non-blocking
protection starts, and the blocking is delayed.
When "UVChkCBState"=1, and three-phase voltage is lower than
"3PhUVBlkSet", or when "UVChkCBState"=0 and three-phase voltage is
lower than the 1.732 times of "3PhUVBlkSet", the blocking is protected,
and the blocking protection starts.
3.1.2 Definite time
When "UVStage1CurveSel"=0, undervoltage is the definite time
97
characteristic, and inverse time function is disabled.

𝑈𝑈 < “UVStage1VoltSet”
When the voltage is lower than "UVStage1VoltSet", timing component
starts and works until "UVStage1Time", then undervoltage protection trips.
When current 𝑈𝑈 > 𝐷𝑟𝑜𝑝𝑜𝑢𝑡 × “UVStage1VoltSet” , timing component and
undervoltage protection reset.
3.1.3 Inverse time
When "UVStage1CurveSel"=1~4, undervoltage is the inverse time
characteristic, definite time function is disabled.
 
 
A
=t  + B  ⋅T
  U P 
1 −   
 Uset  
If the voltage is lower than "UVStage1VoltSet", the timing component
starts, inverse time characteristic curve is selected by
"UVStage1CurveSelection", A, P, B are determined when the value is from
1 to 3, see Table 58; when the value is 4, it is the user defined
characteristics, calculate the trip delay in accordance with the setting of the
A, P, B, T. When time is up, undervoltage protection trips. When the
calculated delay time is shorter than "InvTimeUVMinTime", the component
trips in accordance with "InvTimeUVMinTime".
Where:
A: "InvTimeUVStage1CoefA"
P: "InvTimeUVStage1IndexP"
B: "InvTimeUVStage1TimeB"
T: "InvTimeUVStage1ConstT"
U : Voltage
Uset : "UVStage1VoltSet"
0. Definite time
1. Curve1 1 1 0
2. Curve 2 40 2 1
3. Curve 3 5 2 2
4. User defined

When undervoltage protection is enabled and there is no binary input
blocking, if "UVStage1On"=1, then undervoltage protection is enabled.
When "UVChkPEVolt"=1, check phase-to-earth voltage; when
"UVChkPEVolt"=0, check phase-to-phase voltage.
98
While "3PhVoltConnec"=1, three phases can be equipped with "OR" logic

and the protection starts while at least one voltage is lower than the setting;
it can also be equipped with "AND" logic, and the protection starts while
three voltages are all lower than the setting.
While "3PhVoltConnec"=0, that is, the single phase VT is connected, it is
fixed as the "AND" logic and need to take the maximum phase-to-earth
(phase-to-phase) voltage to judge.
After the starting of protection trip, if the action conditions are met, timing
component starts, take stage 1 for example, when time is over,
"UVStage1Trip" is issued. LED and protection trip can be configured by
AESP.
The three-phase analog quantity U1, U2 and U3 of the trip time issued
when the undervoltage protection trips, the element is based on the
phase-to-earth voltage judgment, it issues three-phase phase-to-earth
voltage; when it is based on the phase-to-phase voltage judgment, it
issues three-phase phase-to-phase voltage.
3.1.5 Logic diagram
Ua<“UVStage1VoltSet”
≥1
&
Ub<“UVStage1VoltSet”
Uc<“UVStage1VoltSet”
“UVChk1Ph”=1 ≥1
“UVChk1Ph”=0
Ua<“UVStage1VoltSet”
& &
&
Ub<“UVStage1VoltSet”
Uc<“UVStage1VoltSet”
“UVChkPEVolt”=1
≥1
VoltProtFcnOn Undervoltage stage 1 protection is on
“UVChkPEVolt”=0
Uab<“UVStage1VoltSet”
≥1
& &
Ubc<“UVStage1VoltSet”
Uca<“UVStage1VoltSet”
“UVChk1Ph”=1
≥1
“UVChk1Ph”=0
Uab<“UVStage1VoltSet”
&
&
Ubc<“UVStage1VoltSet”
Uca<“UVStage1VoltSet”
99
“UVStage1On”=1
Undervoltage stage 1 protection is on
BI blocking

≥1
“UVChkCBState”=1 &
T1
Undervoltage stage 1 trips
“UVChkCBState”=0
max(Ia,Ib,Ic)>“UVCurrSet” &
≥1
≥1
“UVChkCurrOn”=1
“UVChkCurrOn”=0
VT failure blocking
Ua<“3PhUVBlkSet”
Ub<“3PhUVBlkSet”
&
Uc<“3PhUVBlkSet”
“UVChkPEVolt”=1
≥1
“UVChkPEVolt”=0
Uab<“1.732×3PhUVBlkSet”
&
Ubc<“1.732×3PhUVBlkSet”
Uca<“1.732×3PhUVBlkSet”
T1：“UVStage1Time”
Figure 36 Logic diagram low current protection
3.2 Setting list

Table 60 Voltage setting of undervoltage protection
Default
value
1. UVStage1VoltSet 5.00~150 100 0.01 V
2. UVStage1CurveSel 0.00~120.0 120 0.01 s
0: Definite
time
1: A-1; P-1;
B-0
2: A-40; P-2;
3. UVStage1CurveSel 0~4 0 1
B-1
3: A-5; P-2;
B-2
4: User
defined
4. InvTimeUVStage1CoefA 0.001~1000 10 0.001
5. InvTimeUVStage1IndexP 0.01~10.00 10 0.01
6. InvTimeUVStage1TimeB 0.000~100.00 100 0.01
7. InvTimeUVStage1ConstT 0.025~1.5 0.025 0.001
100
Default
value
9. UVStage2Time 0.00~120.0 120 0.01 s
0: Definite
time
1: A-1; P-1;
B-0
2: A-40; P-2;
B-1
3: A-5; P-2;
B-2
4: User
defined
16. UVStage3Time 0.00~120.0 120 0.01 s
0: Definite
time
1: A-1; P-1;
B-0
2: A-40; P-2;
B-1
3: A-5; P-2;
B-2
4: User
defined
23. UVStage4Time 0.00~120.0 120 0.01 s
0: Definite
time
1: A-1; P-1;
B-0
2: A-40; P-2;
24. UVStage4Curve 0~4 0 1
B-1
3: A-5; P-2;
B-2
4: User
defined
101
Default
value
29. InvTimeUVMinTime 0.100~100.00 0.1 0.01 s
30. UVCurrSet 0.04In~40In 10 0.01 A
31. UVStage1DropoffCoef 1.0~2.00 1.02 0.01
35. 3PhUVBlkSet 0-40 2 0.01 V
Table 61 Overvoltage protection Logic switch

Number Set mode Remark
name value
1-undervoltage stage 1 on, 0-
1. UVStage1On 1/0 0
undervoltage stage 1 off
1-undervoltagestage 2 on,
2. UVStage2On 1/0 0
0-undervoltage stage 2 off
1-undervoltage stage 3 on, 0-
3. UVStage3On 1/0 0
undervoltage stage 3 off
1-undervoltage stage 4 on, 0-low
4. UVStage4On 1/0 0
voltage stage 4 off
1-undervoltage check CB state;
5. UVChkCBState 1/0 0
0-undervoltage don't check CB state
1-undervoltage check phase 1 voltage;
6. UVChk1Ph 1/0 0
0-undervoltage check phase 3 voltage
1-undervoltage check phase voltage;
7. UVChkPEVolt 1/0 0
0-undervoltage check line voltage
8. UVChkCurrOn 1/0 0 1-check current on; 0-check current off
1-three-phase voltage connection,
0-Single-phase voltage connection
3.3 Report list


Trip report:
1. UVStage1Trip /
2. UVStage2Trip /
3. UVStage3Trip /
4. UVStage4Trip /
102

Table 63 Undervoltage protection technical data
PPVolt or phase-to-earth
Accessed voltage ≤ ±2.5% setting or 1V
voltage
Phase voltage setting value 5V～75V ≤ ±2.5% setting or 1V
Line voltage setting 10V～150V ≤ ±2.5% setting or 1V
Dropoff coefficient 1.00～1.05 ≤ ±3% setting value
≤ ± 1% times of setting or
Time setting 0.00s～120.00s +60ms, when trip value is set
at 80% of setting
Reset time ≤50ms
Phase voltage setting value 5V～75V ≤ ±2.5% setting or 1V
Line voltage setting 10V～150V ≤ ±2.5% setting or 1V
In the case of
0.05 < U / Uset<0.5 , the
IEC60255-127
allowable trip time error is: ±
5% or +60 ms
 
  ≤ ±5% setting value or
A
User defined curve =t  + B  ⋅T +60ms, when
  U P  0.05 < U / Uset<0.5 , it meets
1 −    IEC60255-151 standard
 Uset  
0.001～1000
time A
103
Chapter 13 Unbalanced voltage protection (59NU59C)
Chapter 13 Unbalanced voltage

protection (59NU59C)
About this chapter

This chapter describes the principles Voltage imbalance
105
1 Overview
Voltage imbalance protection is used to maintain and protect the
dysfunction inside capacitor.
The protection function has the following characteristic: Three imbalance
voltages can consist of a stage of voltage imbalance protection with
function of enabling and disabling.
parallel.

The input and output signals of voltage imbalance protection function are
shown below:
Unbalance voltage protection
1 1
BIBlk Start
2 2
CBOpen Operation
3
ENA_NU
Figure 37 Diagram of input and output signal of voltage imbalance protection function
Input:
BinaryInput
CBOpen breaker trip
Input:
NU_U Output:
Start IED startup
Operation IED trip
Input:
ENA
The total connector of Voltage unbalance protection，the
ENA_NU
corresponding hard connector is ENA_NU_5.
When unbalanced voltage protection function is enabled and no BI
blocking, if "UnbalanceVoltOn"=1, then the unbalanced voltage protection
is enabled.
106
Voltage imbalance protection provides three channels of check in voltage

imbalance protection. The trip conditions of imbalance voltage imbalance
are shown below:
1) Every unit of imbalance voltage input is higher than setting value of
imbalance voltage;
2) Circuit breaker is at close position;
3) The time delay of imbalance voltage is off.
Trip conditions are met, "UnbalanceVoltTrip" is issued. Light, protection
trip and others can be configured by AESP.
max(U1,U2,U3)>“UnbalanceVoltSet”
&
T
Unbalanced voltage protection is on Unbalanced voltage trips
&
Circuit breaker trip position
BI blocking
“UnbalanceVoltOn”=1
T:UnbalanceVoltTime
Figure 38 Logic diagram of voltage imbalance protection
3.2 Setting list

Table 65 Setting value of Voltage imbalance protection
Default
value
1. UnbalanceVoltSet 1~100.0 100 0.01 V
2. UnbalanceVoltTime 0.00~100.0 100 0.01 s
Table 66 Voltage imbalance protection

Set Default
mode value
1. UnbalanceVoltOn 0, 1 0 0: disable; 1: enable
3.3 Report list


Trip report:
1. UnbalanceVoltTrip /

Table 68 Imbalance voltage protection technical parameter
characteristics of voltage
Phase-to-phase voltage 1V～100V ≤ ±2.5% setting or 1V
107
Dropoff coefficient About 0.95 ≤ ±3% setting value

≤ ±1% times of setting or
Time setting 0.00s～100.00s +60ms, when trip value is set
at 120% of setting
Reset time <40ms
108
Chapter 14 Unbalance current protection
(60N-5051_RLC)
Chapter 14 Unbalance current

protection
(60N-5051_RLC)
About this chapter

This chapter describes the principles imbalance current
109
(60N-5051_RLC)
1 Overview
Current imbalance protection is used to maintain and protect the
dysfunction inside capacitor.
The protection function has the following characteristic: Three imbalance
voltages can consist of a stage of voltage imbalance protection with
function of enabling and disabling.
parallel.

The input and output signals of current imbalance protection function are
shown below:
Unbalance current protection

1 1
BIBlk Start
2 2
CBOpen Operation
3
ENA_NI
Figure 39 Diagram of input and output signal of current imbalance protection function
Input:
BinaryInput
Input:
NU_I Output:
Start IED startup
Operation IED trip
Input:
ENA
The total connector of Current unbalance protection ， the
ENA_NI
corresponding hard connector is ENA_NI_5.
When unbalanced current protection function is enabled and no BI
blocking, if "UnbalanceCurrOn"=1, then the unbalanced current protection
is enabled.
110
(60N-5051_RLC)
Current imbalance protection provides three channels of check in current
imbalance protection. The trip conditions of imbalance current are shown
below:
1) Every unit of imbalance current input is higher than setting value of
imbalance current;
2) Circuit breaker is at close position;
3) The time delay of imbalance current is off.
Meet the trip conditions; the "UnbalanceCurrTrip" is issued. LED and
max(I1,I2,I3)>“UnbalanceCurrSet”
&
T
UnbalanceCurrOn UnbalanceCurrTrip
&
BI blocking
“UnbalanceCurrOn”=1
T：“UnbalanceCurrTime”
Figure 40 Logic diagram of current imbalance protection
3.2 Setting list

Table 70 Setting value of current imbalance protection
Default
value
1. UnbalanceCurrSet 0.05In~40In 40 0.01 A
2. UnbalanceCurrTime 0.00~100.0 100 0.01 s
Table 71 logic switch of current imbalance protection

Set Default
mode value
1. UnbalanceCurrOn 0, 1 0 0: disable; 1: enable
3.3 Report list


Trip report:
1. UnbalanceCurrTrip /

Table 73 Imbalance current protection technical parameter
characteristics of current
Current setting 0.05In～40.00In ≤±2.5% setting or ±0.02In
Time setting 0.00s～100.00s ≤±1% setting or +40ms, when
111
(60N-5051_RLC)
trip current is set as 200%
setting
Dropoff coefficient When I/In≥0.5, it is about 0.95
112
Chapter 15 Thermal overload protection (49)
Chapter 15 Thermal overload

protection (49)
About this chapter

This chapter describes the principles of thermal overload
113
1 Overview
Thermal overload protection protects the device against overheating
caused by overload. Overheating can affect insulation characteristics of
insulation material between transformers, lines and other electrical
equipment. In fact, if the device temperature exceeds the allowable
operating temperature, the insulation material will accelerate aging.
Therefore, special protection should be provided to prevent the protected
equipment from excessive temperature. Since the temperature is
proportional to the square of the current, the thermal overload protection is
based on the square of the measured current flowing through the
protected device. In addition, due to the cumulative effect of over
temperature, the thermal overload protection needs to consider the
historical thermal effect of the device. The device realizes the above
functions by providing a thermal model of the simulated protected device.
In this way, the thermal overload protection of the device has the ability of
memory, which can consider the historical overload and heat loss.
parallel.

The input and output signals of thermal overload protection function
diagram are shown below:
Thermal Overload Protection
1 1
ENA_TOL Start
2
Act1
3
Act2
4
Act3
Figure 41 Diagram of input and output signals of thermal overload protection function
Output:
Start IED startup

When the thermal overload is accumulated to RatioAct1, the alarm
Thermal Act1
is sent.
When the thermal overload is accumulated to RatioAct2, the alarm
Act2
is sent.
When the thermal overload is accumulated to 100%, the trip is
Act3
sent.
Output:
ENA
The total connector of Thermal overload protection ， the
ENA_TOL
corresponding hard connector is ENA_TOL_5.
114
The device provides 1 stage thermal overload trip stage and 2 stage
thermal overload alarm stage. The alarm stage needs to adjust the
"ThermalOLAlarmCoef", which means that the value of the alarm stage trip
setting is the product of the setting of the trip stage and the overload alarm
coefficient. The thermal overload protection function is realized by a
temperature model equivalent to the protected device. Temperature model
(low temperature curve or high temperature curve) is selected from
IEC60255-8 standard. Temperature model can be used to calculate the
temperature rise of each phase current. The maximum temperature rise
calculated from the three-phase current is the trip value of thermal
overload protection.

The temperature rise of each phase is calculated by the following formula:
dΘ I
τ + Θ = ( )2
dτ Iϑ
In which, τ is "ThermalTimeConst", and s is the unit; Iθ is

"ThermalOLCurrSet" that is the maximum permissible continuous thermal
overload current, Θ is the temperature rise of unit per unit time under
maximum allowable thermal overload current, I is the fundamental current
that is measured through the phases of the protected device.
Based on the difference model, the calculation formula of overload trip
time:
 I 2  I 2 
   −  P  
 I 
τ = τ ln   ϑ  2 ϑ  
I
  I  − 1 
  I ϑ  
 
Where IP is the steady current before the overload, the formula is the heat
curve in the IEC60255-8 specification, and the trip time is calculated
according to the cold curve is as follows:
  I 2 
   
 I 
τ = τ ln   ϑ 2 
  I  − 1
  I ϑ  
 
Thermal overload protection can reflect the current fundamental frequency

component or RMS value trip, which are divided into stage 1 trip and stage
2 alarm, when𝐼𝐼 > “ThermalOLCurrSet”, over heat protection starts, take
stage 1 alarm for example, when the thermal overload percentage reaches
"ThermalOLCurrSet1", the report "ThermalOLStage1Alarm" is sent out;
when the thermal load percentage reaches 100%, the report
"ThermalOLTrip" is sent out. Light, protection trip and others can be
configured by AESP after the alarm or trip report is issued.
115
While alarming or tripping, three-phase current value Ia, Ib, Ic of trip

moment and each phase of trip moment are sent out.
When overheating protection is enabled, three-phase thermal
accumulative percentage is sent out timely by ThermalA, ThermalB, and
ThermalC.
The stop load current is 0, and the time coefficient of the equipment in the
process of heat dissipation is the product of "ThermalOLCoolingCoef" and
"ThermalTimeConst".
3.2 Setting list

Table 75 Thermal overload protection setting
Default
value
1. ThermalOLCurrSet 0.05In~40In 40 0.01 A
2. ThermalTimeConst 6~9999 60 0.01 s
3. ThermalOLCoolingCoef 0.1~10 10 0.01
4. ThermalOLAlarmCoef1 0.5~1 1 0.01
5. ThermalOLAlarmCoef2 0.5~1 1 0.01
Table 76 Thermal overload logic switch

Setting Default
Mode value
1. ThermalOLOn 1/0 0 Thermal overload input or output
Input or output of thermal
2. ThermalOLAlarm1On 1/0 0
overload alarm stage
Input or output of thermal
3. ThermalOLAlarm2On 1/0 0
overload alarm stage
4. ThermalCurve 1/0 0 1: hot curve; 0: cool curve
3.3 Report list


Trip report:
1. ThermalOLTrip Thermal overload protection sends off tripping order
Alarm report:
Thermal overload protection sends off alarm 1
1. ThermalOLStage1Alarm
command
Thermal overload protection sends off alarm 2
2. ThermalOLStage2Alarm
command
3.4 Technical data

Table 78 Thermal overload protection technical data
Current setting 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
Thermal overload protection
6s～9999s
heating time constant
Cooling coefficient of thermal 0.1～10
116

overload
 I eq2 
IEC low-temperature curve τ = τ ln  2 2
IEC60255–8,
≤ ±5% times of setting or +40ms
 I eq − I θ 
 I eq2 − I P2 
IEC high-temperature curve τ = τ ln  2 2
IEC60255–8,
≤ ±5% times of setting or +40ms
 I eq − I θ 
117
Chapter 16 Power protection (32F)
About this chapter

This chapter describes the power protection principle, input
and output signals, setting parameter, IED report and
technical data.
119
1 Overview
Generally, the power direction of generator is from generator to bus bar.
However, as long as generator losses excitation or something
dysfunctional, generator is like to operate with motor, which means that the
generator will absorb from system, or inverse power. Inverse protection
plays a role in preventing blade damage caused from overheated turbine
as the steam turbine suddenly stops and shifts to operate with motor.
Power direction protection, over power stage 2, power direction can select
positive or opposite direction through logic switch.
parallel.

Power protection function input and output signals are shown below:
Directional power/reverse power protection

1 1
BIBlk Start
2 2
ENA_POWER Operation
Figure 42 Diagram of input and output signal of power protection function

Input:
OP Output:
Start IED startup
Operation IED trip

Input:
ENA The total connector of Thermal overload protection ， the
ENA_POWER
corresponding hard connector is ENA_POWER_5.
Stage 1 power protection will be taken as an example.

When the logic switch "OutgoLineRvsPowerStage1On" is 1, it can judge
that the incoming line is under inverse power.
120
𝑃 < 0 and |𝑃| > “PowerProtStage1PowerSet”

When the logic switch "OutgoLineRvsPowerStage1On" is 0, it can judge
that the outgoing line is under inverse power.
𝑃 > 0 and |𝑃| > “PowerProtStage1PowerSet”
When power protection function is enabled and no BI blocking, if
"PowerProtStage1On"=1, then the power protection is enabled.
If VT failure or CT failure occurs, the power protection will be blocked.
After starting power protection, and BI blocking is zero, the time delay
capacitor will be on. If the requirements of trip are met, start timing
elements until "PowerProtStage1Trip" is on. LED and protection trip can
be configured by AESP.
As the trip signal is output, the power value at the time of outputting is P
(absolute value).
Power <0
&
“OutgoLineRvsPowerStage1On”=1
≥1
Power absolute value> &
“PowerProtStage1PowerSet” T1
PowerProtStage1Trip
&
“OutgoLineRvsPowerStage1On”=0
Power >0
BI blocking
≥1
Instantaneous VT failure
CT failure
Power protection is on
“PowerProtStage1On”=1
T1：“PowerProtStage1Time”
Figure 43 Logic diagram of power protection function
3.2 Setting list

Table 80 Power protection setting value
Default
value
1. PowerProtStage1PowerSet 0~500 500 0.01 W
2. PowerProtStage1Time 0~100 100 0.01 s
3. PowerProtStage2PowerSet 0~500 500 0.01 W
4. PowerProtStage2Time 0~100 100 0.01 s
Table 81 Power protection logic switch

Set Default
mode value
1. PowerProtStage1On 1/0 0 1: On, 0: Off
121
2. OutgoLineRvsPowerStage1On 1/0 0 1: On, 0: Off
3. PowerProtStage2On 1/0 0 1: On, 0: Off
4. OutgoLineRvsPowerStage2On 1/0 0 1: On, 0: Off
3.3 Report list

Trip report:
1. PowerProtStage1Trip /
2. PowerProtStage2Trip /

Table 83 Power protection technical parameter
characteristics of current
Allowable error of power trip
Power setting 0W～500W
value:±3% or ±0.5Pn
Reset time Less than 55ms
122
Chapter 17 Circuit breaker failure protection (50BF)
Chapter 17 Circuit breaker failure

protection (50BF)
About this chapter

This chapter describes the protection principle, input and
output signals, parameter, IED report and technical data for
circuit breaker failure protection function.
123
1 Overview
CBF protection can detect whether CBF is operating or not during the fault
clearance. This protection can clear the fault by tripping the breaker of
corresponding bus bars as fast backup protection. Once there is a breaker
failure on feeder or transformer, the connected bus bar can be
disconnected from the power grid by CBF protection. In addition, the
device sends out a trip order to the protection of other end of the feeder. In
the event of a circuit breaker failure with a bus bar fault, IED sends the trip
command to the opposite of the feeder.
In order to improve the reliability of circuit breaker failure protection, the
current criterion is added. Three phase current, zero sequence current and
negative sequence current can be selected.
Circuit breaker failure protection can be set to issue a trip command to the
local circuit breaker once again to avoid unnecessary tripping of
surrounding breakers due to misjudgment.
CBF protection has the characteristics as below:
1) 2 trip stages (local breaker retrip and trip the busbar);
2) Transfer trip command to the remote line end in second stage;
3) Internal/ external initiation;
4) Three-phase initiating failure;
5) Breaker auxiliary contact check;
6) Current criteria (including phase-to-earth current, zero and negative
sequence currents) ;
soft-hard parallel.

CBF protection function input and output signal diagram is shown as
follow:
Circuit-Breaker Failure Protection

1
BIBlk
2 1
CBOpen CBF_Init
3 2
CBClose BIAlarm
4 3
CBClose3P Trip1
5 4
BIInitCBFDZ Trip2
6
CBFail
7
TrInit3P
8
ENA_CBF
Figure 44 Diagram of CBF protection function input and output signal

124

Input:
BinaryInput
CBClose Circuit breaker close position
BIInitCBFDZ External BI Initiation CBF
Input:
CBFail CBF Spring discharge binary input
TrInit3P Internal initiating failure signal
CBF_3Trip Output:
CBF_Init Circuit breaker failure startup signal
BIAlarm Circuit breaker failure binary input is abnormal
Trip1 Circuit breaker failure stage I trip
Trip2 Circuit breaker failure stage II trip
Input:
ENA
The total connector of circuit breaker failure protection，the
ENA_CBF
corresponding hard connector is ENA_CBF_5.
3.1 Protection function
CBF protection can be enabled or disabled by setting the logic switch In
the case of the protection function is enabled, the protection function trips,
the relevant protection function start failure protection, and the timing of
the counter works until to setting time delay, and the time delay is set
to“CBFTime1". If the circuit breaker is not switched off after the setting
time, the circuit breaker failure protection sends off the trip order to trip the
circuit breaker (e.g., through a second two trip coil). If the breaker has no
response when the other time delay "CBFTime2", then IED will send off
trip command to trip the corresponding breakers to isolate the fault (e.g.
other breakers on the same bus bar connected with the failure circuit
breaker). After tripping, light, protection trip and others can be configured
by AESP.
The internal and external protection function can both start circuit breaker
failure protection. If the external initiating circuit breaker failure is enabled,
then "3PhCBFStartup" needs to be configurated. The startup of circuit
breaker failure protection and disturbance and fault record of trip need
engineering configuration.
CBF check includes two criteria. The first criterion is detecting the
disappeared current after issuing the trip command. The second criterion
is detecting the auxiliary contacts of breaker.
3.1.1 Current check
125
When the current is disappeared, the breaker is considered to be on the

open position. The first criterion (current criterion) is the most effective way
to detect the position of breaker. The current check, therefore, is used to
detect the breaker position in CBF protection. At this time, the current
measurement of each phase compares with the setting of
'CBFCurrentValue'. Besides, the zero sequence (3İ0 = İA + İB + İC ) or
negative sequence (I2=IA+a2IB+aIC) current can also be used as current
criteria by setting the logic switch. If the IED is set to detect zero and
negative sequence currents, then the zero and negative currents should
be compared with the corresponding settings respectively.
Breaker current detection logic diagram is shown below:
&
Ia >“CBFCurrSet”
Calculated 3I0 >“CBF3I0Set” ≥1

&
≥1 &
3I2 > “CBF3I2Set”
Ib >“CBFCurrSet”
Ic >“CBFCurrSet”
“CBFChk3I0/3I2”=1
&
Calculated 3I0 >“CBF3I0Set” ≥1 ≥1

& CBF current criterion three-phase
≥1 & has live current
&
Calculated 3I0 >“CBF3I0Set” ≥1

&
≥1 &
Figure 45 Logic diagram of breaker current detection
3.1.2 Breaker auxiliary contact check

The IED trip logic does not take the current component as the criterion and
the current criterion is not suitable for CBF protection. Circuit breaker
auxiliary contact position can be used to judge whether the circuit breaker
trips or not. If the logic switch 'CBFChkPosn' is set as 1, then breaker
auxiliary contact criterion is on. If the current criterion is not used in the IED,
then breaker auxiliary contact criterion is used to judge breaker position.
The criteria of breaker auxiliary contact are as follows:
126
Circuit breaker close position &

Close position of
three-phase circuit breaker
&
three-phase initiating failure
CBF current criterion three-phase ≥1
has live current
&
≥1
“CBFChkEPosnCurr”=0
Figure 46 Logic diagram of breaker auxiliary contact judgment
3.1.3 Circuit breaker failure protection trip logic diagram

1) The internal and external initiating logic is shown below:
Failure BI abnormal
External T_alarm &
initiating
failure signal
≥1
Internal 3Phase initiating failure
initiating
failure signal
Figure 47 Logic diagram of internal and external initiating CBF

2) Initiating CBF logic diagram is shown below:
“CBFChkEPosnCurr”=1 &
&
“CBFChkPosn”
&
Close position of ≥1
three-phase circuit breaker
≥1
CBF current criterion

three-phase has live current &
&
Three-phase initiating 3PhCBFStartup
circuit breaker failure
circuit breaker failure
protection function is enabled
Figure 48 Logic diagram of initiating CBF

3) CBF state 1 trip logic diagram is shown below:
T1
CBF 3phase initiating CBF stage 1 trips
T1：“CBFTime1”
Figure 49 Logic diagram of CBF stage 1 trip

4) CBF stage 2 trip logic diagram is shown below:
T2
CBF 3phase initiating
≥1
CBF stage 2 trips
&
0
CBFail input
T2：“CBFTime2”
127
Figure 50 Logic diagram of CBF stage 2
3.2 Setting list

Table 85 The settings of circuit-breaker failure protection
Default
value
1. CBFCurrSet 0.05In~40In 40 0.01 A
3 times of zero
2. CBF3I0Set 0.05In~40In 40 0.01 A sequence
current
3 times of
negative
3. CBF3I2Set 0.05In~40In 40 0.01 A
sequence
current
4. CBFTime1 0.00~100.00 100 0.01 s
5. CBFTime2 0.00~100.00 100 0.01 s
6. CBF BIAlarmTime 0.00~100.00 100 0.01 s
Table 86 Thermal overload logic switch

Set Default
mode value
1. CBFOn 1/0 0 Enable/disable CBF protection
Circuit breaker failure check
2. CBFChk3I0/I2 1/0 0 zero and negative sequence
current/disable
Enable/disable CBF check
3. CBFChkPosn 1/0 0
open position
0: check switch position or
current
1: check switch position or
Circuit breaker failure
current
4. protection check position 1/0 0
The check current here is the
and current
criterion of checking failure
and condition of three-phase
current.
3.3 Report list


Trip report:
1. IntrInitCBF /
2. ExtrInitCBF /
3. CBFStage1Trip /
4. CBFStage2Trip /
Alarm report:
1. CBF BIErr /

Table 88 CBF protection technical data
128

Current setting
Negative sequence current setting 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
Zero sequence current setting
Time 1 of circuit breaker failure 0.00s～100.00s ≤ ± 1% setting or +40 ms,
when trip current is set as
Time 2 of circuit breaker failure 0.00s～100.00s 200% setting
Dropoff coefficient About 0.95
Reset time Less than 20ms
129
Chapter 18 Dead zone protection (50DZ)
Chapter 18 Dead zone protection

(50DZ)
About this chapter

This chapter describes the protection principle, input and
output signals, parameter, IED report and technical data for
dead zone protection.
131
1 Overview
IED provides dead zone protection to detect dead zone fault, i.e. when
breaker is in open position, a fault occurs between CT and breaker. So,
when breaker auxiliary contact shows that the breaker is in open position,
IED can detect fault current of dead zone.
parallel.
For busbar side CT, when dead zone fault occurs, IED trips all breakers on
the busbar where the fault bay is located. Trip logic is shown below:
Trip
busbar
IFAULT
Line 1 Line 2 Line N
Legend:
CBF open position

CBF close position
Figure 51 Logic diagram of busbar side trip

For line side CT, when dead zone fault occurs, IED sends remote trip
command to the other IED which located on the opposite side. Trip logic is
shown below:
132
Internal
trip busbar
IFAULT
Line 1 Line 2 Line N
Trip
Device
Legend:
CBF open position

CBF close position
Figure 52 Logic diagram of line side trip

The input and output signals of dead zone protection function diagram are
shown below:
Dead Zone Protection

1 1
BIBlk Start
2 2
CBOpen Operation
3 3
CBClose Alarm
4
BI_InitCBFDZ
5
SigIntDZ
6
ENA_DZ
Figure 53 Diagram of input and output signals of dead zone protection function

Input:
BinaryInput CBClose Circuit breaker close position
BI_InitCB
External startup dead zone binary input
FDZ
Input:
DZ BIBlk Binary input blocking
SigIntDZ Internal startup dead zone
133
Output:
Start IED startup
Operation IED trip
Alarm Abnormal alarm of external BI
Input:
ENA
ENA_DZ The total connector of dead zone protection，the corresponding
hard connector is ENA_DZ_5.
When dead zone protection function is enabled (En=1) and binary input
blocking is disabled, if "DZProtOn"=1, then the corresponding dead zone
protection is enabled.
The trip conditions are shown below:
1) Trip initiates dead zone protection sign is 1, or external BI initiates
dead zone is 1 and no abnormal alarm of external BI;
2) There should be open position but no close position;
3) I∅ > “DZCurrSet”, (∅ = a, b, c);
4) Enabled or disabled the criterion of zero current and negative
sequence current by setting the logic switch "DZChk3I0/3I2". If the
logic switch is set as 1, the zero or negative sequence current is also
necessary to be larger than the corresponding setting.
If the trip conditions are met, time component starts, when time is over,
"DZTrip" is issued. LED and protection trip can be configured by AESP. At
the same time, the three-phase fundamental current values Ia, Ib, Ic, zero
and negative sequence current of trip time are displayed. When current or
breaker position is not satisfied, timing component returns, dead zone
protection returns. When the existing time of external BI initiating dead
zone is lager than the alarm time, "DZ BIErrAlarm” will be issued. LED and
134
&
“DZChk3I0/3I2”=0
Ia>“DZCurrSet”
Ib>“DZCurrSet”
& ≥1
≥1 &
Ic>“DZCurrSet”
3I0>“DZProt3I0Set”
&
Ib>“DZCurrSet”
Ic>“DZCurrSet”
& ≥1 ≥1
≥1 & Dead zone current
Ia>“DZCurrSet” conditions satisfied
“DZChk3I0/3I2”=0 &
Ic>“DZCurrSet”
Ib>“DZCurrSet”
& ≥1
≥1 &
Ia>“DZCurrSet”
Dead zone protection is on
BI blocking
Dead zone current conditions are satisfied

&
&
3phase trip position T
Dead zone trips
≥1
Tripping initiates dead zone
&
External initiates BI of dead zone T_BIErr
Dead zone protection BI abnormal alarm
“DZProtOn”=1
T：“DZTime”
T_BIErr：“BIErrAlarmTime”
Figure 54 Logic diagram of dead zone
135
3.2 Setting list

Table 90 Dead zone protection setting
Default
value
1. DZCurrSet 0.05In~40In 40 0.01 A
2. DZTime 0~100 100 0.01 s

3 times of zero
3. DZProt3I0Set 0.05In~40In 40 0.01 A
sequence current
3 times of negative
4. DZProt3I2Set 0.05In~40In 40 0.01 A
sequence current
5. BIErrAlarmTime 0.00~100 100 0.01 s
Table 91 Dead zone logic switch

Setting Default
Mode value
1. DZProtOn 1/0 0
2. DZChk3I0/3I2 1/0 0
3.3 Report list


Trip report:
1. DZTrip /
Alarm report:
1. DZ BIErrAlarm /

Table 93 Dead zone protection technical data

≤ ±1% setting or +40ms,
200% setting
Dropoff coefficient About 0.95
136
Chapter 19 Stub protection (50STUB)
Chapter 19 Stub protection

(50STUB)
About this chapter

This chapter describes the protection principle, the input
and output signals, fixed value parameters, messages and
technical parameters for stub protection.
137
1 Overview
The stub protection protects the zone between the CTs and the open
dis-connector. The stub protection is enabled when the open position of
the dis-connector is informed to the IED through connected binary input.
The function enjoys stage 1 time limit settings.
parallel.

Stub protection function input and output signals are shown below:
STUB-Bus Overcurrent Stage

1 1
DSOpen Start
2 2
BIBlk Operation
3
ENA_STUB
Figure 55 Diagram of input and output signals of stub protection function

Input:
BinaryInput
DSOpen Isolation position signal input
Input:
STUB Output:
Start IED startup
Operation IED trip
Input:
ENA
The total connector of stub protection，the corresponding
ENA_STUB
hard connector is ENA_STUB_5.
The stub protection is an overcurrent protection which is only in service if
the status of the line disconnector indicates the open condition. Stub
protection is disabled while the disconnector is at the close position. The
stub protection stage provides one definite time stage with settable delay
time. This protection function can be enabled or disabled via the logic
138
switch. Corresponding current setting value can be inserted in setting.

When the current is greater than the setting value and the time delay is
over, the IED sends out "StubTrip". LED and protection trip can be
configured by AESP.
Ia>“StubCurrSet”
≥1
Ib>“StubCurrSet”
Ic>“StubCurrSet”
&
Isolator open position T
Stub trips
BI blocking
“StubOn”=1
Enable stub protection function
T：“StubTime”
Figure 56 Logic diagram of stub protection function

Logic diagram of application scenarios,
Bus line A
CB1
STUB-Bus
CT1 Overcurrent fault
Line1
Switch1
CB3
CT3
Line2
Switch2
CT2
CB2
Bus line B
Figure 57 3/2 Connection mode of stub protection
3.2 Setting list

Table 95 Setting value of stub protection
Default
value
Current setting of
1. StubCurrSet 0.05In~40In 40 0.01 A
stub protection
Time of stub
2. StubTime 0~100 100 0.01 s
protection
139
Table 96 Stub protection logic switch
1. StubOn 0, 1 0 0: disable; 1: enable
3.3 Report list


Trip report:
1. StubTrip /

Table 98 Stub protection technical parameters

≤±1% setting or +40ms, when trip
Time setting 0.00s~100.00s
current is set as 200% setting
140
Chapter 20 Broken conductor protection (46BC)
Chapter 20 Broken conductor

protection (46BC)
About this chapter

This chapter describes the protection principle, the input
and output signals, fixed value parameters, messages and
technical parameters for disconnection protection.
141
1 Overview
The system will monitor the volume of load in real time.
This protection function has the following characteristics:
1) Be able to test the negative sequence current;
2) Be able to test the ratio of negative and positive sequence current.
soft-hard parallel.

Input and output signals of broken conductor protection are shown below:
Broken Conductor
1 1
BIBlk Start
2 2
CBOpen Operation
3 3
ENA_BC Alarm
Figure 58 Diagram of input and output signals of broken conductor protection function
Input:
BinaryInput
CBOpen breaker trip
Input:
Output:
BC
Start IED startup
Operation IED trip
Alarm IED alarm
Input:
ENA
The total connector of Broken conductor protection，the
ENA_BC
corresponding hard connector is ENA_BC_5.
The logic diagram of CT failure protection is shown in below figure:
142
BrokenConductorOn
&
BI blocking

≥1
“BrokenConductorChkCBPosn”=1
&
T
“BrokenConductorChkCBPosn”=0 Broken conductor trips
3I2>“BrokenConductor3I2Set” &
“BrokenConductorChk3I2”=1 ≥1
“BrokenConductorChk3I2”=0 &
3I2>3I1×“I1/I2Coef”
“BrokenConductorOn”=1
“BrokenConductorTripOn”=1
T：“BrokenConductorTime”
Figure 59 Logic diagram of CT failure protection

Where:
f3I1: secondary side positive sequence current value
f3I2: secondary side negative sequence current value
I2_Set：“BrokenConductor3I2Set”
I2_I1_Set: "I1/I2Coef"
Tset：“BrokenConductorTime”
After IED outputs "BrokenConductorTrip", light, IED trip and others can be
configured by AESP.
If "BrokenConductorTripOn" is 0, after IED outputs
"BrokenConductorAlarm", light, protection trip and others can be
configured by AESP.
3.2 Setting list

Table 100 Broken conductor protection setting
Default
value
3 times of
negative
1. BrokenConductor3I2Set 0.05In~40In 40 0.01 A
sequence
current
2. I1/I2Coef 0.2~1 1 0.01
3. BrokenConductorTime 0~100 100 0.01 s
143
Table 101 Broken conductor protection logic switch

Setting Default
Mode value
1. BrokenConductorOn 1/0 0 0: disable; 1: enable
2. BrokenConductorTripOn 1/0 0 1: trip; 0: alarm

1: test negative sequence
current; 0: test ratio of
3. BrokenConductorChk3I2 1/0 0
positive and negative
current
0: non-check switch
4. BrokenConductorChkCBPosn 1/0 0 position; 1: check switch
position
3.3 Report list


Trip report:
1. BrokenConductorTrip /
2. BrokenConductorAlarm /

Table 103 Technical parameters

≤ ±1% setting or +40ms, when trip
Time setting 0.00s～100.00s
current is set as 200% setting
144
Chapter 21 Overexcitation protection (24)
Chapter 21 Overexcitation protection

(24)
About this chapter

This chapter describes the overexcitation protection
principle, the input and output signals, fixed value
145
1 Overview
The overexcitation protection is used to detect impermissible
overexcitation conditions which can endanger power transformers. The
saturation of the iron core and large eddy current losses led by the
situation that the transformer flux exceeds the related values can cause
impermissible temperature rise in transformer core.
This protection function has the following characteristics:
1) Segment 3 definite time limit, alarm/trip is available; stage 1 inverse
time limit, alarm/trip is available;
2) Phase voltage and line voltage is available.
soft-hard parallel.

The input and output signals of overexcitation protection function diagram
are shown below:
Overexcitation Protection
1 1
BIBlk bDefStart
2 2
ENA_OE bDefAlarm
3
bDefOp
4
bInvStart
5
bInvAlarm
6
bInvOp
Figure 60 Diagram of input and output signals of overexcitation protection function

Input:
Output:
bDefStart Definite time start
OFlux bDefAlarm Definite time alarms
bDefOp Definite time trips

Inverse time startup (used only to configure the number of
bInvStart
inverse time stages)
Inverse time alarm (used only to configure the number of
bInvAlarm
inverse time stages)
Inverse time trip (used only to configure the number of inverse
bInvOp
time stages)
ENA Input:
146
The total connector of overexcitation protection ， the

ENA_OE
corresponding hard connector is ENA_OE_5.
Overexcitation will occur when the load uncouples from system and
voltage regulator can't control the increase of voltage promptly. Similarly,
the overexcitation condition may occur as result of a decrease in frequency,
e.g. isolated system. To protect the power transformer in such conditions,
the overexcitation protection function should start operating when the flux
exceeds the permissible limit value of transformer core. The ratio of
overexcitation protection function measures the voltage to frequency (U/f)
is proportional to the flux density B in transformer core, comparing to the
rated flux density BN. The decision is then made based on the calculated
ratio as is shown in below equation.
B U f
N= =
BN U N f N
Where:
N is the ratio of voltage to frequency calculated by the device.
U and f are the measured voltage and frequency
UN and fN are the rated voltage and frequency of the device.
While the rated frequency is fixed to 50Hz or 60Hz in software, device is
informed about rated voltage by setting “ReferenceVolt” which
corresponds to nominal phase-neutral voltage of the protected transformer
when is transferred to secondary value, using the turn ratio of voltage
transformer. Thus, the use of the overexcitation protection presumes that
measured voltage is connected to the device. Calculation of voltage/hertz
ratio above is performed based on the maximum voltage of the three
phase-neutral or phase-phase voltages. Logic switch “OEUsePEVolt”
determines that overexcitation protection should use phase-to-phase
voltage or phase-to-earth voltage. "3PhVoltConnect" is 0, a line voltage is
input to the external, then the over excitation needs to check the line
voltage, namely "OEUsePEVolt" is 0.
The overexcitation protection includes two definite characteristics (alarm
and trip are optional)) and one thermal characteristic. The latter
characteristic provides an approximate replica of the temperature rise
caused by overexcitation in the protected object. The definite alarm stage
can be enabled or disabled by using logic switch "DefTimeOEStage1On".
Thermal characteristic can be enabled or disabled by "InvTimeOExcitOn".
It should be mentioned that the overexcitation protection can be applied at
HV, MV or LV side of the protected transformer. However, it is not
recommended to apply the function on the transformer side with variable
winding turns such as the transformer side with an installed tap changer.
The overexcitation protection uses phase-to-phase voltage or
phase-to-earth voltage of the corresponding side in their calculations,
based on the setting applied at logic switch “OEUsePEVolt”.
Take protection stage1 as an example, if the definite time alarm is enabled,
147
and the calculated volt/hertz ration exceeds the setting value, then a report
“DefTimeOEStage1Alarm” will be sent by the device after the time delay
setting. Similarly, if the trip definite time is enabled, and the calculated
volt/hertz ration exceeds the setting value, a report
“DefTimeOEStage1Trip” will be sent by the device after the time delay
expiration. Light of alarm and protection trip can be configured by AESP.
If thermal characteristic is enabled in one of transformer sides, it uses the
measured voltage and frequency of the corresponding side, together with
the data from the manufacturer. The points correspond to the desired
tripping times for a given volt/hertz ratios. Intermediate values are
determined by performing linear interpolation by the device. The
overexcitation 1 stage factor can be set to 1.05, and the rest stages
increases by differential 0.05 Ratio range is
1.05~1.70(“InvTimeOEStage14Time”,1.70)The inverse times are set as
below: "InvTimeOEStage1Time", "InvTimeOEStage2Time",
"InvTimeOEStage3Time", "InvTimeOEStage4Time",
"InvTimeOEStage13Time", "InvTimeOEStage14Time". These points are
used to draw the inverse time characteristic curve, as shown in the
following figure:
u/f
V/F(T14)
V/F( T13)
V/F( T12)
V/F( T11)
V/F( T10)
V/F( T9)
V/F( T8)
V/F( T7)
V/F( T6)
V/F( T5)
V/F( T4)
V/F( T3)
V/F( T2)
V/F(T1)
T 14 T 13 T 12 T 11 T 10 T 9 T8 T7 T6 T5 T4 T3 T2 T1
t( s)
Figure 61 Overexcitation characteristics
It can be observed from the above picture that N=1.05, which is the
starting threshold of thermal characteristics stage; the calculated ratio of
voltage to frequency exceeds the starting threshold and the thermal model
increases from 0% to 100% through the counter in the device. If the
counter reaches to 100%, then IED will trip. When the voltage / frequency
ratio is lower than the start threshold, the trip signal will be canceled.
According to the transformer cooling time, the counter will be reduced to
148
zero (the value of thermal model counter is from 100% to 0%). The cooling
time is set as "OECoolingTime".
Inverse time limit characteristics are up to 14 points may be less than 14
points. If the time delay setting of T1-T3 are set as 9999 seconds, then the
inverse time characteristic from the setting stage to stage T1 will be
disabled.
3.2 Setting list

Table 105 Overexcitation protection setting
Default
Number Setting Range Step Unit Description
value
1. DefTimeOEStage1TripSet 1~1.4 1.1 0.01
2. DefTimeOEStage1Time 0~9999 100 0.01 s
3. DefTimeOEStage2TripSet 1~1.4 1.1 0.01
5. DefTimeOE3TripSet 1~1.4 1.1 0.01

Voltage
7. VoltFreqT1Time 0~9999 10 0.01 s frequency T1
time
Voltage
time
Voltage
time
Voltage
time
Voltage
time
Voltage
time
Voltage
time
Voltage
time
Voltage
time
Voltage
time
Voltage
17. VoltFreqT11Time 0~9999 10 0.01 s
frequency T11
149
Default
Number Setting Range Step Unit Description
value
time
Voltage
time
Voltage
time
Voltage
time
Cooling time of
21. OECoolingTime 0.1~9999 25 0.01 s
overexcitation
22. OEDropoffCoef 0.95~1.0 1.0 0.01
Rated setting
23. OEVoltRatedVal 10~120 57.74 0.01 V of phase/line
voltage
24. DefTimeOERstTime 0.0~3.00 0.04 0.01 s
25. InvTimeOERstTime 0.0~3.00 0.04 0.01 s
Table 106 Logic switch of overexcitation protection

Set Default
mode value
Enable definite time limit stage 1
1. DefTimeOEStage1On 1/0 0 function
1-On, 0-Off
Enable definite time stage 1 alarm
2. DefTimeOEStage1Alarm 1/0 0
1-alarm, 0-trip
1-On, 0-Off
1-alarm, 0-trip
1-On, 0-Off
1-alarm, 0-trip
Enable the inverse time limit
7. InvTimeOExcitOn 1/0 0 function
1-On, 0-Off
Enable inverse time alarm
8. InvTimeOEAlarm 1/0 0
1-alarm, 0-trip
Choose phase/line voltage
9. OEUsePEVolt 1/0 0 1-phase-to-earth voltage;
0-phase-to-phase voltage
150
3.3 Report list


Trip report:
1. DefTimeOEStage1Trip /
4. InvTimeOETrip /
Alarm report:
1. DefTimeOEStage1Alarm /
4. InvTimeOEAlarm /
5. OEFrequcncyOverLmt /

Table 108 Overexcitation protection technical data
Reference voltage UN 10V～120V, ≤ ±3% setting or ±1V

Ratio: 1.00～1.70 ≤±2.5% setting or 0.01
Time delay 0.1s～9999s ≤ ±5% setting or ±70ms
1.05/1.10/1.15/1.20/1.25/1.30/1.35
V/F characteristics ≤ ±5% setting or ±70ms
/1.40/1.45/1.50/1.55/1.60/1.65/1.7
Reset time about 70ms
dropoff ratio ≥0.96
≤±5% setting or ±70ms, under
Time delay T 0.1s～9999s
the circumstance of twice trip
Reset time about 70ms
dropoff ratio ≥0.96
151
Chapter 22 Underfrequency protection (81UF)
Chapter 22 Underfrequency
protection (81UF)
About this chapter

This chapter describes the principles of low frequency
153
1 Overview
Underfrequency and load shedding protection monitors the performance of
grid by testing the decreasing frequency. Underfrequency load shedding
will trip and certain load will be eliminated as the frequency is lower than
the settings of underfrequency load shedding protection or other
conditions.
The main features of underfrequency load shedding protection are as
follows:
1) Undervoltage blocking;
2) Frequency changing rate(df/dt) blocking;
3) Circuit breaker position check and loaded current blocking;
4) VT secondary circuit failure blocking.
There are four stages of underfrequency protection and each stage can be
enabled or disabled separately.
parallel.

The input and output signals of underfrequency load shedding protection
are shown below:
Under Frequency protection
1 1
BIBlk Start
2 2
CBOpen Operation
3
ENA_UF
Figure 62 Diagram of input and output signals of underfrequency load shedding

protection
Input:
BinaryInput
CBOpen breaker trip
Input:
BIBlk BIBlk
UF Output:
Start IED startup
Operation IED trip
154
Input:
ENA
The total connector of underfrequency protection ， the
ENA_UF
corresponding hard connector is ENA_UF_5.
3.1.1 Protection function introduction
The principle of underfrequency load shedding protection is--shed in the
line of bay. Specifically, the principle means that each interval will be
configured with underfrequency load shedding protection rather than the
incoming line interval will be configured with underfrequency load
shedding protection and send off tripping command through outlet line
interval. Then, every interval can be set with appropriate frequency
settings to start protection and with appropriate time settings to trip
protection. Based on the principle of shedding in the line of bays, the
device will be offered with 4 stages underfrequency load shedding
protection. Each stage will be enabled or disabled through corresponding
plate and underfrequency load shedding protection will be enabled and
disabled by principal plate, companying with each plate to enable and
disable. Trip frequency of underfrequency load shedding protection can be
tested by input three-phase voltage or single or-phase voltage. To choose
the input voltage mode by enabling and disabling logic switch
"3PhVoltConnect". Take underfrequency load shedding stage 1 as
example, as the measured frequency is lower than settings
"UFLoadShedStage1FreqSet", the timing component will start working;
however, as it delays to the definite time "UFLoadShedStage1TimeSet",
the IED will send out a command "UFStage1Trip". LED and protection trip
can be configured by AESP.
As the trip frequency of underfrequency load shedding protection is
calculated by measuring voltage, underfrequency load shedding protection
will be blocked with meeting the following requirement.
1) When three-phase voltage is connected, the lowest line voltage is
lower than settings, "LoadShedVoltBlkSet". When single-phase
voltage is connected, the highest line voltage is lower than settings,
"LoadShedVoltBlkSet";
2) The device will detect VT disconnection or the device will detect
high-level from VT disconnection;
3) When "LSUFCheckIOn", check current meets the blocking condition.
Loaded current is lower than settings, "LoadShedCurrBlkSet". As
voltage transformer is configured at the side of power supply, it is
useful to detect current setting. As the circuit is blocking,
"LoadShedCurrBlkSet" refers to as the smallest loaded current;
4) Circuit breaker is at open position. If it is in the same case, as voltage
transformer is configured at the side of power supply, it is useful to
detect current setting. Meanwhile, although the frequency is lower
than the low frequency load shedding setting, the protection will not
send off trip command;
5) The frequency changing rate (Δf/Δt) succeeds setting value
155
"FreqDf/dtBlkSet".
3.1.2 Logic diagram
Enable or disable underfrequency protection
“GenlUFLSOn”=1
&
“UFStage1On”=1
Frequency<“UFLSStage1FreqSet”
&
Frequency<54Hz or Frequency>66Hz
System frequency=60Hz ≥1
Frequency<45Hz or Frequency>55Hz &
System frequency=50Hz
VT failure blocking
≥1
3phase trip position
BI blocking
&
≥1 T1 Underfrequency load shedding
max(Ia,Ib,Ic)<“LoadShedCurrBlkSet” &
stage 1 trips
“UFLSChkCurrOn”=1
max(Uab,Ubc,Uca)<“LoadShedVoltBlkSet” &
min(Uab,Ubc,Uca)<“LoadShedVoltBlkSet” & ≥1
Df/dt absolute value>“Df/dtBlkSet” &
“UFLSChkDf/dt”=1
T1：“UFLSStage1Time”
Figure 63 Logic diagram of 1st stage distance protection
3.2 Setting list

Table 110 Settings of underfrequency load shedding protection
Default
value
The
frequency
is greater
than the
1. Df/dtBlkFreqSet 0.9Fn~1.0Fn 49.5 0.01 Hz setting
value,
Df/dt
blocking
dropouts
2. UFLoadShedStage1FreqSet 0.9Fn~1.0Fn 49.5 0.01 Hz
3. UFLoadShedStage1Time 0.00~100.00 100 0.01 s
156
Default
value
10. Df/dtBlkSet 0.10~20.00 20 0.01 Hz/s
11. LoadShedVoltBlkSet 10.00~120.00 120 0.01 V
12. LoadShedCurrBlkSet 0.05In~10In 10 0.01 A
Table 111 Logic switch of underfrequency load shedding protection

Set Default
mode value
Enable or disable underfrequency
1. UFLoadShedGenlOn 1/0 0
load shedding protection function
Enable or disable low frequency
2. UFStage1On 1/0 0
load shedding stage 1 function
3. UFStage2On 1/0 0
4. UFStage3On 1/0 0
Enable or disable underfrequency
5. UFStage4On 1/0 0
load shedding stage 4 protection
6. LoadShedChkDfdt 1/0 0 0: no check df/dt; 1: check df/dt
0: no check Dead current t blocking;
7. UFLoadShedChkCurrOn 1/0 0
1: check Dead current blocking
0: Single phase access;
1: three-phase access
3.3 Report list

Trip report:
1. UFStage1Trip /
2. UFStage2Trip /
3. UFStage3Trip /
4. UFStage4Trip /

Table 113 Underfrequency load shedding protection technical parameter
Underfrequency load shedding
Rated frequency fn=50Hz 45.00Hz～50.00Hz ≤±20mHz
Time setting 0.1s～100.00s ≤ ± 1.5% times of setting or +60ms
Blocking condition
Frequency changing rate Δf/Δt 0.3Hz/s～20Hz/s ≤±0.5Hz/s
Blocking voltage setting 10V～120V ≤ ±2.5% setting or 1V
Blocking current setting 0In～10In ≤ ±2.5% setting or ±0.01In
157
Chapter 23 Overfrequency protection (81OF)
Chapter 23 Overfrequency
protection (81OF)
About this chapter

This chapter describes the principles of overfrequency
159
1 Overview
Overfrequency protection is used to monitor whether the network is normal
by detecting the frequency. When the frequency is higher than the
overfrequency protection setting value and meets other conditions, the
overfrequency protection trips to remove the specified load.
Main characteristics of overfrequency protection are as follow:
2) VT secondary circuit failure blocking;
3) Overfrequency protection configuring stage 4 protection can be
enabled or disabled respectively.
soft-hard parallel.

The input and output signals of overfrequency protection function diagram
are shown below:
Over Frequency protection
1 1
BIBlk Start
2 2
ENA_OF Operation
Figure 64 Diagram of input and output signals of overfrequency protection function

Input:
BIBlk BIBlk
OF Output:
Start IED startup
Operation IED trip
Input:
ENA
The total connector of overfrequency protection ， the
ENA_OF
corresponding hard connector is ENA_OF_5.
160
The device provides 4 stages overfrequency protection, and each stage of

protection is enabled and disabled through the corresponding logic switch.
The overfrequency protection trip frequency can be measured by the input
three-phase voltage or single phase voltage. To choose the input voltage
mode by enabling and disabling logic switch "3PhVoltConnect". Take
overfrequency stage 1 as an example, if the measured frequency is higher
than "OFSatge1FreqSet", the timing component will start timing. As time
delay reaches "OFSatge1Time", the device will issue a command
"OFStage1Trip". LED and protection trip can be configured by AESP.
As the trip frequency of overfrequency protection is calculated by
measuring voltage, overfrequency protection will be blocked with meeting
the following requirement.
1) When three-phase voltage is connected, the lowest line voltage is
voltage is connected, the highest line voltage is lower than settings,
2) The device will detect VT disconnection or the device will detect
high-level from VT disconnection.
3.1.2 Logic diagram
Overfrequency protection is on
&
“OFStage1On”=1
Frequency>“OFSatge1FreqSet”
VT failure blocking
&
≥1 ≥1 T1
Overfrequency stage 1 trips
3phase trip position
BI blocking
“3PhVoltConnect”=0 ≥1
min(Uab,Ubc,Uca)<“LoadShedVoltBlkSet” &
T1：“OFSatge1Time”
Figure 65 Logic diagram of overfrequency stage 1 protection
3.2 Setting list

Table 115 Overfrequency protection setting
Default
value
1. OFSatge1FreqSet 1.00Fn~1.10Fn 50.5 0.01 Hz
2. OFSatge1Time 0.00~100.00 100 0.01 s
161
Default
value
4. OFSatge2Time 0.00~100.00 100 0.01 s
6. OFSatge3Time 0.00~100.00 100 0.01 s
8. OFSatge4Time 0.00~100.00 100 0.01 s
Table 116 Logic switch of overfrequency protection

Logic switch Set Default
Number Remark
name mode value
Enable or disable overfrequency
1. OFStage1On 1/0 0
stage 1 protection function
2. OFStage2On 1/0 0
3. OFStage3On 1/0 0
4. OFStage4On 1/0 0
0: Single phase access; 1:
three-phase access
3.3 Report list


Trip report:
1. OFStage1Trip /
2. OFStage2Trip /
3. OFStage3Trip /
4. OFStage4Trip /

Table 118 Overfrequency protection technical parameter
Overfrequency
Time setting 0.1s～100.00s ≤ ±1.5% times of setting or +60ms
Blocking condition
Blocking voltage setting 10V～120V ≤ ±2.5% setting or 1V
162
Chapter 24 Frequency rate protection (81DF)
Chapter 24 Frequency rate

protection (81DF)
About this chapter

This chapter describes the frequency changing rate
protection principle, input and output signals, setting
parameter, IED report and technical parameter.
163
1 Overview
Frequency changing rate protection is used to monitor whether the
network is normal by detecting the frequency. Device provides four-stage
frequency changing rate protection. If frequency changing rate succeeds
the setting of frequency changing rate protection, frequency changing rate
protection will trip.
parallel.

Frequency changing rate protection function input and output signal
diagram is shown below:
Frequency rate of change protection

1 1
BIBlk Start
2 2
ENA_DF Operation
Figure 66 Frequency changing rate protection function input and output signal
diagram
Input:
BIBlk BIBlk
DF Output:
Start IED startup
Operation IED trip
Input:
ENA
The total connector of frequency change rate protection，the
ENA_DF
corresponding hard connector is ENA_DF_5.
The device offers four-stage frequency changing rate protection. Each
stage will be enabled or disabled through corresponding logic switch and
frequency changing rate protection will be enabled and disabled by
principal logic switch and function of each stage will be enabled or
164
disabled through logic switch of each stage. The trip frequency of

frequency changing rate protection trip frequency can be measured by the
input three-phase voltage or single-phase voltage. To choose the input
voltage mode by enabling and disabling logic switch "3PhVoltConnect".
Take frequency changing rate stage 1 as example, if the absolute value of
the measured frequency changing rate is higher than setting value,
"FreqDf/dtStage1Set", the timing component will start timing. As time delay
reaches "FreqDf/dtStage1TimeSet", the IED will send out a command
"FreqDf/dtStage1Trip". LED and protection trip can be configured by
AESP.
As the trip frequency of frequency changing rate protection is calculated by
measuring voltage, frequency changing rate protection will be blocked with
meeting the following requirement.
1) When logic switch "FreqDf/dtStage1DetectVolt"=1, three-phase
voltage are connected, the minimum phase-to-phase voltage is lower
than settings "LoadShedVoltBlkSet". When single-phase voltage is
connected, the maximum phase-to-phase voltage is lower than
settings "LoadShedVoltBlkSet";
2) The IED can trip, when the frequency is in a certain range, when the
logic switch "Df/dtStage1ChkFreq"=1, and the frequency is not in the
range ("Df/dtStage1LFThreshold"~Df/dtStage1HFThreshold), the IED
will be blocked;
3) The IED can trip, when the frequency changing rate is in a certain
range, when the logic switch "Df/dtStage1ChkFreq"=1, and the
frequency is not in the range
("Df/dtStage1LFThreshold"~Df/dtStage1HFThreshold), the IED will be
blocked;
4) If the frequency is in the valid range (±15Hz of rated frequency), the
protection will be unblocked after 2 seconds.
3.1.2 Logic diagram
165
“GenlFreqDf/dtOn”=1
“FreqDf/dtStage1On”=1
&
“DirModeDf/dtStage1”=3
Absolutely value of change rate of frequency

>“FreqDf/dtStage1Set”
Change rate of frequency>0
&
“DirModeDf/dtStage1”=1 ≥1 & T1
FreqDf/dtStage1Trip
Change rate of frequency<0

&
“DirModeDf/dtStage1”=2
45Hz<Frequency<75Hz &
2s
35Hz<frequency<65Hz &
BI blocking
≥1
Absolutely value of change rate of frequency> ≥1
“FreqDf/dtHighThreshold”
Absolutely value of change rate of frequency<

“FreqDf/dtLowThreshold”
&
“Df/dtStage1ChkFreq”=1
Frequency> ≥1
“Df/dtStage1HFThreshold”
Frequency<
“Df/dtStage1LFThreshold”
max(Uab,Ubc,Uca)<
“FreqDf/dtVoltThreshold” &
min(Uab,Ubc,Uca)< & &

“FreqDf/dtVoltThreshold”
“FreqDf/dtStage1DetectVolt”=1
Enable frequency rate changing function
T1：“FreqDf/dtStage1Time”
Figure 67 Logic diagram of frequency changing rate protection stage 1
3.2 Setting list

Table 120 Frequency changing rate protection setting (81DF)
Default
value
1. FreqDf/dtStage1Set 0.1~20 20 0.01 Hz/s
2. FreqDf/dtStage1Time 0.00~100.00 100 0.01 s
3. Df/dtStage1LFThreshold 45~55 45 0.01 Hz
4. Df/dtStage1HFThreshold 45~55 55 0.01 Hz
166
Default
value
17. FreqDf/dtVoltThreshold 30.00~120.00 50 0.01 V
18. FreqDf/dtHighThreshold 0~20 20 0.01 Hz/s
19. FreqDf/dtLowThreshold 0~20 0.1 0.01 Hz/s
Table 121 Frequency changing rate protection logic switch

Setting Default
Number Logic switchdescription Remark
Mode value
1. GenlFreqDf/dtOn 1/0 0
2. FreqDf/dtStage1On 1/0 0
1: Forward;
3. DirModeDf/dtStage1 1~3 1 2: Reverse;
3: Non-directional
4. FreqDf/dtStage1DetectVolt 1/0 0
5. Df/dtStage1ChkFreq 1/0 0
1: Forward;
3: Non-directional

1: Forward;
3: Non-directional

1: Forward;
3: Non-directional
167
Setting Default
Number Logic switchdescription Remark
Mode value

0: Single phase
access;
1: Three-phase
access
3.3 Report list

Number Message name Remark

Trip report:
1. FreqDf/dtStage1Trip /

Table 123 Technical parameter of frequency changing rate protection
Items Setting range Trip value error
Frequency change rate

Frequency changing rate
0.3Hz/s～20Hz/s ≤±0.5Hz/s
setting Δf/Δt
≤ ±1.5% times of setting or
+60ms
Blocking condition
Upper limit of frequency
0Hz/s～50Hz/s ≤±0.5Hz/s
changing rate
Lower limit of frequency
0Hz/s～50Hz/s ≤±0.5Hz/s
changing rate
Blocking voltage 30V～120V ≤ ±2.5% times of setting or ±1V
168
Chapter 25 Switch-on-to-fault protection
Chapter 25 Switch-on-to-fault
protection
About this chapter

This chapter describes the principles of switch-onto-fault
protection, input and output signals, setting parameter,
169
1 Overview
Switch-onto-fault protection is the sub-protection of overcurrent and zero
sequence current. The function shares similarity in logic trip, trip principle
and trip report. Switch-onto-fault protection will not work if circuit breaker is
closed. The trip time will start function after validity. It is mean that
switch-onto-fault protection will not open in short time.
parallel.

The input and output signals of switch-onto-fault protection function
diagram is shown as below:
Switch-Onto-Fault Protection
1 1
BIBlkOC Start
2 2
BIBlkEF OCOp
3 3
BI_SOTF EFOp
4 4
CBOpen SOTFErr
5
CBClose
6
ENA_SOTF
Figure 68 Diagram of input and output signals of Switch-onto-fault protection function

Input:
BI_SOTF manual close circuit breaker

BinaryInput
CBOpen breaker trip
CBClose Circuit breaker close position
Input:
BIBlkOC BI blocking OC
BIBlkEF BI blocking EF
Output:
SOTF
Start IED startup
OCOp Manual closing fault overcurrent trip
EFOp Manual closing fault zero sequence current trip
SOTFErr Manual close binary input error
ENA Input:
170
The total connector of switch-on-to-fault protection ， the

ENA_SOTF
corresponding hard connector is ENA_SOTF_5.
As circuit breaker is closed for a while, switch-onto-fault protection needs
to be detected that if there is any fault in line through detecting current
value.
As logic switch "SOTFChkBI" is set to 1 and "MC BI" appears falling edge,
then within the delay time "SOTFStateLatchedTime", if 3-phase current is
greater than "SOTFOCSet" and experience "SOTFOCTime" or zero
sequence current is greater than "SOTF3I0Set" and experiences
"SOTF3I0Set", switch-onto-fault trips. If the time of "SwitchOntoBI" as high
voltage level exceeds "BIErrTimeSet", the device will send an alarm and a
report "SOTF BIErrAlarm". LED and protection trip can be configured by
AESP.
As logic switch "SOTFChkPosn" is 1, and if CB stays open position stay
time succeeds "OpenPosnConfirmTime" and if three-phase current is
larger than "SOTFOCSet", it will experience "SOTF OCSet" or zero
sequence current is larger than "SOTF3I0Set" and experience
"SOTF3I0Set" switch-onto-fault will trip. LED and protection trip can be
configured by AESP.
Blocking requirement: 2nd harmonic blocking as logic switch
“SOTFFaultChk2ndH” is 1, the 2nd harmonic blocking will be checked.
171
3.1.2 Logic diagram

Logic diagram is shown below:
“SOTFChkBI/Posn”=0
&
≥1
“SOTF BIErrAlarm”
T1 &
SOTF BI
≥1
BI changes from 1 to 0 &
T2
≥1
SOTF permission
“SOTFChkBI”=1
“SOTFChkPosn”=1
& &
CBF open position &
T3
CBF close position

≥1
BI changes from 1 to 0
T2
“SOTFChkBI/Posn”=1
SOTF protection is on
“SOTFOn”=1
SOTF permission
& &
& T4
SOTF overcurrent trips
BI blocking OC
Ia（Ib，Ic）>“SOTFOCSet”
“SOTFFaultChk2ndH”=1 &
≥1
3phase inrush blocking
“SOTFFaultChk2ndH”=0
&
&
“SOTFOn”=1 T5 SOTF zero sequence current trips
SOTF permission
&
BI blocking EF
3I0>“SOTF3I0Set”
SOTF protection is on
T1：“BIErrTime”
T2：“SOTFStateLatchedTime”
T3：“OpenPosnConfirmTime”
T4：“SOTFOCTime”
T5：“SOTF3I0Time”
Figure 69 Logic diagram of switch-onto-fault function
3.2 Setting list

Table 125 Switch-onto-fault protection
Default
value
1. SOTFOCSet 0.05In~40In 40 0.01 A
3 times of zero
2. SOTF3I0Set 0.05In~40In 40 0.01 A sequence
current
3. SOTFOCTime 0.00~100.0 100 0.01 s
4. SOTF3I0Time 0.00~100.0 100 0.01 s
5. OpenPosnConfirmTime 0.00~100.0 1 0.01 s
6. SOTFStateLatchedTime 0.00~100.0 0.04 0.01 s
7. BIErrTime 0.00~100.0 10 0.01 s
172
Default
value
8. OC2ndHI2/I1Ratio 0.07~0.50 0.07 0.01
Table 126 Switch-onto-fault protection

Set Default
mode value
Enable/Disable
1. SOTFOn 1/0 0
switch-onto-fault protection
0: check position or BI, while
"SOTFChkPosn" is 1 or
"SOTFChkBI" is 1;
2. SOTFChkBI&Posn 1/0 0
1: check position and BI, while
"SOTFChkPosn" is 1 and
"SOTFChkBI" is 1.
3. SOTFChkPosn 1/0 0
4. SOTFChkBI 1/0 0
5. SOTFFaultChk2ndH 1/0 0
3.3 Report list


Trip report:
1. SOTF OCTrip /
2. SOTF 3I0Trip /
Alarm report:
1. SOTF BIErrAlarm /

Table 128 Technical parameters of switch-onto-fault protection

≤ ±1% times of setting or
Time setting 0.00s～100.00s +40ms, when trip current is set
as 200% setting
Dropoff coefficient When I/In≥0.5, it is about 0.95
173
Chapter 26 Non-electric protection
About this chapter

This chapter describes the principles of undervoltage
175
1 Overview
Non-electric protection supports four groups of consumer non-electric
tripping.

The input and output signals of non-electric protection function are shown
below:
External trip initiation

1 1
BI Start
2
Operation
Figure 70 Diagram of input and output signals of non-electric protection function

Number Input Description
Input:
BI BIO
ExtBI Output:
Start IED startup
Operation IED trip
External BI stay time reaches non-electric time setting, protection will trip.
LED and protection trip can be configured by AESP.
NonElectricTrip
&
T1
“NonElectricGrp1On”=1 NonElectric1Trip
NonElectricBI1
T1：“NonElectricGrp1Time”
Figure 71 Logic diagram of Non-electric protection 1
176
3.2 Setting list

Table 130 Non-electric protection setting
Number Setting name Range Default value Step Unit Remark
1. NonElectricGrp1Time 0~100 100 0.01 s
Table 131 Non-electric protection logic switch
1. NonElectricGrp1On 1/0 0 1: On, 0: Off
3.3 Report list


Trip report:
1. NonElectric1Trip /

Table 133 Non-electric protection technical parameters
Current 0.00s～100.00s ≤±1% or+40ms
177
Chapter 27 Synchro-check and non-voltage check (25)
Chapter 27 Synchro-check and

non-voltage check (25)
About this chapter

This chapter describes the principles of synchro-check and
non-voltage check, the input and output signals, setting
179
1 Overview
Synchronization voltage check ensures that when line is connected with
busbar, electricity system will stay stable. If the difference between the
charging line voltage and the busbar voltage, phase angle difference and
the frequency difference are in allowable range, the function of voltage
synchronization will be met.
Synchro-check function needs to detect whether the voltage of both sides
of circuit breaker meets the synchronization function, or at least one side is
non-electric power which can ensure the safety of closing.
When the voltage on both sides is needed to be detected, the voltage
selected for synchronization is the busbar side voltage or the line side
voltage. If the voltage transformer used by protection is connected with line
sides, the reference voltage must adopt busbar voltage.

The input and output signals of synchronization voltage check function
diagram is shown as below:
Synchro-Check with Live/Dead
Line/Bus Measurement
1 1
BIBlk syn_Req
2 2
CBOpen syn_meet
3 3
BI_MC syn_time
4
Override
5
LowU_meet
6
LDBL_meet
7
LLBD_meet
8
LDBD_meet
9
MCOut
Figure 72 Diagram of input and output signals of synchronization voltage check

function
Input:
BinaryInput CBOpen breaker trip
BI_MC manual close circuit breaker
Input:
MC BIBlk BIBlk
Output:
180
syn_Req Synchronization request
syn_meet Synchronization satisfied
syn_time Synchronization timeout
Override Manual close non-synchronization mode
LowU_meet Synchronization undervoltage satisfied
LDBL_meet Switch-onto-fault dead line live busbar output
LLBD_meet Switch-onto-fault live line dead busbar output
LDBD_meet Switch-onto-fault dead line dead busbar output
MCOut Manual close condition is met
Synchronization function is suitable for automatic reclosing function or
manual close function or both of them. Therefore, the following situation
needs synchronization check function:
1) Internal or external automatic reclosing request;
2) Manual close request.
Internal or external automatic reclosing signal and manual close signal will
be connected with synchronization function signal. If the device receives
the synchronization signal, the device can be closed through different
synchronization modes. Automatic reclosing and manual close
synchronization are selected respectively. Synchronization closing mode
of automatic reclosing includes "SyncChkModeOn", "OverrideModeOn",
"ChkDLLBOn", "ChkLLDBOn" and "ChkDLDBOn". Manual synchronization
closing mode includes "MCOverrideModeOn", "MCSyncChk",
"MCChkDLLBOn", "MCChkLLDBOn" and "MCChkDLDBOn". The above
synchronization closing modes can be explained as below:
1) Synchronization check: as soon as choose this kind of synchronization
closing modes, the device will receive synchronization request singles
and then continually check whether it is satisfied the requirement of
synchronization or not;
2) \Non-synchronization: when this kind of synchronization closing mode
is chosen, the device will receive synchronization request signals and
continually check whether it is satisfied the synchronization
requirement;
3) Check line non voltage busbar voltage: as soon as this kind of
synchronization closing modes are chosen, the device will receive
synchronization request singles and check whether the line side has
no voltage, and busbar has voltage;
4) Check line voltage busbar non voltage: as soon as this kind of
181
synchronization request singles and check whether the line side has
voltage, and busbar has no voltage;
5) Check line voltage busbar voltage: as soon as this kind of
synchronization request singles and check that the line side has no
voltage, and busbar has not voltage.
Synchronization voltage has various choosing modes. Reference voltage
U4 can serve as line voltage or phase voltage. Synchronization setting:
"SelLineVT"=0 means that voltage transformer protection is connected
with busbar side, and then reference voltage U4 is line voltage.
"SelLineVT"=1 means that voltage transformer protection is connected
with line side, and then reference voltage U4 is phase-to-phase voltage.
Under the condition of check line and busbar voltage or non-voltage: if
"ChkDLLBOn" and " ChkDLDBOn " are enabled at the same time, the
device checks the dead line and closes circuit breaker; when
"ChkLLDBOn" and "ChkDLDBOn" are enabled at the same time, the
device checks the dead busbar and closes circuit breaker".
Note: check synchronization can detect phase-to-earth voltage and
phase-to-phase voltage. When the sampled voltage is greater than the
minimum phase-to-phase voltage (i.e., 1.732* "SyncChkMinVolt"), it is
considered that the sampled voltage UX is connected to the
phase-to-phase voltage. When judging synchronization voltage abnormal
and phase voltage difference is calculated for the same period, it should
be noted that UX is calculated as the phase-to-phase voltage. Manual
close synchronization is the same.
When "3PhVoltConnect" is 1, while synchronization or non-voltage is
detected, compare the minimum value of three-phase voltage with the
sampled voltage; when "3PhVoltConnect" is 0, compare the maximum
value of three-phase voltage with the sampled voltage.
3.1.2 Synchronization check mode
Synchronization check function can use device to measure the voltage
amplitude difference, frequency difference and phase angle difference.
Device will receive synchronization request signals and continually check
whether it is satisfied the synchronization requirement. When the line
voltage and busbar voltage are all larger than "SyncChkMinVolt" and
meets the synchronization check requirements, the automatic reclosing
will trip.
At equal synchronization time, the device will receive synchronization
request signals and continually check whether it is satisfied the
synchronization requirements. However, when "WaitSyncTime" is over,
the device stops checking synchronization requirement. If during
"WaitSyncTime", synchronization check requirement is satisfied; timing
component will stop timing and start closing. Switch-onto-fault check
synchronization phase will be set by "SyncPh"; When the
"3PhVoltConnect" =1, the automatic reclosing synchronization phase is
self-adaptive; When the "3PhVoltConnect" =0, automatic reclosing
synchronization phase is set by "SyncPh". If reclosing synchronization
phase difference and manual close synchronization phase difference are
chosen differently, 10s alarm "SyncPhaseDiffChoice" will turns out.
If synchronization check is applied to manual close function, the
182
corresponding BI should be high power level, and timing component will

start timing “MCWaitSyncTime”. During "MCWaitSyncTime", if
synchronization requirement is satisfied and succeeds "CheckSyncTime",
timing component will stop and "MCSyncMet" will be issued. "MCSyncMet"
signal will stay the same in the following situations:
1) Synchronization check requirements are satisfied;
2) Manual close synchronization requests high power level;
3) Time delay "WaitMCTime" is not arrived;
4) Synchronization check sends off closing command, the following
requirements should be satisfied:
a) Reference voltage ratio is larger than "SyncChkMinVolt";
b) Voltage amplitude difference is smaller than "SyncVoltDiffSet";
c) Phase difference of voltage is smaller than "SyncAngleDiffSet";
d) Voltage frequency difference is smaller than "SyncFreqDiffSet".
3.1.3 Modes of non-voltage check
Non voltage check sends off closing command, the following requirements
should be satisfied:
1) If logic switch "ARChkDLLBOn" is set to 1, the line voltage that is
detected by check non-voltage is lower than dead voltage setting, and
busbar voltage is higher than live voltage setting;
2) If logic switch "ARChkLLDBOn" is set to 1, the line voltage that is
detected by check non-voltage is higher than live voltage setting, and
busbar voltage is lower than dead voltage setting;
3) Logic switch "ChkDLDBOn" is 1, non voltage check needs to detect
that line voltage ratio and busbar voltage ratio is lower than setting.
3.1.4 Non synchronization mode
Under the condition of non-synchronization mode, if receives
synchronization request at any time, synchronization requirements will be
satisfied which is suitable for reclosing function and manual close function.
When automatic reclosing non-synchronization mode is reclosing, the
device will send off "AROverrideMode" alarm report.
The setting of reclosing mode synchronization is set wrongly, the device
will send off "ARSyncChkModeErr" alarm report; take the manual close
synchronization mode as example, reclosing synchronization check
modes are similar. As shown in logic diagram.
183
3.1.5 Logic diagram

“OverrideModeOn”
“SyncChkModeOn”
“ChkDLLBOn”
&
≥1
“ChkLLDBOn”
≥1
“ChkDLDBOn” ARLSErr
&
≥1
Figure 73 Logic diagram of reclosing synchronization check function

Ua(Ub,Uc) >“MCSyncChkMinVolt”
Ux>“MCSyncChkMinVolt”
Voltage phase angle Difference
<“MCSyncAngleDiffSet”
Voltage frequency difference &
<“MCSyncFreqDiffSet” ≥1
Voltage amplitude difference &
<“MCSyncVoltDiffSet” & T1
SyncChk or ChkDeadVolt satisfied
“MCSyncOn”=1
Circuit breaker
trip position
MC BI T2
SyncChk exceeds time or ChkDeadVolt failed
“ChkDLLBOn”
Ux <“MCChkDeadVoltMaxVolt” &
&
≥1
“SelLineVT”=1
&
Ua(Ub,Uc) <“MCChkDeadVoltMaxVolt” &
“MCLiveLineAndDeadBus”=1
&
Ux<“MCChkDeadVoltMaxVolt”
&
Ua(Ub,Uc) <“MCChkDeadVoltMaxVolt”
“MCChkDLDBOn”=1
“MCDeadLineAndLiveBus”=1 &
&
Ua(Ub,Uc) <“MCChkDeadVoltMaxVolt”
“SelLineVT”=1
&
&
Ux <“MCChkDeadVoltMaxVolt”
“MCLiveLineAndDeadBus”=1
T1：“MCSyncChkTime”
T2：“MCWaitSyncTime”
Figure 74 Logic diagram of synchronization check
3.2 Setting list

Table 135 Setting of synchronization check and non-voltage check
Default
value
1. SyncDetectTime 0.02~100.00 0.05 0.01 s
2. WaitSyncTime 0.05~100.00 0.05 0.01 s
184
Default
value
3. MCSyncChkTime 0.02~100.00 0.05 0.01 s
4. MCWaitSyncTime 0.05~100.00 0.05 0.01 s
5. SyncAngleDiffSet 1.00~10.00 10 0.01 degree
6. SyncVoltDiffSet 1.00~40.00 40 0.01 V
7. SyncFreqDiffSet 0.02~2.00 2 0.01 Hz
8. ChkDeadVoltMaxVolt 10.00~50.0 30 0.01 V
9. SyncChkMinVolt 30.00~65.00 40 0.01 V

1: Ua
2: Ub
3: Uc
10. SyncPh 1-6 1 1
4: Uab
5: Ubc
6: Uca
Table 136 Manual close synchronization setting
Default
Number Setting name Range Unit Remark
value
1. MCSyncChkTime 0.05~100.00 0.05 s
2. MCWaitSyncTime 0.05~100.00 0.05 s
3. MCSyncAngleDiffSet 1.00~10.00 10 degree
4. MCSyncVoltDiffSet 1.00~40.00 40 V
5. MCSyncFreqDiffSet 0.02~2.00 2 Hz
6. MCChkDeadVoltMaxVolt 10.00~50.0 30 V
7. MCSyncChkMinVolt 30.00~65.00 40 V
1: Ua
2: Ub
3: Uc
8. SyncPh 1-6 1
4: Uab
5: Ubc
6: Uca
Table 137 Logic switch of manual close synchronization check and non-voltage check
Set Default
mode value
1. SelLineVT 1/0 0
2. SyncChkModeOn 1/0 0
3. OverrideModeOn 1/0 0
4. ChkDLLBOn 1/0 0
5. ChkLLDBOn 1/0 0
6. ChkDLDBOn 1/0 0
7. MCSyncOn 1/0 0
185
Set Default
mode value
8. MCNoSyncChk 1/0 0
9. MCSyncChk 1/0 0
10. MCDeadLineAndLiveBus 1/0 0
11. MCLiveLineAndDeadBus 1/0 0
12. MCChkDLDBOn 1/0 0

1-three-phase voltage connection,
13. 3PhVoltConnect 1/0 1 0-Single-phase voltage
connection
3.3 Report list


Trip report:
1. MCVoltDiffFail /
2. MCFreqDiffFail /
3. MCAngleDiffFail /
4. MCDeadVoltChkFail /
5. MCSyncRequest /
6. MCSyncMet /
7. MCSyncUVMet /
8. MCSyncTimeout /
9. MCOverrideMode /
10. MCMet
11. MCChkDLLBMet
12. MCChkLLDBMet
13. MCChkDLDBMet
Alarm report:
1. MCSyncVoltExchg /
2. MCSyncVoltErr /
3. MCOverrideModeErr /
Alarm of reclosing synchronization phase difference and
4. SyncPhSelConflict manual close synchronization phase difference choosing
differently
186
3.4 Technical data

Table 139 Synchronization check and non-voltage check technical parameters
Synchronization check mode:
1) Synchronization Check
2) Check non voltage failure, if the
check non voltage is failure, the
check synchronization
3) Non-synchronization
Trip mode Modes of non-voltage check
1) Line (V4) non-voltage busbar
(V3Ph) non-voltage
2) Line 4(V4) non-voltage busbar
(V3Ph) voltage
3) Line 4(V4) voltage busbar (V3Ph)
non-voltage
The setting of line or
10V to 50V (phase-to-earth voltage) ≤ ±3% setting or 1V
busbar non voltage
The setting of line or
30V to 65V (phase-to-earth voltage) ≤ ±3% setting or 1V
busbar voltage
∆V-voltage difference 1V to 40V (phase-to-earth voltage) ≤±1V
Δf-frequency
difference (f2>f1; 0.02Hz～2.00Hz ≤±20mHz
f2<f1)
Δα- angle difference
1°~10° ≤ ±3°
(α2>α1; α2<α1)
Minimum ≤ ± 1.5% times of setting
0.02～100.00s
measurement time or +60ms
The largest
broadening time of 0.05s～100.00s ≤ ± 1% setting or +50ms
synchronization check
187
Chapter 28 Automatic reclosing (79)
About this chapter

This chapter describes the principles of automatic reclosing
function, the input and output signals, setting parameters,
189
1 Overview
When transient faults occur to lines, automatic reclosing function can be
reset to operate. Statistics show that 85% of the faults are transient faults,
after automatic reclosing function, these faults will disappear. Therefore,
temporal short circuit may occur in the line. After automatic reclosing
function tripping, the line will be charged again. If the fault is permanent or
short circuit arc current has not disappeared, the protection will trip circuit
breaker again.
Main features of automatic reclosing function are shown as below:
1) There are 4 times reclosing (available);
2) Each reclosing time can be set respectively;
3) Externally BI start reclosing/protection trip start reclosing;
4) Three-phase reclosing ;
5) Position of circuit breaker monitoring;
6) To coordinate with automatic reclosing check synchronization function.
soft-hard parallel.

Automatic reclosing function input and output signal is shown below,
Three-Pole Auto-Reclosure
1 1
BIBlk ChkARFail
2 2
CBOpen Ph3TripInitAR
3 3
AR_BLOCK Ph3CBOTripInitAR
4 4
AR_OFF AR_IN
5 5
CB_FAULTY Ph3TripBlkAR
6 6
PH3_INIT_AR ARFail
7 7
ENA_AR ARSucc
8
AR_FinalTrip
9
syn_Req
10
syn_meet
11
LowU_meet
12
AR_Trip
13
AR_Block
14
syn_time
15
FirstARTrip
16
SecondARTrip
17
ThirdARTrip
18
FourthARTrip
Figure 75 Automatic reclosing function input and output signal diagram
190

Input:
BinaryInput CBOpen breaker trip
AR_BLOCK Enable blocking reclosing
Input:
BIBlk BIBlk
AR_OFF Auto-reclosing off binary input
CB_FAULTY SpringDischargeBI
PH3_INIT_AR Three-phase initiating auto-reclosing binary input
Output:
ChkARFail Reclosing failure
Ph3TripInitAR Three-phase trip initiates auto-reclosing
Ph3CBOTripInitAR Three-phase spontaneous trip initiates auto reclosing
AR_IN Auto-reclosing is in process
Ph3TripBlkAR Three-phase trip blocking auto-reclosing
ARFail Auto-reclosing failure
AR_3C ARSucc Auto-reclosing is successful

Auto-reclosing trip, then three-phase trip and blocking
AR_FinalTrip
auto-reclosing
syn_Req Auto-reclosing synchronization request
syn_meet Auto-reclosing synchronization is met
LowU_meet Undervoltage criteria are satisfied
AR_Trip Auto-reclosing trip
AR_Block Auto-reclosing blocking
syn_time Synchronization timeout
FirstARTrip Primary auto-reclosing trip
SecondARTrip Second reclosing trip
ThirdARTrip Third reclosing trip
FourthARTrip Fourth auto-reclosing trip
ENA Input:
191
The total connector of automatic reclosing protection，the

ENA_AR
corresponding hard connector is ENA_AR_5.
3.1.1 Auto-reclosing startup
Reclosing could be initiated by protection or by external BI reclosing.
The protections that can start auto-reclosing include: overcurrent stage 1,
overcurrent stage 2, overcurrent stage 3, overcurrent stage 4, zero
sequence current stage 1, zero sequence stage 2, zero sequence stage 3,
zero sequence stage 4, high voltage side zero sequence current stage 1,
high voltage side zero sequence current stage 2, high voltage side zero
sequence current stage 3, high voltage side zero sequence current stage 4,
negative sequence current stage 1, negative sequence current stage 2,
negative sequence current stage 3, negative sequence current stage 4. If
external binary input startup is reclosed, then the corresponding binary
input will be configured to three-phase startup reclosing binary input of
reclosing startup pin. If the signal of starting auto-reclosing protection that
is configured in IOMatrix is sent to the pin of ARFinalTrip->FinalTrip, then
the corresponding section is protected by blocking auto-reclosing.
After other protections tripping, auto-reclosing logic is blocked.
3phase initiating reclosing BI, falling edge ≥1
3phase internal initiating reclosing, falling edge &
3phase has no current ≥1
≥1
3phase initiating reclosing
“3PhSpontaneousTripInitAR”=1
Figure 76 Logic diagram of auto-reclosing startup
3.1.2 Auto-reclosing logic

In order to avoid equipment maintenance or circuit breaker open position
in the state of testing starts reclosing, only does the reclosing experience
the circuit breaker close position and the "ARBlkTime" is delayed; the
reclosing can be started again. Then reclosing will start and the fault will
disappear without current or with tripping. The first reclosing will start
timing. Actually, one time of reclosing time delays the setting
"WaitSyncTime". During this time, as long as circuit breaker is tripping,
one-time reclosing time start timing. If waiting synchronization timing is
tested finished and the device cannot test circuit breaker is tripping,
reclosing function will be blocked at the time of reclosing blocking time and
report reclosing failure alarm.
If the circuit breaker failure protection is used to (internal or external) circuit
192
breaker, the setting of "WaitSyncTime" should be set shorter than the time
of failure protection time delay, to protect each stage of reclosing will not
affect fault circuit breaker. After failure protection tripping, the reclosing
function will be blocked.
As showed above, after starting reclosing, reclosing time starts timing and
will be delayed by time setting, "3PhARTime1" will begin the first time
reclosing (or "3PhARTime2", "3PhARTime3", and "3PhARTime4" begin
the 2nd, 3rd and 4th stage reclosing). After the first reclosing time, equal
synchronization time will start timing. In fact, the first reclosing time is
stretched by the waiting synchronization time. After the first reclosing time,
the device starts synchronization check judgment. During waiting
synchronization time, if the synchronization check succeeds within the
time, which means synchronization time is over, and the device will send
off the reclosing command. However, if the synchronization success is not
detected within synchronization time, the reclosing will be blocked within
the "ARBlkTime", and send off reclosing failure alarm.
As for reclosing command, the maximum broadening of closing pulse is
500ms. In general, the device does not detect synchronization check in the
pulse broadening time. During this time, if the circuit breaker auxiliary
contact position binary input CBOpen is set to“0” or the device detects the
current, closing pulse returns.
Once closing command disappears, reclosing will confirm the time and
begin to timing, to detect whether there is fault arrival during this period of
time. If there is no fault in the reclosing time, the device thinks that the fault
disappears. Therefore, after the confirmation of the time delay, the
reclosing starts timing. In the blocking time of reclosing, the reclosing
function is blocked. In the definite time of reclosing, if the fault still exists,
the protection will trip and the next stage of reclosing logic will start. This
process is repeated until the maximum number of reclosing.
If all stages of reclosing do not succeed, the fault still exists and the
protection trips. After the last reclosing, if the protection still trips, the
device thinks that the reclosing trips and reports the "ARTrip3Ph/BlkAR"
alarm. Besides, during the blocking time of reclosing, reclosing blocking
function will be protected and reclosing failure alarm will be issued.
Manual close binary input blocking reclosing. When manual close binary
input is in high power level, the manual close binary input function works,
therefore, the auto-reclosing function will be blocked within the setting
"ARBlkTime".
In the process of automatic reclosing, if the spring discharge binary input is
in high power level and "SpringDischargeAlarmTime" is still disappeared,
the circuit breaker fails and reclosing function is blocked.
1) Single reclosing
When the protection or external BI starts reclosing, the reclosing logic will
be enabled. After the start condition is satisfied, through the time setting
“3PhARTime1" delay, the device begins to time of "WaitSyncTime". In the
synchronization time, if the setting "CheckSyncTime" meets the
synchronization conditions, closing pulse signal will be triggered and the
"ARConfirmTime" start timing. During this period of time, if the reclosing
condition is satisfied, the reclosing will block and the reclosing fails; if there
is no block condition is satisfied during this period and there is no fault, the
coincidence is successful. Reclosing resets and waits for the next
193
reclosing.
2) Multiple reclosing
After the first trip of reclosing, multiple reclosing logics resumes with single
reclosing. If the first reclosing fails, the protection will start the next
reclosing logic. Therefore, during "ARConfirmTime", if there exits failures,
the next reclosing logic will be started and will experience the next
reclosing time. This process will be repeated according to the number of
reclosing until all stages of reclosing times are finished. All stages of
reclosing time can be set through "3PhARTime1", "3PhARTime2",
"3PhARTime3" and "3PhARTime4". If any of these stages is successful,
the reclosing function returns; and if all the four stages reclosing fail, then
the whole reclosing logic fails and finally the protection will trip. The
following diagram is a schematic diagram of two stages reclosing.
Fault
Trip command
Circuit breaker
trip position
Initiate reclosing BI
3PhARTime1 3PhARTime2
3phase reclosing
delay set
SyncChk or chk3PhVolt
success
Auto- Auto-
reclosing reclosing
pulse time pulse time
Closing command
Reclosing
success time
Reclosing
charging time
Figure 77 Permanent trip after two stages of reclosing
3.2 Setting list

Table 141 Auto-reclosing setting
Default
value
1. 3PhARTime1 0~600 600.00 0.01 s
2. 3PhARTime2 0~600 600.00 0.01 s
3. 3PhARTime3 0~600 600.00 0.01 s
4. 3PhARTime4 0~600 600.00 0.01 s
5. ARPulse 0.08~0.5 0.5 0.01 s
6. ARTimes 1~4 1 1
194
Default
value
7. ARConfirmTime 0.1~100 100.00 0.01 s
8. ARBlkTime 0.05~100 100.00 0.01 s
9. SyncDetectTime 0.02~100 0.05 0.01 s
10. WaitSyncTime 0.05~100 60.00 0.01 s
11. SpringDischargeAlarmTime 0.10~100 10.00 0.01 s
12. SyncAngleDiffSet 1.00~10.00 10 0.01 degree
13. SyncVoltDiffSet 1.00~40.00 40 0.01 V
14. SyncFreqDiffSet 0.02~2.00 2 0.01 Hz
15. ChkDeadVoltMaxVolt 10.00~50.0 30 0.01 V
16. SyncChkMinVolt 30.00~65.00 40 0.01 V
Table 142 Auto-reclosing logic switch
1. AROn 1/0 0
2. StopModeOn 1/0 0
3. ARTrip3Ph&BlkAR 1/0 0
4. 3PhSpontaneousTripInitAR 1/0 0
5. OverrideModeOn 1/0 0
6. SyncChkModeOn 1/0 0
7. ChkDLLBOn 1/0 0
8. ChkLLDBOn 1/0 0
9. ChkDLDBOn 1/0 0
3.3 Report list


Trip report:
1. ReclosingFail /
2. 3PhTripInitAR /
3. 3PhSpontaneousTripInitAR /
4. ARProcessing /
5. 3PhTripBlkAR /
6. ARFail /
7. ARSuccess /
195

8. ARChkVoltDiffFail /
9. ARChkFreqDiffFail /
10. ARChkAngleDiffFail /
11. ARDeadVoltChkFail /
12. ARTrip3Ph&BlkAR /
13. ARSyncRequest /
14. ARSyncMet /
15. UVCondMet /
16. BlkAR /
17. SyncTimeout /
18. AROverrideMode /
19. 1stARTrip /
20. 2ndARTrip /
21. 3rdARTrip /
22. 4thARTrip /
Alarm report:
1. ARSyncChkModeErr /

Table 144 Auto-reclosing Technical parameters
Items Reference value Error range (V)

Auto-reclosing times 4
Protection startup or reclosing
Reclosing startup function
external startup BI
Every reclosing time 0.05s～600.00s
Auto-reclosing confirmation time 0.10s～100.00s ≤ ± 1.5% times of setting
Auto-reclosing blocking time 0.50s～100.00s or +60ms
Waiting synchronization time 0.050s~100.00s
196
Chapter 29 Blocking simple busbar differential
protection
Chapter 29 Blocking simple busbar

differential protection
About this chapter

This chapter describes the principles of blocking simple
busbar differential protection function, the input and output
signals, setting parameters, messages and technical
parameters.
197
Chapter 29 BlockingChapter 1 simple busbar
1 Protection principle
The function cooperates with simple busbar differential protection function
that is installed to the low voltage side of transformer or at the sectionalizer
(bus coupler) to complete the protection of busbar. If the failure occurs at
outlets, protection starts and sends off blocking simple busbar differential
protection signal, simple busbar differential protection which is at low
voltage side of blocking transformer or at the sectionalizer (bus coupler)
trips failure through line protection trip; if the failure occurs at the busbars,
simple busbar differential protection function that is installed to the low
voltage side of transformer or at the sectionalizer (bus coupler) is
unblocked, and the failures can be cut off in a short time.
When overcurrent protection any one stage starts, IED sends out GOOSE
blocking signal, the signal will return after the failure is cut off; if the failure
is not still cut off until the protection lasts for 500ms, the signal will return
automatically to realize simple busbar differential protection.
If the simple busbar differential protection is blocked by direction, then
overcurrent protection must be blocked by direction, and the direction is
forward.
The input and output signals of simple busbar differential protection
BlkSimpleDiff
1 1
ENA_BSBus BlkSDiff_BO
Figure 78 Diagram of input and output signal of simple busbar differential protection
function
Output:
BOConfig
BlkSDiff_BO Blocking simple busbar differential protection trip
Input:
ENA The total connector of blocking simple busbar differential
ENA_BSBus protection ， the corresponding hard connector is
ENA_BSBus_5.
2 Setting list
Table 146 Logic switch of blocking simple busbar differential protection

1. BlkSimpleBusDiffOn 1/0 0
1-Judge overcurrent
protection in direction
2. DirBlkSimpleBusDiff 1/0 0
area; 0-don't judge
direction
198
Chapter 29 Blocking simple busbar differential
protection
3 Report list
Trip report:
1. BlkSimpleBusDiffTrip /
199
Chapter 30 Simple busbar differential protection
Chapter 30 Simple busbar

About this chapter

This chapter describes the principles of blocking simple
busbar differential protection function, the input and output
signals, setting parameters, messages and technical
parameters.
201
The input and output signals of simple busbar differential protection
SimpleDiff
1 1
BIBlk Start
2 2
ENA_SBus Operation
Figure 79 Diagram of input and output signal of simple busbar differential protection
function
Input:
BIBlk BIBlk
SimpleDiff Output:
Start IED startup
Operation IED trip
Input:
ENA
The total connector of simple busbar differentia ， the
ENA_SBus
corresponding hard connector is ENA_SBus_5.
Simple busbar differential protection logic diagram:

Ia>SimpleBusDiffCurrSet
≥1
&
Ib>SimpleBusDiffCurrSet T
Simple busbar trips
Ic>SimpleBusDiffCurrSet
BI blocking
“SimpleBusDiffOn”=1
SimpleBusDiffOn
T：“SimpleBusDiffTime”
Figure 80 Logic diagram of simple busbar differential protection
2 Setting list
Table 149 Time setting of simple busbar differential protection
Default
value
1. SimpleBusDiffCurrSet 0.05In~40In 40 0.01 A
202
2. SimpleBusDiffTime 0~100 100 0.01 s
Table 150 Simple busbar differential logic switch

Set Default
mode value
1. SimpleBusDiffOn 1/0 0
3 Report list

Trip report:
1. SimpleBusDiffTrip /
203
Chapter 31 Undervoltage load shedding protection
Chapter 31 Undervoltage load

shedding protection
About this chapter

This chapter describes the principles of undervoltage load
shedding protection, the input and output signals, setting
205
1 Overview
Undervoltage load shedding is necessary when the power grid is
connected with a huge system with vast power capacity. Under this
condition, low frequency load shedding scheme cannot work properly.
Undervoltage load shedding scheme would be a useful criterion whenever
Automatic Voltages Regulator (AVR) is out of service. The main features
of underfrequency load shedding protection are as follows:
1) Negative sequence voltage blocking;
2) Sliding pressure (du/dt) blocking;
3) CB position checking;
4) Load current blocking;
5) VT secondary circuit failure supervision.
soft-hard parallel.

The input and output signals of undervoltage load shedding protection are
shown below:
Load Shedding Under Voltage protection
1 1
BIBlk Start
2 2
CBOpen Operation
3
ENA_LSUV
Figure 81 Diagram of input and output signals of multi-round of undervoltage load

shedding protection
Input:
BinaryInput
CBOpen breaker trip
Input:
BIBlk BIBlk
LSUV Output:
Start IED startup
Operation IED trip
ENA Input:
206
The total connector of undervoltage load shedding

ENA_LSUV protection ， the corresponding hard connector is
ENA LSUV 5.
Undervoltage load shedding is provided based on bay load shedding
principle. This means that the protection function is implemented in each
bay separately, instead of being applied in an incoming bay and sending
trip command to various outgoing bays. In this regard, coordination
between the undervoltage load shedding protection functions applied at
various bays can be achieved by selecting appropriate settings for pickup
threshold and time delay of the protection in various bays. Based on the
bay load shedding principle, one trip stage is provided for the protection.
Trip voltage of undervoltage load shedding protection can be tested by
input three-phase voltage or single voltage. The voltage connection mode
is selected by enabling and disabling logic switch "3PhVoltConnect". If all
the voltages are lower than setting value "UVLSVoltSet", timing
component starts, when the delay runs toward "UVLSTime", the load
shedding command is issued. It is noted that "UVLSVoltSet" is line voltage
setting.
Since the protection operates based on measured voltages, the protection
should be blocked if some conditions are satisfied as following:
1) The device will detect VT failure or switch tripping;
2) When three-phase voltage is connected, the minimum line voltage is
lower than "LoadShedVoltBlkSet". When single-phase voltage is
accessed, the maximum line voltage is lower than
3) The current blocking conditions can be enabled and disabled through
logic switch "UVLSChkCurrOn". If the voltage transformer is installed
on the power supply side, and does not want to protect the
undervoltage protection check current, the setting of
"UVLSChkCurrOn" can be set to 0;
4) Circuit breaker is at open position. If it is in the same case, as voltage
transformer is configured at the side of power supply, it is useful to
detect current setting. Meanwhile, although the voltage is lower than
undervoltage load shedding voltage setting, the protection will not send
off trip command;
5) Sliding pressure (Δu/Δt) is greater than "LoadShedDv/dtBlkSet".
Setting value is line voltage Δu/Δt;
6) One time of negative sequence voltage is greater than 5V. When logic
switch "3PhVoltConnect" is set to 0, the undervoltage load shedding
protection is unblocked.
207
3.1.2 Logic diagram

min(Uab,Ubc,Uca)<“UVLSVoltSet” & ≥1
&
max(Uab,Ubc,Uca)<“UVLSVoltSet” &
“UVLSOn”=1
Enable undervoltage load

shedding function
InstantVTFail
≥1
BI blocking
&
& ≥1 T
min(Uab,Ubc,Uca)<LoadShedVoltBlkSet” ≥1
UVLSTrip
&
Negative sequence voltage>5V
max(Ia,Ib,Ic)<“LoadShedCurrBlkSet” &
“UVLSChkCurrOn”=1
Max absolute value of Dv/dt >“LoadShedDv/dtBlkSet” &
“Chkdu/dt”=1
T：“UVLSTime”
Figure 82 Logic diagram of undervoltage load shedding protection
3.2 Setting list

Table 153 Settings of undervoltage load shedding protection
Default
value
1. UVLoadShedVoltSet 50~120 80 0.01 V
2. UVLoadShedTime 0.1~100 100 0.01 s
4. LoadShedCurrBlkSet 0.05In~10In 10 0.01 A
5. LoadShedDv/dtBlkSet 2~200 100 0.01 V/s
Table 154 Logic switch of undervoltage load shedding

Set Default
mode value
1. UVLoadShedOn 1/0 0 1-Enabled;0-disabled;
2. Chkdu/dt 1/0 0 1-Enabled;0-disabled;
3. UVLoadShedChkCurrOn 1/0 0 1-Enabled;0-disabled;

voltage connection
208
3.3 Report list


Trip report:
1. UVLoadShedTrip /

Table 156 Undervoltage load shedding protection technical parameter
Name Scope and step Error
Undervoltage load shedding

Voltage 50V～110V ≤ ±3% setting or ±1V
Time 0.1s～100.00s ≤ ±1.5% setting or +60ms
Blocking condition
Voltage change rate Δu/Δt 2V/s～200V/s ≤ ±3% setting or ±1V/s
1 to 200 V/s, step 0.01 V/s 10V～120V ≤ ±3% setting or ±1V
209
Chapter 32 Overload load shedding protection
Chapter 32 Overload load shedding

protection
About this chapter

This chapter describes the principles of overload load
shedding protection, the input and output signals, setting
211
1 Overview
The multi-overload load shedding protection is on the basis of the load
current passing through feeder. This function will be essential in conditions
that feeder is connected to a huge network with constant frequency and
additional AVR is continuously used for voltage regulation. In this case,
load shedding protection should come into effect based on load current
measured in following conditions.
1) dV/dt Blk (in the case of voltage access);
2) dF/dt Blk (in the case of voltage access);
4) VT secondary circuit failure supervision (in the case of voltage
access).
soft-hard parallel.

The input and output signals of the overload load shedding protection
function diagram are shown below:
Load Shedding Overcurrent protection
1 1
BIBlk Start
2 2
ENA_LSOL Operation
Figure 83 Diagram of input and output signals of the overload load shedding
protection
Input:
BIBlk BIBlk
LSOL Output:
Start IED startup
Operation IED trip
Input:
ENA The total connector of overload load shedding protection，
ENA_LSOL
the corresponding hard connector is ENA_LSOL_5.
212
Overload load shedding is provided based on bay load shedding principle.
This means that the protection function is implemented in each bay
separately, instead of being applied in an incoming bay and sending trip
command to various outgoing bays. In this regard, coordination between
loads shedding protection functions applied at various bays can be
achieved by selecting appropriate settings for pickup threshold and time
delay of the protection in various bays. Based on the bay load shedding
principle, if all of the measured phase currents exceed setting
"OLLSCurrValue", timing component starts, when the delay runs toward
"OLLSTimeValue", the command "OLLSProtection" is issued. LED and
If the device is accessed to the voltage, and the logic switch
"OLLSChkVolt" is set to 1, then when the following conditions are met, the
blocking over load shed is blocked.
1) Sliding pressure (Δu/Δt) is greater than "LoadShedDv/dtBlkSet";
2) The Δf/Δt exceeds "Df/dtBlkSet";
3) The device will detect VT failure or switch tripping;
4) When three-phase voltage is connected, the minimum line voltage is
voltage is accessed, the highest line voltage is lower than settings,
"LoadShedVoltBlkSet".
3.1.2 Logic diagram
max(Ia,Ib,Ic)>“OLLSCurrSet” &
“OLLSOn”=1
Enable overload load

shedding function
BI blocking
≥1
InstantVTFail
min(Uab,Ubc,Uca)<“LoadShedVoltBlkSet” & ≥1
& &
≥1 T
OLLSTrip
Df/dt absolute value>“Df/dtBlkSet” &
“LoadShedChkDf/dt”=1
Max absolute value of Dv/dt>“LoadShedDv/dtBlkSet” &
“LoadShedChkDu/dt”=1
“OLLSChkVolt”=1
“OLLSChkVolt”=0
T：“OLLSTime”
Figure 84 Logic diagram of overload load shedding protection
213
3.2 Setting list

Table 158 Overload load shedding protection setting
Setting Default
mark value
OLLoadShedC
1. LSOL_ISet (0.05~40)In 40 0.01 A
urrSet
OLLoadShedTi
2. LSOL_TSet 0.1~100 100 0.01 s
me
3. dfdt_Set Df/dtBlkSet 0.10~20.00 20 0.01 Hz/s
LoadShedDv/d
4. LS_dudtSet 2~200 100 0.01 V/s
tBlkSet
LoadShedVolt
5. LS_UBlk 10.00~120.00 120 0.01 V
BlkSet
Table 159 Logic switch of undervoltage load shedding
mark value
1-Enabled;
1. LSOL_On OLLoadShedOn 1/0 0
0-disabled;
1-Enabled;
2. LSOL_ChkU OLLoadShedChkVolt 1/0 0
0-disabled;
1-Enabled;
3. LS_Chkdudt Chkdu/dt 1/0 0
0-disabled;
1-Enabled;
4. LS_Chkdfdt Chkdf/dt 1/0 0
0-disabled;
1-three-phase
voltage
connection,
5. Ph3_V_Connet 3PhVoltConnect 1/0 1
0-Single-phase
voltage
connection
3.3 Report list


Trip report:
1. OLLoadShedTrip /

Table 161 Overload load shedding protection technical parameter
Name Scope and step Error
Overload load shedding
Current 0.05In～40InA ≤ ±3 % setting or ±0.02Ir
Time 0.1s～100.00s ≤ ± 1.5% setting or +60ms
Blocking condition
Frequency changing rate Δf/Δt 0.3Hz/s～20Hz/s ≤±0.5Hz/s
Voltage change rate Δu/Δt 2V/s～200V/s ≤ ±3% setting or ±1V/s
1 to 200 V/s, step 0.01 V/s 10V～120V ≤ ±3% setting or ±1V
214
Chapter 33 Cooling load startup protection
Chapter 33 Cooling load startup

protection
About this chapter

This chapter describes the cooling overload protection
principle, the input and output signals, setting value
215
Input and output signals of cooling load startup protection function are
shown below:
CLP
1
BIBlk
2
Init
3
ShortRst
4
CBOpen
5
ENA_CLP
Figure 85 Diagram of input and output signal of cooling load startup protection
function
Input:
BinaryInput
CBOpen breaker trip
Input:
BIBlk BIBlk
CLP
Init External trigger
ShortRst Fast reset binary input
Input:
ENA The total connector of Cooling load startup protection，the
ENA_CLP
corresponding hard connector is ENA_CLP_5.
The device provides cooling load startup logic which can be used as the
designed protection component within a specified time and also can
improve the setting of designed protection component, therefore, the
protection setting value can be set in accordance with load curve, and the
setting value is automatically higher to prevent mis-operation in the
process of excitation circuit. Cooling load startup logic provides protection
functions that are stable and easy to maintain for startup process.
Cooling load startup logic is used for overcurrent protection and earth fault
protection, and the output of cooling load startup logic can be used as
blocking signals for these protections.
The logic diagram of cooling load startup function is shown below. After
the circuit breaker open state continues to exceed "CoolLoadTripTime",
the startup logic of cooling load is enabled while the circuit breaker close
state is detected. After circuit breaker close position state exceeds
"CoolLoadStartRstTime", the cooling load startup logic is disabled; if the
quick reset function is enabled, after circuit breaker open position state
exceeds "CoolLoadStartFastRstTime", cooling load startup logic will be
disabled. There are two ways of detecting open state of circuit breaker,
216
when "CoolLoadStartLogicSel" =0, check whether there is no current in

three-phase circuit to detect open state of circuit breaker. When
"CoolLoadStartLogicSel" =1, only the auxiliary position signal of switch
needs to be checked.
When the output of cooling load startup logic is 1, related setting of cooling
load startup logic is enabled, and the overcurrent protection and zero
sequence current trip in accordance with the setting judgment; when the
output of cooling load startup logic is 0, related setting of cooling load
startup logic is disabled, and overcurrent protection and zero sequence
current trip in accordance with the function setting that is respectively set.
≥1
“CoolLoadStartLogicSel”=1 T1 S Q
>
3phase circuit has no current &
R Q
“CoolLoadStartLogicSel”=0
T2 ≥1
& ≥1
≥1
T3
Fast reset BI
Protection starts
External initiate CLP function input
&
BI blocking CoolLoadStart
CoolLoadStartProtOn
“CoolLoadStartProtOn”=1
T1：“CoolLoadTripTime”
T2：“CoolLoadStartRstTime”
T3“CoolLoadStartFastRstTime”
Figure 86 Logic diagram of cooling load startup protection function
2 Setting list
Table 163 Cooling load startup protection setting
Default
value
1. CoolLoadTripTime 0~4000 4000 0.01 s
2. CoolLoadStartRstTime 0~4000 4000 0.01 s
3. CoolLoadStartFastRstTime 0~600 600 0.01 s
4. CoolLoadStartOC1Multiple 1~10 10 0.01
5. CoolLoadStartOCStage1Time 0~100 100 0.01 s
6. CoolLoadStartInvTimeOC1T 0.05~100 100 0.01
217
Default
value
16. CoolLoadStart3I01Multiple 1~10 10 0.01
17. CoolLoadStart3I0Stage1Time 0~100 100 0.01 s
18. CoolLoadStartInvTime3I01T 0.05~100 100 0.01
Table 164 Cooling load startup logic switch

Set Default
mode value
1: check current to detect the
position of circuit breaker; 0:
1. CoolLoadStartLogicSel 1/0 0
check position of auxiliary
contact of circuit breaker.
2. CoolLoadStartProtOn 1/0 0
3 Report list

Trip report:
1. CoolLoadStart /
218
Chapter 34 Temperature protection
About this chapter

This chapter describes the temperature protection principle,
input and output signals, setting parameters, reports and
technical data.
219
1 Overview
Temperature protection is used to protect transformers, reactors and
capacitors from overload or overheating.
Device provides two lines of DC (4-20mA) input circuits; the external
circuit converts temperature into DC signal through temperature sensor
and connects to the device through DC circuit.
The analog menu of device displays temperature values of
corresponding two lines of DC circuits. When function is disabled,
temperature shows as 0.
parallel.
The input and output signals of temperature protection function are
shown as follow:
TEMP
1
ENA_TEMP
Figure 87 The input and output signals of temperature protection function diagram
The left side is the input and the right is the output, parameter description
is shown in the following table.
Input：
ENA
The total connector of temperature protection ， the
ENA_TEMP
corresponding hard connector is ENA_TEMP_5.
IED receives the DC signal of the external temperature sensing circuit,
"MinTemp" Tmin corresponds with the minimum DC Cmin , "MaxTemp"
Tmax corresponds with the maximum DC Cmax . After setting the valid
temperature within DC range, the actual tripping temperature can be
calculated by the following formula.
T = Tmin + k(C − Cmin )
Where T represents the measurement temperature, C is the
measurement DC
Tmax − Tmin
k=
Cmax − Cmin
220
Tmin : "MinTemp"
Tmax : "MaxTemp"
Cmin : The minimum DC 4mA
Cmax : The maximum DC 20mA
Take temperature stage 1 as an example, when temperature is higher
than "TempProt1TripSet", the device will issue trip signal to cut off circuit
breaker, the tripping criterion is
T > Ttrip
Ttrip "TempProt1TripSet".
When temperature is higher than "TempProt1AlarmSet", the device will
issue alarm signal, the tripping criterion is
T > Talarm
Talarm "TempProt1AlarmSet".
When "TemperatureProt1Trip"=1 and there is no binary input blocking,
the temperature protection function is enabled, and the operation is
determined by the setting of trip logic switch or alarm logic switch. After
IED tripping or alarm, light, protection trip and others can be configured
by AESP.
3 Setting list
Table 167 Temperature IED setting
Default
value
1. MinTemp -100~1000 -100 0.01 ℃
2. MaxTemp -100~1000 1000 0.01 ℃
3. TempProt1TripSet -100~1000 1000 0.01 ℃
4. TempProt1AlarmSet -100~1000 1000 0.01 ℃
5. TempProt1TripTime 0.01~4800.0 4800 0.01 s
6. TempProt1AlarmTime 0.01~4800.0 4800 0.01 s
7. TempProt2TripSet -100~1000 1000 0.01 ℃
8. TempProt2AlarmSet -100~1000 1000 0.01 ℃
9. TempProt2TripTime 0.01~4800.0 4800 0.01 s
10. TempProt2AlarmTime 0.01~4800.0 4800 0.01 s
Table 168 Temperature protection logic switch

Set Default
mode value
1-temperature protection 1 is
TempProt1On/Off
1. 0/1 0 enabled; 0-temperature protection
1 is disabled
1-temperature protection 1 tripping
2. TempProt1TripOn 0/1 0
is enabled
1-temperature protection 1 alarm is
3. TempProt1AlarmOn 0/1 0
enabled
221
1-temperature protection 2 is
4. TempProt2On/Off 0/1 0 enabled; 0-temperature protection
2 is disabled
1-temperature protection 2 tripping
5. TempProt2TripOn 0/1 0
is enabled
1-temperature protection 2 alarm is
6. TempProt2AlarmOn 0/1 0
enabled
4 Report list

Trip report:
1. TempProt1Start /
2. TempProt2Start /
3. TempProt1Trip /
4. TempProt2Trip /
Alarm report:
5. TempProt1Alarm /
6. TempProt2Alarm /
222
Chapter 35 Frequency auto-reclosing protection
Chapter 35 Frequency
auto-reclosing protection
About this chapter
This chapter describes the frequency auto-reclosing
protection principle, input and output signals, setting
parameter, IED report and technical data.
223
1. Overview
According to the installation rules of electrical equipment, frequency
auto-reclosing device is used for power reserve realization of power
generation, on the basis of re-synchronization of the disconnected power
line or on the basis of synchronization and on the condition of frequency
recovery, reduce the customers number of power outage.
When allocate equipment and distribute load in sequence, frequency
auto-reclosing function should consider the importance level of the uses.
Generally speaking, the load connection sequence of frequency
auto-reclosing is opposite to the sequency of frequency load shedding.
parallel.
2. Function module description

The input and output signals of frequency auto-reclosing protection
function diagram are shown as follow:
FAR Protection
1 1
BIBlk Start
2 2
ENA_FAR Operation
Figure 88 The input and output signal diagram of frequency auto-reclosing protection
The input signals are on the left side and the output signals are on the
right.
Function Logo Description
Input:
BIBlk BI blocking
FAR Output:
Start IED startup
Operation Protection trip
Input:
ENA The total connector of frequency auto-reclosing

ENA_FAR protection, the corresponding hard connector is
ENA_FAR_5.
224
3. Detailed description
Take the stage 1 of frequency auto-reclosing as an example, when the stage 1
of underfrequency trips, it triggers the RS trigger, and the signal is triggered
continuously during the "AutoFreqCloseCBRstTime". During this period of
time, if the normal frequency is detected, and the voltage is greater than
live voltage setting, the frequency auto-reclosing 1 trips; if the frequency is
not recovered to normal, the triggering signal resets, then even though the
frequency is recovered, there is no aut0-reclosing.
If the auto-reclosing conditions are met, in order to prevent the repeated
auto-reclosing after cutting off the load, in the period of
"AutoFreqCloseCBBlkTime", protection is blocked. During this period of time,
the stage 1 of frequency auto-closing cannot trip for the second time. After
the blocking time, the trip of stage 1 of underfrequency should be detected
again, and the auto-reclosing can trip again.
On the basis of the above principle, the setting of
"AutoFreqCloseCBBlkTime" should be greater than the setting of
"AutoFreqCloseCBRstTime" to ensure the auto-reclosing trips for the
second time. After tripping, LED, IED output and others can be configured by
AESP.
Enable frequency
auto-reclosing function
“FreqARStage1On”
=1
Underfrequency load S Q &

shedding stage 1 trip
>
FreqARStage1Trip R Q
f>”FreqARStage1
Set”
&
T1 Tp FreqARStage1Trip
Umax>”FreqARLi &
veVoltSet”
≥1
&
Umin>FreqARLive
VoltSet
T1:FreqARStage1Time
Tp:FreqARPulseSet
Figure 89 Logic diagram of frequency auto-reclosing
3.2 Setting list

Table 171 Settings of frequency auto-reclosing protection
Default Step
value
1. FreqARStage1Set 0.90Fn~1.00Fn 49.5 0.01 Hz
2. FreqARStage1Time 0.10~100.00 100 0.01 s
225
Default Step
value
9. FreqARLiveVoltSet 0.25~120 80 0.01 V
10. FreqARPulseSet 0.08~0.5 0.5 0.01 s
11. FreqARRstTime 1~1200 1200 0.01 s
12. FreqARBlkTime 1~1200 1 0.01 s
Table 172 Frequency auto-reclosing logic switch
Number Logic switch Setting Default Remark

description value
1. FreqARStage1On 1/0 0
3.3 Report list

Trip report:
1. FreqARStage1Trip /
226

Table 174 Technical parameter list
≤ ±1.5% times of setting or

+60ms
227
Chapter 36 Secondary circuit monitoring
Chapter 36 Secondary circuit

monitoring
About this chapter

This chapter describes CT failure and VT failure secondary
circuit monitoring function.
229
1 CT failure
1.1 Overview
Current transformer failure or short circuit can cause earth fault protection
and negative sequence current protection misoperation.
If there is no protection trip when CT disconnection occurs, it will produce a
very high voltage to cause damage to the secondary circuit. In order to
prevent the device from misoperation, the device monitors the sudden
change of the current of the secondary circuit of the current transformer
and alarms.
1.2 Function module description

CT failure check function input and output signal diagram is shown below:
CT-Secondary Current Supervision
1
CTFail
Figure 90 Diagram of CT failure check function input and output signal

Output:
CTFail
Alarm IED alarm
1.3 Detailed description

1.3.1 Protection principle
When the calculated zero sequence current exceeds “CTFail3I0Set ", it
sends off the report "CTFailAlarm" and the earth fault protection is blocking
through the delay of "CTFailTime". Light, protection trip and others can be
configured by AESP after the alarm report is issued.
CT failure protection is on
“CTFailAlarmOn”=1
&
InstantVTFail ≥1 T
CTFailAlarm
Calculated 3U0<1.5V
Calculated 3I0>“CTFail3I0Set”
T：“CTFailTime”
Figure 91 Logic diagram of CT failure protection
230
1.3.2 Setting list

Table 176 CT failure check setting
Default Step
value
1. CTFail3I0Set 0.05In~10In 1 0.01 A
2. CTFailTime 0.1~100 100 0.01 s
Table 177 CT failure check logic switch

Number Remark
name mode value
Enable/Disable CT failure alarm
1. CTFailAlarmOn 1/0 0
function
1.3.3 Report list


Alarm report:
1. CTFailAlarm /
2 VT failure
2.1 Overview
When the secondary circuit of the voltage transformer is broken or short
circuit, the measured voltage is zero by the protections based on the
undervoltage criterion and this can cause the mis-operation of IED. VT
failure check provides voltage monitoring for such protections. VT
monitoring is used to monitor the voltage transformer circuit, single-phase
VT failure, two-phase VT failure and three-phase VT failure. Main
characteristics are as follows:
1) Symmetry/ asymmetry (asymmetric) VT failure;
2) Three-phase AC voltage miniature transformer failure monitoring;
3) It is used in grounding system, non-direct grounding system and
ungrounded system.

VT failure check function input and output signal diagram is shown below,
Symmetrical and asymmetrical VT Fuse
Fail Detection
1 1
V3P_BI VoltLost
2
VTFail_TI
VTFail 3
V3P_BI_Err 4
Figure 92 Diagram of VT failure check function input and output signal

231
Input:
V3P_BI Three-phase VT failure BI
Output:
VTFail VoltLost Three-phase voltage loss
VTFail_TI Instantaneous VT failure
VTFail VT failure alarm
V3P_BI_Err Abnormal alarm of three-phase VT failure binary input

2.3.1 Protection principle
2.3.1.1 Protection principle
VT failure function can be enabled or disable by setting the logic switch
'VTFailOn', when the logic switch is set as 1, VT failure protection is
enabled, it can be used to detect single-phase, two-phase and
three-phase VT failure.
There are three main criteria for detecting VT failure, which are the check
of the three phase failure, the check of the asymmetric failure of the
grounding system, and the check of the asymmetry of the non-direct
grounding system. The prerequisite is that the protection device starting
component does not start and the zero sequence current and negative
sequence current are less than " VTFail3I0/3I2Set " Specifically as follows:
1) Three-phase (symmetry) VT failure: when the secondary side
three-phase of VT failure occurs, if the stating component does not
start, then the maximum of compounded zero sequence voltage 3U0
and the three-phase phase-to-earth voltage are both less than
"VTFailPEVolt", when the “3PhVTFailCurrConfirm” is enabled, the
maximum of three-phase current is greater than "VTFailCurrSet".
When the “3PhVTFailCurrConfirm” is disabled, the current condition is
not judged.
2) Single-phase/ two-phase (asymmetric) VT failure:
a) When the secondary side single-phase or two-phase of VT failure
occurs, if the system is directly grounded and the stating
component does not start, then the maximum of compounded
zero sequence voltage 3U0 exceeds "VTFailPEVolt".
b) When the secondary side single-phase or two-phase of VT failure
occurs, if the system is not directly grounded and the stating
component does not start, then then compounded zero sequence
voltage 3U0 exceeds "VTFailPEVolt" and the difference between
the maximum and minimum of voltage exceeds "VTFailPPVolt".
In addition, when the device detects binary input of three-phase VT failure,
then it is judged as three-phase VT failure. If the device detects binary
input of three-phase VT failure and the voltage exceeds "VTFailPEVolt",
then it is judged as abnormal BI signal.
232
After "InstantVTFail", "VTFailAlarm" or "VTFailBIErrAlarm" are issued, light,

protection trip and others can be configured by AESP after the alarm
report is issued.
2.3.1.2 Logic diagram
If the secondary circuit failure of VT is detected, the protection based on
the standard of direction or undervoltage will be blocked and it will send off
the report "VTFailAlarm" through the delay of "VTFailAlarmTime". When
one of the following conditions is met within the delay of
"VTFailDelayAlarm" (that is, before sending off the report "VTFailAlarm"),
VT failure blocking opens.
1) While the protection does not start, the minimum phase-to-phase
voltage exceeds "VTFailRstVolt" with 500ms delay;
2) While the protection does not start, the minimum phase-to-phase
voltage exceeds "VTFailRstVolt" and the zero sequence current and
negative current exceed "VTFail3I0/I2";
3) After "VTFailAlarm" sending off, if the protection is not started, the
smallest phase voltage is larger than "VTFailRstVolt"; after
experiencing the "VTFailDelayAlarm", VT disconnection blcoking will
be open.
The report "VTFailRst" is issued when the third VT failure recovery is
checked.
233
max(Ia,Ib,Ic)>“VTFailCurrSet” &
“3PhVTFailCurrConfirm”=1 ≥1
“3PhVTFailCurrConfirm”=0
&
max(Ua,Ub,Uc)<“VTFailPEVoltSet”
Calculated 3U0<“VTFailPEVoltSet”
“NutrPointEarth”=1 & ≥1
Calculated 3U0>=“VTFailPEVoltSet”
“NutrPointEarth”=0 &
Difference of max and min value of PP voltage

>“VTFailPPVoltSet”
&
“3PhVoltConnect”=0 ≥1
&
InstantVTFail=1
Current type protection startup
3PhVTFailBI
VT failure protection is on
“VTFailOn”=1
“VTFailOn”=0
&
Calculated 3I0>“VTFail3I0/3I2Set” ≥1 &
≥1
InstantVTFail=0
3I2>“VTFail3I0/3I2Set”
min(Ua,Ub,Uc)>“VTFailNormalVolt”
&
VTFailAlarm=1
&
&
T
T
InstantVTFail=1 VTFailAlarm=1
T：“VTFailAlarmTime”
Figure 93 Logic diagram of VT failure protection

Min PE voltage>“VTFailPEVoltSet” &
Max PE voltage>“VTFailPEVoltSet” & ≥1

T_Err
VTFailBIErrAlarm
3PhVTFailBI
T_Err：“VTFailBIErrAlarmTime”
Figure 94 Logic diagram of binary input VT failure protection
234
2.3.2 Setting list

Table 180 VT failure check setting
Default
value
1. VTFailCurrSet 0.05In~40In 0.25 0.01 A
3 times of
zero and
2. VTFail3I0/3I2Set 0.05In~40In 0.25 0.01 A negative
sequence
current
3. VTFailPEVoltSet 5.00~20.00 8 0.01 V
4. VTFailPPVoltSet 10.00~30.00 16 0.01 V
5. VTFailNormalVolt 40.00~120.00 40 0.01 V
6. VTFailAlarmTime 0.04~100 10 0.01 s
7. VTFailBIErrAlarmTime 0~100 10 0.01 s
Table 181 VT failure check logic switch

Set Default
mode value
Single-phase voltage access or
three-phase voltage access
Neutral grounding system or
2. NutrPointEarth 1/0 0
neutral non-grounding system
3. VTFailOn 1/0 0 VT failure on or off
To 0: VT disconnection blocking
requirement retreat
To 1: VT disconnection blocking
protection
Set to 0: three-phase VT failure
does not detect live current
5. 3PhVTFailCurrConfirm 1/0 0
Set to 1: three-phase VT failure
detects live current
2.3.3 Report list


Alarm report:
1. InstantVTFail /
2. VTFailAlarm /
3. VTFailBIErrAlarm /
4. 3PhLossDeadVolt /
Operation report
1. VTFailRst /
235
2.3.4 Technical parameter

Table 183 VT failure check technical data
VT Failure Current 0.05In~40In ≤ ±3% setting or ±0.02In

Zero and negative sequence currents of
0.05In~40In ≤ ±5% setting or ±0.02In
VT failure
VT failure phase-to-earth voltage setting 5.0V～20.0V ≤ ±3% setting or ±1V
VT failure phase-to-phase voltage
10.0V～30.0V ≤ ±3% setting or ±1V
setting
return to VT normal voltage setting 40.0V～120.0V ≤ ±3% setting or ±1V
In: CT secondary rated current, 1A or 5A.
236
Chpater 37 User-defined function
Chapter 37 User-defined function
About this chapter

This chapter describes BI, BO, LED configuration and user
defined logic function.
237
1 Overview
The BI, BO, report, LED of device can be enacted secondary user defined
by engineer according to demand. According to the actual situation of the
project, users can user-define the logic. This chapter mainly describes the
function of the AESPStudio tool software which may be used in
engineering application to perform the user defined function and the
matters needing attention.
2 User-defined configuration
2.1 Open project
Click the file→open, in the open file dialog box, open the file named
aespro.
2.2 Binary input configuration

The title of BI can be modified by engineering example. The property of
each BI can be set in BI configuration according to demand.
Table 184 Binary input configuration
Binary input configuration

Configuration item Description
Excitation changes from 0 to 1, experiencing time delay 1 to

BI time delay 1:
definite BI close position.
Excitation changes from 1 to 0, experiencing time delay 2 to

Binary input time delay 2
definite BI close position.
Waveform record set Configure "DRF", "RisingEdgeTrigger" and "FallingEdgeTrigger"
Configuration "SirenBit", "BellBit", "PulseQuantity", "SendSOE",

Property 1
"DualPosnBI", "ACInput" and "BCUProtocol".
Configure "NonSmartModule", "24V", "48V", "110V", "125V",

Property 2
"220V", "250V"
Property 3 Configure "OrdinaryBI", "MaintState", "Rmt/Local", "Invalid"
Bay control unit and

Configure "Prot", "BCU"
protection property
Note: when setting waveform record, if "DRF" is configured, then the BI will
be in the waveform recording. If "RisingEdgeTrigger" is configured, when
the BI changes from 0 into 1, the waveform record will be generated. If
"FallingEdgeTrigger" is configured, when the BI changes from 1 into 0, the
waveform record will be generated. The generated waveform record file
will be saved into the list of startup waveform records.
The work voltage can only be configured within ranges defined by this
module unit. Hardware board contains high power voltage level and low
power voltage level, respectively marked with the work voltage of DC
"110V", "125V", "220V", "250V" and "24V", "48V".
The explanation of time sequence of "BITime1" and "BITime1" is shown as
238
below.
Excitation
BI delay 1
BI
BI delay 2
Figure 95 Binary input time delay sequence

Configuration way of double position binary input:
Two single-position binary inputs can be used to describe the
double-position binary input, and the close position of single input
accesses to the n hardware binary input, and then the open position of
single input accesses to the n+1 hardware binary input. "DualPosnBI" can
be selected for the property 1 of binary input n; but it cannot be selected for
the property 1 of binary input n+1; and "Invalid “can be selected for the
property 3.
The logic state of a pair of binary inputs (binary input n and n+1)
configured with double-0position will no longer be that of the hardware
binary input. Only when (hardware binary input n, n+1) = (1, 0), the logic
binary input n refers to the close position state; only when (hardware
binary input n, n+1) = (0, 0) or (1, 1), the property of double-position of
binary input is 1, which means the invalid state.
Both the BI state and BI state in Mask-I/O of double-position hardware BI
and logic BI are shown below
Table 185 State list for hardware binary input of double position and logic binary input
Binary input of hardware (binary input n, binary
0, 0 0, 1 1, 0 1, 1
input n+1)
Logic binary input(binary input n, binary input
0, 1 0, 0 1, 0 0, 1
n+1)
2.3 Binary output configuration

The title of BI can be modified by engineering example. The property of
each BI can be set in BI configuration according to demand.
Table 186 Binary output configuration
Binary output configuration
Retention time: Excitation returns and BO also returns experiencing retention time.
Waveform record set Configure "DRF", "RisingEdgeTrigger" and "FallingEdgeTrigger"
Configure "ElectricLatched", "TripRedundancy",

Binary output property
"ReclaimRedundancy", "BlkedByStartup", "NCContact"
239
To configure "ElectricLatched" property, the electric relay will return only

after the signals recovering. The movement sequence is shown as below.
When the device is powered down and then power up, the electric relay
can recover the state before power down.
Excitation
Reset
Relay
Figure 96 Electric latched relay trip sequence

Configuration is the node of electric retention, which can't
"BlkedByStartup"; otherwise startup relay will return and so does BI.
None "ElectricLatched" BI can configure "LatchedTime ", excitation will
return, after the set time, the relay returns.
Excitation
Relay
Figure 97 Non-electric latched relay trip sequence

Please configure in line with the hardware jumper of BO, and determine
whether BO is "BlkedByStartup" or not, and whether "the contact is always
closed" or not.
As CPU and other redundant CPU will send off command; the
configuration as "BORedundancy" of node relay trips; as CPU and other
redundant CPU retreat all the command, the configuration as
"ReclaimRedundancy" of node relay will trip. If the protection configuration
doesn't configure redundancy, "ReclaimRedundancy" and
"BORedundancy" can't be set.
See figure 98, one of configuration properties of BO "BlkedByStartup"
must be linked with the contact of hardware, and every three BOs shall
form a group to be configured similarly. Which means BO1, BO2 and BO3
shall form a group; BO4, BO5 and BO6 form a group and so on.
Figure 98 Diagram of binary output configuration
240
2.4 LED configuration

The title of LED can be modified by engineering example. On control plate,
the calibrated LED indicator tag can be embedded into the corresponding
position of the indicator light. The property of each LED can be set in LED
configuration according to demand.
Table 187 Light configuration.
Light configuration.
Configuration "Latched", "Unlatched", and configuration is "Latched",

Holding property
recovery action should be enacted to eliminate light state.
Light color The color of LED is "Yellow", "Green" and "Red"
The LED is flashing or constant on, n represents the flash frequency is

Flashing
n*50ms; when it is 0 or 1, the LED is always on.
As the configuration is "Redundancy" property, multiple CPU will trigger

Redundancy
light at the same time and the LED will be enlightened.
As CPU and other redundant CPU all sendoff lighting command, the
configuration is "Redundancy" and the LED can be enlightened. If LED
doesn't have redundancy property, "Redundancy" property cannot be set.
2.5 IO-Matrix configuration

The IO-Matrix configuration achieves a fast correlation between virtual and
real points in the software. Virtual point comes from the application
software, corresponding to the functional software to modify the data
points, the real point from the limited resources provided by the device.
2.5.1 IO-Matrix channel configuration
The IO-Matrix channel configuration is used to specify the source of the
required input information for the application, the AC or DC excitation of
the device is configured as AC sampling or SV data.
“X” means the valid selection.
241
Figure 99 Diagram of channel configuration
2.5.2 IO-Matrix function configuration

The IO-Matrix function configuration is used to specify the protection action
of the device. External input signal is dependent on each function of the
device and external manifestations of action include the opening and the
lights, etc., through the configuration to achieve the definition.
“H” refers to the valid high power level; “L” represents the valid low power
level.
Figure 100 Diagram of function configuration
2.6 Binary input switch setting group

2.6.1 Function description
IED can switch the setting zone in two ways. When the setting
"BISwitchSetGrp" is set as 0, IED will response to the panel or SCADA to
switch the setting group; when the setting "BISwitchSetGrp" is set as 1,
IED will not response to the panel or SCADA to switch the setting group, it
will switch the setting group automatically according to the status of binary
input.
The device provides four defaults configurable BI to switch setting group,
in BIToSetGrp, BI1, BI2, BI3 and BI4 can be set by users in the
engineering research and development version.
242
Table 188 Four binary input switch setting group configuration examples
Number BIToSetGrp4/2/1 Setting group

1. 0000 1
2. 0001 2
3. 0010 3
4. 0011 4
5. 0100 5
6. 0101 6
7. 0110 7
8. 0111 8
9. 1000 9
10. 1001 10
11. 1010 11
12. 1011 12
13. 1100 13
14. 1101 14
15. 1110 15
16. 1111 16
If the various BI groups designate target setting group randomly, and the
user-defined logic of engineering research and development is realized,
then write the target setting group to **::ChangeSettingGrp.InSettingZone.
IED provides up to 32 setting groups.
Figure 101 Diagram of binary input switch setting group configuration
2.6.2 Setting list

Table 189 Logic switch of binary input switching setting group diagram

mark mode value
1. BISetGrp BISwitchSetGrp 1/0 0
2.7 Configuration startup

The function configuration of IO-Matrix offers a settable startup trip to
decide whether the protection trip of IED should be blocked by starting.
Taking the overcurrent stage 1 as an example, see figure 101 and 102:
243
Figure 102 Diagram of initiated blocking configuration

Protection trip of overcurrent stage 1 is configured via startup relay
blocking:
The corresponding Start of OC1 is the startup trip of overcurrent stage 1,
which is connected with the node PickupContact of startup relay, and the
output of BIO module is set as initiated by jumper.
Figure 103 Diagram of non-initiating blocking configuration

Protection trip of overcurrent stage 1 is configured without startup relay
blocking:
The corresponding Start of OC1 is not connected with the node
PickupContact of startup relay, and the IED trip of BIO module is set as
non-initiation by jumper.
If the protection trip of overcurrent stage 1 doesn't connect with the node
PickupContact of startup relay, but the output of BIO module is set as
initiated by jumper, then the output of overcurrent stage 1 will be blocked.
2.8 Other configuration

The name of the device can be changed according to the requirements of
the project, and it can be named in accordance with the project schedule,
so as to facilitate the maintenance of the project.
The default length of waveform recording file generated by IED is 2.5
cycles before fault and 20 cycles before and after the fault together. It
supports to instantiate RS_WAVEPARAM by AESP tool and the users can
define the length of waveform records according to their needs. The length
of single waveform record cannot be longer than 200ms before fault; the
total length of waveform records cannot be longer than 20s. Single
244
waveform record cannot be greater than 512k.
Figure 104 Setting configuration figure
2.9 Defined logic

The AESP tool provides the basic elements of the module to support
user-defined simple engineering logic. The intermediate data and the
intermediate nodes in the application software which is open to the user
can be used conveniently in the configuration interface, and the logical
application of the project is realized.
Figure 105 AESPStudio working interface
2.10 Connector attribute change

The AESP tool provides the basic elements of the module to support
user-defined simple engineering logic. The intermediate data and the
intermediate nodes in the application software which is open to the user
can be used conveniently in the configuration interface, and the logical
application of the project is realized.
The stabilization time of all hard connector is 10s, which is not
configurable.
245
Figure 106 Example of connector attribute change
246
Chapter 38 8 Control function
Chapter 38 Control function
About this chapter

This chapter describes the control functions, including the
isolator telecontrol, direct control and tap control functions.
The required control functions can be configured according to
the requirements of the project.
247
1 CB/Isolator control
1.1 Introduction
The CB/Isolator control function is used to control the opening and closing
operation of the circuit breaker or the isolator or the earthswitch, and the
control objects can be added according to the different bay requirement.

Input and output signals of isolator telecontrol function are shown as
follow:
CB/Isolator Control
1 1
OpenPermit OpenBO
2 2
ClosePermit CloseBO
3
BIState
Figure 107 The diagram of input and output signals of CB/Isolator control function
right.
Input:
OpenPermit Open permission of object
ClosePermit Close permission of object
CB/Isolator Control BIState Binary input state of double position
Output:
OpenBO Open command
CloseBO Close command

Object pre-selection operation is required before executing the SBO
(Select before operation) command.
The Object is blocked by the remote/local state. When the device is in the
remote state, it is only remotely controllable; when the device is in the local
state, it is only locally controllable.
The opening of object permission and closing of object permission can be
connected to the interlock signal or the permission logic of user-defined
opening/closing object.
The object can be configured for position check. When using the check
function, the input state of dual position needs to be connected to the
function block. If the check is not selected, it can provide open and close
command without the position check.
When using position check, if the input position state match with control
command sended, IED will return success, if not retrun fail after 30s.
248
Chapter 38 8 Control function
2 Direct control
2.1 Introduction
Direct control can be used for directly controlled objects, such as
intermediate relay reset or any free output command without
pre-sellection.

Input and output signals of direct control function are shown as follow:
Direct Control
1
OpenBO
2
CloseBO
Figure 108 The diagram of input and output signals of direct control function
right.

Output:
Direct Control OpenBO Open command
CloseBO Close command

The direct control does not require a pre-selection and is directly execute
operation.
The direct control is blocked by the remote/local state. When the device is
in the remote state, it is only remotely controllable; when the device is in
the local state, it is only locally controllable.
3 Tap control
3.1 Overview
The tap control is used to control the tap position of the transformer to
perform the operation of rise, low and stop.
3.2 Description of function module

Input and output signals of direct control function are shown as follow:
249
Tap Control
1 1
Permit TapUpBO
2 2
ATap TapDnBO
3 3
BTap TapStopBO
4
CTap
Figure 109 Input and output signal diagram of tap control

right.

Input:
Permit Allowable voltage adjustment
ATap Phase A gear
BTap Phase B gear
Tap Control CTap Phase C gear
Output:
TapUpBO Tap rise
TapDnBO Tap low
TapStopBO Tap stop

The direct control is blocked by the remote/local state. When the device is
in the remote state, it is only remotely controllable; when the device is in
the local state, it is only locally controllable.
4 Report list

Operation report:
1. TelectrlObject /
2. TelectrlCmdSrc /
3. TelectrlResult /
4. TelectrlCmd /
5. TelectrlType /
6. FailReason /
250
Chapter 39 Substation communication
Chapter 39 Substation
communication
About this chapter

This chapter describes functions such as substation
communication interface and protocol, clock
synchronization and so on.
251
1 Overview
Each IED provides communication port to communicate with one or more
substation system. IED supports following communication protocols:
1) IEC 61850-8-1 communication protocol;
2) IEC 60870-5-103 communication protocol;
3) DNP 3.0;
4) MODBUS.
1.1 Communication protocol

1.1.1 IEC61850-8 communication protocol
Protocol IEC61850-8-1 allows two or more IEDs from one or more vendors
to exchange information and use it in the performance of their functions
and for correct co-operation.
GOOSE (Generic Object Oriented Substation Event) is a part of IEC
61850-8-1 standard. By publishing and subscribing mechanism, GOOSE
standardizes communication state and control information between IEDs.
That is to say, if event is tested to happen, IED shall send information to
devices which have subscribed the event by multi cast.
1.1.2 IEC60870-5-103 communication protocol
Protocol IEC 60870-5-103 belongs to master-slave protocol and
communicates with control system through serial port. According to IEC
rules, main station is the master and substation is the slave.
Communication is carried out on the basis of point-to-point principle. Main
station should be equipped with the software that is able to receive IEC
60870-5-103 communication report. For a more comprehensive
understanding of the IEC60870-5-103 protocol, you can refer to the fifth
part of "IEC60870 standard": 103 section of "communication protocol": "the
standard of information communication interface for IED protection"
1.2 Communication port

1.2.1 Front plate communication port
Front plates of all IEDs have a RJ45 communication port respectively. By
this port, users can use PC to operate Sifang debug software to connect
IED for setting, testing, configuring and so on.
1.2.2 RS485 communication port
IED provides two electric RS485 communication ports connecting to
automatic system for substation. The port supports protocol
IEC60870-5-103. RS485-1
1.2.3 Time synchronization port
One port of the IED can be used for clock synchronization.
1.2.4 Ethernet communication port
IED provides two Ethernet ports to connect to substation's automatic
system.
252
1.3 Technical data

Table 194 Front plate communication port
Items Data
Number 1
Connection mode Debugging RJ45 port for software
Communication rate 100Mbit/s
Table 195 RS485 communication port
Items Data
Number 2
By two conductors
Connection mode
Backboard communication port
Maximum communication distance 1.0km
Test voltage 500V AC grounding
Support protocol IEC60870-5-103
Parameter is set as 9600 baud,
Communication rate Minimum 1200 baud rate, maximum 19200
baud rate
Table 196 Ethernet communication port
Items Data
Ethernet communication port
Number 2
Cable or optical fibers/backboard
Connection mode
communication port
Maximum communication distance 100m
Support protocol IEC 6087050
Support protocol IEC60870-5-103
Table 197 Time synchronization port
Items Data
Time synchronization mode Pulse or optical signal time synchronization
IRIG-B signal format IRIG-B000
Connected by two conductors or optical fibers
Connection mode
Communication port of rear plate
Volt level Differential signal
253
1.4 Typical substation communication mode

Through communication protocols supported by communication port, IED
is able to communicate with one or more substation system or device.
Figure 110 Multiple network substation automatic system connection case
1.5 Typical clock synchronization mode

All IEDs provide a clock synchronization port; it is able to choose IRIG-B
code or pulse time synchronization. For pulse time synchronization, IED
can automatically adapt to second or minute pulse time synchronization
mode. Meanwhile IED could adopt SNTP mode to synchronize.
Figure 111 Clock synchronization mode
254
Chapter 40 Man-machine interface (MMI) and operation
Chapter 40 Man-machine interface

(MMI) and operation
About this chapter

This chapter describes the relative display of man-machine
interface and its operation.
255
1 Overview
The MMI is composed of liquid crystal display (LCD), LED, panel buttons
and panel Ethernet port. Users can view information, set parameters and
debug through MMI.
2 Function description
2.1 Liquid crystal display (LCD)
The LCD back light of HMI is blue, 9 lines can be displayed. When
operating Sifang key or IED issuing alarm or trip report, background blue
light automatically lights up. Soon after the latest trip or alarm, background
blue light dies out after 5 minutes of time setting.
2.2 Man-machine interface (MMI)

MMI is man-machine interface. LCD screen displays the device running
information, such as measured value for current and voltage, connector
state and BI, BO and bay signal line diagram.
If there is no key operation, the MMI main cycle interface shows part of
device information in a cycle way. User could press “ESC” to lock current
display, and press “ESC” again to restore circulation display.
Take 19/2 inches enclosure of multi-fuction protection IED as an example,
faceplate area description is as follows: zone one is for the user-defined
indicator area; zone two is for the key area of the control function; zone
three is for the debugging of net port; zone four is for the key district of the
basic key.
CSC-211
Figure 112 MMI schematic diagram
256
The user-defined indicator area consists of 24 lights, where the position of

running lights and alarm light are fixed, and the functions of other 22 lamps
can carry out the configuration of light color, light property according to the
needs of the user; in key areas, there is indicator indicating device state on
each of the remote, local and blocking key respectively.
RUN: When running lights, the green light is lightened during the normal
operation, while the running light is off if there is an alarm of class 1.
ALARM: alarm indicator, the device alarm lightens the red light.
The faceplate uses the Ethernet port to connect PC and device, which
supports setting device parameter, measuring function, downloading
programs and analyzing data. The debugging IP address of Ethernet port
is 196.178.111.1 which is unchangeable.
The key includes basic key and control functional key. Basic key is on the
right of the screen and control functional key is below the screen to realize
human-computer interaction. Keys for IED of CSC series contain the same
appearance and operation mode, for details in below table.
Table 198 IED MMI key
Key Function
Move to the next line in menu
Move to the next line in menu
Move left in the menu
Move right in the menu
 Reset LED light

 Directly back to normal circulation display interface
 Entering main menu or sub-menu

 Affirming revised setting
 Back to previous menu

 Exit revising setting
 Back to circulation display interface
 Locking or unlocking circulation display interface (when locking, top
right corner of LCD displays an icon of a small key)
 Value adds 1;
+ 

Page down
Logic switch shift from the present value to the opposite value;
namely "1" to "0", or "0" to "1"
257
Key Function
 Value reduces 1;
- 

Page up
Logic switch shift from the present value to the opposite value;
namely "1" to "0", or "0" to "1"
F1
F2  User-defined function key
 The shortcuts for menu options are able to set to relate with menu
items to execute functions of this menu.
F3  as the input signal to participate in logic
F4
 Switching to remote operation mode and grounding control shall be
blocked.
 Switching to grounding control mode, remote operation shall be
blocked.
 It is used for locking and unlocking control key and user-defined key
so as to prevent mistakenly touching.
 Breaker closes
 Breaker opens
2.3 Menu structure

Click the key MMI to enter the IED menu, and view information or take
some related operations. Due to the differences in the function of various
type of IED, the following lists show the maximum menu configuration; the
value of related setting information and various type of IED is on the basis
of actual display.
Table 199 IED menu
L1 menu L2 menu L3 menu L4 menu Description
Read the measure

PriVal input primary-value of
the IED
Calc
Read the measure
SecVal input second-value of
the IED
ViewInfo IEDState
Read the measure
PriVal input primary-value of
the IED
Measure
Read the measure
SecVal input second-value of
the IED
258
Read the analog input

Analog
of the IED
Read the power

PowerMetr
metering of the IED
Read the binary input

ConventionalBI
of the IED
Read the
BIO GOOriginBI GOOSEoriginal binary
input
Read the binary output

ConventionalBO
of the IED
ReadGOOSEsubscrib
GOOSESubState
e information
GOState
ReadGOOSE
GOOSEPubState
publishing information
Read state information

StateMon
of the IED
Read the current alarm

AlarmInfo
information
ProtSet Read the IED setting
Read the equipment

EquipParm
ViewSet parameters
Read the parameter of

BCUParm
bay control unit
Read the function

FunctionCon
connector information
Read connector state

GOOSEPubCon information of GOOSE
ConnState
publishing
ReadGOOSEsubscrib
GOOSESubSoft
e connector
Con
information
Read the unique code

IED IDCode
of IED
Read the version

VerInfo IEDVer
information of IED
Read the check code

VrTrmlChkCode
of virtual terminal
259
Read the
TimeSyncMode synchronization mode
of IED
IEDSet
Read the Ethernet
CommParm EthernetSet
information of IED
Set function connector

FunctionCon
state
Set state information of

GOOSEPubCon
ConnOn/Off GOOSE publishing
ReadGOOSE
GOOSESubSoft
subscribe connector
Con
state
Operate
SwitchSetGr Switch present
p operation setting group
Switch remote/local
LocalCtrl
control mode
Bay single line diagram

Bay0
control
SLDCtrl
…
GenlRpt Read general report
StartupRpt Read the startup report
TripRpt Read the trip report
AlarmRpt Read the alarm report
Read the operation

OperRpt
report
ViewRpt
Read the BI change
BIChgRpt
report
Startup disturbance
StartupDFR
and fault record shown
List
in list
Trip disturbance and

TripDFRList fault record shown in
list
ProtSet ProtSet Setting the ProtSet

WriteSet
CopySetGro Copy setting of setting
up group
260
Set the substation

name, use Unicode
StationName
coding, input up to 24
characters
Set the name of the

protected equipment,
EquipParm
ProtEquipName use Unicode coding,
input a maximum of 24
characters
Set equipment
EquipParm
parameters
Set parameter of bay

BCUParm
control unit
ConventionalBO Test the BO contacts

BOTest
GOOSE BO Test GOOSE signal
FnAlarmChk
TripRepChk
GOAlarmChk
BIChk
Test communication
CommChk
signal
MSTAlarmChk
ConnChk
AnalogChk
TestMenu
MeasureChk
LEDTest Test LED light
Manual triggering to
MC DFR generate fault and
disturbance record
ViewZeroDrift
ViewScale
FactoryTest AdjZeroDrift
AdjScale
AngleCorrection
Print ProtSet Print various
261

information
SoftConn
Analog
SampleVal
IEDState BIO
ConnState
VerInfo
StartupRpt
TripRpt
Rpt AlarmRpt
OperRpt
BIChgRpt
IEDSet
SetClock Set time
Choose
TimeSyncMode
synchronization mode
NetTimeSyncIPS
TimeSet et
SetTimeZone
Mode1
Set daylight saving
DST
time
Mode2
Set the Ethernet

IEDSet EthernetSet
information of IED
IEDAddr Set IED address

Serial1Set
Set serial port
SetSerialPort Serial2Set
parameters
Serial3Set
CommParm
Set the protocol
ProtocolSet
information
PRPSet
Set the IED name,

IEDName using Unicode
encoding, up to 24
262

characters
SetPassword Set IED password
Contrast Set the contrast
Set report parameters

and the mode that
OtherSet
DisplayMode sending
primary-secondary
value to SCADA
PowerMeterZeroi Set the power metering

ng as 0
CHN Confirm
Language ENG Confirm Switch language
RUS Confirm
Click the key in the recycle main interface, the menu tree will be shown
in the MMI interface; click the key or to select menu items, when the
cursor stays in the corresponding menu item, if there is a symbol
""behind this menu item, it can click the key or to enter the next menu;
if there is no signal "", it can click the key to enter the menu items.
SIFANG 2017-10-01 21:30:1D
IEDState  Calc  ConventionalBI

ViewSet  Measure  GOOriginBI
ConventionalBO
ConState  Analog
VerInfo  PowerMetr
BIO 
ViewInfo  IEDSet 
GOOSEState
Operate  StateMon
ViewRpt  AlarmInfo
WriteSet 
TestMenu
IEDSet 
Language 
PresentSetGrpNo.:
Figure 113 Menu tree diagram
263
The following diagram is an example of "ConverBO" menu.
BO 1/2
IEDFaultAlarm 0
RunErrAlarm 0
X9_BO3 0
X9_BO4 0
X8_BO1 0
X8_BO2 0
X8_BO3 0
X8_BO4 0
X8_BO5 0
Figure 114 Menu diagram
264
Chapter 41 IED hardware
About this chapter

This chapter describes hardware for device.
265
1 Overview
1.1 IED structure
Height for IED crate is 4U and width is 19 2 inches. The whole is for
embedded installation with back-wiring mode.
Figure 115 Installation size diagram (unit mm)

1) The front panel of IED is aluminum alloy by founding in integer and
overturn downwards. LCD, LED and setting keys are mounted on the
panel. There is a RJ45 interface on the panel suitable for connecting a
PC;
2) Back plug mode, module is fixed by screw spike;
3) Module is connected through bus of rear plate.
266
1.2 Module arrangement diagram
Figure 116 IED rear plate module layout diagram
2 Analog input module

2.1 Overview
AC module contains voltage and current transformers. The module
converts two-side current and voltage to processable signal for IED data
collecting system and serves as electrical isolation. IED in different type
shall be with different current and voltage transformers. The module is
optional according to different project requirements.
2.2 Analog input module introduction

The following figure shows the AC module terminal diagram of a certain
type of configuration, the module supports the access of 4 channels of
protective current, 1 measuring voltage and 4 channels of voltage.
The 4 channels of protection current channels Ia, Ib, Ic, I0 support 1A or
rated 5A current access, and each current channel provides 3 wiring
terminals. The terminal identification without ' suffix is shared inlet positive
terminal, while that with' suffix is the outlet negative terminal. For example,
the use of rated 1A shift of Ia should access the amount of current from the
Ia terminal to the Ia_1’ terminal, with Ia_5 ' terminal suspended; the use of
rated 5A shift should access the amount of current from the Ia terminal to
Ia_5' terminal with the Ia_1' terminal suspended; the wiring principle of
other protection type of current channels is same.
Is in the following figure is measured current channel, automatic
compatible of rated 1A/5A input, the terminal identification without ' suffix is
shared inlet positive terminal, while that with' suffix is the outlet negative
terminal, the magnitude of current should always be accessed from Is
terminal, and extracted from Is' terminal.
267
U4, Ua, Ub, Uc in the following figure are voltage channels, and the
terminal identification without ' suffix is shared inlet positive terminal, while
that with' suffix is the outlet negative terminal.
Figure 117 AC module terminal diagram
2.3 Technical data

Table 200 Current transformer parameters
Executive
Items Data
standard
Rated current IEC60255-1 1A or 5A
Protection CT is 0.05 In to 40
Sampling range for nominal current
In, while measurement CT is
transformer
0.05 In to 1.2 In.
Sampling range for high sensitive
0.005 to 1.2A
current transformer
When In=1A,≤0.2VA;
Power consumption (per phase)
When In=5A,≤0.5VA
Thermal overload capacity of nominal IEC60255-1 100In overload 1s
current transformer IEC60255-27 Continuous 4 In
Thermal overload capacity for high IEC 60255-27 80A, load for 1S
sensitive current transformer DL/T 478-2013 2A, continuous
268
Table 201 Voltage transformer parameter
Items Executive standard Data

Rated voltage Vr (line voltage) IEC60255-1 100V/110V
Sampling range (phase-to-earth
0.4V~180V
voltage)
IEC60255-27
Power consumption (Vr = 110V) ≤ 0.1VA each 5VA phase
DL/T478-2013
Thermal overload capacity (phase IEC60255-27 400V overload 60s

voltage) DL/T478-2013 200V, continuous
3 BIO module
3.1 Overview
BIO module provides certain of protection tripping and closing control so
as to realize tele-control switching of the switch and isolator.
The BI and BO of the hardware of BIO module include two types of
welding: 1) high power voltage level, adaptive 110V, 220V, 125V, 250V
and 2) low power voltage level, adaptive 24V and 48V. Work rated power
source of device BI is modified by configuration file before applying.
3.2 BIO module introduction

There are three indication lights on the BIO panel to show the status of the
board, the indication light definition is shown in the following.
Table 202 Definition of BIO module indicator
Serial number
Function of indicator
of indicator Introduction of indicator status
light
light
1 Power supply light Light is on when power on
2 Running light Flash when operating properly
3 Spare Off
According to the different slot locations of the BIO module, different board
addresses need to be set and address is set through jumper J6. Take the
side away from single board as L side, the side near single board as H side,
from bottom to top is AD0, AD1, AD2, AD3.
Table 203 BIO module address definition
Slot Control
Jumper Jumper settings
location content
BIO1
BIO1 J6 AD3~AD0 are short connected to the L side
address
BIO2 AD3~AD1 are short connected to the L side, AD0 is
BIO2 J6
address short connected to the H side
BIO3 AD3, AD2, AD0 are short connected to the L side, AD1
BIO3 J6
address is short connected to the H side
BIO4 AD3, AD2 are short connected to the L side, AD1 and
BIO4 J6
address AD0 are short connected to the H side
Each BIO board has 6 BI and 12 BO. 6 BI are divided into 2 groups, and
each of 3 BI shares a common terminal.
12 BO are divided into 4 groups, and each group can be set as whether
through the starting through jumper, with total four groups of jumpers
269
J11~J14. The jumper inserting into 1, 2 pin represents through starting
relay outlet, inserting into 2, 3 pin represents not through starting relay
outlet.
Table 204 Description 1 for jumper of BIO module
BIO module address
Binary output 1 and 2 pin 2 and 3 pin
definition jumper
J11 BO1~BO3 Start Without start
BO12 can switch normally open or normally closed contact by JP1 jumper,
when the jumper jumps to NC side, it is normally closed contact, when the
jumper jumps to NO side, it is normally open contact.
Table 205 Description 2 for jumper of BIO module
Jumper Binary output NC NO
Normally closed Normally opened
JP1 BO12
contact contact
BIO
1 2 3
c a
2 BO1
4 BO2
6 BO3
BINARY OUTPUT
8 BO4
10 BO5
12 BO6
14 BO7
16 BO8
18 BO9
20 BO10
22 BO11
24 BO12
26 BI4 BI1
BINARY INPUT
28 BI5 BI2
30 BI6 BI3
32 COM2 COM1
Figure 118 BIO module terminal diagram
270
3.3 Technical data
Table 206 BI parameter
Exec
Items utive Data
standard
110V/125V/220V/250V DC
Rated voltage IEC60255-1
24V/48V DC
Startup voltage IEC60255-1 70%Ur, rated DC 24V/48V, 110V/125V/220V/250V
Return voltage IEC60255-1 55%Ur, rated DC 24V/48V, 110V/125V/220V/250V
286V, rated DC voltage 110V/125V/220V/250V;
The maximum BI voltage IEC60255-1
62V, rated DC voltage 24V/48V;
Maximum 0.5W/ input, 110V DC
Power consumption IEC60255-1
Maximum 1W/ input, 220V DC
Table 207 BO parameter
Executive
Items Data
standard
Maximum work voltage IEC60255-1 250V AC
5A continuous,
Current carrying capacity IEC60255-1
30A, 200msON,15sOFF
1100W(DC) at inductive load L/R>40 ms
Closing capacity IEC60255-1
1000VA(AC)
220V(DC), 0.15A, L/R≤40ms
Arc breaking capacity IEC60255-1
110V(AC),0.30A, L/R≤40ms
Mechanical endurance IEC60255-1 50,000,000 times (switching frequency is 3HZ)

Opening times IEC60255-1 ≥1000
Closing times IEC60255-1 ≥1000
IEC60255-1
Authentication IEC60255-23 UL/CSA, TŰV
IEC61810-1
IEC60255-1
Contact circuit resistance IEC60255-23 30mΩ
IEC61810-1
Contact insulation test (AC IEC60255-1
AC1000V, 1min
dielectric strength ) IEC60255-27
Maximum temperature that

IEC60255-1 70℃
operation allows
4 CPU module
4.1 Overview
CPU module is the core of the IED and responsible for running all
protection logic to carry out the hardware self-check and communication
with external devices such as MMI, PC, measurement, substation
automatic system, working station, RTU, printers and so on. Besides, CPU
module sends telemetry, telesignalisation, SOE, event report and recorded
wave to backstage, it provides time synchronization and communication
port.
271
CPU module provides multiple configurations for user's need. Differences
lie in quantities for Ethernet port, optical/electric port, time synchronization
mode, storage capacity and so on.
4.2 CPU module introduction

The CPU module panel has six indicators to indicate the operation status
of the board and the definition of indicator is shown as below table.
Table 208 Definition of indicator of CPU module
Indicator
serial Indicator function Indicator state introduction
number
Panel Ethernet 1 Flash when communicating normally while close
1
indicator when communicating abnormally
Panel Ethernet 2 Flash when communicating normally while close
2
indicator when communicating abnormally
3 Spare /
Flash when operating normally while close when
4 Running LED of CPU
operating abnormally
5 Spare /
6 Spare /
CPU
1 2 3
4 5 6
ETH1
ETH2
ETH3
1
RS485-1A/PULSE-
2
RS485-1B/PULSE+
RS485-1GND 3
4
RS485-2A 5
RS485-2B 6
RS485-2GND 7
8
RS232-TXD 9
RS232-RXD 10
RS232-GND 11
Figure 119 CPU module terminal diagram

The serial port 1 of the standard CPU is only used as a time
synchronization port, and the protocol of serial port 1 needs to be set to
none.
272
Table 209 Definition of CPU module in serial communication terminal
Terminals Definition Remark

01 485-1A
02 485-1B Serial port 1
03 485-1GND
04
05 485-2A
07 485-2GND
08
09 RS232-TXD
10 RS232-RXD Serial port 3
11 RS232-GND
Table 210 Net port configuration
Number Configuration
1 RJ45 electrical port+RJ45 electrical port
3 Light port+light port
4.3 Technical data

Table 211 RS485 communication port
Items Data
Number 2
Extract twisted pair. On the CPU module
Port type
bottom plate
Maximum transmission distance 1.0km
Voltage withstand test 500V earthing AC voltage
Used for protocol IEC60870-5-103
Default setting 9600bps
Transmission rate
Minimum: 1200bps; maximum: 19200bps
Table 212 Ethernet communication port
Items Data
Ethernet port
Number 2
RJ45 or optical Ethernet port. On the CPU
Port type
module bottom plate
Maximum transmission distance 100m
Used for IEC61850 Protocol
Transmission rate 100Mbit/s
Used for protocol IEC60870-5-103
Transmission rate 100Mbit/s
273
Table 213 Time synchronization
Items Data
Synchronization mode IRIG-B time synchronization
IRIG-B signal format IRIG-B000
Twisted-pair connection or optical fibers On the
Port type
CPU module bottom plate
Voltage level Differential signal input
5 Power supply module

5.1 Overview
The input of the power supply module is the working voltage of the device,
and the output is the working voltage of the other boards of the device. The
input and output circuits of the power supply module are not common,
which plays the electric isolation role. In order to improve anti-interference
ability for power supply module circuit, the power supply module is
equipped with anti-interference filter inside the device. What's more, the
module is equipped with sophisticated power protection function
(undervoltage, overvoltage, overcurrent, overpower, etc.) to prevent IED
breakdown from power supply module failure. Power supply module
provides 11 channels BI and 4 channels relay BO, and provide reliable
electric isolation.
5.2 Power module introduction

There is a power indicator light on the power supply panel to indicate the
status of the board; it is often on when normal.
BI10 on the power supply module is fixed defined as "IEDRst", BO1 is
fixed defined as "IEDFaultAlarm", and BO2 is fixed defined as
"RunErrAlarm". Other BI and BO can be user-defined according to
different functional requirements by the user. Each channel of BO has two
sets of nodes, respectively corresponding to BO common port 1 and BO
common port 2, BO relay are non-retaining type.
Note: BO1 is constant-closed contact, other BOs are constant-opened
contacts, and BO3 and BO4 are fixed to trip not by starting relay.
274
POWER
PWR
c a
2 BI7 BI1
4 BI8 BI2
BINARY INPUT
6 BI9 BI3
8 BI10 BI4
10 BI11 BI5
12 BICOM BI6
SIGNAL CONTACT
14 COM2 COM1
16 FAIL 1 FAIL 2
18 ALARM 1 ALARM 2
20 BO3-1 BO3-2
22 BO4-1 BO4-2
24 IN+ POWER INPUT
26
28 IN-
30
32
Figure 120 Terminal diagram of POWER module

Table 214 The definition of power supply module terminals
Number c a
2 Binary input 7 BI1
4 Binary input 8 Binary input 2
8 Device reset Binary input 4
12 BI common terminal Binary input 6
14 BO common port 1 BO common port 2
16 IED fault alarm 1 IED fault alarm 2
18 Run abnormal alarm 1 Run abnormal alarm 2
20 BO 3-1 BO 3-2
22 BO 4-1 BO 4-2
24 Power supply positive Power supply positive
26 Undefined Undefined
28 Negative power supply Negative power supply
30 Undefined Undefined
32 Grounding Grounding
275
5.3 Technical data

Table 215 Technical data
Item number Executive standard Data
Rated voltage Uaux IEC60255-1 110V to 250V
Input voltage range IEC60255-1 ±%20, Uaux
Static power consumption IEC60255-1 ≤ 50W for each power module
Maximum load power
IEC60255-1 ≤ 60W for each power module
consumption
6 TCS Module
6.1 Overview
It shall be noticed that the plate shall be assembled and welded according
to the different rated working power, please make sure before use.
The built-in TCS function is applicable to the occasion when the trip
contacts in device are used for trip directly; generally, it is applied to the
occasion when installing protection device with medium voltage in switch
cabinet. In 80% occasions, only the trip circuit is monitored, the closing
circuit doesn't get monitored. Therefore, the device provides a module with
TCS circuit and trip relay cooperating with each other.
6.2 TCS Module instructions

TCS plate provides one tripping monitoring circuit, two large capacity BI
circuits and two pairs of relays and four outlet contacts.
276
Figure 121 TCS module terminal diagram

There are three indication lights on the TCS panel to show the status of the
board, the indication light definition is shown in the following.
Table 216 Definition of indicators of TCS module
Serial number
Function of
of indicator Introduction of indicator status
indicator light
light
1 Power supply light Light is on when power on
2 Running light Flash when operating properly
3 Spare Off
277
6.2.1 TCS trip monitoring circuit
TCS module can monitor the open circuit of breaker the whole time,
including various operating conditions.
Figure 122 TCS circuit schematic diagram

Terminal a2, c4, a4 are connected with tripping circuit via auxiliary contact,
when failure occurs in circuit, K1 and K2 open simultaneously, and send
alarm signal; block can be realized through external circuit connection.
Figure 123 TCS circuit wiring diagram
278
6.2.2 Binary output circuit with large capacity
Taking the binary output circuit with large capacity PO1 as an example, the
schematic diagram and wiring instruction are as follows; open PO1 to drive
trip coil or closing coil.
Figure 124 Binary output circuit with large capacity schematic diagram
When the binary output current is larger than 6A, then the terminals of list
a and list c need to be connected in parallel.
6.2.3 Ordinary BO circuit
Figure 125 Ordinary BO circuit schematic diagram

Table 217 Binary output instruction
Relay BO name Terminals BO type
c26～a26 Normally open

RELAY3A BO1

RELAY4A BO2
c32～a32 Always close
279
6.3 Technical data

Table 218 Binary output circuit with large capacity parameters
Executive
Items Data
standard
Maximum work voltage IEC60255-1 250V, AC
8A continuous,
30A, 200msON,15sOFF
240W (DC)
2000VA(AC)
220V(DC), 0.15A, L/R≤40ms
110V(DC), 0.30A, L/R≤40ms
Mechanical endurance IEC60255-1 10100,000 times (resistive load)

IEC60255-1
IEC61810-1
IEC60255-1
IEC61810-1
AC1000V, 1min

IEC60255-1 70℃
operation allows
Table 219 TCS circuit (binary input) parameter

Rated voltage IEC60255-1 110V, 220V DC
Startup voltage IEC60255-1 70%Ur
Return voltage IEC60255-1 55%Ur
143V, rated DC voltage 110V
The maximum BI voltage IEC60255-1
286V, rated DC voltage 220V
Power consumption IEC60255-1
Table 220 BO parameter
Maximum work voltage IEC60255-1 250V AC
8A continuous,
30A, 200ms, ON; 15s, OFF
240W(DC) at inductive load L/R>40ms
2000VA(AC)
220V(DC), 0.15A, L/R≤40ms
110V(DC), 0.30A, L/R≤40ms
Mechanical endurance IEC60255-1 10100,000 times (resistive load)

280
IEC60255-1
IEC61810-1
IEC60255-1
IEC61810-1
AC1000V, 1min
IEC60255-1 70℃
operation allows
7 Test
Table 221 Insulation test
Items Executive standard Measurement methods
Front panel: IP54
IEC60255-27
Protection level (IP) Side panel: IP52
IEC60529
Front panel: IP30
2KV, 50Hz (rated
voltage >63V) tested between
the following circuits:
 Power supply
 CT / VT input
IEC60255-5
 Binary input
EN60255-5
 Binary output
Dielectric Strength ANSIC37.90
Case grounding 500V, 50Hz
GB/T15145-2017
(rated voltage ≤63V)
DL/T478-2013
Test between the following
circuits:
 Communication port
 Time synchronization port
 Case earthing
5kV (rated voltage>60V)(
1kV (rated voltage≤60V)
1.2/50μs,0.5J
IEC60255-5 Test between the following
IEC60255-27 circuits:
EN60255-5  Power supply
Impulse voltage
ANSIC37.90  CT / VT input
GB/T15145-2017  Binary input
DL/T478-2013  Binary output
 Communication port
 Time synchronization port
 Case earthing
IEC60255-5
IEC60255-27
EN60255-5
Insulation resistance ≥100MΩ, 500V, DC
ANSIC37.90
GB/T15145-2017
DL/T478-2013
Earthing resistance IEC60255-27 ≤0.1Ω
Flame rating IEC60255-27 Level V2
281
Table 222 EMC test
IEC60255-22-1
IEC60255-26 Level III
1MHz pulse group
IEC61000-4-18 2.5kV, CM;
interference test
EN60255-22-1 1kV, DM
ANSI/IEEEC37.90.1
IEC60255-22-2 Level IV
Electrostatic discharge
IEC61000-4-2 ±8kV electro-contact discharge;
immunity
EN60255-22-2 15kV air discharge;
Level IV
Radiated electromagnetic IEC60255-22-3
10V/m, 80MHz~1GHz,
field immunity EN60255-22-3
1.4GHz~2.7GHz
IEC60255-22-4,
Immunity degree of Level IV
IEC61000-4-4
electrical fast transient pulse Communication port: 4KV;
EN60255-22-4
group Other ports: 2KV
ANSI/IEEEC37.90.1
Level IV
IEC60255-22-5
Surge (impact) immunity 4.0kV, CM;
IEC61000-4-5
2.0kV, DM
Frequency scanning: 150kHz–
80MHz
Radio frequency IEC60255-22-6 Calibration frequency: 27MHz and
interference test IEC61000-4-6 68MHz
10V
AM,80%,1kHz
Level A
Power frequency immunity
IEC60255-22-7 300V, CM
test
150V, DM
Class V
Power frequency magnetic
IEC61000-4-8 100A / m greater than 30s
field immunity test
1000A/m, from 1s to 3s
Level III
100KHz pulse-group noise
IEC61000-4-18 Communication port: 2KV
immunity
Other ports: 4KV
Damped oscillation Class V
IEC61000-4-10
magnetic field immunity test 100A/m
Pulse magnetic field Class V
IEC61000-4-9
immunity 1000A/m
Conducted emission IEC60255-25 0.15MHz~30MHz, Class A
Radiated emission IEC60255-25 30MHz~30MHz, Class A
Table 223 Mechanical test
Sinusoidal vibration IEC60255-21-1
Grade 1
response test EN60255-21-1
Sinusoidal vibration and IEC60255-21-1
Grade 1
endurance test EN60255-21-1
IEC60255-21-2
Impact response test Grade 1
EN60255-21-2
IEC60255-21-2
Impact and endurance test Grade 1
EN60255-21-2
282
Collision test IEC60255-21-2 Grade 1
Aseismic test IEC60255-21-3 Grade 1
Table 224 Environmental test
Items Data
High and low temperature test -40°C to +70°C
Temperature storage test -40°C to +70°C
Maximum relative humidity 95% , no
Humidity test
condensation
8 Structural design
Table 225 Structural design
Items Data
Dimension 4U×1/2, 19 inches
Weight ≤ 9kg
9 CE Certification
Table 226 CE Certification
Items Data
EN61000-6-2 and EN61000-6-4(EMC
EMC
steering committee 2004/108/EC)
LVD EN60255-27(LVD2006/95EC)
10 Permissible environmental conditions

Table 227 Permissible environmental conditions(IEC 60255-1:2009)
Environmental parameters Conditions
Operating temperature -40℃ - + 70℃(Except LCD)
Storage temperature -40℃ - + 70℃
Relative humidity 5% - 95%
Altitude ≤ 2 000 m
Pollution degree 2
Mechanical class 1
EMC emission class A
EMC immunity zone A
283
Chapter 42 Appendix
Chapter 42 Appendix
285
Chapter 42 Appendix
1 Setting list
Table 228 IED parameter
Number Name Range Unit Default Remark

1. IEDCTPriVal 0~9999 A 8000
2. IEDCTSecVal 1~5 A 1
3. 3I0CTPriVal 0~9999 A 8000
4. 3I0CTSecVal 1~5 A 1
5. SEF/REFCTPriVal 0~9999 A 8000
6. SEF/REFCTSecVal 1 A 1
7. VTPriVal 0~1000 V 110
8. VTSecVal 0~120 V 100
9. U4VTPriVal 0~1000 V 110
10. U4VTSecVal 0~120 V 100
11. UnbalanceVTPriVal 0~1000 V 110
12. UnbalanceVTSecVal 0~120 V 100
13. UnbalanceCTPriVal 0~9999 A 8000
14. UnbalanceCTSecVal 1~5 A 1
15. MeasureCTPriVal 0~9999 A 8000
16. MeasureCTSecVal 1~5 A 5
17. BISwitchSetGrp 0/1 0
18. 4-20mAScaleVal 4~20 mA 20
2 Report list
About operation report and protection alarm report please see the
report list in the protection chapter.
2.1 Alarm report

IED contains three kinds of alarm reports, showing as follows:
1) Alarm I belongs to IED alarm. When alarm I happens, the alarm LED
on the front panel of the IED will flash, all of protection function will be
out of service and the trip power of protection will be blocked by the
IED.
2) Alarm II belongs to other alarm. When alarm II happens, the alarm
LED on the front panel of the IED will flash. Alarm II won't block the trip
power of protection.
The alarm report shall block all protection functions.
286
Chapter 42 Appendix
Table 229 Class I alarm report list
Number Report name Alarm code Description
1. SampleValErr 32769
2. IEDParmErr 32770
3. ROMSumChkErr 32771
4. SetErr 32772 Need to rewrite setting
5. UnconfirmConnMode 32773
6. SoftConnErr 32774
7. SystemCfgErr 32775
8. IED CPUModuleErr 32778
9. SetGrpPointerErr 32780
10. LogicFileErr 32798 Need to reload sf、esdc file
11. CfgFileErr 35769
12. CfgFileInconsist 35770
13. IOMatrixErr 35771 Need to reload sf、esdc file

The setting of binary
output module jumper is
not consistent with the
14. BOChkNoResponse 33769
software configuration,
and the jumper should be
reset.
15. BOBreakdown 33770
16. BIBreakdown 33784
17. BIO CPUErr 33789
18. BIO ROMSumErr 33790
The module of BI and BO
19. BIO EEPROMErr 32779 is unmarked, please
remark it.
20. BIOCfgErr 32777
21. BISelfChkCircuitErr 33787
22. BOLatchedPropertyCfgErr 33793
You need to confirm the
module address jumper,
23. BICommInterrupt 33781 module should be plugged
tightly, and confirm that the
program of BI is correct.
You need to confirm the
module address jumper,
24. BOCommInterrupt 33782 module should be plugged
tightly, and confirm that the
program of BI is correct.
287
Chapter 42 Appendix
Table 230 Report list of system class 2 alarm
Number Alarm report Alarm code Description
1. SRAMSelfChkErr 33771
2. TestStateNotRst 33772
3. OperFail 33773
4. CanCommInterrupt 33775
5. FLASHSelfChkErr 33776
6. WorkInTestSetGrp 33783
7. BIInputErr 33785
8. DualPosnInputIncosist 33786
9. BIOInputPowerErr 33788
2.2 Operation report

Table 231 System operation report list
Number Report Alarm code

1. 32769
SwitchSetGrpSuccess
2. 32789
CopySetGrpSuccess
3. 32770
WriteIEDSetSuccess
4. 32771
WriteParmSuccess
5. 32772
WriteCfgSuccess
6. 32773
AdjScaleSuccess
7. 32788
AdjAngleSuccess
8. 32774
HardConnOn/OffSuccess
9. 32775
SoftConnOn/OffSuccess
10. 32776
ClearCfg
11. 32778
IEDRst(CPUReboot)
12. 32779
FactoryRst
13. 32780
BOTestSuccess
14. 32782
ZeroDriftAdjSuccess
15. 32783
ClearAllRptSuccess
16. 32785
MaintModeOn
17. 32786
MaintModeOff
18. 32868
AutoRebootAfterCfg
288
Chapter 42 Appendix
3 Typical wiring
The CT rated value of 1A will be taken as the example in the following
wiring diagrams. For CT of 5A, just switch its grounding end to the
corresponding grounding terminal of 5A.
3.1 As to incoming and outlet line feeder protection

and line backup protection
A
B
C
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
Figure 126 Apply to feeder protection measurement three phase earth current
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
Figure 127 Apply to feeder protection measurement three phase earth current and three
phase earth voltage beside busbar
289
Chapter 42 Appendix
A
B
C
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
Figure 128 Apply to feeder protection measurement three phase earth current and three
phase voltage beside line
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
Figure 129 Apply to feeder protection measurement three phase earth current and one
line voltage beside busbar
290
Chapter 42 Appendix
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
Figure 130 Apply to feeder protection measurement three phase earth current and
single phase voltage beside busbar
A
B
C
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
a7
*
I1
b7
Figure 131 Apply to feeder protection measurement line three phase, zero sequence
and highly sensitive zero sequence current
291
Chapter 42 Appendix
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6
IN
AIM1
a7
*
I1
b7
Figure 132 Apply to feeder protection measurement line three-phase, zero sequence
and highly sensitive zero sequence current and three-phase voltage beside busbar
A
B
C
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM1
* a7
I1
b7
and highly sensitive zero sequence current and three-phase voltage beside line
292
Chapter 42 Appendix
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
* a7
I1
b7
Figure 134 Apply to feeder protection measurement line three phase, zero sequence
and highly sensitive zero sequence current and one line voltage beside busbar
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
* a7
I1
b7
and highly sensitive zero sequence current and single-phase voltage beside busbar
293
Chapter 42 Appendix
3.2 As for transformer backup protection IED
A
B
C
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
* a7
b7
I1
Figure 136 Apply to transformer backup protection measurement three phase current,
zero sequence current and neutral point earth current
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
* a7
b7 I1
Figure 137 Apply to transformer backup protection measurement three-phase current,

zero sequence current and neutral point earth current and three-phase voltage beside
busbar
294
Chapter 42 Appendix
A
B
C
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM1
* a7
b7 I1
Figure 138 Apply to transformer backup protection measurement three-phase current,

zero sequence current and neutral point earth current and three-phase voltage beside line
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
* a7
b7 I1
zero sequence current and neutral point earth current and single line voltage beside
busbar
295
Chapter 42 Appendix
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
* a7
b7 I1
zero sequence current and neutral point earth current and single-phase voltage beside
busbar
3.3 As for synchronization function

A
B
C
A
B
C
AIM2
a9
U4
b9
a10
UA
a11
UB
a12
UC
b10b11b12
UN
Figure 141 Double busbar performance synchronization application typical connection
296
Chapter 42 Appendix
A
B
C
AIM2
a9
U4
b9
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
Figure 142 Feeder current protection synchronization application typical connection
297
Chapter 42 Appendix
3.4 As for capacitor protection

A
B
C
Capacitor bank AIM1

* a6
b6 IC1
* a7
b7
IC2
* a9
b9 IC3
Figure 143 Capacitor imbalance protection three line imbalance connection mode of
current connection
A
B
C
Capacitor bank AIM1

I03
I04 IC1
*
I05
I06
IC2
I07
I08 IC3
Figure 144 Capacitor imbalance protection single line imbalance connection mode of
current connection
298
Chapter 42 Appendix
A A
B
B C
C
I1 I1
I2
I3
Figure 145 On earth capacitor suits Figure 148 On earth Capacitor suits
single line imbalance current protection single line imbalance current protection
connection mode connection mode
A A
B B
C C
U1
I1
Figure 149 Not on earth Y-pattern
Figure 146 On earth Y-pattern connection capacitor suits neutral points
connection capacitor suits neutral points voltage protection connection mode
differential current protection connection
mode A
B
A C
B
C
U1
I1
Figure 150 On earth Y-pattern
Figure 147 Not on earth Y-pattern connection capacitor suits neutral points
connection capacitor suits neutral points voltage protection connection mode
current protection connection mode
299
Chapter 42 Appendix
A A
B
C B
C
U1 U1
Figure 151 On earth Y-pattern Figure 153 On earth Y-pattern
connection capacitor suits neutral connection capacitor suits neutral points
position three phase imbalance voltage imbalance voltage protection connection
mode
A
B A
C B
C
U1
U1
U2
Figure 152 Non on earth Y-pattern U3
connection capacitor suits three PT Figure 154 Capacitor suits three phase
measurement neutral points current imbalance voltage measurement
connection mode connection mode
300
Chapter 42 Appendix
CSC-211
Figure 155 As for load shedding protection function typical connection
4 Inverse time characteristic

4.1 Twelve types of IEC and ANSI time inverse
property curve
In setting, if time inverse property curve is set, the corresponding curve will
be related. To support IEC and ANSI time inverse curve.
Table 232 Twelve types of IEC and ANSI time inverse property curve
Serial
number Inverse time curve Parameter A Parameter P Parameter B
of curve
1 IEC inverse time 0.14 0.02 0
2 IEC Very inverse time 13.5 1.0 0
3 IEC extreme inverse time 80.0 2.0 0
4 IEC short inverse time 0.05 0.04 0
5 IEC long inverse time 120.0 1.0 0
6 ANSI inverse time 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
9 ANSI moderate inverse time 0.0103 0.02 0.0228
10 ANSI very inverse time 3.922 2.0 0.0982
11 ANSI extreme inverse time 5.64 2.0 0.02434
12 ANSI definite inverse time 0.4797 1.5625 0.21359
4.2 User definable properties

For inverse time characteristic, when the curve number is set 13, it is
user-defined characteristic.
301
Chapter 42 Appendix
A
t=� i p
+ B�T
� � −1
I
Where:
A: time coefficient of inverse time
B: time delay of inverse time
P: inverse time index
T: inverse time constant
5 CPU module upgrading introduction

CPU
1 2 3
4 5 6
ETH1
ETH2
ETH3
1
RS485-1A/PULSE-
2
RS485-1B/PULSE+
RS485-1GND 3
4
RS485-2A 5
RS485-2B 6
RS485-2GND 7
8
RS232-TXD 9
RS232-RXD 10
RS232-GND 11
Figure 156 CPUmodule terminal diagram

The enhanced CPU supports serial port 1 and time synchronization
multiplex hardware ports. The functions are switched by software. When
used as time synchronization port, the protocol of serial port 1 needs to be
set to none.
Table 233 Definition of CPU module in serial communication terminal
Terminal Definition Remark
01 485-1A
Serial port 1
02 485-1B
302
Chapter 42 Appendix
03 485-1GND
04
05 485-2A
07 485-2GND
08
09 RS232-TXD
10 RS232-RXD Serial port 3
11 RS232-GND
6 Connector list
connector, soft-hard series, soft-hard parallel, and soft-hard parallel by
default.
Table 234 CSC-211-EB Connector list
No. Connector name Explanation Remark
1. MaintConn 1-On, 0-Off
2. OCConn 1-On, 0-Off
3. 3I0Conn 1-On, 0-Off
4. SEF/REFConn 1-On, 0-Off
5. I2Conn 1-On, 0-Off
6. UnderCurrentConn 1-On, 0-Off
7. UnbalanceUConn 1-On, 0-Off
8. UnbalanceIConn 1-On, 0-Off
9. ThermalOLConn 1-On, 0-Off
10. CBFConn 1-On, 0-Off
11. DZConn 1-On, 0-Off
12. StubConn 1-On, 0-Off
13. BCConn 1-On, 0-Off
14. FreqDf/dtConn 1-On, 0-Off
15. SOFTConn 1-On, 0-Off
16. OLLoadShedConn 1-On, 0-Off
17. UVLoadShedConn 1-On, 0-Off
303
Chapter 42 Appendix
No. Connector name Explanation Remark
18. ARConn 1-On, 0-Off
19. SimpleBusDiffConn 1-On, 0-Off
20. BlkSimpleBusDiffConn 1-On, 0-Off
21. CoolLoadStartConn 1-On, 0-Off
22. TempProtConn 1-On, 0-Off
23. OVConn 1-On, 0-Off
24. 3U0Conn 1-On, 0-Off
25. U2Conn 1-On, 0-Off
26. UVConn 1-On, 0-Off
27. PowerProtConn 1-On, 0-Off
28. OEConn 1-On, 0-Off
29. HVSideUFConn 1-On, 0-Off
30. HVSideOFConn 1-On, 0-Off

For the customized
31. FreqCloseConn 1-On, 0-Off
version of Armenia
7 Explanation of abbreviations
7.1 Explanation of setting abbreviations
Table 235 Explanation of setting abbreviations
Abbreviations Explanation
OCStage1CurrSet Current setting of overcurrent stage 1
OCSatge1Time Overcurrent stage 1 time setting
OCStage1AlarmSet Current alarm setting of overcurrent stage 1
OCStage1TimeAlarmSet Overcurrent stage 1 alarm time
OCStage1Curve Overcurrent stage 1 curve
Coefficient A of inverse time overcurrent stage
InvTimeOCStage1CoefA
1
InvTimeOCStage1IndexP Index P of inverse time overcurrent stage 1
InvTimeOCStage1TimeB Time B of inverse time overcurrent stage 1
InvTimeOCStage1ConstT Constant T of inverse time overcurrent stage 1
2
304
Chapter 42 Appendix
3
4
InvTimeOCMinTime Inverse time minimum of overcurrent
PPVoltBlkSet Phase-to-phase voltage blocking setting
U2BlkSet Blocking setting of negative sequence voltage
DirOCSensitiveAngle Overcurrent direction sensitive angle
Harmonic unblocking overcurrent protection
HarmUnblkOCCurr
current
OC2ndHI2/I1Ratio I2/I1 ratio of second harmonic of overcurrent
HarmCrossBlkTime Harmonic cross blocking time
Current setting of zero sequence current stage
3I0Stage1CurrSet
1
3I0Satge1Time Time of zero sequence current stage 1
Current alarm setting of zero sequence current
3I0Stage1AlarmSet
stage 1
Time alarm setting of zero sequence current
3I0Satge1TimeAlarmSet
stage 1
3I0Stage1Curve Curve of zero sequence current stage 1
Coefficient A of inverse time zero sequence
InvTime3I0Stage1CoefA
current stage 1
Index P of inverse time zero sequence current
InvTime3I0Stage1IndexP
stage 1
Inverse time B of zero sequence current stage
InvTime3I0Stage1TimeB
1
Constant T of inverse time zero sequence
InvTime3I0Stage1ConstT
current stage 1
3I0Stage2CurrSet
2
current stage 2
stage 2
2
current stage 2
3I0Stage3CurrSet
3
305
Chapter 42 Appendix
current stage 3
stage 3
3
current stage 3
3I0Stage4CurrSet
4
current stage 4
stage 4
4
current stage 4
3I0InvTimeMinTripTime Minimum trip time of zero current inverse time
Dir3I0SensitiveAngle Zero sequence current direction sensitive angle
Zero sequence current negative sequence
3I0NSDSensitiveAngle
direction sensitive angle
Overcurrent open harmonic blocking phase
HarmUnblkPhCurr
current
Harmonic blocking current is unblocked by zero
3I0UnblkHarmBlkCurr
sequence current
I02/I01 ratio of second harmonic of zero
3I02ndHI02/I01
sequence current
SEF/REFStage1CurrSet Current setting of SEF/REF stage 1
SEF/REFStage1Time SEF/REF stage 1 time setting
SEF/REFStage1Curve SEF/REF stage 1 curve
Coefficient A of inverse time stage 1 of
InvTimeSEF/REFStage1CoefA
SEF/REF
InvTimeSEF/REFStage1IndexP Index P of inverse time stage 1 of SEF/REF
InvTimeSEF/REFStage1ConstB Constant B of inverse time stage 1 of SEF/REF
InvTimeSEF/REFStage1ConstT Constant T of inverse time stage 1 of SEF/REF
SEF/REF
InvTimeSEF/REF2ConstB Constant B of inverse time stage 2 of SEF/REF
SEF/REF
306
Chapter 42 Appendix
SEF/REF
InvTimeSEF/REFMinTime Inverse time minimum time of SEF/REF
SEF/REFDirSensitiveAngle Directional sensitive angle of SEF/REF
SEF/REF_IsCosSet SEF/REF_IsCos setting
Current setting of negative sequence current
3I2Stage1CurrSet
stage 1
3I2Stage1Time Time of negative sequence current stage 1
3I2Stage1Curve Negative sequence current stage 1 curve
Inverse time coefficient A of negative sequence
current stage 1
Inverse time index P of negative sequence
current stage 1
Time B of inverse time of negative sequence
current stage 1
Inverse time constant T of negative sequence
current stage 1
3I2Stage2CurrSet
stage 2
current stage 2
current stage 2
current stage 2
current stage 2
3I2Stage3CurrSet
stage 3
current stage 3
current stage 3
current stage 3
current stage 3
3I2Stage4CurrSet
stage 4
307
Chapter 42 Appendix
current stage 4
current stage 4
current stage 4
current stage 4
Minimum time of inverse time negative
InvTimeI2MinTime
sequence current
UCSet Undercurrent setting
UCTime Undercurrent time setting
OVStage1VoltSet Voltage setting of overvoltage stage 1
OVStage1Time Time of overvoltage stage 1
OVStage1Curve Overvoltage stage 1 curve
Coefficient A of inverse time overvoltage stage
InvTimeOVStage1CoefA
1
InvTimeOVStage1IndexP Index P of inverse time overvoltage stage 1
InvTimeOVStage1TimeB Time B of inverse time overvoltage stage 1
InvTimeOVStage1ConstT Constant T of inverse time overvoltage stage 1
2
3
4
InvTimeOVMinTime Minimum time of overvoltage inverse time
OVStage1DropoffCoef Overvoltage Stage1 dropoff coefficient
3U0Stage1VoltSet Voltage setting of zero voltage stage 1
308
Chapter 42 Appendix
3U0Stage1Time Time of zero voltage stage 1
3U0Stage1Curve Curve of zero sequence voltage stage 1
InvTime3U0Stage1CoefA
voltage stage 1
Index P of inverse time zero sequence voltage
InvTime3U0Stage1IndexP
stage 1
Time B of inverse time zero sequence voltage
InvTime3U0Stage1TimeB
stage 1
InvTime3U0Stage1ConstT
voltage stage 1
3U0Stage2Time Time of zero voltage stage 2
3U0Stage2CoefA Coefficient A of zero voltage stage 2
3U0Stage2IndexP Index P of zero voltage stage 2
3U0Stage2TimeB Time B of zero voltage stage 2
3U0Stage2ConstT Constant T of zero voltage stage 2
Time setting on zero sequence voltage stage
3U0Stage3Time
3
3U0Stage3CoefA Coefficient A of zero voltage stage 3
3U0Stage3IndexP Index P of zero voltage stage 3
3U0Stage3TimeB Time B of zero voltage stage 3
3U0Stage3ConstT Constant T of zero voltage stage 3
Inverse time minimum of zero sequence
InvTime3U0MinTime
voltage
DeadVoltSet Non-voltage setting
LiveVoltSet Live voltage setting
Voltage setting of negative sequence voltage
3U2Stage1VoltSet
stage 1
3U2Stage1Time Time of negative sequence voltage stage 1
3U2Stage1Curve Negative sequence voltage stage 1 curve
voltage on stage 1
voltage stage 1
voltage stage 1
voltage on stage 1
3U2Stage2VoltSet
stage 2
Inverse time curve of negative sequence
InvTimeU2Stage2Curve
voltage stage 2
voltage on stage 2
voltage stage 2
voltage stage 2
InvTime3U2Stage2ConstT Inverse time constant T of negative sequence
309
Chapter 42 Appendix
voltage on stage 2
Minimum time of inverse time negative
InvTimeU2MinTime
sequence voltage
3U2Stage3VoltSet
stage 3
voltage stage 3
voltage on stage 2
voltage stage 3
voltage stage 3
voltage on stage 3
3U2Stage4VoltSet
stage 4
voltage stage 4
voltage on stage 4
voltage stage 4
voltage stage 4
voltage on stage 4
UVStage1VoltSet Undervoltage stage 1 setting
UVStage1Time Undervoltage stage 1 time
UVStage1Curve Curve of undervoltage stage 1
Coefficient A of inverse time undervoltage
InvTimeUVStage1CoefA
stage 1
InvTimeUVStage1IndexP Index P of inverse time undervoltage stage 1
InvTimeUVStage1TimeB Time B of inverse time undervoltage stage 1
Constant T of inverse time undervoltage stage
InvTimeUVStage1ConstT
1
UVStage2Set Undervoltage stage 2 setting
stage 2
2
stage 3
310
Chapter 42 Appendix
3
stage 4
4
InvTimeUVMinTime Inverse time minimum time of low voltage
UVCurrSet Undervoltage current setting
UVStage1DropoffCoef Undervoltage stage1 dropoff coefficient
3PhUVBlkSet Undervoltage blocking setting of three-phase
UnbalanceVoltSet Voltage of unbalance voltage protection
UnbalanceVoltTime setting Voltage imbalance time delay
UnbalanceCurrSet Current of unbalance current protection
UnbalanceCurrTime Time of unbalance current
ThermalOLCurrSet Current setting of thermal overload
ThermalTimeConst Hhermal time constant
ThermalOLCoolingCoef Cooling coefficient of thermal overload
ThermalOLAlarmCoef1 Alarm coefficient 1 of thermal overload
ThermalOLAlarmCoef2 Alarm coefficient 2 of thermal overload
PowerProtStage1PowerSet Power setting of power protection stage1
PowerProtStage1Time Time of power protection stage 1
PowerProtStage2PowerSet Power setting of power protection stage 2
PowerProtStage2Time Time of power protection stage 2
CBFCurrSet Current setting of circuit breaker failure
Zero sequence current setting of circuit breaker
CBF3I0Set
failure
Negative sequence current setting of circuit
CBF3I2Set
breaker failure
CBFTime1 Time 1 of circuit breaker failure
CBFTime2 Time 2 of circuit breaker failure
CBF BIAlarmTime Binary input alarm time of circuit breaker failure
DZCurrSet Dead zone current setting
DZTime Dead zone time
Dead zone protection zero sequence current
DZProt3I0Set
setting
Dead zone protection negative sequence
DZProt3I2Set
current setting
BIErrAlarmTime Time of binary input error alarm
StubCurrSet Current setting of stub protection
StubTime Time of stub protection
Negative sequence current setting of broken
BrokenConductor3I2Set
conductor
I1/I2Coef Positive and negative sequence current
311
Chapter 42 Appendix
coefficient
BrokenConductorTime Time of broken conductor
DefTimeOEStage1TripSet Overexcitation definite time stage 1 trip setting
DefTimeOEStage1Time Overexcitation definite time stage 1 setting
DefTimeOEStage2TripSet Overexcitation definite time stage 2 trip setting
DefTimeOE3TripSet Overexcitation definite time stage 3 trip setting
VoltFreqT1Time Voltage frequency T1 time
OECoolingTime Cooling time of overexcitation
OEDropoffCoef Dropoff coefficient of overexcitation
OERatedVoltVal Rated voltage of overexcitation
DefTimeOERstTime Reset time of overexcitation definite time
InvTimeOERstTime Reset time of overexcitation inverse time
Df/dtBlkFreqSet Df/dt blocking frequency setting
Frequency setting of underfrequency load
UFLSStage1FreqSet
shedding stage 1
UFLSStage1Time Time of underfrequency load shedding stage 1
UFLSStage2FreqSet
shedding stage 2
UFLSStage3FreqSet
shedding stage 3
UFLSStage4FreqSet
shedding stage 4
Df/dtBlkSet Blocking setting of rate of change of frequency
LoadShedVoltBlkSet Load shedding voltage blocking setting
LoadShedCurrBlkSet Load shedding current blocking setting
OFSatge1FreqSet Overfrequency stage 1 frequency setting
OFSatge1Time Overfrequency stage 1 time setting
312
Chapter 42 Appendix
FreqDf/dtStage1Set Setting of rate of change of frequency stage 1
FreqDf/dtStage1Time Time of rate of change of frequency of stage 1
Underfrequency threshold of stage 1 of rate of
Df/dtStage1LFThreshold
change of frequency
Overfrequency threshold of stage 1 of rate of
Df/dtStage1HFThreshold
change of frequency
change of frequency
change of frequency
change of frequency
change of frequency
change of frequency
change of frequency
Voltage threshold of rate of change of
FreqDf/dtVoltThreshold
frequency
FreqDf/dtHighThreshold High threshold of rate of change of frequency
FreqDf/dtLowThreshold Low threshold of rate of change of frequency
SOTF OCSet Current setting of manual close fault
SOTF3I0Set Switch-onto-fault zero sequence current setting
SOTFOCTime Time of manual closing overcurrent
SOTF3I0Time Time of manual closing zero sequence current
OpenPosnConfirmTime Definite time of open position
SOTFStateLatchedTime Latching time of manual close state
BIErrTime Binary input abnormal time
NonElectricGrp1Time Non-electric group 1 time
SyncDetectTime Synchronization time detection
WaitSyncTime Waiting synchronization time
MCSyncChkTime Time of manual closing synchronization
MCWaitSyncTime Manual close waiting synchronization time
SyncAngleDiffSet Setting of synchronization angle difference
SyncVoltDiffSet Setting of synchronization voltage difference
SyncFreqDiffSet Setting of synchronization frequency difference
ChkDeadVoltMaxVolt Maximum voltage of dead voltage check
313
Chapter 42 Appendix
SyncChkMinVolt Minimum voltage of synchronization check
SyncPh Synchronization phase difference
MCSyncDetectTime Manual close synchronization check time
MCSyncChkTime Time of manual closing synchronization
Manual close synchronization angle differential
MCSyncAngleDiffSet
setting
MCSyncVoltDiffSet Synchronization voltage difference setting
MCSyncFreqDiffSet Synchronization frequency difference setting
Maximum voltage of manual close dead voltage
MCChkDeadVoltMaxVolt
check
Minimum voltage of manual close
MCSyncChkMinVolt
synchronization check
SyncPh Synchronization phase difference
3PhARTime1 Time 1 of three-phase auto-reclosing
ARPulse Auto-reclosing pulse
ARTimes Auto-reclosing times
ARConfirmTime Auto-reclosing confirmation time
ARBlkTime Auto-reclosing blocking time
SyncDetectTime Synchronization time detection
WaitSyncTime Waiting synchronization time
SpringDischargeAlarmTime Spring discharge alarm time
SyncAngleDiffSet Setting of synchronization angle difference
SyncVoltDiffSet Setting of synchronization voltage difference
SyncFreqDiffSet Setting of synchronization frequency difference
ChkDeadVoltMaxVolt Maximum voltage of dead voltage check
SyncChkMinVolt Minimum voltage of synchronization check
SimpleBusDiffCurrSet Current setting of simple busbar differential
SimpleBusDiffTime Time of simple busbar differential
UVLSVoltSet Voltage setting of undervoltage load shedding
UVLSTime Undervoltage load shedding time
LoadShedCurrBlkSet Load shedding current blocking setting
LoadShedDv/dtBlkSet Load shedding dv/dt blocking setting
OLLSCurrSet Overload load shedding current value
OLLSTime Overload load shedding time
Df/dtBlkSet Blocking setting of rate of change of frequency
LoadShedDv/dtBlkSet Load shedding dv/dt blocking setting
CoolLoadTripTime Trip time of cool load
CoolLoadStartRstTime Reset time of cool load startup
CoolLoadStartFastRstTime Fast reset time of cool load startup
CoolLoadStartOC1Multiple Multiple 1 of cool load startup overcurrent
CoolLoadStartOCStage1Time Time 1 of cool load startup overcurrent
CoolLoadStartInvTimeOC1T T 1 of cool load startup inverse time overcurrent
314
Chapter 42 Appendix
Multiple 1 of cool load startup zero sequence
CoolLoadStart3I01Multiple
current
Time 1 of cool load startup zero sequence
CoolLoadStart3I0Stage1Time
current
T 1 of cool load startup inverse time zero
CoolLoadStartInvTime3I01T
sequence current
current
current
sequence current
current
current
sequence current
current
current
sequence current
MinTemp Minimum temperature
MaxTemp Maximum temperature
TempProt1TripSet Temperature protection 1 trip setting
TempProt1AlarmSet Temperature protection 1 alarm setting
TempProt1TripTime Temperature protection 1 trip time
TempProt1AlarmTime Temperature protection 1 alarm time
TempProt2TripSet Temperature protection 2 trip setting
TempProt2AlarmSet Temperature protection 2 alarm setting
TempProt2TripTime Temperature protection 2 trip time
TempProt2AlarmTime Temperature protection 2 alarm time
ChargingOCCurrSet Charging overcurrrent setting
ChargingOCTime Charging overcurrrent time
Charging3I0CurrSet Charging zero sequence current setting
Charging3I0Time Charging zero sequence current time
PPVoltBlkSet Phase-to-phase voltage blocking setting
U2BlkSet Blocking setting of negative sequence voltage
PD3I0Set Pole discrepancy zero sequence current setting
Pole discrepancy negative sequence current
PD3I2Set
setting
315
Chapter 42 Appendix
PDTripTime Pole discrepancy trip time
CTFail3I0Set Zero sequence current setting of CT failure
CTFailTime Time setting of CT failure
VTFailCurrSet VT failure current setting
Zero and negative sequence current settings of
VTFail3I0/3I2Set
VT failure
VTFailPEVoltSet VT failure phase-to-earth voltage setting
VTFailPPVoltSet VT failure phase-to-phase voltage setting
VTFailNormalVolt VT failure normal voltage setting
VTFailAlarmTime CT failure alarm time setting
VTFailBIErrAlarmTime Alarm time of abnormal VT failure binary input
BISwitchSetGrp Binary input switch setting group
IEDCTPriVal IED CT primary value
IEDCTSecVal IED CT secondary value
3I0CTPriVal CT primary value of zero sequence current
3I0CTSecVal CT secondary value of zero sequence current
Primary value of sensitive zero sequence
SEF/REFCTPriVal
current CT of high voltage side
Highly sensitive zero sequence current
SEF/REFCTSecVal
secondary value of high voltage side
VTPriVal VT primary value
VTSecVal VT secondary value
U4VTPriVal U4VT primary value
U4VTSecVal U4VT secondary value
UnbalanceVTPriVal Imbalance VT primary value
UnbalanceVTSecVal Imbalance VT secondary value
UnbalanceCTPriVal Imbalance CT primary value
UnbalanceCTSecVal Imbalance CT secondary value
MeasureCTPriVal Measurement CT primary value
MeasureCTSecVal Measurement CT secondary value
BISwitchSetGrp Binary input switch setting group
7.2 Explanation of logic switch abbreviations

Table 236 Explanation of logic switch abbreviations
Abbreviations Explanations
OCStage1On Enable stage 1 of overcurrent
3I0Stg1RMSOn Enable stage 1 of overcurrent root mean square
OCStage1AlarmOn Enable overcurrent stage 1 alarm
DirOCStage1 Directional overcurrent stage 1
OCStage1FwdDir Forward direction overcurrent stage 1
OCStage1BlkByVolt Overcurrent stage 1 blocked by voltage
OC1BlkBy2ndH Overcurrent stage 1 blocked by second harmonic
316
Chapter 42 Appendix
3PhVoltConnect Three-phase voltage connection
VTFailProtOff VT failure occurs, disable protection
3I0Stage1On Enable stage 1 of zero sequence current:
3I0Stg1RMSOn Enable stage 1 of zero sequence current root mean square
3I0Stage1AlarmOn Zero sequence current enable stage 1 alarm
Dir3I0Stage1 Directional zero sequence current stage 1
3I0Stage1FwdDir Forward direction of zero sequence current stage 1
3I0Stage1BlkBy2ndH Zero sequence current stage 1 is blocked by 2nd harmonic
Extr3I0Stage1 External zero sequence current stage 1
Extr3U0Stage1 External zero sequence voltage stage 1
ZeroSeqChkU2/I2DirOn Enable zero sequence check U2/I2 direction
3I0HarmonChkExtrI02/I01 Zero sequence current harmonics check external
connection I02/I01
CTFailBlk3I0 CT failure blocking earth fault protection
317
Chapter 42 Appendix
SEF/REFStage1On Enable stage 1 of SEF/REF
DirSEF/REFStage1 Enable directional SEF/REF stage 1
SEF/REFStage1FwdDir Forward direction SEF/REF stage 1
SEF/REFStage2On Enable SEF/REF stage 2
SEF/REFStage2FwdDir SEF/REF stage 2 forward direction
SEF/REFStage3FwdDir Forward direction ESF/REF stage 3
SEF/REFStage4FwdDir Forward direction SEF/REF stage 4
Chk3U03I0Criterion Check zero sequence criterion
Extr3U0 External zero sequence voltage
3I2Stage1On Enable stage 1 of negative sequence current
UCOn Enable undercurrent protection
OVChkPEVolt Overvoltage check phase-to-earth voltage
OVChk1Ph Overvoltage check 1 phase
OVStage1On Enable stage 1 of overvoltage
3U0Stage1On Enable stage 1 of zero sequence voltage
Extr3U0 External zero sequence voltage
3U2Stage1On Enable stage 1 of negative sequence voltage
UVStage1On Enable stage 1 of undervoltage
UVChkCBState Undervoltage check circuit breaker state
UVChk1Ph Undervoltage check 1 phase
UVChkPEVolt Undervoltage check phase-to-earth voltage
UVChkCurrOn Enable undervoltage check current
UnbalanceVoltOn Enable unbalance voltage protection
UnbalanceCurrOn Enable unbalance current protection
ThermalOLOn Enabled thermal overload
318
Chapter 42 Appendix
ThermalOLAlarm1On Enabled thermal overload alarm1
ThermalOLAlarm2On Enabled thermal overload alarm 2
ThermalCurve Thermal curve
PowerProtStage1On Enable stage 1 of power protection
OutgoLineRvsPowerStage1On Enable stage 1 of outgoing line reverse power
PowerProtStage2On Enable stage 2 of power protection
OutgoLineRvsPowerStage2On Enable stage 2 of outgoing line reverse power
CBFOn Enable circuit breaker failure protection
CBFChk3I0/3I2 Circuit breaker failure check zero/negative sequence
currents
CBFChkPosn Circuit breaker failure check position
DZProtOn Enable dead zone protection
DZChk3I0/3I2 Dead zone protection check zero/negative sequence
currents
StubOn Enable stub protection
BrokenConductorOn Enable broken conductor
BrokenConductorTripOn Enable Broken conductor protection trip
BrokenConductorChk3I2 Broken conductor protection check negative sequence
current
BrokenConductorChkCBPosn Broken conductor protection check circuit breaker position
DefTimeOEStage1On Enable stage 1 of overexcitation definite time
DefTimeOEStage1Alarm Definite time overexcitation stage 1 alarm
InvTimeOExcitOn Enable overexcitation inverse time
InvTimeOEAlarm Overexcitation inverse time alarm
OEUsePEVolt Overexcitation using phase-to-earth voltage
GenlUFLSOn Enable general underfrequency load shedding
UFStage1On Enable stage 1 of underfrequency
LoadShedChkDf/dt Load shedding check dF/dt
UFLSChkCurrOn Enable current checking of underfrequency load shedding
OFStage1On Enable stage 1 of overfrequency
GenlFreqDf/dtOn Enable general rate of change of frequency
FreqDf/dtStage1On Enable stage 1 of rate of change of frequency
DirModeDf/dtStage1 Directional mode of rate of change of frequency stage 1
FreqDf/dtStage1DetectVolt Detection voltage of rate of change of frequency stage 1
Df/dtStage1ChkFreq Detection frequency of rate of change of frequency stage 1
319
Chapter 42 Appendix
SOTFOn Enable manual closing fault
SOTFChkBI/Posn Switch on to fault fault check binary input and position
SOTFChkPosn Switch on to fault fault check position
SOTFChkBI Switch on to fault fault check binary input
SOTFFaultChk2ndH Switch on to fault checks second harmonic
NonElectricGrp1On Enable non-electric group 1
SelLineVT Select line VT
SyncChkModeOn Enable synchronization check mode
OverrideModeOn Enable override mode
ChkDLLBOn Enable checking dead line live busbar
ChkLLDBOn Enable checking live line dead busbar
ChkDLDBOn Enable checking dead zone of both sides
MCSyncOn Enable manual close synchronization
MCOverrideModeOn No synchronization check of manual closing
MCSyncChk Manual closing synchronization check
MCDeadLineAndLiveBus Manual close dead line and live busbar
MCLiveLineAndDeadBus Manual close live line and dead busbar
MCChkDLDBOn Manual close check dead line dead busbar
AROn Enable auto-reclosing
StopModeOn Enable stopping mode
ARTrip3Ph/BlkAR Auto-reclosing trip three-phase and blocking auto-reclosing
3PhSpontaneousTripInitAR Three-phase spontaneous trip initiates auto-reclosing
OverrideModeOn Enable override mode
SyncChkModeOn Enable synchronization check mode
ChkDLLBOn Enable checking dead line live busbar
ChkLLDBOn Enable checking live line dead busbar
ChkDLDBOn Enable checking dead zone of both sides
BlkSimpleBusDiffOn Enable blocking simple busbar differential protection
DirBlkSimpleBusDiff Directional blocking simple busbar differential
SimpleBusDiffOn Enable simple busbar differential protection
UVLSOn Enable undervoltage load shedding
Chkdu/dt Load shedding check du/dt
UVLSChkCurrOn Enable current checking of undervoltage load shedding
320
Chapter 42 Appendix
OLLSOn Enable overload load shedding
OLLSChkVolt Overload load shedding check voltage
Chkdu/dt Load shedding check du/dt
Chkdf/dt Load shedding check df/dt
CoolLoadStartLogicSel Logic selection of cool load startup
CoolLoadStartProtOn Enable cool load startup protection
TempProt1On/Off Enable/disable stage 1 of temperature protection
TempProt1TripOn Enable temperature protection 1 trip
TempProt1AlarmOn Enable temperature protection 1 alarm
TempProt2On/Off Enable/disable stage 2 of temperature protection
TempProt2TripOn Enable temperature protection 2 trip
TempProt2AlarmOn Enable temperature protection 2 alarm
ChargingOCOn Enable charging OC protection
Charging3I0On Enable charging earth fault protection
ChargingExtr3I0 External charging zero sequence current 3I0
PDProtOn Enable pole discrepancy protection
PDChk3I0/3I2 Pole discrepancy check zero/negative sequence current
CTFailAlarmOn Enable CT failure alarm
NutrPointEarth Neutral point earthing
VTFailOn Enable VT failure
7.3 Explanation of trip report and alarm report

Table 237 Explanation of trip report and alarm report
OCStage1Trip Overcurrent stage 1 protection trip
OCStage1PhATrip Overcurrent stage 1 phase A trip
OCStage1PhBTrip Overcurrent stage 1 phase B trip
OCStage1PhCTrip Overcurrent stage 1 phase C trip
InrushBlk Inrush blocking
OCStage1Alarm Overcurrent stage 1 protection alarm
3I0Stage1Trip Trip of zero sequence current stage 1
321
Chapter 42 Appendix
InrushBlk Inrush blocking
3I0Stage1Alarm Alarm of zero sequence current stage 1
SEF/REFStage1Trip Protection trip of SEF/REF stage 1
3I2Stage1Trip Negative sequence current stage 1 trip
UCTrip Undercurrent protection trip
OVStage1Trip Overvoltage stage 1 protection trip
3U0Stage1Trip Zero sequence voltage stage 1 trip
PhAEarth Phase A earthing
PhBEarth Phase B earthing
PhCEarth Phase C earthing
3U0SetErr Setting error of zero sequence voltage
3U2Stage1Trip Trip of negative sequence voltage stage 1
UVStage1Trip Undervoltage stage 1 trip
UnbalanceVoltTrip Unbalance voltage protection trip
UnbalanceCurrTrip Unbalance current protection trip
ThermalOLTrip Protection trip of thermal overload
ThermalOLStage1Alarm Stage 1 alarm of thermal overload
ThermalOLStage2Alarm Stage 2 alarm of thermal overload
PowerProtStage1Trip Power protection stage 1 trip
PowerProtStage2Trip Power protection stage 2 trip
IntrInitCBF Internal initiating failure
ExtrInitCBF External initiating failure
CBFStage1Trip Trip of circuit breaker failure stage 1
CBFStage2Trip Trip of circuit breaker failure stage 2
CBF BIErr Circuit breaker failure binary input is abnormal
DZTrip Dead zone protection trip
DZ BIErrAlarm Dead zone protection binary input abnormal alarm
StubTrip Stub protection trip
BrokenConductorTrip Disconnection protection trip
322
Chapter 42 Appendix
BrokenConductorAlarm Broken conductor protection alarm
DefTimeOEStage1Trip Overexcitation definite time stage 1 trip
InvTimeOETrip Overexcitation inverse time trip
InvTimeOEAlarm Overexcitation inverse time alarm
OEFrequcncyOverLmt Overexcitation frequency overlimit
UFStage1Trip Underfrequency stage 1 trip
OFStage1Trip Overfrequency stage 1 trip
FreqDf/dtStage1Trip Trip of rate of change of frequency stage 1
SOTF OCTrip Switch on to fault fault overcurrent trip
SOTF 3I0Trip Switch on to fault fault zero current trip
SOTF BIErrAlarm Manual close binary input abnormality alarm
NonElectric1Trip Non-electric 1 trip
MCSyncVoltExchg Manual close synchronization voltage changing
MCSyncVoltErr Manual close synchronization voltage is abnormal
SyncPhSelConflict Synchronization phase difference choice conflict
MCVoltDiffFail Manual close voltage difference fail
MCFreqDiffFail Manual close frequency difference fail
MCAngleDiffFail Manual closing angle difference failure
MCDeadVoltChkFail Manual close dead voltage check fail
MCSyncRequest Manual close synchronization request
MCSyncMet Manual close synchronization is satisfied
MCSyncUVMet Manual close synchronization undervoltage is satisfied
MCSyncTimeout Manual closing synchronization timeout
MCOverrideMode Manual closing override mode
MCMet Manual close condition is met
MCChkDLLBMet Manual close checkigng dead line and live busbar is met
MCChkLLDBMet Manual close checking live line and dead busbar is met
MCChkDLDBMet Manual close checking dead line and dead busbar is met
ReclosingFail Reclosing failure
3PhTripInitAR Three-phase trip initiates auto-reclosing
3PhSpontaneousTripInitAR Three-phase spontaneous trip initiates auto reclosing
323
Chapter 42 Appendix
ARProcessing Auto-reclosing is in process
3PhTripBlkAR Three-phase trip blocking auto-reclosing
ARFail Auto-reclosing failure
ARSuccess Auto-reclosing is successful
ARChkVoltDiffFail Auto-reclosing check voltage difference failure
ARChkFreqDiffFail Reclosing check frequency difference failure
ARChkAngleDiffFail Auto-reclosing check angle difference failure
ARDeadVoltChkFail Auto-reclosing check dead voltage failure
ARTrip3Ph/BlkAR Auto-reclosing trip three-phase and blocking auto-reclosing
ARSyncRequest Auto-reclosing synchronization request
ARSyncMet Auto-reclosing synchronization is met
UVCondMet Undervoltage conditions are met
BlkAR Blocking auto-reclosing
SyncTimeout Synchronization timeout
AROverrideMode Auto-reclosing override mode
1stARTrip Primary auto-reclosing trip
2ndARTrip Second auto-reclosing trip
3rdARTrip Third auto-reclosing trip
4thARTrip Fourth auto-reclosing trip
ARSyncChkModeErr Auto-reclosing synchronization ckeck mode error
BlkSimpleBusDiffTrip Blocking simple busbar differential protection trip
SimpleBusDiffTrip Trip of simple busbar differential
UVLSTrip Protection trip of undervoltage load shedding
OLLSTrip Overload load shedding protection trip
CoolLoadStart Cooling overload protection startup
TempProt1Start Stage 1 startup of temperature protection
TempProt2Start Stage 2 startup of temperature protection
TempProt1Trip Temperature protection 1 trip
TempProt2Trip Temperature protection 2 trip
TempProt1Alarm Temperature protection 1 alarm
TempProt2Alarm Temperature protection 2 alarm
ChargingOCTrip Charging overcurrent protection trip
Charging3I0Trip Charging earth fault protection trip
PDStart Pole discrepancy start
PDTripPosnErr Abnormal trip of pole discrepancy
PDTrip Pole discrepancy protection
CTFailAlarm CT failure alarm
InstantVTFail Instantaneous VT failure
VTFailAlarm VT failure alarm
VTFailBIErrAlarm Abnormal alarm of VT failure binary input
3PhVoltDead Three phase dead voltage
VTFailRst VT failure reset
SampleValErr Sampling value error
IEDParmErr IED parameter error
ROMSumChkErr ROM sum check error
SetErr Setting error
UnconfirmConnMode Unconfirmed connector mode
SoftConnErr Soft connector error
324
Chapter 42 Appendix
SystemCfgErr System configuration error
IED CPUModuleErr IED CPU module error
SetGrpPointerErr Setting group pointer error
LogicFileErr Logic file error
CfgFileErr Configuration file error
CfgFileInconsist Configured files are inconsistent
IOMatrixErr IOMatrix error
BOChkNoResponse Binary output checking has no response
BOBreakdown Binary output breakdown
BIBreakdown Binary input breakdown
BIO CPUErr The CPU of binary input and output works improperly
BIO ROMSumErr ROM summing error of binary input and output
BIO EEPROMErr EEPROM error of binary input and binary output
BIOCfgErr Configuration error of binary input and binary output
BISelfChkCircuitErr Binary input selfcheck circuit error
BOLatchedPropertyCfgErr Configuration error of binary output latched property
BICommInterrupt Binary input communication is interrupted
BOCommInterrupt Binary output communication is interrupted
SRAMSelfChkErr SRAM self-check is abnormal
TestStateNotRst Test state is not reset
OperFail Operate unsuccessfully
CanCommInterrupt CAN communication is interrupted
FLASHSelfChkErr FLASH Self-checking error
WorkInTestSetGrp Work in test setting group
BIInputErr Input error of binary input
DualPosnInputIncosist Double position inputs are not consistent
BIOInputPowerErr Input power error of binary input and binary output
7.4 Explanation of operation report abbreviations

Table 238 Explanation of operation report abbreviations
SwitchSetGrpSuccess Setting group switching is successful
CopySetGrpSuccess Setting group copy is successful
WriteIEDSetSuccess Write IED setting successfully
WriteParmSuccess Writing IED parameter is successful
WriteCfgSuccess Configure writing is successful
AdjScaleSuccess Scale adjustment is successful
AdjAngleSuccess Angle adjustment is successful
HardConnOn/OffSuccess Enable/disable hard connector successfully
SoftConnOn/OffSuccess Enable and disable soft connector successfully
ClearCfg Clear configuration
IEDRst(CPUReboot) IED reset (CPU restart)
FactoryRst Factory reset
BOTestSuccess Binary output test success
ZeroDriftAdjSuccess Zero drift adjustment is successful
ClearAllRptSuccess Clear all report successfully
325
Chapter 42 Appendix
MaintModeOn Check mode on
MaintModeOff Maintenance mode is off
AutoRebootAfterCfg Auto reboot after configuration
7.5 Explanation of device menu abbreviations

Table 239 Explanation of device menu abbreviations
ViewInfo Information view
RunOper Running operation
ViewRpt View report
WriteSet Write
TestMenu Debugging menu
IEDSet IED set
Language Language set
IEDState Protection state
ViewSet View setting
ConnState Connector state
VerInfo Version information
IEDSet IED set
ConnOn/Off Enable/Disable connector
SwitchSetGrp Switch setting group
LocalCtrl Local control
SLDCtrl Single line diagram control
StartupRpt Startup report
TripRpt Trip report
AlarmRpt Alarm report
OperRpt Operation report
BIChgRpt BI change report
StartDFRList Startup disturbance and fault record list
TripDFRList Trip disturbance and fault record list
ProtSet Protection setting
GroupCopy Zone copy
EquipParm Equipment parameter
BCUParm Bay control parameter
BOTest Binary output test
CommChk Communication check
LEDTest LED Test
MC DFR Manual disturbance and fault record
FactoryTest Factory debugging
TimeSet Time set
CommParm Communication parameter
OtherSet Other setting
CHN Chinese
ENG English
RUS Russian
Analog Analog
Measure Measurement
326
Chapter 42 Appendix
Analog Analog input
PowerMeter Power metering
BIO BIO
GOState GO state
StateMon State monitor
AlarmInfo Alarm information
BCUParm Bay control parameter
FcnConn Function connector
GOOSEPubSoftConn GOOSE publishing soft connector
GOOSESubSoftConn GOOSE subscription soft connector
IED IDCode IED identification code
IEDVer IED version
VrTrmlChkCode VT check code
TimeSyncMode Time synchronization mode
CommParm Communication parameter
FcnConn Function connector
GOOSEPubSoftConn GOOSE publishing soft connector
GOOSESubSoftConn GOOSE subscription soft connector
Bay0 Bay 0
StationName Substation name
ProtEquipName Protection equipment name
ConventionalBO Conventional BO
GOOSE BO GOOSE BO
FnAlarmChk Protection function alarm check
TripRepChk Trip report check
GOAlarmChk GO alarm check
BIChk Binary input check
MSTAlarmChk MST alarm test
ConnChk Connector check
AnalogChk Analog check
MeasureChk Measurement check
ViewZeroDrift View zero drift
ViewScale View scale
AdjZeroDrift Adjust zero drift
AdjScale Adjust scale
AngleCorrection Angle correction
SetClock Set clock
TimeSyncMode Time synchronization mode
NetTimeSyncIPSet Network synchronization IP setting
TimeZone Time zone setting
DST Daylight saving time
EthernetSet Ethernet setting
SerialSet Serial port setting
ProtocolSet Protocol setting
327
Chapter 42 Appendix
SetPassword Set password
Contrast Contrast
DisplayMode Display mode
PowerMeterZeroing Power metering reset
Confirm Confirm switch
EthernetSet Ethernet setting
Mode1 Mode 1
Mode2 Mode 2
Serial1Set Serial port 1 set
7.6 Explanation of Connector list

Table 240 Explanation of Connector list
Connector name Explanation
ENA Enable (for hard connector configuration in IOMatrix)
MaintConn Maintenance connector
OCConn Overcurrent protection connector
3I0Conn Earth fault protection connector
SEF/REFConn High sensitive earth fault protection connector
I2Conn Negative sequence current protection connector
UnderCurrentConn Undercurrent protection connector
UnbalanceUConn Voltage unbalance protection connector
UnbalanceIConn Unbalanced current protection connector
ThermalOLConn Thermal overload protection connector
CBFConn Circuit breaker failure protection connector
DZConn Dead zone protection connector
StubConn Stub protection connector
BCConn Broken conductor protection connector
FreqDf/dtConn Frequency change rate protection connector
SOFTConn Switch-onto-fault protection connector
OLLoadShedConn Overload load shedding protection connector
UVLoadShedConn Undervoltage load shedding connector
ARConn Auto-reclosing connector
SimpleBusDiffConn Simple busbar protection connector

BlkSimpleBusDiffCo
Blocking simple busbar protection connector
nn
328
Chapter 42 Appendix
Connector name Explanation
ENA Enable (for hard connector configuration in IOMatrix)
CoolLoadStartConn Cooling load startup protection connector
TempProtConn Temperature protection connector
OVConn Overvoltage protection connector
3U0Conn Zero sequence voltage protection connector
U2Conn Negative sequence voltage protection connector
UVConn Undervoltage protection connector
PowerProtConn Power protection connector
OEConn Overexcitation protection connector
HVSideUFConn Undre frequency connector
HVSideOFConn Overfrequency protection connector
FreqCloseConn Frequency auto-reclosing protection connector
329

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CSC-211

Multifunction Protection IED

Manufacturer: Beijing Sifang Automation Co., Ltd.

Applicability of this manual

Strictly follow the company and international safety regulations.

Do not touch any circuitry during operation. Potentially lethal

Never connect or disconnect wire and/or linker to or from IED

Always connect the IED to protective earth regardless of the

Do not disconnect the secondary connection of current

Do not remove the screw from a powered IED or from an IED

Using the certified conductive bags to transport PCBs (modules).

Do not connect live wires to the IED, internal circuitry may be

When replacing modules using a conductive wrist strap

When installing and commissioning, take care to avoid electrical

About this chapter

Type Sub-type Description

3.2 Monitoring function

3.3 Measurement function

3.4 Control function

3.5 Communication mode

Communication port on the front plate

RJ45 Ethernet communication port

Isolated RS485 communication port

Chapter 2 General functions

About this chapter

1 Event record and analysis

1.2 Fault record

1.3 Wave form record

1.4 Sequence of events (SOE)

1.5 Operation record

2.2 Diagnostic principle

3 Time synchronization function

3.2 Synchronization principle

Figure 1 Synchronization principle diagram

3.3 IRIG-B code synchronization mode

3.4 PPS synchronization mode

automatically adapt to the positive and negative pulses.

3.5 SNTP time synchronization mode

3.6 1588 synchronization mode

Chapter 3 Fault phase selection

About this chapter

2. Function module description

Faulty Phase Selection

Number Key Unit Type Description

confirm whether the phase selection is correct.

Figure 3 Relationship diagram between zero sequence current component and

Phase area Angle range Phase selection results

Figure 4 Phase-to-phase (A-B) short circuit

Figure 5 Single phase earth (A-E) short circuit

3.2 Setting list

Table 9 Fault location setting

3. LineLengthSet 0.1~999 999 0.01 km Line length

4. ZeroSeqXCompCoef -0.33~10 8 0.001

5. ZeroSeqRCompCoef -0.33~10 8 0.001

Chapter 4 Overcurrent Protection

About this chapter

2 Function module description

Directional / Non-directional Overcurrent Protection

Figure 6 Diagram of input and output signals of overcurrent protection function