KNOH

WLED
UNIVER
SoUT
North South University
Department of Electrical & Computer Engineering
LAB REPORT-01

Course Code: CSE 231L

Course Title: Digital Logic Lab

Section: 08

LabNumber: 01

Experiment Name: Digital Logic Gates and Boolean Functions

Digital Logic Gates and Boolean Functions

Experiment Date: 13 February 2023

Date of Submission: 20 February 2023

Submitted by Group Number: 05

|Group members:
Name ID Obtained Mark Obtained Mark
Simulation [5] Lab Report [15]

1. Sazid Hasan 2211513642

2. Joy Kumar Ghosh 2211424642

3. Syed Tashriful Alam 2212623042

4. Md. Nifat Hossain 2212923042

5. Md. Rafawat Islam 2122343642

Course Instructor: Dr. Md. Abdur Razzak (Azz)

Submitted To: Pritthika Dhar
 Page 01
Expri ments-1 Name: Introduetion to Basic Logie Ghates

Ojec tive Ant AND,OR ,NOT, NAND,NOR

Knouoing tho logie gedes ,

XDR and thein truth tuble

Tdentifyimg an Ie and its PIN Chdo
ttou to test an Ie wonking on not,

Aparatus
IC z40o Guadrupla 2-input NAND gakes
IC 7402 Guadnupla 2-inpudt NOR gates,
. Ie 7404 Hex Imverters (NOT gotes).
Ic 7403 Guadrupla 2-imput And AND gokes
IC 7432 Guadupla 2-input OR gakes.
.Ie z436 Guadruplo. 2-input xOR gates,
.Traine Board.
WiresS.
Thaoy
bigito logie gates oporates ot tuo dis enate
voltage lavels rapresenting fhe binany velues
o Clogical LOw) ond 1 (Logieal HIG H) .A brief
gate is given balou.
daserup iom of each

AND GLOtas
A Logical gate prnoduees a tto HTGH output only
whan al of the inpuds ane HlGH

Symbo:
 po qe:02
Tuth Tablo.
AND
AB A:B

O 1O
O

11
IC740% Guaduple. 2-input AND gotes.
OR Gahes
A Logie gate tho prolu cos a HIGH outp wham
one o mone nputs ae HIGH.

Symbo

Tuth table' odO

A BE-a
OO O_

11
IC: 7432 Guaduple 2-imput ORgakes,

NOT Gates
AA logie gate. tat inveds o
eomplmants ib nput
Symbol
 page:03
Trulh tabl.;

NOT
AF
oL

IC F4D4 Hox In veruters (NOT Grates)

NAND Gates
A lglogie gate o t produeas a LO ouhput ony den
al
au the inpus ane HIGH.

Symbol

Truth Table
NAND
AB A

TC740o Guadnupla. 2-inpuut NAND gabes.

NOR Gudes:
A logic 8ate in okich the outpuut is louo uhen
Dna or more impus ahe HI nH.

Symbo
 Poge 04

Truth Table!
A NOR
BF A0

oe

IC 7402 Guadruple 2-input NOR ates,

XOR Gotes uporg

A logieol gate produces a High owtput only
oham its two inputs one at opposi te lavols,
Symbols;

Truudh Table.
XOR
A B F AOB

IC 7486 Guadruple 2-imput XOR gakes

dMAM
dentifying ICi eod the num bor of
Fort
fo IC mumbuis, w e
need to
laturs. tot exAmple, 74Hco4 N
am, ignoring otho
Ehe 7404 Hex Imveten IC,
Lohane the HC
is
iut MOS veUu@nt.
denote s a kigh- spead TTL
 Page'os

denhty ing IC PIN Num borrs:

GAL Th basae nule fon most Ies is that than is

a polaiy mak, Such as t half- moon notch
shouom im t fgw.Ano thwr standarrd polarity
mank is a tiny dot, tvuangla. o tab by pin 1, Tha
ule is to mova coumten-eloekwise anound
ehip rom the polonity mark okile numbour
tha Pins startim9 ot 1,

iraui Diagno dMAVM

D
Expermenta Pnoeodwa
. Finst, we ploea t 7408 AND Ie on the
bread boond as very evaTy pin is im a sparate

Nodo
2. Then we mne t h e Ve and GND pinhs

of tha IC to the t5V cnd GND poruts of th

tnaime boatd raspetiívely.
3. After tat, wie eomat eaeh input bf tha gate
gate
to a toggla dsuitch and eonnaut tthe
output
to Om LED on tha tnaire board.

4.Then, we test all thoComhmations of inputs

by tha twning ta
togglesuoitas on (1) amd
ofSlo) amd 7utotudmg if the LED is om(4) on
 o:06
offCo) as the output of t gode
5, Them we rapla eo the AND TC with OR, NOT,NAND
NOR and XOR TeS. Then we rapeat shep 4 for
eaeh Ies also maintunte input ond output
nder by apaokin9 step 3.

simuulation_ N/A
Expoumertal Data Tahla

Tnpuu AND OR NAND OR NOR Input NOT

A B F A B f Ate F=AB F=A®B A+B A A
O O O 1
1 O
10
1

Rosults
t h e dota r eouae aeeondung to t a tutm
tabl of 2ach 9oke

uosions &Ansuwas(G/A):
1. we nod,
7408 Guuduple 2-mput AND gates Ie - Sx
7404 Her Imvertets (NOT gates) I e - 2x
7402 Guadrupla2-imput NOR gates Te-

2.14 t a +5V porutis mot tuorlkmg , we cam dosign

atSV pow Supply v0y ealy as balou. We

y rayina a 10v battery and two L00 0hm

 pa: 0 7
esistons so that tha output voltode s +5V, This
o we eam design a vol tage divi
atwonk, as shoom btnlouo.
L00-
W Vo

0D0
10

Diseusion'
fnom t t s t test rum, ow I s wgra wOTKing
Penfetty hen we trued to maka NAND Qada
oy
oy eomming tha AND ond NOT gotes fes.But
we ecudWt do that, ten wa
igwre out ttat
the bad board was o t tight enough to
th
eommeet all th pims o Ies. ham on tasker
won we bung NAND fe amd eomplete out
onna
othor test. Fimally, we Lomplated al ow
test nuns seh within t time
on
Puga
 page o

Experuments-2 Nom: Construeing 3-1nput AND &OR

gadtes from 2-input AND & OR
Objeehvoas
Prove th ertension of inpuds of AND and OR

ga-es usima the assotiate la

& OR getes using too
Making trse inpuds AND

impus AND & OR gates [Cs,

Appanahus:
Ie 7408 Guadrusa 2-input ANDg gekes.
I e 7432 Guudupla 2-input OR gates.
Irainwl Boad.
.Wines.

Thoo
|Wa ttat 7403 IC has fow AND gakes witth
Krou
btwo tnpus.Bud if w nand to tako We inpus,
we com combin two AND gates of tis 1e.Jus
eorma outpus pin with m nput pîn of
amothor gate usirmg a wina. Thim eonneet tha
thind imput to tha saeomd inpus pin of the
sAcond godes. Them the oufput pim of tho second
got will give us t a output of t u e înputs

AND gates
 POae09

ineut Diagomm

D DF F
A

Experumental Proco dwe

.FiRst, we complete the truth table fort ta 3-inp
AND gote in Truth tabla
2. Than we plae tthe 7408 AND IC om the broad boane
as ever pin is im a Separnte noda and tan wa
COmeut t t vee ond aND pins ofF tta Ie to the
+5V and GND Ports of tha train boand,

ruspeethive
3.After that, we eonmuet ttwo inputs in PINs 1&
2 Tham we onna ttha owtput pin 3 uwith inp
pin A. Afte tat, we eome e the tind
tnput bo tto input pin S
4. Then w eonnet tCutpu pin to te th LED
5. han, we test all tha eombimasms of iputs by
tuning
twn ta toggla suwitehes on Ca) &bff (o) &
rucondimg i thLED is om (0) or off(o) as t
output of tta gadt Tham match ta outp to
tha tuth tabla
6 Thwn wa epla to tha AND IC with oR I an d
apa step S.
Simulahion
A ta cha d.

Expoumental Data Table

A BCF ABC FAt B+C

O 0 0 O

OL

O 00

Resuls
All t data outpu e rasuulls m ateh t h
tabla's
truuth toabla of twaa impuss AND geke. Also, madthad
ith OR gose.
GuOShion amd Answwrs (a7A):
N/A
DseusSiom
ASto tte tinst expenimand ,we wue so exited

tbuild ow inst n e w ,Then wa make a

tainpu AND 8te usig th two- Imput
AND gate very uiekly.We dont fae any
difelhy in tis expoiman
 Page: 11

Expoximent-3 Name, Implementation of Boolaan funtions

0bjecives:
uat aequaintes with the epnasontolion of Boelaan
funetions using truuth tablo, logie diogroms and
usin
Boolaam Algba
Becom dumiliar with combinakona Logie ineuiks.
APpanahus
.IL AD8 Guodruple 2-inpdt AND gates.
Te 7432 Quodnupla 2- input OR gates.
1C 2404 Hex Inverters (NOT gotes)
Trainer Boaid
Wios.

Theony
Booleomn algebra is tho mathemaies of logie uneuiks
The Boolaam aiables Qe epraSentes as inany

MumburS to TaprasQnÚ'S tuth: 1 tnue k0=falsa

lmenunalgebra deals with numerú al operations
wharaas Booleam lgbna deals wi t
logi eal oRenetons.
Som Pos tudates and heorems ane given laloo
 pag:12

fbsulates Theonems Name

AtoA A1 A Ide ruit
A+A= A EO
AtAA A:AA
AHL-1 A0 0
Invotulion
(AY-A AB BAA Commuutlive
AtB=CtA Ago iakve
A+B+)=A+B)1 ACB)=AB) D i s k iDukva
ABH) ABtAC A+Re=O) CA+)
(AE=A+B De MoTQAn
A+E) Alb Sorption
AtAR=A ACAtB) A

Cirit Dagram. i

A D
F

B
D 2

ExporumenBal Pnocodwe;

Comside tha followimg Boela.am Equaiom

F Ac t AK+BC
forr th
1.Tan complte ta truh tabla
impli comts

I=A, I AG, I3 =B
2, Than, we maka t h L impu bram ehas senarately
to tako mulhpla imyinpts from
Cna
for A B &
inpu switeh.
 Pag 13
3, thanwe impicam IL,Firet, we toko am irbut from
A amd Come et it witm NOT 9ate PrN-1& eomat the

outpu from AND gate pLN-L, Tusn uwa

PIN-2 to tta
connet anote input fnom ewith t a AND gate
PIN-2 And eonnaot utta t output pin of AND gate
PIN-3 to a led for testing pwhposes. Afteru a
sueuessfu test, we eomet ttha oudpuf with OR
gate PIN-1.

4.After that, we implamented I2.finst w e taka inped

from A and eonne with AND gate inpu PIN- 4.
Tham we t a k another imput nom PLN-4 amd

coTmat with AND aate i n p PIN5.Than w tak

tt ouput drom PIN-6 and
conme ut it wi th
LED for tasting pwrposas AStera a sueasshul
test, w conm at t a okput with OR gate
impu PIN-2

5. Aten ttat, wa implemamted 13. First, wataka

tuo 1nputs nem B and C and eomeit uitth
O e AND ga imput pins 9 and L0 Than
take
tha oukpu from PIN- amd Comee?Fwith a
LED for tecting Fur
posas. Aftera suecassful test
w conmeet the output t e with OR gate inpuF
PIN-5.
 Page 14

6, We eomeet t t OR gate autput PIN-3 wíth

input PIN-4, Then we tonn eut tha output

PIN-6 with an LED And test for 2va

evey
possibl combination ana vaufy with tha truth

table.

Simulodtion
Attache d.
bxpaumental Data Tabla
A
AB C I A e T A IBFTtI+I3
0 O O

1 O O 0
O O
|1
O
10o O
O 1

Resuts
Al data collected nom step 6 are aeewmkee

with tha tnuth talble of this Boolaam funtion

And we2 ebmpleted ttis erpeimont sue eessfully.

 Paae15

Gstions& Answer (G/A)

O LED-0

SWIS SH19

Diseussio
Ohan we d o i y step 6, we faca soma
di ffieuties. Tha a s u l was lifferart from the
tuth tabl at the finst autpud. Then u tried
to figw ou why it not
was wonking and
eheeka tha wine eonmetion drom step2, And
we found that n th OR gate, we
give ha wrong
mput n Vee and GND Then we TLOverse the

inpwts tam tesf agaim.And tten it's wonki ng

porfefly.
Experiment-02:

DDDDD
Name: Sazid Hasan
ID: 2211513642

Experiment-03:

Name: Sazid Hasan

ID:2211513642
 Name: Joy Kumar Ghosh
D ID: 2211424642
Experiment-2

4)1038 PM
n 4 2/19/2023

Name: Joy Kumar Ghosh

D: 2211424642
Experiment -3

1041 PM
2/19/2023
 Name: 8yed TAshrifulAlam
ld:221 2623042.

D
OF

. .

Name: Syed.Tashriful Aam .

ID:2212623042
Name: Md. Nifat Hossain, ld: 2212923042

D
D O
D

16:55
T: 0.06 KB/s
:037 KB/s
ENG
US
0) 19/02/2023

1.77 KB/s ENG ) O

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 Name: Md. Rafawat 1slam

D: 2122343642

D 4

Name: Md. Rafawat Islam

ID: 2122343642

D
 EEE/ETE211L Digital Logic Design Lab
Department of Electrical &Computer
Engineering
F. Data Sheet
Gates
F.1 Introduction to Basic Logic

D D
F.1.1: Pin configurations
of gales in ICs
Figure

XOR NOR Input NOT

Input AND OR
NAND A r=A
=1 B F=ADBF=A+
AB_ F=ABF=A + B 0
00
1
O
01

10 0
1 1

Logic Gatess
Table F.1.1: Truth Table of

OR gates
F.2 Constructing 3-input AND & OR gates from 2-input AND &

A BC = ABC F=1+B+C
000 0 0

O01 0

010 0

011

100 0

01 0

0 1
110
1
1 11

3-input AND and OR

Table F.2.1: Truth Tables for

F = BC = (A.D). C

F =A + B +C =(A+B)+C

associative law.
Table F.2.2: Expressing 3-input gates as 2-input gates using

Extension of inputs of AND and OR gates

Figure F.2.1:

6
 Departmenl of Electrical& Computer Engineering EEE/ETE211L Digilal Logic Design Lab

F.3 Implementation of Boolean Functions

ABC I1=A'C l2 =AB I=BC F= ih th +l3|

000 0

001 1 0 0

0
010 0 0

011
100 0 0

101
0
110

111

F.3.1: Truth Table for the given Boolean Function

Figure

C D-
A

F.3.1: Logic Diagram for the given Boolean Function

Figure

19/62/2