CMOS Analog IC Design

Learning by Problem Solving

Ivan Jørgensen; Erik Bruun
ERIK BRUUN AND IVAN JØRGENSEN

CMOS ANALOG
IC DESIGN
LEARNING BY
PROBLEM SOLVING

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CMOS Analog IC Design: Learning by Problem Solving
1st edition
© 2022 Erik Bruun and Ivan Jørgensen & bookboon.com
ISBN 978-87-403-3961-1

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CMOS ANALOG IC DESIGN Contents

CONTENTS
Preface 8

Problems 9

Problem 1 - CMOS opamp, feedback 10

Problem 2 - feedback, filter design 12

Problem 3 - transresistance amplifier 14

Problem 4 - differential amplifier, transconductance amplifier 16

Problem 5 - current mirror, regulated cascode 18

Problem 6 - feedback, stability 19

Problem 7 - current mirror, regulated cascode 21

Problem 8 - Inverting amplifier, frequency response 22

Problem 9 - feedback, stability 23

Problem 10 - differential pair, single-ended output,

frequency response 24

Problem 11 - inverting amplifier, common-source stage,

frequency response 26

Problem 12 - differential amplifier, body effect 28

Problem 13 - feedback amplifier, phase margin 30

Problem 14 - cascode amplifier, cascade amplifier 31

 Problem 15 - source follower, common-drain stage, body effect 33

 Problem 16 - bias circuit, common-source stage 35

Problem 17 - bias circuit 37

 Problem 18 - feedback amplifier, phase margin 38

 Problem 19 - common-source amplifier, gain-bandwidth product 39

 Problem 20 - common-source amplifier, Miller capacitor 40

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CMOS ANALOG IC DESIGN Contents

Problem 21 - feedback amplifier, phase margin 42

 Problem 22 - common-source amplifier, cascode amplifier,

Miller capacitor 44

 Problem 23 - feedback amplifier, phase margin 46

 Problem 24 - differential amplifier 47

 Problem 25 - common-drain stage, common-gate stage 49

 Problem 26 - feedback amplifier, integrating amplifier 51

 Problem 27 - common-source amplifier, two-stage amplifier 53

 Problem 28 - feedback amplifier, Miller compensation 54

 Problem 29 - two-stage opamp 56

 Problem 30 - feedback amplifier, phase margin 58

Problem 31 - dual-output gain stage 59

Problem 32 - dc current source 60

Problem 33 - feedback amplifier, phase margin 61

Problem 34 - inverting amplifier, common-source stage 63

Problem 35 - cascode gain stage 65

Problem 36 - common-source amplifier, Miller compensation 67

Problem 37 - feedback amplifier, phase margin 69

Problem 38 - voltage regulator 71

Problem 39 - feedback, phase margin 73

Problem 40 - source follower, common-drain stage 74

Problem 41 - feedback amplifier, phase margin 76

Problem 42 - opamp, voltage follower 77

Problem 43 - feedback amplifier, bandwidth 79

Solutions 81

Solution to Problem 1 82

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CMOS ANALOG IC DESIGN Contents

Solution to Problem 2 88

Solution to Problem 3 91

Solution to Problem 4 97

Solution to Problem 5 104

Solution to Problem 6 111

Solution to Problem 7 116

Solution to Problem 8 122

Solution to Problem 9 125

Solution to Problem 10 130

Solution to Problem 11 136

Solution to Problem 12 144

Solution to Problem 13 151

Solution to Problem 14 157

Solution to Problem 15 165

Solution to Problem 16 169

Solution to Problem 17 173

Solution to Problem 18 176

Solution to Problem 19 180

Solution to Problem 20 182

Solution to Problem 21 187

Solution to Problem 22 193

Solution to Problem 23 201

Solution to Problem 24 208

Solution to Problem 25 213

Solution to Problem 26 217

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CMOS ANALOG IC DESIGN Contents

Solution to Problem 27 221

Solution to Problem 28 226

Solution to Problem 29 229

Solution to Problem 30 236

Solution to Problem 31 239

Solution to Problem 32 244

Solution to Problem 33 248

Solution to Problem 34 252

Solution to Problem 35 257

Solution to Problem 36 260

Solution to Problem 37 264

Solution to Problem 38 269

Solution to Problem 39 274

Solution to Problem 40 277

Solution to Problem 41 282

Solution to Problem 42 287

Solution to Problem 43 291

Appendix A 298

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CMOS ANALOG IC DESIGN Preface

PREFACE
This book is a supplementary book to the textbook ‘CMOS Analog IC Design: Fundamentals’
by Erik Bruun, published by bookboon. It comprises a number of exercises and problems
which can be solved on basis of the theory presented in the textbook. Most of the problems
in the present book have been designed to cover learning objectives spanning across several
chapters in the textbook whereas the topics in the end-of-chapter problems in the textbook
are limited to the current chapter.

The majority of the problems in the present book are based on problems which have been
used for written exams in a course on integrated analog electronics during the last 25 years.

For solving the problems, you may use analytical methods and in some cases Spice simulations.
The Spice simulator used for this book is LTspice. For information about how to use LTspice
for simulating CMOS integrated circuits, you may turn to the book ‘CMOS Integrated
Circuit Simulation with LTspice’ by Erik Bruun and also published by bookboon.

In many problems, you are asked to derive a small-signal equivalent circuit from a large-signal
schematic. Deriving a small-signal equivalent circuit requires some experience. Many years of
teaching have convinced us that this is a discipline which is not so easy for students who are
new to analog IC design. For the beginner, it may be useful to apply a step-by-step procedure
when creating the small-signal equivalent circuit. In Appendix A, we show some examples of
how such a procedure can be applied when deriving a small-signal equivalent circuit.

Erik Bruun and Ivan Jørgensen

Department of Electrical Engineering, Technical University of Denmark

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CMOS ANALOG IC DESIGN

PROBLEMS

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CMOS ANALOG IC DESIGN Problem 1 - CMOS opamp, feedback

 ROBLEM 1 - CMOS
P
OPAMP, FEEDBACK

The figure above shows a CMOS opamp connected in a series-shunt feedback configuration,
i.e., voltage sensing, voltage mixing.

All transistors except M5 have ߤ‫ܥ‬௢௫ (ܹ/‫ = )ܮ‬0.1 mA/V ଶ . For M5, ߤ‫ܥ‬௢௫ (ܹ/‫ = )ܮ‬0.2 mA/V ଶ ..
All NMOS transistors have a threshold voltage of 0.6 V. All PMOS transistors have a threshold
voltage of −0.6 V. All transistors have a channel-length modulation parameter ߣ = 0.05 V ିଵ .

The input voltage has a quiescent value of ܸூே = 0 V . The supply voltages are ܸ஽஽ = ܸௌௌ = 5 V .
The resistor values are �� = 2 kΩ and �� = 10 kΩ.

Question 1: Calculate the bias voltage ܸ஻ needed to ensure that the drain current of M5
is 360 µA and calculate the quiescent values of the drain current, the gate-source voltage
and the drain-source voltage for each of the transistors in the opamp. In this question, you
may neglect the channel-length modulation.

Question 2: Calculate the small-signal parameters ݃௠ and ‫ݎ‬ௗ௦ for each of the transistors in
the opamp. You may use the approximate values of quiescent currents and voltages found
in Question 1 when calculating the small-signal parameters.

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CMOS ANALOG IC DESIGN Problem 1 - CMOS opamp, feedback

Question 3: Use the quiescent value for the drain-source voltage of M5 found in Question
1 to re-calculate the bias voltage ܸ஻ needed to ensure a drain current in M5 of 360 µA
when taking the channel-length modulation for M5 into consideration. With this value of
ܸ஻, simulate the circuit using LTspice and explain the differences between calculated and
simulated values of the small-signal parameters.

Question 4: Determine the loop gain ‫ ߚܣ = ܮ‬of the feedback loop by breaking the loop
at the gate of M2 and finding the returned voltage across ܴଵ (when applying a signal to the
gate of M2 while the input signal ‫ݒ‬ூே is reset).

Question 5: Calculate the feedback factor ߚ and find the gain ‫ ܣ‬from the loop gain ‫ ܮ‬and
the feedback factor ߚ.

Question 6: Calculate the closed-loop gain ‫ܣ‬஼௅ = ‫ݒ‬௢ /‫ݒ‬௜௡ and the closed-loop output
resistance ‫ݎ‬௢௨௧஼௅.

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CMOS ANALOG IC DESIGN Problem 2 - feedback, filter design

 ROBLEM 2 - FEEDBACK,
P
FILTER DESIGN

A feedback amplifier using an opamp and a resistive feedback network as shown above is
sensitive to a dc offset voltage in the input stage of the opamp. A dc offset voltage can be
modeled as a voltage in series with the input. Obviously, it is amplified by the closed-loop
gain of the feedback amplifier, causing a dc offset voltage at the output of the amplifier.
This problem can be reduced by connecting a capacitor ‫ܥ‬ଵ in series with the resistor ܴଵ
as shown in the figure below where the opamp is shown as an ideal opamp with an input
offset voltage ܸoff . In the following two questions, the value of ‫ܥ‬ଵ is 500 nF, and the resistor
values are �� = 2 kΩ and �� = 10 kΩ.

Question 1: Assuming that the opamp can be considered as an ideal opamp (i.e., infinite
gain, zero output resistance, infinite input resistance) with a dc offset voltage of �off = 10 mV ,
what is the voltage at the output of the feedback amplifier shown above when the input
voltage is reset?

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CMOS ANALOG IC DESIGN Problem 2 - feedback, filter design

Question 2: Sketch a Bode plot for the voltage gain ܸ௢ (݆݂)/ܸ௜௡ (݆݂) for the circuit shown
above. The opamp is still assumed to be ideal.

By connecting a capacitor ‫ܥ‬ଶ in parallel with ܴଶ, we obtain a circuit which can be used as
a wideband bandpass filter with a passband gain larger than 0 dB.

Question 3: Design such a wideband bandpass filter with a passband gain of 20 dB and a
−3 dB bandwidth extending from 100 Hz to 10 kHz. As a starting point, select �� = 500 Ω .
It is assumed that the opamp is ideal. Component values for ܴଶ, ‫ܥ‬ଵ and ‫ܥ‬ଶ should be
calculated. Note that the values of ܴଶ and ‫ܥ‬ଵ have changed from the previous questions. As
a reasonable approximation, you may assume that ‫ܥ‬ଵ together with the resistors determines
the lower −3 dB frequency and the response below this frequency whereas ‫ܥ‬ଶ together with
the resistors determines the upper −3 dB frequency and the response above this frequency.

Question 4: Sketch a Bode plot for the voltage gain |ܸ௢ (݆݂)/ܸ௜௡ (݆݂)| |for the bandpass filter
designed in Question 3. Verify the frequency response by an LTspice simulation.

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CMOS ANALOG IC DESIGN Problem 3 - transresistance amplifier

 ROBLEM 3 - TRANSRESISTANCE
P
AMPLIFIER

The figure above shows a transimpedance amplifier built from two identical NMOS transistors
M1 and M2, a resistor � = 30 kΩ and the dc current sources ‫ܫ‬஻ଵ, ‫ܫ‬஻ଶ and ‫ܫ‬஻ଷ. The input
signal is the current ݅ூே and the output signal is the voltage ‫ݒ‬ை. The dc current sources ‫ܫ‬஻ଵ
and ‫ܫ‬஻ଶ are used to provide the quiescent current (bias current) for M1 and M2. The NMOS
transistors are assumed to have the following parameters: ߤ௡ ‫ܥ‬௢௫ (ܹ/‫ = )ܮ‬1 mA/V ଶ , threshold
voltage ܸ௧ = 0.6 V and channel-length modulation parameter ߣ = 0.05 V ିଵ . The dc current
sources ‫ܫ‬஻ଵ, ‫ܫ‬஻ଶ and ‫ܫ‬஻ଷ are assumed to be ideal constant-current sources with the values
‫ܫ‬஻ଵ = ‫ܫ‬஻ଶ = 0.25 mA and ‫ܫ‬஻ଷ = 0.20 mA. The gate of M1 is connected to a dc bias voltage
ܸ஻ூ஺ௌ = 2.0 V, and the supply voltage is ܸ஽஽ = 5.0 V.

Question 1: Calculate the quiescent value ܸூே of the input voltage and the quiescent value
ܸை of the output voltage when the quiescent value of the input current signal is zero. In
this question, you may neglect the channel-length modulation.

Question 2: Find the quiescent values ܸூே and ܸை taking the channel-length modulation into
account. You may use either an iteration from the approximate results found in Question
1, or you may use an LTspice simulation.

Question 3: Draw a small-signal diagram for the amplifier and calculate the values of the
small-signal parameters included in the diagram.

Question 4: Calculate the small-signal transresistance, input resistance and output resistance
of the amplifier.

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CMOS ANALOG IC DESIGN Problem 3 - transresistance amplifier

Question 5: Calculate the maximum value (positive) and the minimum value (negative)
of the input current which can be applied without overloading the amplifier, i.e., without
bringing any of the transistors outside the active region. It can be assumed that the voltage
across the current sources ‫ܫ‬஻ଵ, ‫ܫ‬஻ଶ and ‫ܫ‬஻ଷ must be ≥ 0.2 V in order to assure that they can
be considered as ideal current sources.

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 PROBLEM 4 - DIFFERENTIAL AMPLIFIER,
CMOS ANALOG IC DESIGN TRANSCONDUCTANCE AMPLIFIER

 ROBLEM 4 - DIFFERENTIAL
P
AMPLIFIER, TRANSCONDUCTANCE
AMPLIFIER

The figure above shows a CMOS differential transconductance amplifier. All transistors
except M7 have ߤ‫ܥ‬௢௫ (ܹ/‫ = )ܮ‬2.00 mA/V ଶ . For M7, ߤ‫ܥ‬௢௫ (ܹ/‫ = )ܮ‬4.00 mA/V ଶ . All NMOS
transistors have a threshold voltage of 0.5 V. All PMOS transistors have a threshold voltage
of −0.5 V. All transistors are assumed to be in the active region, and unless otherwise noted,
the channel-length modulation can be ignored.

The differential input voltage is ‫ݒ‬ூே = ‫ீݒ‬ଵ െ ‫ீݒ‬ଶ and the differential output voltage is ‫ݒ‬ை =
‫ݒ‬஽ଵ െ ‫ݒ‬஽ଶ . Both the gate voltages and the drain voltages of M1 and M2 are assumed to have
a quiescent value of 0 V. The supply voltages are ܸ஽஽ = ܸௌௌ = 1.5 V. The load impedance
ܼ௅ is either a resistor ܴ௅ or a parallel connection of a capacitor ‫ܥ‬௅ and an inductor ‫ܮ‬௅ as
specified in the questions below.

Question 1: Calculate ܴ஻ே and ܴ஻௉ so that the quiescent current in M1 and M2 is
‫ܫ‬஽ଵ = ‫ܫ‬஽ଶ = 0.2 mA .

Question 2: Verify that all transistors are in the active region in the bias point specified
for the circuit.

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 PROBLEM 4 - DIFFERENTIAL AMPLIFIER,
CMOS ANALOG IC DESIGN TRANSCONDUCTANCE AMPLIFIER

Question 3: It is now assumed that the channel-length modulation for all transistors is
given by a channel-length modulation parameter of ߣ = 0.1 V ିଵ . It is also assumed that the
only transistor capacitances which must be taken into account are drain-bulk capacitances
for M1 - M4. Each of the transistors M1 - M4 is assumed to have a drain-bulk capacitance
of ‫ܥ‬ௗ௕ = 0.1 pF . In this question and in Question 4, the load impedance is assumed to
be a resistor with the value �� = 10 kΩ. Draw the equivalent small-signal model of the
differential half-circuit and calculate the values of the small-signal parameters in the circuit
using the values of quiescent currents and voltages found in the previous questions.

Question 4: Calculate the small-signal gain ‫ܣ‬ௗ = ‫ݒ‬௢ /‫ݒ‬௜௡ = (‫ݒ‬ௗଵ െ ‫ݒ‬ௗଶ )/൫‫ݒ‬௚ଵ െ ‫ݒ‬௚ଶ ൯ at
very low frequencies when the load impedance ܼ௅ is a resistor with a value �� = 10 kΩ.

Question 5: It is now assumed that the load impedance ܼ௅ is a parallel connection of a

capacitor ‫ܥ‬௅ = 0.8 pF and an inductor ‫ܮ‬௅ = 20 nH, so that the transconductance amplifier
forms a bandpass filter. Calculate the resonance frequency ݂଴ and the quality factor ܳ of
the bandpass filter.

Question 6: Find the maximum passband gain |‫ܣ‬ௗ |max and the −3 dB bandwidth.

Question 7: Verify the numerical results from Questions 3 - 6 using LTspice.

Hint: Start by adjusting the value of ܴ஻௉ so that the bias values ܸ஽ଵ and ܸ஽ଶ of the output
voltages are 0 V.

Question 8: Now assume that the inductor ‫ܮ‬௅ has a series resistance of �� = 2.5 Ω. Use
LTspice to find the maximum passband gain and the −3 dB bandwidth.

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CMOS ANALOG IC DESIGN Problem 5 - current mirror, regulated cascode

 ROBLEM 5 - CURRENT MIRROR,

P
REGULATED CASCODE

The figure above shows a current mirror where transistors M1 and M2 form the current mirror
while transistors M3 and M4 are inserted to increase the small-signal output resistance of the
current mirror. All transistors are assumed to be in the active region and they have the small-
signal transconductances ݃௠ଵ - ݃௠ସ and the small-signal output resistances ‫ݎ‬ௗ௦ଵ - ‫ݎ‬ௗ௦ସ . The
current source ‫ܫ‬஻ is a dc bias current source with a finite small-signal output resistance ‫ݎ‬௢஻.

Question 1: Draw a small-signal diagram for the current mirror and find an expression for
the small-signal output resistance ‫ݎ‬௢௨௧ .

Assume that all transistors are characterized by the Shichman-Hodges transistor model with
���� = 180 μA/V � , �/� = 10 , ܸ௧ = 0.4 V and ߣ = 0.1 V ିଵ. The quiescent value of the
input current is ��� = 100 μA and the bias current ‫ܫ‬஻ is �� = 25 μA. The output resistance
‫ݎ‬௢ of the bias current source is ��� = 400 kΩ .

Question 2: Calculate the numerical value of the small-signal output resistance of the current
mirror. For the calculation, you may assume ���� ≪ 1 for all transistors.

Question 3: Find the minimum dc value of the output voltage for which all transistors are
in the active region. Again, you may assume ���� ≪ 1 for all transistors.

Question 4: Use LTspice to find the small-signal output resistance and minimum dc value
of the output voltage for which all transistors are in the active region. Assume a supply
voltage ܸ஽஽ = 1.8 V. Compare the simulated results to the calculated results from Questions
2 and 3 and explain the differences between simulated results and calculated results.

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CMOS ANALOG IC DESIGN Problem 6 - feedback, stability

PROBLEM 6 - FEEDBACK, STABILITY

An amplifier with a differential input and a single-ended output is intended for use in a
feedback amplifier configuration with voltage sensing and series mixing (series-shunt feedback).
The amplifier is assumed to have infinite input impedance and zero output impedance. The
transfer function (differential gain) of the differential amplifier is given by

ܸ௢ (݆݂) ‫ܣ‬଴ (1 െ ݆݂/݂௭ଵ )

‫ܣ‬ௗ (݆݂) = =
ܸௗ (݆݂) ൫1 + ݆݂/݂௣ଵ ൯൫1 + ݆݂/݂௣ଶ ൯

In the expression above, ‫ܣ‬଴ = 10ହ V/V is the gain at very low frequencies, ݂௭ଵ = 10 MHz
is the frequency of a right-half-plane zero, ݂௣ଵ = 1 kHz is the frequency of a left-half-plane
pole, and ݂௣ଶ = 100 kHz is the frequency of a left-half-plane pole.

Question 1: Sketch a Bode plot of the amplifier response using piecewise-linear approximations
to the amplitude response and the phase response.

Question 2: Find the frequency at which the phase response is −180°.

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CMOS ANALOG IC DESIGN Problem 6 - feedback, stability

Question 3: Verify that the gain at the frequency found in Question 2 is 20 dB.

The amplifier is now used in the feedback configuration shown below.

Question 4: Is the amplifier stable if �� = 10 k٠and �� = 2 k٠? Give a reason for your

answer.

In order to control the phase margin of the feedback amplifier, a frequency compensation
is introduced in the basic amplifier such that the dominant pole is moved to a lower
frequency and the non-dominant pole is moved to a higher frequency. The zero is assumed
to be unaffected by the compensation and the feedback network is still �� = 10 k٠and
�� = 2 k٠.

Question 5: Assuming that the non-dominant pole is moved to a frequency which is much
higher than the frequency of the zero, what should be the new location of the dominant
pole when a phase margin of 60° is required?

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CMOS ANALOG IC DESIGN Problem 7 - current mirror, regulated cascode

 ROBLEM 7 - CURRENT MIRROR,

P
REGULATED CASCODE

The figure above shows a current mirror where transistors M1 and M2 form the current
mirror while transistor M3 and an amplifier with a gain ‫ܣ‬଴ and an infinite input resistance
are inserted to increase the small-signal output resistance of the current mirror. All transistors
are assumed to be in the active region and they have the small-signal transconductances
݃௠ଵ - ݃௠ଷ and the small-signal output resistances ‫ݎ‬ௗ௦ଵ - ‫ݎ‬ௗ௦ଷ . The noninverting input to
the amplifier is connected to a dc bias voltage ܸ஻.

Question 1: Draw a small-signal diagram for the current mirror and find an expression for
the small-signal output resistance ‫ݎ‬௢௨௧ .

Assume that all transistors are characterized by the Shichman-Hodges transistor model with
���� = 180 μA/V � , �/� = 10 , ܸ௧ = 0.4 V and ߣ = 0.1 V ିଵ. The maximum value of the
input current is ���max = 200 μA. For the amplifier, assume ‫ܣ‬଴ = 50 V/V.

Question 2: Calculate the numerical value of the small-signal output resistance of the
current mirror when ݅ூே = ‫ܫ‬ூேmax and when ݅ூே = ‫ܫ‬ூேmax /2. For the calculations, you may
assume ���� ≪ 1 for all transistors.

Question 3: Find the minimum value of the bias voltage ܸ஻ and the minimum value of the
output voltage required to keep all transistors in the active region for ݅ூே ൑ ‫ܫ‬ூேmax . Again,
you may assume ���� ≪ 1 for all transistors.

Question 4: Use LTspice to find the small-signal output resistance and minimum dc value
of the output voltage for which all transistors are in the active region. Assume a supply
voltage ܸ஽஽ = 1.8 V . Compare the simulated results to the calculated results from Questions
2 and 3 and explain the differences between simulated results and calculated results.
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 PROBLEM 8 - INVERTING AMPLIFIER,
CMOS ANALOG IC DESIGN FREQUENCY RESPONSE

 ROBLEM 8 - INVERTING AMPLIFIER,

P
FREQUENCY RESPONSE

The figure above shows an inverting amplifier stage. The transistor threshold voltages are
ܸ௧௡ = 0.7 V for the NMOS transistor and ��� = −0.7 V for the PMOS transistor. Both
transistors have ���� (�/�) = 300 μA/V � and both transistors have a channel-length
modulation parameter ߣ = 0.1 V ିଵ . The supply voltages are ܸ஽஽ = ܸௌௌ = 1.5 V.

Question 1: Calculate the value of the quiescent current (bias current) in the transistors.
It can be assumed that the quiescent value (bias value) of both the input voltage and the
output voltage is 0 V.

Question 2: Draw a small-signal diagram of the inverting amplifier stage and calculate the
values of the small-signal components in the diagram.

Question 3: Find the small-signal voltage gain (open-circuit voltage gain), the input
resistance and the output resistance of the amplifier stage at low frequencies where capacitive
components can be neglected.

The input of the amplifier is now connected to a signal source with a source resistance of
ܴ௦ = 100 kΩ and the output is loaded with a capacitance with a negligibly small value.
Also, a capacitor ‫ܥ‬௉ = 5 pF is connected between the input and the output of the amplifier
stage. It can be assumed that the frequency response of the amplifier has a dominant pole
caused by the resistance ܴ௦ of the signal source and the capacitor ‫ܥ‬௉.

Question 4: Calculate the −3 dB frequency caused by the dominant pole.

Question 5: Use LTspice to verify your results for the previous questions.

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CMOS ANALOG IC DESIGN Problem 9 - feedback, stability

PROBLEM 9 - FEEDBACK, STABILITY

The figure above shows a noninverting feedback amplifier configuration with an opamp and
a feedback network consisting of �� = 45 kΩ, �� = 5 kΩ and ‫ = ܥ‬3.2 nF.

Question 1: Find the transfer function ܸ௢ (‫)ݏ‬/ܸ௜௡ (‫ )ݏ‬assuming that the opamp is an ideal
opamp. Sketch the transfer function |ܸ௢ (݆݂)/ܸ௜௡ (݆݂)| in a Bode plot.

The opamp is now assumed to have a transfer function given by

ܸ௢ (݆݂) ‫ܣ‬଴
=
ܸ௜ௗ (݆݂) ൫1 + ݆݂/݂௣ଵ ൯൫1 + ݆݂/݂௣ଶ ൯

where the low-frequency gain is 80 dB and the pole frequencies are ݂௣ଵ = 10 kHz and
݂௣ଶ = 20 MHz.

Question 2: Sketch a Bode plot of the loop gain and estimate the phase margin from the
Bode plot.

Question 3: Use LTspice to simulate the circuit. Assume the opamp transfer function given
above and plot the frequency response of the amplifier with feedback.

Question 4: Simulate the loop gain and find the phase margin from the simulated loop gain.

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 PROBLEM 10 - DIFFERENTIAL PAIR, SINGLE-
CMOS ANALOG IC DESIGN ENDED OUTPUT, FREQUENCY RESPONSE

 ROBLEM 10 - DIFFERENTIAL
P
PAIR, SINGLE-ENDED OUTPUT,
FREQUENCY RESPONSE


The figure above shows a differential input stage for a CMOS operational amplifier. It has
a single-ended output which can be connected to a subsequent stage in the operational
amplifier. For the purpose of this analysis, the load at the output of the differential stage
is modeled as a parallel connection of the resistor �� = 100 kΩ and the capacitor ‫ܥ‬௅, the
value of which will be found in Question 3.

The NMOS transistors M1, M2 and M4 have the following model parameters: ߤ௡ ‫ܥ‬௢௫ (ܹ/‫= )ܮ‬
4.00 mA/V ଶ and threshold voltage ܸ௧ = 0.5 V. The NMOS transistor M6 has ߤ௡ ‫ܥ‬௢௫ (ܹ/‫= )ܮ‬
8.00 mA/V ଶ and ܸ௧ = 0.5 V. The PMOS transistors M3 and M5 have the model parameters
ߤ௣ ‫ܥ‬௢௫ (ܹ/‫ = )ܮ‬0.50 mA/V ଶ and �� = −0.5 V.. All transistors are assumed to be in the active
region, and in the following five questions, the channel-length modulation can be neglected.
The quiescent value of the input voltage is ܸீଵ = ܸீଶ = 0 V and the input signal is purely
differential. The supply voltages are ܸ஽஽ = ܸௌௌ = 1.5 V.

Question 1: Calculate ܴ஻ so that the quiescent current in M1 and M2 is ‫ܫ‬஽ଵ = ‫ܫ‬஽ଶ = 0.1 mA.

Question 2: Draw a small-signal diagram for the differential stage, assuming that all parasitic
capacitances can be neglected and that the transistors M3 and M6 can be considered as ideal
dc current sources. Calculate the values of the small-signal parameters in the circuit.

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 PROBLEM 10 - DIFFERENTIAL PAIR, SINGLE-
CMOS ANALOG IC DESIGN ENDED OUTPUT, FREQUENCY RESPONSE

Question 3: Find an expression for the differential gain function ‫ܣ‬ௗ (‫ܸ = )ݏ‬௢ (‫)ݏ‬/ܸ௜௡ (‫)ݏ‬.
Calculate the differential small-signal gain ‫ܣ‬଴ at very low frequencies. Find an expression
for the gain-bandwidth product and calculate ‫ܥ‬௅ so that a gain-bandwidth product of 100
MHz is obtained.

Question 4: In this question (and only in this question), we assume that a mismatch
between M3 and M5 causes the drain current of M3 to be 1% larger than the drain current
of M5. Calculate the resulting quiescent value of the output voltage and the corresponding
input offset voltage.

Question 5: Use LTspice to verify your results for the previous questions.

Question 6: It is now assumed that the load resistor ܴ௅ is not a separate resistor but is the
small-signal output resistance of the gain stage caused by the channel-length modulation
in the transistors. All transistors are assumed to have the same value of channel-length
modulation parameter h .

Use LTspice to find a value of h resulting in an output resistance of 100 kΩ.

Hint: Specify h as a parameter which can be stepped through a suitable range of values.

(݆݂)with
Question 7: Use LTspice to simulate the frequency response of ‫ܣܣ‬ௗௗ(݆݂) withߣߣ =
with 0.01 VVିଵ
= 0.01 ିଵ
,,ߣߣ =
=
0.07 V ିଵ and ߣ = 0.13 V ିଵ . For each of the three values of h , find the low-frequency gain
and the gain-bandwidth product.

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 PROBLEM 11 - INVERTING AMPLIFIER, COMMON-
CMOS ANALOG IC DESIGN SOURCE STAGE, FREQUENCY RESPONSE

 ROBLEM 11 - INVERTING
P
AMPLIFIER, COMMON-SOURCE
STAGE, FREQUENCY RESPONSE

The figure above shows an inverting amplifier stage.

For the transistors, we assume �� ��� = 90 μA/V � and �� ��� = 30 μA/V � where ߤ௡ and ߤ௣
are the electron mobility and the hole mobility, respectively, and ‫ܥ‬௢௫ is the gate capacitance
per unit area. The transistor threshold voltages are ܸ௧௡ = െܸ௧௣ = 0.5 V for NMOS and
PMOS, respectively.

For all transistors, we assume a channel length of 0.7 µm and a channel width of 2.1 µm.
For all transistors, we assume that channel-length modulation can be neglected.

The supply voltages are ܸ஽஽ = 1.5 V and −��� = −1.5 V, and the load resistor is �� = 100 kΩ .

Question 1: Calculate the value of the biasing resistor ܴ஻ so that the quiescent current
(bias current) in the transistors is 10 µA. It can be assumed that the quiescent value of the
output voltage is ܸை = 0 V. What is the bias value ܸூே of the input voltage when the bias
value of the output voltage is 0 V?

Question 2: Calculate the output voltage range for an input voltage range from −1 V to
+0.5 V.

Question 3: Draw a small-signal diagram valid for low frequencies of the inverting amplifier
stage and calculate the small-signal voltage gain ‫ݒ‬௢ /‫ݒ‬௜௡ at low frequencies.

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 PROBLEM 11 - INVERTING AMPLIFIER, COMMON-
CMOS ANALOG IC DESIGN SOURCE STAGE, FREQUENCY RESPONSE

A capacitor ‫ܥ‬௉ = 2 is now connected between the input and the output of the amplifier
stage. This capacitor is assumed to be much larger than any other capacitor in the circuit
and it causes the input impedance to be capacitive for frequencies well below 1/(2ߨܴ௅ ‫ܥ‬௉ ) .

Question 4: Calculate the input capacitance of the amplifier.

Next, assume that a resistor ܴௌ is connected between the input voltage source ‫ݒ‬ூே and the
gate of transistor M1.

Question 5: Find the −3 dB bandwidth of the amplifier stage when �� = 500 kΩ,, assuming
that a dominant pole is caused by ܴௌ and the input capacitance.

Question 6: Derive an expression for the transfer function ܸ௢ (‫)ݏ‬/ܸ௜௡ (‫ )ݏ‬when ܴௌ is connected
between the input voltage source ‫ݒ‬ூே and the gate of transistor M1.
Hint: Use node equations for the output node and the gate node of M1.

Question 7: From the transfer function ܸ௢ (‫)ݏ‬/ܸ௜௡ (‫ )ݏ‬, find the −3 dB bandwidth for
ܴௌ = 0, 10 kΩ, 100 kΩ and 500 kΩ.

Question 8: Verify the results of the previous questions by LTspice simulations.

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CMOS ANALOG IC DESIGN Problem 12 - differential amplifier, body effect

 ROBLEM 12 - DIFFERENTIAL
P
AMPLIFIER, BODY EFFECT

The figure above shows a differential amplifier stage.

For the transistors, we assume �� ��� (�/�)� = 300 μA/V � and �� ��� (�/�)� = 100 μA/V �
where ߤ௡ and ߤ௣ are the electron mobility and the hole mobility, respectively, ‫ܥ‬௢௫ is the
gate capacitance per unit area, and (ܹ/‫)ܮ‬௡ and (ܹ/‫)ܮ‬௣ are the channel width-to-length
ratios for the NMOS transistors and the PMOS transistors, respectively. The transistor
threshold voltages are ܸ௧௡ = െܸ௧௣ = 0.7 V for NMOS and PMOS, respectively, and both the
NMOS transistors and the PMOS transistors have a channel-length modulation parameter
ߣ = 0.1 V ିଵ. The body effect constant is � = 0.5 √V and the Fermi potential of the body
is given by |2Φ� | = 0.7 V .

The supply voltages are and ��� = 1.5 V and −��� = −1.5 V..

Question 1: Calculate the value of the bias voltage ܸ஻ required for a quiescent drain current
(bias current) of 20 µA in M5. The channel-length modulation can be neglected in this
calculation. It can be assumed that the quiescent values (bias values) ܸூேశ and ܸூேష of both
the input voltages are 0 V.

Question 2: Use LTspice to find a value for ܸ஻ taking the channel-length modulation into
account.

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CMOS ANALOG IC DESIGN Problem 12 - differential amplifier, body effect

Question 3: Calculate the range of the common-mode input voltage ‫ݒ‬ூ஼ெ when ‫ݒ‬ூ஼ெ = ‫ݒ‬ூேశ =
‫ݒ‬ூேష and all transistors should be kept in the active region. The channel-length modulation
can be neglected in this calculation.

Question 4: Use LTspice to find the common-mode input voltage range when the channel-
length modulation is taken into account. All transistors should be kept in the active region.

Question 5: Calculate the differential small-signal voltage gain ‫ܣ‬ௗ = ‫ݒ‬௢ /(‫ݒ‬௜௡శ െ ‫ݒ‬௜௡ష ) and
the output resistance of the amplifier stage at low frequencies where capacitive components
can be neglected.

Question 6: Use LTspice to verify the calculations from Question 5.

It is now assumed that transistors M1 and M2 have their bulk connected to the negative
supply voltage rather than to the source so that the body effect must be taken into account.

Question 7: Repeat Questions 1 - 6 with the body effect taken into account.

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CMOS ANALOG IC DESIGN Problem 13 - feedback amplifier, phase margin

 ROBLEM 13 - FEEDBACK
P
AMPLIFIER, PHASE MARGIN

The figure above shows a noninverting feedback amplifier configuration with an opamp and
a feedback network consisting of �� = 45 kΩ, �� = 5 kΩ and ‫ܥ‬ଵ = 35.4 nF.

Question 1: Find the feedback factor ߚ(‫)ݏ‬.

Question 2: Find the transfer function ܸ௢ (‫)ݏ‬/ܸ௜௡ (‫ )ݏ‬assuming that the opamp is an ideal
opamp. Sketch the gain function |ܸ௢ (݆݂)/ܸ௜௡ (݆݂)| in a Bode plot using a piecewise-linear
approximation to the gain function.

The opamp is now assumed to have a transfer function given by

ܸ௢ (݆݂) ‫ܣ‬଴
=
ܸ௜ௗ (݆݂) ൫1 + ݆݂/݂௣ଵ ൯൫1 + ݆݂/݂௣ଶ ൯

where the low-frequency gain is 60 dB and the pole frequencies are ݂௣ଵ = 100 kHz and
݂௣ଶ = 200 MHz.

Question 3: Sketch a Bode plot of the loop gain using piecewise-linear approximations for
the gain and the phase and estimate the phase margin from the Bode plot.

Question 4: Find an exact value for the phase margin using either an analytical calculation
or using an LTspice simulation.

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CMOS ANALOG IC DESIGN Problem 14 - cascode amplifier, cascade amplifier

 ROBLEM 14 - CASCODE
P
AMPLIFIER, CASCADE AMPLIFIER

The figure above shows a common-source stage with a capacitive load ‫ܥ‬௅ = 5 pF which is
much larger than the transistor capacitances. The current source ‫ܫ‬஻ is an ideal dc current
source with the value �� = 50 μA. The transistor is biased in the active region and it has
the small-signal parameters ݃௠ଵ = 0.40 mA/V and ���� = 200 kΩ .

Question 1: Calculate the output resistance, the small-signal voltage gain at low frequencies,
the −3 dB bandwidth and the gain-bandwidth product for the amplifier stage.

In order to increase the gain of the amplifier, a cascode transistor M2 is inserted as shown below.
The cascode transistor is assumed to be identical to M1 and it has a bulk transconductance
of ݃௠௕ଶ = 0.1 mA/V . Both M1 and M2 are biased in the active region with an unchanged
bias current �� = 50 μA.

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CMOS ANALOG IC DESIGN Problem 14 - cascode amplifier, cascade amplifier

Question 2: Calculate the output resistance, the small-signal voltage gain at low frequencies,
the −3 dB bandwidth and the gain-bandwidth product for the cascode amplifier.

An alternative to the cascode amplifier is a two-stage amplifier using common-source stages

in a cascade as shown below. The two transistors are assumed to be identical and identical to
the transistors in the amplifiers above. In order to have the same total current consumption
in this circuit as in the amplifiers above, the quiescent current for each of the transistors
has been reduced to 25 µA. This reduction in quiescent current affects the small-signal
parameters of the transistors.

Question 3: Calculate the output resistance, the small-signal voltage gain at low frequencies,
the −3 dB bandwidth and the gain-bandwidth product for the cascade amplifier.

In order to be able to simulate the amplifiers above, we need a transistor design. Assume the
following Shichman-Hodges transistor parameters: �� ��� = 200 μA/V � , ܸ௧௢ = 0.4 V , ߣᇱ =,
�� = 0.10 μm/V, � = 0.5 √V and |2Φ� | = 0.7 V.

Question 4: Using reasonable approximations, find transistor dimensions which result in

small-signal parameters approximately equal to the parameters given above and simulate
the three amplifiers. Find a bias value for the input voltage ܸ஻ of each amplifier and find
the small-signal parameters in the bias point. Use a value of the cascode bias voltage which
ensures that both transistors are in the active region and that the bulk transconductance
is approximately 0.1 mA/V. Also simulate the low-frequency gain and the bandwidth and
compare the simulated results to results calculated from the simulated values of the small-
signal parameters.

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 PROBLEM 15 - SOURCE FOLLOWER, COMMON-
CMOS ANALOG IC DESIGN DRAIN STAGE, BODY EFFECT

 ROBLEM 15 - SOURCE
P
FOLLOWER, COMMON-DRAIN
STAGE, BODY EFFECT

The figure above shows a source follower (common-drain stage).

For the transistors, we assume �� ��� (�/�)� = 300 μA/V � where ߤ௡ is the electron mobility,
‫ܥ‬௢௫ is the gate capacitance per unit area, and (ܹ/‫ )ܮ‬is the transistor channel width-to-
length ratio. The source follower is implemented in an n-well process where the NMOS
transistors are placed directly in the p-substrate. Therefore the body contact of all NMOS
transistors must be connected to െܸௌௌ as shown above. Thus, the body effect must be taken
into account for transistor M1. The transistor threshold voltage is ܸ௧௢ = 0.5 V when the
source-bulk voltage is 0 V, and the threshold voltage increases due to the body effect to
the value ܸ௧ଵ = 0.8 V when the source-bulk voltage for M1 reaches its maximum value, i.e.,
when the output voltage of the source follower reaches its maximum value.

The channel-length modulation can be neglected for all transistors.

The supply voltages are ��� 1.5VVand

���==1.5 and−�
and −�
����==−1.5
−1.5V.V. and the load resistor is
�� = 50 kΩ.

Question 1: Calculate the value of the bias resistor ܴ஻ required for a bias current of 20 µA
in M1. It can be assumed that the bias value of the output voltage is ܸை = 0 V.

Question 2: Calculate the output voltage range assuming that all transistors must be in
the active region and that the input voltage can assume any value between െܸௌௌ and ܸ஽஽ .

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 PROBLEM 15 - SOURCE FOLLOWER, COMMON-
CMOS ANALOG IC DESIGN DRAIN STAGE, BODY EFFECT

Question 3: Draw a low-frequency small-signal diagram for the source follower, taking
the body effect into account. You may neglect all capacitances. The body transconductance
݃௠௕ = ߲݅஽ /߲‫ݒ‬ௌ஻ can be assumed to be given by ݃௠௕ = ߯݃௠ where ߯ = 0.137. Assume a
bias point with ܸை = 0 V. Calculate the values of the small-signal parameters in the small-
signal diagram and calculate the small-signal gain ‫ݒ‬௢ /‫ݒ‬௜௡ (at low frequencies) of the source
follower.

Question 4: Use LTspice to verify the results for Questions 1 - 3. For the transistor model,
use |2Φ� | = 0.7 V and calculate ߛ from the value of the threshold voltage when the output
voltage of the source follower is at its maximum value.

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CMOS ANALOG IC DESIGN Problem 16 - bias circuit, common-source stage

 ROBLEM 16 - BIAS CIRCUIT,

P
COMMON-SOURCE STAGE

The figure above shows an inverting amplifier and a bias circuit for the amplifier. The input
voltage to the amplifier is a dc bias voltage ܸ஻ = 0.9 V in series with the small-signal voltage
‫ݒ‬௜௡. The output is loaded capacitively with a load capacitance of ‫ܥ‬௅ = 0.5 pF .

The transistors have the following parameters: �� ��� = 160 μA/V � , �� ��� = 50 μA/V � , ��� =
0.6 V, ��� = −0.6 V. The body effect can be neglected for all transistors. For M3 - M6, the
channel-length modulation can be neglected, and for M1 and M2, it can be assumed that
they have the same value of the channel-length modulation parameter ߣ but the exact value
is not known, only it can be assumed to be smaller than 0.1 Vିଵ .

All transistors have a channel length of 1 µm, and M2, M5 and M6 have the same channel
width. The drain current of M5 is ��� = 18 μA and the effective gate voltage of M5 is
ܸீௌହ െ ܸ௧௣ = −0.3 V .

Question 1: Calculate the channel width of M5.

Question 2: Calculate the channel width of M1 so that the dc value of the output voltage
is ܸ஽஽ /2.

Question 3: Calculate the transconductance of M1 and the minimum value (absolute value)
of the small-signal gain at low frequencies.

Question 4: Calculate the gain-bandwidth product of the inverting amplifier, assuming that
the bandwidth is limited by ‫ܥ‬௅.

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CMOS ANALOG IC DESIGN Problem 16 - bias circuit, common-source stage

Transistors M1 and M3 have the same value of channel width whereas the channel width
of transistor M4 is four times the channel width of M3.

Question 5: Calculate the effective gate voltage ܸீௌସ െ ܸ௧௡ for M4.

Question 6: Calculate ܴ஻ so that ��� = 18 μA.

Question 7: Use LTspice to verify the analytical results from Questions 1 - 6.

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CMOS ANALOG IC DESIGN Problem 17 - bias circuit

PROBLEM 17 - BIAS CIRCUIT

The figure above shows a bias circuit which generates a constant bias current ‫ܫ‬஻ூ஺ௌ from a
bandgap reference voltage ܸ஻ீ = 1.24 V.

The transistors have the following parameters: �� ��� = 160 μA/V � , �� ��� = 50 μA/V � , ��� =
0.6
0.6 V, V, =
���
and ���−0.6 V V. For all transistors, the channel length is � = 1 μm and the channel
= −0.6
width is � = 2.5 μm .

The channel-length modulation can be neglected for all transistors.

Question 1: Calculate the value of ܴ஻ so that the bias current ‫ܫ‬஻ூ஺ௌ is 20 µA, assuming
that all transistors are in the active region.

Question 2: Calculate the minimum value of the supply voltage ܸ஽஽ for which all transistors
operate in the active region, assuming the voltage across the load to be ܸ௅ = 1.0 V.

Question 3: With ܸ஽஽ = 3 V, calculate the maximum value of the voltage ܸ௅ across the
load for which all transistors operate in the active region.

Question 4: Use LTspice to verify the results for Questions 1 - 3. You may model the load
as a dc voltage source with a value of 1 V for Questions 1 and 2, and for Question 3, you
may sweep the value of ܸ௅ to find the maximum value for which all transistors operate in
the active region.

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CMOS ANALOG IC DESIGN Problem 18 - feedback amplifier, phase margin

 ROBLEM 18 - FEEDBACK
P
AMPLIFIER, PHASE MARGIN

The figure above shows a noninverting feedback amplifier configuration with an amplifier with
gain ‫ ܣ‬and a feedback network consisting of two resistors �� = 45 kΩ and �� = 5 kΩ . The
amplifier (without feedback) is assumed to have a low-frequency gain of 34 dB and infinite
input resistance and zero output resistance.

Question 1: Calculate the low-frequency closed-loop gain of the feedback amplifier.

Question 2: Calculate the −3 dB bandwidth of the amplifier with feedback, assuming that
the basic amplifier has a −3 dB bandwidth caused by a single pole at the frequency ݂௣ଵ =
2 MHz.

The transfer function of the basic amplifier (without feedback) is now assumed to be given by

ܸ௢ (݆݂) ‫ܣ‬଴ (1 െ ݆݂/݂௭ )

‫= )݂݆(ܣ‬ =
ܸ௜ௗ (݆݂) ൫1 + ݆݂/݂௣ଵ ൯൫1 + ݆݂/݂௣ଶ ൯

where the low-frequency gain is 34 dB and the pole frequencies are 2 MHz and 200 MHz.
The zero is a right-half-plane zero with a frequency of 20 MHz.

Question 3: Sketch a Bode plot of the loop gain ‫( )݂݆(ܣߚ = )݂݆(ܮ‬where ߚ is the feedback
factor) and estimate the phase margin from the Bode plot.

Question 4: Use LTspice to simulate the loop gain and find the phase margin from the
simulated loop gain.

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 PROBLEM 19 - COMMON-SOURCE AMPLIFIER,
CMOS ANALOG IC DESIGN GAIN-BANDWIDTH PRODUCT

 ROBLEM 19 - COMMON-
P
SOURCE AMPLIFIER, GAIN-
BANDWIDTH PRODUCT

The figure above shows a common-source amplifier with an NMOS transistor M1 with
�������
��� (�/�)==800
(�/�) 800 μA/V
μA/V , �,�����==0.6
� �
0.6 and� �==0.1
V Vand
and 0.1 V �� . The resistor ܴ is assumed to
V ��
be so large that it does not affect the gain of the amplifier stage and the capacitor ‫ ܥ‬is
assumed to be so large that it represents a short circuit for ac signals but an open circuit
for dc voltages. For Questions 1 - 3, the bias current source ‫ܫ‬஻ is assumed to be ideal, i.e.,
the output resistance of the current source is infinite.

Question 1: Calculate ‫ܫ‬஻ so that the small-signal gain ‫ݒ‬௢ /‫ݒ‬௜௡ is �� = −80 V/V at low
frequencies (i.e., frequencies in the range where ‫ ܥ‬is treated as a short circuit and ‫ܥ‬௅ is
treated as an open circuit). You may use the approximation 1 + ���� ≃ 1.

Question 2: Calculate the quiescent value (bias value) of the output voltage, assuming a bias
current of �� = 25 μA. In this question, the channel-length modulation can be neglected.

Question 3: Calculate the load capacitance ‫ܥ‬௅ so that the gain-bandwidth product is 300
MHz, assuming a bias current of �� = 25 μA. The transistor capacitances can be neglected.

Question 4: It is now assumed that the current source ‫ܫ‬஻ is realized as a PMOS transistor
with the same value of ߣ as M1. How does this affect the small-signal gain at low frequencies
and the gain-bandwidth product?

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39
 PROBLEM 20 - COMMON-SOURCE
CMOS ANALOG IC DESIGN AMPLIFIER, MILLER CAPACITOR

 ROBLEM 20 - COMMON-SOURCE
P
AMPLIFIER, MILLER CAPACITOR

The figure above shows a common-source amplifier stage. Transistor M1 is biased by a

current source which can be treated as an ideal current source �� = 100 μA in parallel with
a resistor ‫ݎ‬௢ = 100 kΩ representing the finite output resistance of a practical realization of
the current source. A capacitor ‫ܥ‬௖ = 1.2 pF is connected between the input and output
of the amplifier stage as shown in the figure. This is the only capacitor which must be
considered in the circuit. All transistor capacitances can be neglected. The input voltage to
the amplifier is a dc bias voltage ܸீீ = 1 V in series with a small-signal source ‫ݒ‬௦ which
has a series resistance of �� = 500 k٠as shown in the figure. The dc supply voltage to the
amplifier stage is ܸ஽஽ = 3 V.

Transistor M1 has the following parameters: �� ��� = 160 μA/V � , ��� = 0.5 V and
ߣ = 0 V ିଵ, so the channel-length modulation can be neglected. The transistor channel
length is � = 1 μm .

The transistor drain current ݅஽ is described by the Shichman-Hodges transistor model, i.e.,

1
݅஽ = ߤ௡ ‫ܥ‬௢௫ (ܹ/‫ீݒ()ܮ‬ௌ െ ܸ௧௡ )ଶ (1 + ߣ‫ݒ‬஽ௌ )
2

Question 1: Calculate the channel width ܹଵ of M1 so that the dc bias value (quiescent
value) of the output voltage is ܸை = 2 V. Alternatively, use LTspice to find the value of ܹଵ
resulting in ܸை = 2 V.

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 PROBLEM 20 - COMMON-SOURCE
CMOS ANALOG IC DESIGN AMPLIFIER, MILLER CAPACITOR

Question 2: Draw a small-signal diagram of the amplifier stage and calculate the small-
signal gain ‫ܣ‬௩௦ = ‫ݒ‬௢ /‫ݒ‬௦ at low frequencies.

Question 3: Calculate or simulate the −3 dB bandwidth of ‫ܣ‬௩௦ for the amplifier stage.

The current source (‫ܫ‬஻ in parallel with ‫ݎ‬௢ )) is now assumed to be implemented by a resistor
ܴ஻ and a PMOS current mirror with transistors M2 and M3 as shown in the following figure.
The two PMOS transistors are identical and can also be described by the Shichman-Hodges
model with �������
���==5050μA/V
μA/V and
��
and���
and ���==−0.5
−0.5VV. The channel length is � = 1 μm and
the channel-length modulation parameter ߣ has a value which results in the small-signal
output resistance ‫ݎ‬௢ = 100 kΩ of the current source. The absolute value of the effective
gate voltage (overdrive voltage) หܸீௌ െ ܸ௧௣ ห is 0.5 V for the two PMOS transistors.

Question 4: Calculate the channel width ܹଶ of M2 (and M3) so that M2 represents a

constant current source �� = 100 μA in parallel with a resistor ‫ݎ‬௢ ).

Question 5: Calculate the value of ߣ for the PMOS transistors which results in �� = 100 kΩ .

Question 6: Calculate the required value of ܴ஻.

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CMOS ANALOG IC DESIGN Problem 21 - feedback amplifier, phase margin

 ROBLEM 21 - FEEDBACK
P
AMPLIFIER, PHASE MARGIN

The figure above shows a noninverting feedback amplifier configuration with an amplifier with
gain ‫ ܣ‬and a feedback network consisting of two resistors �� = 400 kΩ and �� = 50 kΩ. The
amplifier (without feedback) is assumed to have a low-frequency gain of 46 dB and infinite
input resistance and zero output resistance.

Question 1: Calculate the low-frequency closed-loop gain of the feedback amplifier.

In the following three questions, it is assumed that the transfer function of the basic
amplifier (without feedback) can be described by the low-frequency gain of 46 dB and a
single, dominant pole at the frequency ݂௣ଵ = 270 kHz.

Question 2: Calculate the −3 dB bandwidth of the amplifier with feedback.

Question 3: Find the phase margin of the amplifier with feedback.

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42
CMOS ANALOG IC DESIGN Problem 21 - feedback amplifier, phase margin

A parasitic capacitance ‫ܥ‬௣ = 0.6 pF is now assumed to be connected from the inverting
amplifier input to ground as shown above.

Question 4: Sketch a Bode plot of the loop gain ‫( )݂݆(ܣ)݂݆(ߚ = )݂݆(ܮ‬where ߚ(݆݂) is
the feedback factor) using asymptotic piecewise-linear approximations. Estimate the phase
margin from the Bode plot.

Question 5: Use LTspice or an exact analytical calculation to find a more precise value for
the phase margin.

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 PROBLEM 22 - COMMON-SOURCE AMPLIFIER,
CMOS ANALOG IC DESIGN CASCODE AMPLIFIER, MILLER CAPACITOR

 ROBLEM 22 - COMMON-
P
SOURCE AMPLIFIER, CASCODE
AMPLIFIER, MILLER CAPACITOR

The figure above shows a common-source amplifier stage. Transistor M1 is the common-source
gain transistor and transistor M2 is the load transistor. The input voltage ‫ݒ‬ூே to the amplifier
is a dc bias voltage ܸூே in series with a small-signal source ‫ݒ‬௜௡ . The load transistor is biased
by a dc gate voltage ܸ஻ଵ, and the dc supply voltage to the amplifier stage is ܸ஽஽ = 3.3 V .

The transistors can be described by the Shichman-Hodges transistor model, i.e.,

1
�� = ���� (�/�)(|��� | − |�� |)� (1 + �|��� |)
2

which is valid for both the NMOS transistor M1 and the PMOS transistor M2 when they
are in the active region (saturation region).

Transistor M1 has the following parameters: ���� = 200 μA/V � , � = 10 μm, � = 1 μm, �� =
0.6 V and ߣ = 0 V ିଵ, so the channel-length modulation can be neglected for M1.

Transistor M2 has the following parameters: ���� = 60 μA/V � , � = 10 μm , � = 0.35 μm ,

) = 800 μA/V ��, ��= and � = 0.1 V �� .
= 0.6VV and
�� −0.6

The capacitors ‫ܥ‬ଵ = 0.1 pF and ‫ܥ‬ଶ = 0.05 pF are the only capacitors which should be taken
into consideration.

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 PROBLEM 22 - COMMON-SOURCE AMPLIFIER,
CMOS ANALOG IC DESIGN CASCODE AMPLIFIER, MILLER CAPACITOR

Question 1: Find the dc bias value ܸூே of the input voltage such that the bias current (quiescent
current) of M1 is 250 µA, assuming that M1 is in the active region (saturation region).

Question 2: Find the dc bias voltage ܸ஻ଵ for M2 such that the bias value (quiescent value)
of the output voltage is 1.8 V.

Question 3: Draw a small-signal diagram of the amplifier stage and find the output resistance
and the small-signal gain ‫ܣ‬௩ = ‫ݒ‬௢ /‫ݒ‬௜௡ at low frequencies.

Question 4: Find the input capacitance for the amplifier stage.

In order to reduce the input capacitance, a common-gate stage M3 (cascode stage) is now
inserted after the common-source stage as shown above. Transistor M3 has the same transistor
parameters and the same dimensions as transistor M1, and also for M3, the channel-length
modulation can be neglected. Since M3 has source and bulk connected, the bulk effect can
also be neglected.

The dc bias voltage ܸ஻ଶ is ܸ஻ଶ = 1.8 V , and ܸ஻ଵ and ܸ஽஽ are the same as for the circuit
from Questions 1 to 4.

Question 5: Draw a small-signal diagram of the two-stage amplifier and find the output
resistance and the small-signal gain ‫ܣ‬௩ = ‫ݒ‬௢ /‫ݒ‬௜௡ at low frequencies.

Question 6: Find the small-signal gain ‫ܣ‬௩ଵ = ‫ݒ‬௫ /‫ݒ‬௜௡ at low frequencies for the common-
source stage M1.

Question 7: Find the input capacitance for the two-stage amplifier stage.

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CMOS ANALOG IC DESIGN Problem 23 - feedback amplifier, phase margin

 ROBLEM 23 - FEEDBACK
P
AMPLIFIER, PHASE MARGIN

The figure above shows an amplifier with feedback. The amplifier is assumed to have an
infinite input resistance and an output resistance of zero. The low-frequency gain of the
amplifier is 46 dB, and the amplifier frequency response has two poles at the frequencies
݂௣ଵ = 100 kHz and ݂௣ଶ = 1 MHz . The feedback network provides a frequency-independent
feedback factor of ߚ = 0.1.

Question 1: Find the low-frequency closed-loop gain of the amplifier with feedback.

Question 2: Find an expression for the transfer function of the loop gain ‫ )݂݆(ܮ‬and sketch
a Bode plot of the loop gain ‫)݂݆(ܮ‬. For the sketch, you may use asymptotic piecewise-linear
approximations for the gain plot and the phase plot.

Question 3: Find the phase margin of the amplifier with feedback. You may use asymptotic
piecewise-linear approximations for the Bode plot.

In order to increase the phase margin, it is now assumed that the pole at the frequency ݂௣ଵ
can be moved to a lower frequency.

Question 4: Find the new, lower value of ݂௣ଵ required to provide a phase margin of 60°.
You may use asymptotic piecewise-linear approximations for the Bode plot.

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CMOS ANALOG IC DESIGN Problem 24 - differential amplifier

 ROBLEM 24 - DIFFERENTIAL
P
AMPLIFIER

The figure above shows a differential amplifier stage. Transistors M1 and M2 are perfectly
matched and form the differential pair. Transistors M3 and M4 are also perfectly matched and
form an active load providing a single-ended output. Transistor M5 is providing a constant
bias current for the differential pair. All transistors have bulk and source connected, so the
bulk effect can be neglected. The two input voltages are ‫ݒ‬ூேశ and ‫ݒ‬ூேష , respectively, so
the differential input voltage is ‫ݒ‬௜ௗ = ‫ݒ‬ூேశ െ ‫ݒ‬ூேష and the common-mode input voltage is
ܸூ஼ெ = (‫ݒ‬ூேశ + ‫ݒ‬ூேష )/2.

The supply voltage is ܸ஽஽ = 3 V and the gate voltage to M5 is a dc bias voltage ܸ஻ = 0.75 V.

The transistors can be described by the Shichman-Hodges transistor model, i.e.,

1
�� = ���� (�/�)(|��� | − |�� |)� (1 + �|��� |)
2

which is valid for both the NMOS transistors and the PMOS transistors when they are in
the active region (saturation region).

All transistors have a channel length of � = 0.5 μm. For Questions 1 - 5, the channel-length
modulation can be neglected, i.e., ߣ = 0 V ିଵ for all transistors.

The NMOS transistors have the following parameters: and �� ��� = 200 μA/V � and �� = 0.50 V.
The PMOS transistors have the following parameters: and �� ��� = 62 μA/V � and �� = −0.54 V .

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CMOS ANALOG IC DESIGN Problem 24 - differential amplifier

The output of the differential stage is connected to a load capacitor ‫ܥ‬௅ = 0.16 pF, and this
is the only capacitor which should be taken into consideration.

Question 1: Find the channel width ܹହ of M5 so that a dc bias current of 12.5 µA is

achieved for M1 and M2. Assume that all transistors are in the active region (saturation
region).

Question 2: Find the transconductance ݃௠ଵ = ݃௠ଶ of transistors M1 and M2 so that a

gain-bandwidth product of 100 MHz is achieved.

Question 3: Find the channel width ܹଵ = ܹଶ of transistors M1 and M2 so that the

transconductance of M1 and M2 results in a gain-bandwidth product of 100 MHz.

Question 4: Find the minimum value of the common-mode input voltage ܸூ஼ெ for which
all transistors remain in the active region (saturation region).

Question 5: Find the channel width ܹଷ = ܹସ of transistors M3 and M4 so that a maximum

common-mode input voltage of ܸூ஼ெ of 2.7 V can be applied with all transistors remaining
in the active region (saturation region).

It is now assumed that the channel-length modulation is described by ߣ = 0.16 V ିଵ for

all transistors.

Question 6: Assuming that the bias currents remain unchanged and that the common-
mode input voltage is ܸூ஼ெ = 2.0 V , calculate the small-signal output resistance ‫ݎ‬௢௨௧ of the
differential amplifier stage.

Question 7: Assuming that the bias currents remain unchanged and that the common-
mode input voltage is ܸூ஼ெ = 2.0 V, calculate the low-frequency small-signal differential
gain ‫ܣ‬ௗ = ‫ݒ‬௢ /‫ݒ‬௜ௗ .

Question 8: Verify the answers to Questions 1 - 7 by LTspice simulations.

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 PROBLEM 25 - COMMON-DRAIN STAGE,
CMOS ANALOG IC DESIGN COMMON-GATE STAGE

 ROBLEM 25 - COMMON-DRAIN
P
STAGE, COMMON-GATE STAGE

The circuit shown above is an amplifier with a single-ended input ‫ݒ‬ூே = ܸூே + ‫ݒ‬௜௡ where
the bias value of the input voltage is equal to the voltage ܸ஻ which is a dc bias voltage
connected to the gate of M2.

The NMOS transistors M1 and M2 are identical and have the following parameters:
ߤ௡ ‫ܥ‬௢௫ (ܹ/‫ = )ܮ‬2.00 mA/V ଶ and threshold voltage ܸ௧ = 0.5 V . The PMOS transistors
M3 and M4 are identical and have ߤ௡ ‫ܥ‬௢௫ (ܹ/‫ = )ܮ‬2.00 mA/V ଶ and �� = −0.5 V . All
transistors have a channel-length modulation parameter ߣ = 0.04 V ିଵ . All transistors are
assumed to be in the active region. The supply voltage is ܸ஽஽ = 3 V, the bias voltage ܸ஻ is
ܸ஻ = ܸ஽஽ /2 = 1.5 V and the bias current ‫ܫ‬஻ is �� = 250 μA.

Question 1: Draw a low-frequency small-signal diagram for the amplifier and calculate
the values of the small-signal parameters in the circuit. You may assume ‫ܫ‬஽ଵ = ‫ܫ‬஽ଶ and
���� ≪ 1 for all transistors.

Question 2: The amplifier may be analyzed as a cascade of a common-drain input stage

and a common-gate output stage. Find the small-signal voltage gain ‫ܣ‬ଵ = ‫ݒ‬௦ /‫ݒ‬௜௡ of the
input stage where ‫ݒ‬௦ = ‫ݒ‬௦ଵ = ‫ݒ‬௦ଶ is the source voltage for both M1 and M2.

Question 3: Find the small-signal voltage gain ‫ܣ‬ଶ = ‫ݒ‬௢ /‫ݒ‬௦ of the output stage and find
the total gain ‫ܣ‬௩ = ‫ݒ‬௢ /‫ݒ‬௜௡ .

Question 4: Find the small-signal output resistance.

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 PROBLEM 25 - COMMON-DRAIN STAGE,
CMOS ANALOG IC DESIGN COMMON-GATE STAGE

Question 5: Use LTspice to verify the numerical results for the previous questions.

Question 6: Assuming that transistors M1 and M2 have a gate-source capacitance of

‫ܥ‬௚௦ = 50 fF and a gate-drain capacitance of ‫ܥ‬௚ௗ = 3 fF , what is the input capacitance of
the amplifier?

Question 7: What is the input capacitance of a common-source amplifier providing an

inverting gain of the same magnitude as the amplifier analyzed above and using a common-
source gain transistor with a gate-source capacitance of ‫ܥ‬௚௦ = 50 fF and a gate-drain
capacitance of ‫ܥ‬௚ௗ = 3 fF?

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 PROBLEM 26 - FEEDBACK AMPLIFIER,
CMOS ANALOG IC DESIGN INTEGRATING AMPLIFIER

 ROBLEM 26 - FEEDBACK
P
AMPLIFIER, INTEGRATING AMPLIFIER

The figure above shows an integrating amplifier implemented using an opamp with feedback.
The opamp is assumed to have an infinite input resistance and an output resistance of zero.

Question 1: Find an expression for the transfer function ‫ܣ‬஼௅ (݆݂) = ܸ௢ (݆݂)/ܸ௜௡ (݆݂) for
the amplifier with feedback, assuming that the opamp is an ideal opamp (infinite gain,
independent of frequency).

It is now assumed that the opamp does not provide an infinite gain but is described by a
transfer function

ܸ௢ (݆݂) ݂௧௔
‫= )݂݆(ܣ‬ =
ܸ௜ௗ (݆݂) ݆݂Ԝ൫1 + ݆݂/݂௣ ൯

at the frequencies of interest. The frequency ݂௧௔ is the gain-bandwidth product of the opamp
and ݂௣ is the frequency of a non-dominant pole for the opamp.

Question 2: Show that the loop gain of the amplifier with feedback is given by

2ߨԜܴ‫ܥ‬Ԝ݂௧௔ ݂௧௔ /݂ோ஼

‫= )݂݆(ܮ‬ =
(1 + ݆݂Ԝ2ߨԜܴ‫)ܥ‬൫1 + ݆݂/݂௣ ൯ (1 + ݆݂/݂ோ஼ )൫1 + ݆݂/݂௣ ൯

where ݂ோ஼ = 1/(2ߨԜܴ‫ )ܥ‬.

The resistor ܴ and the capacitor ‫ ܥ‬are now given by � = 10 kΩ and ‫ = ܥ‬15.9 pF .

Question 3: Determine the gain-bandwidth product ݂௧௔ of the opamp so that a low-
frequency loop gain of 40 dB is obtained.

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 PROBLEM 26 - FEEDBACK AMPLIFIER,
CMOS ANALOG IC DESIGN INTEGRATING AMPLIFIER

Question 4: Assuming ݂௧௔ = 100 MHz , determine the pole frequency ݂௣ so that a phase
margin of 60° is obtained. When calculating the phase margin, you may assume that the
frequency for which |‫ = |)݂݆(ܮ‬1 is much larger than ݂ோ஼ . Also sketch a Bode plot (magnitude
and phase) of the loop gain. You may use asymptotic piecewise-linear approximations for
the Bode plot.

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52
 PROBLEM 27 - COMMON-SOURCE
CMOS ANALOG IC DESIGN AMPLIFIER, TWO-STAGE AMPLIFIER

 ROBLEM 27 - COMMON-SOURCE
P
AMPLIFIER, TWO-STAGE AMPLIFIER

The figure above shows an amplifier consisting of two cascade-connected inverting gain stages.
The supply voltages are ܸ஽஽ = 1 V and −��� = −1 V . The transistors have the following
parameters: �� ��� = 100 μA/V � , �� ��� = 40 μA/V �, ��� = 0.8 V, ��� = −0.8 V.. The channel-
length modulation can be neglected for both transistors. Also, �� = 1 kΩ, �� = �� = 10 kΩ
and �� = 40 kΩ..

Question 1: Show that the quiescent values ܸைଵ and ܸைଶ of the output voltages from stage
1 and stage 2, respectively, are both 0 V when the transistor aspect ratios are ܹଵ /‫ܮ‬ଵ = 50
and ܹଶ /‫ܮ‬ଶ = 125 and the quiescent value of the input voltage is ܸூே = 0 V .

Question 2: Draw the small-signal diagram for the amplifier for low frequencies and
calculate the gain of each gain stage (‫ܣ‬௩ଵ = ‫ݒ‬௢ଵ /‫ݒ‬௜௡ and ‫ܣ‬௩ଶ = ‫ݒ‬௢ଶ /‫ݒ‬௢ଵ ) and the total gain,
‫ܣ‬௩ = ‫ݒ‬௢ଶ /‫ݒ‬௜௡ .

Question 3: For an output signal swing with an amplitude of 100 mV at low frequencies,
find the corresponding amplitude of the input signal.

For the two transistors, it can be assumed that the only parasitic capacitors are: ‫ܥ‬௚௦ଵ = 100 fF,
‫ܥ‬௚ௗଵ = 20 fF , ‫ܥ‬௚௦ଶ = 250 fF and ‫ܥ‬௚ௗଶ = 50 fF . Also, a capacitor ‫ܥ‬௙௕ = 200 fF is connected
between the gate and the drain of M2.

Question 4: Find the −3 dB cut-off frequency for the amplifier assuming that there is a
dominant pole.

Question 5 : Use LTspice to verify your results for the previous questions.

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 PROBLEM 28 - FEEDBACK AMPLIFIER,
CMOS ANALOG IC DESIGN MILLER COMPENSATION

 ROBLEM 28 - FEEDBACK
P
AMPLIFIER, MILLER COMPENSATION

The figure above shows the small-signal equivalent circuit for a two-stage operational amplifier
equipped with a Miller compensation capacitor ‫ܥ‬௖ . This is the only capacitor which must
be considered when analyzing the frequency response of the amplifier.

Question 1: Find an expression for the low-frequency gain ���� =

= ����/�
/��� where
�� where
where ���� = ����
�� = −
���� −
‫ݒ‬௜௡ష.

Question 2: Show that the transfer function ‫ܣ‬ௗ (‫ܸ = )ݏ‬௢ (‫)ݏ‬/ܸ௜ௗ (‫ )ݏ‬is given by

1 െ ‫ݏ‬Ԝ‫ܥ‬௖ /݃௠ଶ
‫ܣ‬ௗ (‫ܣ = )ݏ‬଴ ൬ ൰
1 + ‫ݏ‬Ԝ‫ܥ‬௖ (ܴଵ + ܴଶ + ܴଵ ܴଶ ݃௠ଶ )

and find expressions for the frequencies of poles and zeros in the transfer function.

Question 3: Show that the gain-bandwidth product of the amplifier is ݂௧௔ ؄ ݃௠ଵ /(2ߨԜ‫ܥ‬௖ )
when ��� ≫ 1/�� and ��� ≫ 1/�� .

The opamp is now used in a feedback amplifier with a feedback factor ߚ as shown below.

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 PROBLEM 28 - FEEDBACK AMPLIFIER,
CMOS ANALOG IC DESIGN MILLER COMPENSATION

Question 4: Find an expression for the closed-loop gain ‫ܣ‬஼௅ (‫ܸ = )ݏ‬௢ (‫)ݏ‬/ܸ௜௡ (‫ )ݏ‬and show
that the closed-loop gain has a right-half-plane zero at ߱Ԝ௭஼௅ = ߱Ԝ௭ = ݃௠ଶ /‫ܥ‬௖ and a left-
half-plane pole at ߱௣஼௅ = (1 + ߚ‫ܣ‬଴ )߱௣ /൫1 െ ߚ‫ܣ‬଴ ߱௣ /߱Ԝ௭ ൯ where �� ≃ 1/(��� �� �� �� )
when ��� ≫ 1/�� and ��� ≫ 1/�� .

Now, assume that the low-frequency loop gain ‫ܮ‬଴ = ߚ‫ܣ‬଴ is much larger than 1, i.e., ��� ≫ 1.

Question 5: Show that the gain-bandwidth product of the amplifier with feedback is

1 1
GBW ؄ ݂௧௔ ൬ ൰ ؄ ݂௧௔ ൬ ൰
1 െ ߚ݂௧௔ /݂௭ 1 െ ߚ݃௠ଵ /݃௠ଶ

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 CMOS ANALOG IC DESIGN Problem 29 - two-stage opamp

PROBLEM 29 - TWO-STAGE OPAMP

The figure above shows a two-stage operational amplifier with a bias network consisting
of transistors M1 and M2 and the resistor ܴ஻. A Miller compensation capacitor ‫ܥ‬௖ is also
included. As shown, bulk and source are connected for all transistors. The supply voltage
is ܸ஽஽ = 3 V and the bias voltage at the two inputs is ܸூேశ = ܸூேష = 1.5 V. The Miller
compensation capacitance is ‫ܥ‬௖ = 1 pF.

The transistors can be described by the Shichman-Hodges transistor model, i.e.,

1
�� = ���� (�/�)(|��� | − |�� |)� (1 + �|��� |)
2

which is valid for both the NMOS transistors and the PMOS transistors when they are in
the active region (saturation region).

All transistors have a channel length of ‫ = ܮ‬0.5 and a channel-length modulation parameter
, ��� = 0.6 V and
of � = 0.1 V �� .

The NMOS transistors have the following parameters: �� ��� = 200 μA/V � and �� = 0.5 V..
The PMOS transistors have the following parameters: �� ��� = 100 μA/V � and �� = −0.7 V .

The channel widths are

�� = �� = �� = �� = 5 μm, �� = 10 μm, �� = �� = 20 μm, �� = �� = 50 μm.

Question 1: Find ܴ஻ so that the current through M1 and M2 is 20 µA and find the bias
current in M3 and M8. The channel-length modulation can be neglected in this question.

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CMOS ANALOG IC DESIGN Problem 29 - two-stage opamp

Question 2: Show that all transistors are biased in the active region. It can be assumed
that the dc output voltage of the operational amplifier is ܸை = ܸ஽஽ /2 . The channel-length
modulation can be neglected in this question.

Question 3: Find expressions for the small-signal differential gain ‫ܣ‬ௗ = ‫ݒ‬௢ /(‫ݒ‬௜௡శ െ ‫ݒ‬௜௡ష )
and the small-signal output resistance ‫ݎ‬௢௨௧ at low frequencies and calculate the numerical
values.

Question 4: Assuming that the Miller compensation capacitor is the only capacitor which
must be taken into account, find the −3 dB frequency for the differential gain.

Now the operational amplifier is used as a buffer, i.e., the output ‫ݒ‬ை is connected to the
inverting input ‫ݒ‬ூேష . The input to the buffer is ‫ݒ‬ூேశ and the output from the buffer is ‫ݒ‬ை.

Question 5: Find the small-signal output resistance and −3 dB bandwidth for the buffer.

Question 6: Use LTspice simulations to verify your answers to Questions 1 - 5. Explain

the differences between calculated and simulated results.

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CMOS ANALOG IC DESIGN Problem 30 - feedback amplifier, phase margin

 ROBLEM 30 - FEEDBACK
P
AMPLIFIER, PHASE MARGIN

The figure above shows an amplifier with negative feedback. The transfer function for the
amplifier is

‫ܣ‬଴ (1 െ ‫ݏ‬/߱Ԝ௭ )
‫= )ݏ(ܣ‬
൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯

where‫ܣܣܣ‬଴଴=
଴‫ܣ‬ ଴=1000
==1000
1000V/V
1000
V/V
V/V,,, ,݂,݂௣ଵ
V/V ݂௣ଵ
݂௣ଵ====
௣ଵ ߱߱߱
߱
௣ଵ
௣ଵ/(2Ԝߨ)
௣ଵ/(2Ԝߨ)
௣ଵ/(2Ԝߨ)====
/(2Ԝߨ) 111kHz
1kHz
kHz,, ,݂,݂௣ଶ
kHz ݂௣ଶ
݂௣ଶ====
௣ଶ ߱߱߱
߱
௣ଶ
௣ଶ/(2Ԝߨ)
௣ଶ/(2Ԝߨ)
௣ଶ/(2Ԝߨ)====
/(2Ԝߨ) 111MHz
MHzand ݂௭ = ߱Ԝ௭ /
1MHz
MHz
(2Ԝߨ) = 1 MHz .
The amplifier is assumed to have an infinite input impedance and an output impedance
of zero. The ߚ−circuit is also assumed to have an infinite input impedance and an output
impedance of zero.

Question 1: Sketch a Bode plot of the loop gain ‫ )݂݆(ܣߚ = )݂݆(ܮ‬for a feedback factor
ߚ = 0.1 using piecewise-linear approximations to the amplitude response and the phase
response.

Question 2: Find the unity-gain frequency ݂௧ of the loop gain and find the phase margin
PM for ߚ = 0.1.

Question 3: Find the maximum feedback factor for which the phase margin is PM ≥ 60°.

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CMOS ANALOG IC DESIGN Problem 31 - dual-output gain stage

 ROBLEM 31 - DUAL-
P
OUTPUT GAIN STAGE

The figure above shows a gain stage with two outputs, ‫ݒ‬஽ and ‫ݒ‬ௌ . The resistors ܴ஽ and
ܴௌ have the values �� = 30 kΩ and �� = 15 kΩ. The supply voltage is ܸ஽஽ = 1.8 V . The
transistor has ܸ௧ = 0.4 V and �� ��� = 180 μA/V � . The channel length is � = 0.9 μm and
the channel-length modulation can be neglected. As shown, source and bulk are connected
for the transistor, so there is no body effect.

Question 1: Design the channel width of the transistor so that the transistor has
transconductance of 0.2 mA/V and the bias value of ‫ݒ‬஽ is 1.2 V.

Question 2: Calculate the bias values of ‫ݒ‬ௌ and ‫ݒ‬ூே .

Question 3: Draw a small-signal equivalent circuit and find expressions for the small-signal
gains ‫ݒ‬ௗ /‫ݒ‬௜௡ and ‫ݒ‬௦ /‫ݒ‬௜௡ . Find numerical values for the small-signal gains.

Question 4: Find expressions for the small-signal output resistances at the two outputs and
calculate the numerical values.

Now a capacitor ‫ܥ‬௚௦ = 0.318 pF is connected between the gate and the source of M1. This
introduces both a pole and a zero in the transfer function ܸ௦ (‫)ݏ‬/ܸ௜௡ (‫)ݏ‬.

Question 5: Use a node equation to find the frequency of the pole and the frequency of
the zero ܸ௦ (‫)ݏ‬/ܸ௜௡ (‫ )ݏ‬in introduced by ‫ܥ‬௚௦ . You may assume that ‫ܥ‬௚௦ is the only capacitor
which must be taken into account.

Question 6: Find an expression for the transfer function ܸௗ (‫)ݏ‬/ܸ௜௡ (‫ )ݏ‬and find the −3 dB
frequency for ܸௗ (݆݂)/ܸ௜௡ (݆݂).

Question 7: Verify your answers to Questions 1 - 6 using LTspice.

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 CMOS ANALOG IC DESIGN Problem 32 - dc current source

PROBLEM 32 - DC CURRENT SOURCE

The figure above shows a circuit used to generate a small dc output current ‫ܫ‬ை to flow through
a load resistor ܴ௅. M1 and M2 are two identical transistors with a channel length of 1 µm and
a channel width of 2 µm and they have ܸ௧ = 0.4 V and �� ��� = 180 μA/V � . The input
current is ��� = 45 μA and the supply voltage is ܸ஽஽ = 1.8 V.

Question 1: Find the value for ܴ஻ resulting in an output current of �� = 5 μA when M2

is in the active region.
In this question, the channel-length modulation is ignored for both M1 and M2.

Question 2: Find the maximum value of ܴ௅ for which both M1 and M2 are in the active
region. In this question, the channel-length modulation is ignored for both M1 and M2.

Question 3: Find the output resistance of the current source when both M1 and M2 are
in the active region.
In this question, the channel-length modulation is modeled by the channel-length parameter
�� = 0.6 V and � = 0.1 V �� . You may use reasonable approximations for the calculation of the small-signal
transistor parameters and the output resistance.

Question 4: How does it affect the output resistance if the transistor geometry is changed
to ܹ = 4 μm and ‫ = ܮ‬42 μm for both transistors?

Question 5: Verify your answers to Questions 1 - 4 using LTspice.

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CMOS ANALOG IC DESIGN Problem 33 - feedback amplifier, phase margin

 ROBLEM 33 - FEEDBACK
P
AMPLIFIER, PHASE MARGIN

The figure above shows an amplifier with feedback. The input voltage ܸ௜௡ is applied to the
inverting input of the input stage which is a gain stage with the transfer function

ܸ௠ ‫ܩ‬଴
‫= )ݏ(ܩ‬ =
ܸௗ ൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯

where ߱௣ଵ is a dominant pole and ߱௣ଶ ‫߱ ب‬௣ଵ is a non-dominant pole. The low-
frequency gain is ‫ܩ‬଴ = 1000 V/V and the pole frequencies are ߱௣ଵ = 20 × 10ଷ rad/s and
߱௣ଶ = 4 × 10଺ rad/s.

The output stage is an inverting common-source gain stage with a PMOS transistor M1
having a transconductance ݃௠ଵ = 0.1 mA/V . The channel-length modulation can be ignored.

The resistors ܴଵ and ܴଶ have the values �� = 1 kΩ and �� = 9 kΩ.

Question 1: Find expressions for the open-loop gain ‫ )ݏ(ܣ‬and the feedback factor and
show that the loop gain is

‫ܩ‬଴ Ԝ݃௠ଵ Ԝܴଵ

‫= )ݏ(ܮ‬
൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯

Calculate the low-frequency values of the open-loop gain and the loop gain. Also calculate
the value of the low-frequency closed-loop gain ܸ௢ /ܸ௜௡ .

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CMOS ANALOG IC DESIGN Problem 33 - feedback amplifier, phase margin

Question 2: Find the gain-bandwidth product ߱௧௟ of the loop gain.

Question 3: Find the phase margin of the amplifier with feedback. You may use reasonable
approximations.

In order to increase the phase margin, it is now assumed that the dominant pole can be
moved to a lower frequency without affecting ‫ܩ‬଴ and ߱௣ଶ .

Question 4: Find the new, lower value of ߱௣ଵ required to provide a phase margin of 76°.

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62
 PROBLEM 34 - INVERTING AMPLIFIER,
CMOS ANALOG IC DESIGN COMMON-SOURCE STAGE

 ROBLEM 34 - INVERTING
P
AMPLIFIER, COMMON-
SOURCE STAGE

The figure above shows an inverting amplifier stage.

For the transistors, we have �� ��� = 300 μA/V � and �� ��� = 100 μA/V � . The transistor
threshold voltages are ܸ௧௡ = 0.6 V and ��� = −0.7 V.. The channel-length modulation is
given by �� = �� = 0.1 μm/V for the NMOS transistor and �� = �� = 0.2 μm/V for the
PMOS transistor. The channel length is � = 0.5 μm for both transistors and M1 has a
channel width of �� = 4 μm while the channel width ܹଶ is to be found in Question 2.

The supply voltage is ܸ஽஽ = 2 V and the gate voltage for M2 is ܸ஻ = 1.1 V . The dc input
bias voltage is ܸூே = 0.7 V .

The load resistor is �� = 200 kΩ and the capacitor ‫ ܥ‬is assumed to be so large that it
represents a short circuit for ac signals but an open circuit for dc voltages.

Question 1: Find the bias value of the drain current in M1 and M2 assuming that the dc
bias value of the voltage ܸ௑ at the output of the transistor stage is 1 V.

Question 2: Find the channel width ܹଶ of transistor M2 so that the dc bias voltage ܸ௑ at
the output of the transistor stage is 1 V.

In the following questions, the bias voltages are assumed to be ܸூே = 0.7 V and ܸ௑ = 1.0 V.

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 PROBLEM 34 - INVERTING AMPLIFIER,
CMOS ANALOG IC DESIGN COMMON-SOURCE STAGE

Question 3: Find the transconductance ݃௠ଵ for M1.

Question 4: Find the small-signal drain-source resistance ‫ݎ‬ௗ௦ଶ for M2.

Question 5: Find the small-signal gain ‫ܣ‬௩ = ܸ௢ /ܸ௜௡ at low frequencies where ‫ ܥ‬can be
treated as a short circuit.

Question 6: Find the maximum voltage ܸ௑max for which both transistors are in the active
region.

Question 7: Use LTspice to verify the results from Questions 1 - 6.

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64
CMOS ANALOG IC DESIGN Problem 35 - cascode gain stage

 ROBLEM 35 - CASCODE
P
GAIN STAGE

The figure above shows a telescopic cascode stage consisting of a common-source stage M4
followed by a common-gate stage M3 and loaded by a cascode current source consisting of
M1 and M2.

The amplifier has been simulated by LTspice and from a ‘.op’ simulation, we have the
following results from the output file and the error log file.

Output file

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65
CMOS ANALOG IC DESIGN Problem 35 - cascode gain stage

Error log file

Question 1: Verify that all transistors are in the active region for the dc bias point of the
gain stage.

Question 2: From the simulation results, calculate the small-signal output resistance ‫ݎ‬௢௨௧
of the cascode stage.

Question 3: From the simulation results, calculate the small-signal gain ‫ܣ‬௩ = ‫ݒ‬௢ /‫ݒ‬௜௡ .

Question 4: From the simulation results, calculate the small-signal gain ‫ܣ‬௩,௖௦ = ‫ݒ‬ௗସ /‫ݒ‬௜௡
of the common-source stage, i.e., the small-signal gain from the input to the drain of M4.

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 PROBLEM 36 - COMMON-SOURCE
CMOS ANALOG IC DESIGN AMPLIFIER, MILLER COMPENSATION

 ROBLEM 36 - COMMON-SOURCE
P
AMPLIFIER, MILLER COMPENSATION

The figure above shows a common-source amplifier stage with M1 as the common-source
gain transistor and M2 as the load transistor. The input voltage ‫ݒ‬ூே to the amplifier has
a dc bias value of ܸூே = 0.8 V and the signal source resistance is �� = 250 kΩ. The load
transistor is biased by a dc gate voltage ܸ஻ = 1.1 V, and the dc supply voltage to the
amplifier is ܸ஽஽ = 2.0 V..

The capacitors shown in the schematic are the only capacitors which should be considered in
the analysis of the amplifier stage and they have the values ‫ܥ‬ଵ = 0.5 pF, ‫ܥ‬ଶ = 2.0 pF and ‫ܥ‬௅ =
1.0 pF .

The transistors can be described by the Shichman-Hodges transistor model, i.e.,

1
�� = ���� (�/�)(|��� | − |�� |)� (1 + �|��� |)
2

which is valid for both the NMOS transistor and the PMOS transistor when they are in
the active region.

Transistor M1 has the following parameters: �� ��� = 300 μA/V � , �� = 6 μm , �� = 1 μm ,

��� = 0.6 V and ��� = �� �� = 0.1 μm/V .

Transistor M2 has the following parameters: �� ��� = 100 μA/V � , �� = 36 μm, �� = 2 μm,
��� = −0.7 V and ��� = �� �� = 0.2 μm/V..

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 PROBLEM 36 - COMMON-SOURCE
CMOS ANALOG IC DESIGN AMPLIFIER, MILLER COMPENSATION

Question 1: Find the dc bias value of the output voltage and of the drain current in M1
and M2.

Question 2: Draw a small-signal diagram of the amplifier stage and find the values of the
small-signal parameters for the transistors in the diagram.

Question 3: Find the output resistance ‫ݎ‬௢௨௧ of the amplifier and the small-signal gain
‫ܣ‬௩ = ‫ݒ‬௢ /‫ݒ‬௜௡ at low frequencies.

Question 4: Find the frequency ݂௣ଵ of the dominant pole for the amplifier.

Question 5: Find the frequency ݂௣ଶ of the non-dominant pole for the amplifier. You may
assume ݂௣ଶ ‫݂ ب‬௣ଵ .

Question 6: Use LTspice to verify the results from Questions 1 - 5.

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68
CMOS ANALOG IC DESIGN Problem 37 - feedback amplifier, phase margin

 ROBLEM 37 - FEEDBACK
P
AMPLIFIER, PHASE MARGIN

The figure above shows an amplifier with feedback. The amplifier is assumed to have an
infinite input resistance and an output resistance of zero.

The open-loop gain of the amplifier is given by

1000 V/V
‫= )ݏ(ܣ‬
൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯

where ߱௣ଵ = 2Ԝߨ݂௣ଵ and ߱௣ଶ = 2Ԝߨ݂௣ଶ with ݂௣ଵ = 1.2 kHz and ݂௣ଶ = 300 kHz.

The feedback factor is given by ߚ(‫ = )ݏ‬0.06 V/V.

Question 1: Find the low-frequency closed-loop gain of the amplifier with feedback.

Question 2: Use LTspice to find the gain-bandwidth product GBW of the amplifier with
feedback.

Question 3: Find the phase margin of the amplifier with feedback.

The feedback amplifier is now modified to have an open-loop gain given by ‫= )ݏ(ܣ‬
(100 V/V)/൫1 + ‫ݏ‬/߱௣ଵ ൯ and a feedback factor given by ߚ(‫( = )ݏ‬0.6 V/V)/൫1 + ‫ݏ‬/߱௣ଶ ൯ .

The values of ߱௣ଵ and ߱௣ଶ remain unchanged, i.e., ߱௣ଵ = 2Ԝߨ݂௣ଵ and ߱௣ଶ = 2Ԝߨ݂௣ଶ with
݂௣ଵ = 1.2 kHz and ݂௣ଶ = 300 kHz.

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CMOS ANALOG IC DESIGN Problem 37 - feedback amplifier, phase margin

Question 4: Find the low-frequency closed-loop gain of the modified amplifier with feedback.

Question 5: Use LTspice to find the gain-bandwidth product GBW of the modified amplifier
with feedback.

Question 6: Find the phase margin of the modified amplifier with feedback.

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70
CMOS ANALOG IC DESIGN Problem 38 - voltage regulator

PROBLEM 38 - VOLTAGE REGULATOR

The figure above shows a low dropout voltage regulator turning an unregulated dc voltage
ܸூே into a regulated dc output voltage ܸை. The opamp ‫ܣ‬ଵ has the transfer function ‫ܣ‬ଵ (‫= )ݏ‬
‫ܣ‬଴ /൫1 + ‫ݏ‬/߱௣ ൯ where the low-frequency gain is ‫ܣ‬଴ = 500 V/V and the pole frequency is
߱௣ = 2ԜߨԜ݂௣ where ݂௣ = 100 kHz . The opamp has an infinite input impedance and zero
output impedance.

Transistor M1 has a transconductance ݃௠ଵ = 10.0 mA/V and a small-signal drain-source

resistance ���� = 5 kΩ . The transistor capacitances can be neglected. The input voltage ܸூே
is large enough to keep M1 in the active region and the reference voltage ܸref has the value
ܸref = 1.25 V. The resistors ܴଵ and ܴଶ both have a value of 20 kΩ.

The load can be modeled as a dc current source with a value of 2.0 mA.

Question 1: Find an expressions for the loop gain ‫ )ݏ(ܮ‬and calculate the output voltage
ܸை at low frequencies (well below ݂௣).

Question 2: Find the line regulation ߲ܸை /߲ܸூே at low frequencies.

Question 3: Find the output resistance of the regulator at low frequencies.

Question 4: Design transistor M1 to provide ݃௠ଵ = 10.0 mA/V and ���� = 5 kΩ , i.e., find
ܹଵ and find the channel-length modulation parameter ߣ . Use the Shichman-Hodges transistor

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71
CMOS ANALOG IC DESIGN Problem 38 - voltage regulator

model assuming a channel length �� = 1 μm , �� ��� = 100 μA/V � and ��� = −0.4 V .
Also, assume ܸூே = 3.0 V.

Question 5: Use LTspice to simulate the line regulation and the output impedance versus
frequency and find the line regulation and the output impedance at a frequency of ݂ =
2 MHz.

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72
CMOS ANALOG IC DESIGN Problem 39 - feedback, phase margin

 ROBLEM 39 - FEEDBACK,
P
PHASE MARGIN

The figure above shows a feedback amplifier implemented by an operation amplifier ‫ܣ‬
and two resistors ܴଵ and ܴଶ. The resistors both have a value of 200 kΩ. The operational
amplifier has a transfer function

1 െ ‫ݏ‬/߱௭
‫ܣ = )ݏ(ܣ‬଴
1 + ‫ݏ‬/߱௣

where the low-frequency gain is ‫ܣ‬଴ = 1000 V/V , the pole is located at the frequency ݂௣ =
20 kHz and the zero is located at the frequency ݂௭ = 30 MHz. The output impedance of
the opamp is zero and the input resistance is infinite but each of the two inputs to the
opamp has a parasitic capacitance of 200 fF to ground.

Question 1: Find the low-frequency closed-loop gain ‫ܣ‬஼௅଴.

Question 2: Find the closed-loop gain ‫ܣ‬஼௅ஶ for ݂ ՜ λ .

Question 3: Sketch a Bode plot of the loop gain ‫ )݂݆(ܣߚ = )݂݆(ܮ‬and estimate the phase
margin from the Bode plot.

Question 4: Use LTspice to simulate the loop gain and find the phase margin from the
simulated loop gain.

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 PROBLEM 40 - SOURCE FOLLOWER,
CMOS ANALOG IC DESIGN COMMON-DRAIN STAGE

 ROBLEM 40 - SOURCE FOLLOWER,

P
COMMON-DRAIN STAGE

The figure above shows a common-drain amplifier stage with an NMOS transistor M1 and
a bias current source �� = 100 μA.

The transistor has a channel length of �� = 0.5 μm, a channel width of �� = 100 μm and
the process parameters are �� ��� = 240 μA/V � , ��� = 0.5 V and ��� = �� �� = 0.08 μm/V.

The supply voltages are ܸ஽஽ = ܸௌௌ = 1.5 V and the input voltage ‫ݒ‬ூே is connected to the
gate of M1 via a resistor �� = 20 kΩ. The input voltage can vary between the negative
supply voltage and the positive supply voltage.

The output is connected to a load resistor �� = 1 k٠in parallel with a load capacitor

‫ܥ‬௅ = 1 nF.

Question 1: Find the bias value of the drain current in M1 assuming that the dc bias value
of the voltage ܸை at the output of the transistor stage is 0 V.

Question 2: Find the transconductance ݃௠ଵ of transistor M1 when ܸை = 0 V.

Question 3: Find the low-frequency small-signal gain ‫ܣ‬௩ = ‫ݒ‬௢ /‫ݒ‬௜௡ when the bias value of
the output voltage is ܸை = 0 V.

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 PROBLEM 40 - SOURCE FOLLOWER,
CMOS ANALOG IC DESIGN COMMON-DRAIN STAGE

Question 4: Find the minimum value ܸை,min of the output voltage with ܸூே in the range
���� ≤ ‫ݒ‬ூே ൑ ܸ஽஽ .

Question 5: Find the maximum value ܸை,max of the output voltage with ܸூே in the range
���� ≤ ‫ݒ‬ூே ൑ ܸ஽஽ .

Assume that the only capacitances in the circuit to be taken into consideration are the
load capacitance ‫ܥ‬௅ = 1 nF, the gate-source capacitance ‫ܥ‬௚௦ଵ = 200 fF and the gate-drain
capacitance ‫ܥ‬௚ௗଵ = 10 fF.

Question 6: Find the frequency ݂௣ of the dominant pole in the circuit.

Question 7: Use LTspice to verify the results from Questions 1 - 6.

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CMOS ANALOG IC DESIGN Problem 41 - feedback amplifier, phase margin

 ROBLEM 41 - FEEDBACK
P
AMPLIFIER, PHASE MARGIN

The figure above shows an amplifier with feedback. The amplifier is assumed to have an
infinite input resistance and an output resistance of zero.

The open-loop gain of the amplifier is given by

‫ܣ‬଴ (1 െ ݆݂/݂௭ )
‫= )݂݆(ܣ‬
൫1 + ݆݂/݂௣ଵ ൯൫1 + ݆݂/݂௣ଶ ൯

where ‫ܣ‬଴ = 1000 V/V, ݂௭ = 10 MHz, ݂௣ଵ = 20 kHz and ݂௣ଶ = 50 MHz. The feedback
factor is ߚ = 0.2 V/V.

Question 1: Find the low-frequency closed-loop gain of the amplifier with feedback.

Question 2: Find the unity-gain frequency ݂௧ of the loop gain ‫)݂݆(ܣߚ = )݂݆(ܮ‬.

Question 3: Find the phase margin of the amplifier with feedback.

Question 4: Use LTspice to verify the results for Questions 1 - 3.

Question 5: Use LTspice to find the −3 dB bandwidth ݂ିଷԜdB and the unity-gain bandwidth
݂௧஼௅ for the closed-loop gain of the amplifier.

Question 6: Use LTspice to find the maximum value ߚmax of the feedback factor for which
the amplifier is stable.

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CMOS ANALOG IC DESIGN Problem 42 - opamp, voltage follower

 ROBLEM 42 - OPAMP,
P
VOLTAGE FOLLOWER

The figure above shows a two-stage CMOS opamp with a PMOS differential pair with active
load as the input stage and an NMOS common-source stage as the second stage. The differential
input signal to the amplifier is ‫ݒ‬ூ஽ = ‫ݒ‬ூேଵ െ ‫ݒ‬ூேଶ and the output voltage is ‫ݒ‬ை. The capacitor
‫ܥ‬௖ = 0.2 pF is a compensation capacitor and the capacitor ‫ܥ‬௅ = 1 is a load capacitor. The
amplifier has been simulated with LTspice and the error log file from a ‘.op’ simulation provides
the bias values and small-signal parameters listed in the following table.

Error log file

Question 1: Use the simulation results to find the bias current ‫ܫ‬஻ூ஺ௌ and the supply voltage
ܸ஽஽ .

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CMOS ANALOG IC DESIGN Problem 42 - opamp, voltage follower

Question 2: Use the simulation results to find the quiescent values of the input voltages
and the output voltage.

Question 3: Use the simulation results to find the low-frequency small-signal gain ‫ܣ‬௩ = ‫ݒ‬௢ /‫ݒ‬௜௡ .

Question 4: Use the simulation results (including simulated transistor capacitances) and
the values of the capacitors ‫ܥ‬௖ and ‫ܥ‬௅ to estimate the frequency ݂௣ଵ of the dominant pole
for the amplifier.

Question 5: Use the simulation results (including simulated transistor capacitances) and
the values of the capacitors ‫ܥ‬௖ and ‫ܥ‬௅ to estimate the frequency ݂௣ଶ of the non-dominant
pole for the amplifier.

Question 6: Use the simulation results (including simulated transistor capacitances) and the
values of the capacitors ‫ܥ‬௖ and ‫ܥ‬௅ to estimate the frequency ݂௭ of the zero for the amplifier.

The amplifier is now configured as a buffer by connecting the output ‫ݒ‬ை to the inverting
input ‫ݒ‬ூேଶ while using ‫ݒ‬ூேଵ as the input and ‫ݒ‬ை as the output.

Question 7: Use the simulation results to find the low-frequency closed-loop output
resistance ‫ݎ‬௢௨௧஼௅ of the buffer.

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CMOS ANALOG IC DESIGN Problem 43 - feedback amplifier, bandwidth

 ROBLEM 43 - FEEDBACK
P
AMPLIFIER, BANDWIDTH

The figure above shows an amplifier with feedback. The amplifier is assumed to have an
infinite input resistance and an output resistance of zero.

The open-loop gain of the amplifier is given by ‫ܣ = )ݏ(ܣ‬଴ /൫1 + ‫ݏ‬/߱௣ଵ ൯ where the low-
frequency gain ‫ܣ‬଴ is 80 dB and the pole frequency ߱௣ଵ is ߱௣ଵ = 2Ԝߨ݂௣ଵ with ݂௣ଵ = 1.2 kHz .

The feedback factor is ߚ = 0.05 V/V.

Question 1: Find the low-frequency closed-loop gain of the feedback amplifier.

Question 2: Find the −3 dB bandwidth of the feedback amplifier.

Question 3: Find the phase margin of the feedback amplifier.

In order to increase the −3 dB bandwidth of the feedback amplifier, a non-dominant pole

is introduced in the feedback loop by modifying ‫ )ݏ(ܣ‬to
‫ܣ‬଴
‫= )ݏ(ܣ‬
൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯

where the pole frequency ߱௣ଶ is ߱௣ଶ = 2Ԝߨ݂௣ଶ with ݂௣ଶ = 1.2 MHz. The dominant pole
remains unchanged with ݂௣ଵ = 1.2 kHz .

Question 4: Use LTspice to find the −3 dB bandwidth of the modified feedback amplifier.

Question 5: Find the phase margin of the modified feedback amplifier.

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79
CMOS ANALOG IC DESIGN Problem 43 - feedback amplifier, bandwidth

Alternatively, the non-dominant pole may be introduced in the feedback network.

In this case, ߚ(‫ߚ = )ݏ‬଴ /൫1 + ‫ݏ‬/߱௣ଶ ൯ with ߚ = 0.05 V/V and ‫ܣ = )ݏ(ܣ‬଴ /൫1 + ‫ݏ‬/߱௣ଵ ൯.

Question 6: Use LTspice to find the −3 dB bandwidth of the modified feedback amplifier.

Question 7: Find the phase margin of the modified feedback amplifier.

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CMOS ANALOG IC DESIGN

SOLUTIONS

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81
CMOS ANALOG IC DESIGN Solution to Problem 1

SOLUTION TO PROBLEM 1

Question 1:
Neglecting the channel-length modulation, we have the Shichman-Hodges model

1
‫ܫ‬஽ = ߤ‫ܥ‬௢௫ (ܹ/‫ீܸ()ܮ‬ௌ െ ܸ௧ )ଶ
2

For M5, this gives

2‫ܫ‬஽ 2 × 0.36 mA
ܸ஻ = ܸீௌହ = ඨ + ܸ௧ = ඨ + 0.6 V = 2.50 V
ߤ‫ܥ‬௢௫ (ܹ/‫)ܮ‬ 0.2 mA/V ଶ

For M1 - M4, we have �� = ��� /2 = 180 μA for symmetry reasons.

For M7, we have ��� = ��� /2 = 180 μA because of the scaling between M5 and M7.
For M6, we have ��� = ��� = 180 μA .

Since all transistors have the same current density ‫ܫ‬஽ /൫ߤ‫ܥ‬௢௫ (ܹ/‫)ܮ‬൯ and operate in the
active region, they all have the same gate-source voltage |ܸீௌ | = 2.50 V. For the NMOS
transistors, ܸீௌ is positive. For the PMOS transistors, ܸீௌ is negative.

For M1, we have �� = ��� − |���� | = 5.00 V − 2.50 V = 2.50 V , and for M2, we have ܸ஽ =
��� − |���� | = 5.00 V − 2.50 V = 2.50 V . Also, ��� = ��� = −���� = −2.50 V , i.e. ܸ஽ௌଵ =
ܸ஽ௌଶ = 5.00 V. We notice that ��� > ��� − �� = 2.50 V − 0.6 V = 1.9 V,, so the transistors
are in the active region.

For M3, we have ���� = ���� = −2.50 V, and for M4, we have ���� = ���� = −2.50 V .
With ܸ஽ௌ = ܸீௌ , the transistors are in the active region.

and �� = −��� = −5.00 V , i.e., ��� = 2.50 V . We

−2.50 � and
For M5, we have ��� = ��� = −2.50��
notice that ��� > ��� − �� = 2.50 V − 0.6 V = 1.9 V so the transistor is in the active region.

For M6, the negative feedback causes �� = �� = 0 V and with �� = ��� = 5.00 V, we find
ܸ஽ௌ = −5.00 V. We notice that |��� |> |��� | − |�� | = 2.50 V − 0.6 V = 1.9V so the transistor
is in the active region.

��==��
Also for M7, we have��� �=
�� = −2.50
0 V and and �� = −��� = −5.00 V , we find ��� = 5.00 V.
� with
We notice that ܸ஽ௌ > ܸீௌ െ ܸ௧ = 2.50ԛܸ െ 0.6ԛܸ = 1.9ԛܸ so the transistor is in the active region.

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CMOS ANALOG IC DESIGN Solution to Problem 1

Question 2:

The transconductance ݃௠ can be calculated from

2Ԝ‫ܫ‬஽
݃௠ =
|ܸீௌ െ ܸ௧ |

This gives ��� = 2 × 360 μA/(2.50 V − 0.6 V) = 0.38 mA/V.

For all other transistors, ݃௠ = 0.19 mA/V.

The output resistance ‫ݎ‬ௗ௦ can be calculated from

1 + ߣ|ܸ஽ௌ |
‫ݎ‬ௗ௦ =
ߣ‫ܫ‬஽

For M1 and M2, we find ‫ݎ‬ௗ௦ = ൫1 + 0.05 Vିଵ × 5 V൯/൫0.05 Vିଵ × 180 μA൯ = 139 kΩ.
For M3 and M4, we find ‫ݎ‬ௗ௦ = ൫1 + 0.05 Vିଵ × 2.5 V൯/൫0.05 Vିଵ × 180 μA൯ = 125 kΩ .
For M5, we find ‫ݎ‬ௗ௦ = ൫1 + 0.05 Vିଵ × 2.5 V൯/൫0.05 Vିଵ × 360 μA൯ = 62.5 kΩ.
For M6 and M7, we find ‫ݎ‬ௗ௦ = ൫1 + 0.05 Vିଵ × 5 V൯/൫0.05 Vିଵ × 180 μA൯ = 139 kΩ..

Question 3:
Taking the channel-length modulation into account, we have

1
‫ܫ‬஽ହ = ߤ‫ܥ‬௢௫ (ܹହ /‫ܮ‬ହ )(ܸ஻ െ ܸ௧ )ଶ (1 + ߣܸ஽ௌହ )
2

Using ܸ஽ௌହ = 2.5 V as found in Question 1, we may re-calculate ܸ஻ as follows:

2‫ܫ‬஽ହ
ܸ஻ = ඨ + ܸ௧
ߤ‫ܥ‬௢௫ (ܹହ /‫ܮ‬ହ )(1 + ߣܸ஽ௌହ )

2 × 0.36 mA
=ඨ + 0.6 V = 2.39 V
0.2 mA/V × (1 + 0.05 ܸ ିଵ × 2.5 V)
ଶ

With the new value of ܸ஻ and hence ܸீௌ, we also have new values for ܸ஽ௌ for the transistors,
so an additional iteration step may be performed with a new value of ܸ஽ௌହ. However, this
can only be expected to have very minor influence on ܸ஻, so we refrain from an additional
iteration step and proceed with LTspice simulations.

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83
CMOS ANALOG IC DESIGN Solution to Problem 1

The following figure shows an LTspice schematic for the circuit. For the transistors, we have
selected the geometries and the parameter ‘Kp’ such that ���� (�/�) = 100 μA/V � for both
the NMOS transistors and the PMOS transistors (except M5 where ���� (�/�) = 200 μA/V � ).
The value of ‘Kp’ for the NMOS transistors has been specified to be 4 times as large as the
value for the PMOS transistors, reflecting a typical ratio of �� /�� ≃ 4. Consequently, the
channel widths of the PMOS transistors M3, M4 and M6 are 4 times the channel widths
of the NMOS transistors M1, M2 and M7. For all transistors, a channel length of 5 µm has
been selected. Both transistor models without the channel-length modulation and with the
channel-length modulation are included in the schematic.

When running a ‘.op’ simulation with the models without channel-length modulation and a
value of 2.50 V for ܸ஻ as found in Question 1, the error log file returns the following results.

Error log file

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84
CMOS ANALOG IC DESIGN Solution to Problem 1

We notice a very good match to the calculated values for drain-source voltages, gate-source
voltages, drain currents and transconductances. However, with ߣ = 0, the small-signal
output conductances are infinite and cannot be found from this simulation. Repeating
the simulation with ߣ = 0.05 V ିଵ and ܸ஻ = 2.39 V as found in Question 3, we find the
following error log file.

Error log file

We notice that the bias currents, especially for M6 and M7, are somewhat larger than the
calculated values due to the larger values of drain-source voltage. Also, the gate-source voltages
are slightly smaller than the value of 2.5 V found in Question 1. This causes somewhat
larger values of the transconductances and slightly smaller values of the output resistances.

Notice that the error log file does not show ‫ݎ‬ௗ௦ but instead shows Gds = 1/‫ݎ‬ௗ௦.

Question 4:
The loop gain is ‫ܣ = ܮ‬ଵ ‫ܣ‬ଶ ߚ where �� = ���� (���� � ���� ) is the gain in the differential
stage, �� = ���� ������ ∥ ���� ∥ (�� + �� )� is the gain in the common-source stage (which
is loaded by the series connection of ܴଵ and ܴଶ) and ߚ = ܴଵ /(ܴଵ + ܴଶ ) is the voltage-
divider ratio between ܴଵ and ܴଶ. Thus

��
� = �� = ��� (���� ∥ ���� )��� ����� ∥ ���� ∥ (�� + �� )� � �
�� + ��
��� ��� ��
=� �� � � �
���� + ���� ���� + ���� + (�� + �� )�� �� + ��

Inserting the calculated values for the small-signal parameters, we find

0.19 mA/V 0.19 mA/V 2

�=� �� �� �
(139 kΩ) + (125 kΩ)
�� �� (139 kΩ) + (139 kΩ) + (12 kΩ)
�� �� �� 12
= 12.5 × 1.96 × 0.167 V/V = 4.08 V

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85
CMOS ANALOG IC DESIGN Solution to Problem 1

With the simulated small-signal parameters taking the channel-length modulation into
account, we find

0.213 mA/V 0.224 mA/V 2

�=� �� �� �
7.30 μA/V + 8.12 μA/V 8.03 μA/V + 8.01 μA/V + (12 kΩ)�� 12
= 13.81 × 2.25 × 0.167 V/V = 5.19 V/V

Alternatively, the loop gain may be simulated using a ‘.tf ’ simulation as shown in the following
schematic. The loop gain is found as � = −v(Vf)/Vt = 5.09416 V/V. The small difference
between this result and the result calculated above can be attributed to the rounding off of
the values of the small-signal parameters in the error log file.

Question 5:
The feedback factor is the voltage-divider ratio between ܴଵ and ܴଶ, i.e., ߚ = ܴଵ /(ܴଵ + ܴଶ ) =
2 kΩ/(2 kΩ + 10 kΩ) = 0.167 V/V.
With a loop gain of ‫ = ܮ‬4.08 V/V , we find ‫ܮ = ܣ‬/ߚ = 4.08/0.167 = 24.4 V/V.
Using the simulated value of the loop gain, we find ‫ܮ = ܣ‬/ߚ = 5.09416/0.167 = 30.6 V/V.

Question 6:
Using the calculated values of ‫ ܣ‬and ‫ܮ‬, we find a closed-loop gain of

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86
CMOS ANALOG IC DESIGN Solution to Problem 1

‫ܣ‬஼௅ = ‫ܣ‬/(1 + ߚ‫ = )ܣ‬24.4/(1 + 0.167 × 24.4) = 4.82 V/V.

With the simulated values of ‫ ܣ‬and ‫ܮ‬, we find ‫ܣ‬஼௅ = 5.02 V/V.

The output resistance is calculated from ‫ݎ‬௢௨௧஼௅ = ‫ݎ‬௢௨௧ /(1 + ߚ‫ )ܣ‬where ‫ݎ‬௢௨௧ is the output
resistance of the ‫ܣ‬-circuit, i.e., ���� ∥ ���� ∥ (�� + �� ).

Inserting the calculated values of the small-signal parameters, we find:

������ = 10.3 kΩ/(1 + 4.1) = 2.02 kΩ.

Inserting the simulated values of the small-signal parameters, we find:

������ = 10.1 kΩ/(1 + 5.1) = 1.66 kΩ .

Gain and output resistance may also be simulated from the LTspice schematic from Question
3 using the simulation directive ‘.tf v(Vo) Vin’.
From the output file, we find ‫ܣ‬஼௅ = 5.03 V/V and ������ = 1.66 kΩ .

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87
CMOS ANALOG IC DESIGN Solution to Problem 2

SOLUTION TO PROBLEM 2

Question 1:
For dc voltages, the amplifier is a voltage follower since ‫ܥ‬ଵ can be considered an open circuit.
Hence, the output voltage is �� = −�off = −10 mV.

Question 2:
With an ideal opamp, we find the closed-loop gain as ‫ܣ‬஼௅ = (ܼଵ + ܼଶ )/ܼଵ where ܼଵ = ܴଵ +
(‫ܥݏ‬ଵଵ))ିଵ
(‫ܥݏ‬ ିଵ
and
and = ܴܴଶଶ,,,i.e.
and ܼܼଶଶ = i.e.
i.e.,

ܸ௢ ܴଶ + ܴଵ + (‫ܥݏ‬ଵ )ିଵ 1 + ‫ܴ(ݏ‬ଵ + ܴଶ )‫ܥ‬ଵ

‫ܣ‬஼௅ = = =
ܸ௜௡ ܴଵ + (‫ܥݏ‬ଵ )ିଵ 1 + ‫ܴݏ‬ଵ ‫ܥ‬ଵ

From this, we find a pole at the frequency �� = (2��� �� )�� = (2 × � × 500 nF × 2 kΩ)�� =
��
159 Hz and a zero at the frequency �� = �2��� (�� + �� )� = �2 × � × 500 nF × (2 kΩ +
��
10 kΩ)� = 26.5 Hz..

The high-frequency gain is � = (�� + �� )/�� = 6 V/V ∼ 15.6 dB.

A Bode plot (piecewise-linear approximation) is sketched below.

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88
CMOS ANALOG IC DESIGN Solution to Problem 2

Question 3:
By inspection of the circuit, we see that at midband frequencies where (2Ɏ݂‫ܥ‬ଵ )ିଵ ‫ܴ ا‬ଵ
and (2Ɏ݂‫ܥ‬ଶ )ିଵ ‫ܴ ب‬ଶ , ‫ܥܥ‬ଵଵ can be treated as a short circuit and ‫ܥ‬ଶ can be treated as an open
circuit. Thus, the gain is ܸ௢ /ܸ௜௡ = 1 + ܴଶ /ܴଵ . With a desired passband gain of 20 dB or
10 V/V, we get �� = 9��� = 9 × 500 Ω = 4.5 kΩ.

By inspection, we also see that at very low frequencies and at very high frequencies the gain
approaches unity. This implies that the filter has two poles ݂௣௟ and ݂௣௛ , defining the −3 dB
lower passband edge and higher passband edge, respectively. Also the filter has two zeros, one at
݂௭௟ = ݂௣௟ /10 and one at ݂௭௛ × 10. The lower pole is determined by ‫ܥ‬ଵ and is ݂௣௟ = (2ߨ‫ܥ‬ଵ ܴଵ )ିଵ
��
(compare to Question 2). From this we get �� = �2���� �� � = (2 × � × 100 Hz × 500 Ω)�� =
3.18 μF.

The frequency response at high frequencies is determined by ‫ܥ‬ଶ with ‫ܥ‬ଵ treated as a short
circuit. This gives

��
���� �� + �� ∥ (��� )�� � + �(�� ∥ �� )�� �
= =
��� �� � + (�� �� )��
ିଵ
From this, we find the pole frequency ݂௣௛ = (2ߨ‫ܥ‬ଶ ܴଶ )ିଵ , so ‫ܥ‬ଶ = ൫2ߨ݂௣௛ ܴଶ ൯ = (2 × ߨ ×
10 kHz × 4.5 kΩ)�� = 3.54 nF .

Question 4:
A Bode plot showing the bandpass filter with a passband gain of 20 dB, a lower −3 dB
frequency of 100 Hz and a higher −3 dB frequency of 10 kHz is shown below. The stopband
gain is 0 dB.

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89
CMOS ANALOG IC DESIGN Solution to Problem 2

The frequency response can be verified using LTspice. The following figure shows an LTspice
schematic where the opamp has been modeled by a voltage-controlled voltage source with
a gain of 106. The similarity between the simulated frequency response and the Bode plot
above is apparent.

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90
CMOS ANALOG IC DESIGN Solution to Problem 3

SOLUTION TO PROBLEM 3

Question 1:
Neglecting the channel-length modulation, we have from the Shichman-Hodges model

1
‫ܫ‬஽ = ߤ‫ܥ‬௢௫ (ܹ/‫ீܸ()ܮ‬ௌ െ ܸ௧ )ଶ
2

Transistors M1 and M2 are identical and have the same quiescent current ‫ܫ‬஽ = ‫ܫ‬஻ଵ = ‫ܫ‬஻ଶ =
0.25 mA. Assuming that both transistors are in the active region, they also have the same
gate-source voltage given by

2‫ܫ‬஽ 2 × 0.25 mA
ܸீௌ = ඨ + ܸ௧ = ඨ + 0.6 V = 1.307 V
ߤ௡ ‫ܥ‬௢௫ (ܹ/‫)ܮ‬ 1 mA/Vଶ
From this, we find:

��� = ����� − ��� = 2.0 V − 1.307 V = 0.693 V

For M1, we have ݅஽ଵ = ‫ܫ‬஻ଷ + ݅ோ (where ݅ோ = (ܸ஽஽ െ ‫ݒ‬஽ଵ )/ܴ is the current in ܴ) and
��� = ��� − ݅ூே . As ݅஽ଵ = ݅ௌଵ , we find

݅ோ = (ܸ஽஽ െ ‫ݒ‬஽ଵ )/ܴ = ‫ܫ‬஻ଵ െ ‫ܫ‬஻ଷ െ ݅ூே ֜ ‫ݒ‬஽ଵ = ܸ஽஽ െ ܴ(‫ܫ‬஻ଵ െ ‫ܫ‬஻ଷ െ ݅ூே )

For a quiescent value of ‫ܫ‬ூே = 0, we find a quiescent value of

��� = ��� − �(��� − ��� ) = 5.0 V − 30 kΩ × (0.25 mA − 0.20 mA) = 3.5 V

Thus, ܸ஽ଵ > ܸீଵ െ ܸ௧ = 1.4 V (implying ܸ஽ௌଵ > ܸீௌଵ െ ܸ௧ ), so M1 is in the active region.

The quiescent value of the output voltage is �� = ��� − ��� = ��� − ��� = 3.5 V − 1.307 V =
2.193 V.

For M2, the drain voltage is ܸ஽ଶ = ܸ஽஽ = 5.0 V and the gate voltage is ܸீଶ = ܸ஽ଵ = 3.5 V ,
so ܸ஽ଶ > ܸீଶ െ ܸ௧ = 2.6 V, i.e., M2 is in the active region.

Question 2:
Taking the channel-length modulation into account, we have

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91
CMOS ANALOG IC DESIGN Solution to Problem 3

1
‫ܫ‬஽ = ߤ௡ ‫ܥ‬௢௫ (ܹ/‫ீܸ()ܮ‬ௌ െ ܸ௧ )ଶ (1 + ߣܸ஽ௌ )
2

from which we find

2‫ܫ‬஽
ܸீௌ = ඨ + ܸ௧
ߤ௡ ‫ܥ‬௢௫ (ܹ/‫()ܮ‬1 + ߣܸ஽ௌ )

Assuming that the channel-length modulation has only a minor impact on the values of
ܸ஽ௌ found in Question 1, we find ���� = ��� − ��� ≃ 3.5 V − 0.693 V = 2.807 V and
���� = ��� − �� = 5.0 V − 2.193 V = 2.807 V.

This results in

2 × 0.25 mA
ܸீௌଵ = ܸீௌଶ = ඨ + 0.6 V = 1.262 V
1 mA/Vଶ × ൫1 + 0.05 Vିଵ × 2.807 V൯
With this value of ܸீௌ , we find ��� = ����� − ��� = 2.0 V − 1.262 V = 0.738 V and ܸை =
��� − ��� = 3.5 V − 1.262 V = 2.238 V.

These results are fairly close to the approximate results from Question 1, so no further
iteration (with new values of ܸ஽ௌ) is needed.

Alternatively, the circuit may be simulated using LTspice. For the transistors, we use the
model directive ‘.model NMOS-SH nmos (Kp=100u Vto=0.6 lambda=0.05)’ and ܹ = 10 μm
and ‫ = ܮ‬1 μm , corresponding to ߤ௡ ‫ܥ‬௢௫ (ܹ/‫ = )ܮ‬1 mA/Vଶ .

The LTspice schematic is shown below.

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92
CMOS ANALOG IC DESIGN Solution to Problem 3

Running a ‘.op’ simulation, we find ܸூே = 0.737 V and ܸை = 2.237 V, both results matching
the analytically calculated values very well.

In the LTspice schematic, also a ‘.model’ directive with ߣ = 0 is shown (as a comment).
Running the ‘.op’ simulation with this model, the results from Question 1 may be verified.

Question 3:
The following figure shows a small-signal diagram of the amplifier. This is achieved by
replacing the transistors with their small-signal models and resetting the supply voltage, the
bias voltage and the bias current sources. The supply voltage and the bias voltage are replaced
by short circuits and the bias current sources are replaced by open circuits, i.e., removed.

The small-signal parameters included in the diagram are:

��� = ��� = 2��� /(��� − �� ) = 2 × 0.25 mA/(1.262 V − 0.6 V) = 0.755 mA/V

and ݃ௗ௦ଵ = ݃ௗ௦ଶ = (ߣ/2)ߤ௡ ‫ܥ‬௢௫ (ܹ/‫ீܸ()ܮ‬ௌ െ ܸ௧ )ଶ = ൫0.05 Vିଵ /2൯ × 1 mA/Vଶ ×
(1.262 V − 0.6 V)� = 10.96 μA/V, corresponding to ���� = ���� = 91.3 kΩ .

These results may also be verified from the error log file from the LTspice simulation.

Question 4:
From the small-signal diagram, a node equation at the output gives
݃௠ଶ ‫ݎ‬ௗ௦ଶ
݃௠ଶ ‫ݒ‬௚௦ଶ = ‫ݒ‬௢ /‫ݎ‬ௗ௦ଶ ֜ ‫ݒ‬௢ = ݃௠ଶ ‫ݒ‬௚௦ଶ ‫ݎ‬ௗ௦ଶ = ݃௠ଶ ൫‫ݒ‬௚ଶ െ ‫ݒ‬௢ ൯‫ݎ‬ௗ௦ଶ ֜ ‫ݒ‬௢ = ൬ ൰‫ݒ‬
1 + ݃௠ଶ ‫ݎ‬ௗ௦ଶ ௚ଶ

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93
CMOS ANALOG IC DESIGN Solution to Problem 3

Also, we see that the current iin flows through ܴ, so from Ohm’s law we find ‫ݒ‬௚ଶ = ܴ݅௜௡ .

From these expressions, we find the transresistance ܴ௧:

��� ����
�� = � � �����
1 + ��� ����
�� ��� ���� 0.755 mA/V × 91.4 kΩ
� �� = =� �� = � � × 30 kΩ = 29.6 kΩ
��� 1 + ��� ���� 1 + 0.755 mA/V × 91.4 kΩ

The input resistance ‫ݎ‬௜௡ is found from a node equation at the input:

��� = ���� ���� + ���� � ��� �/���� = ��� ��� + (��� � ���� )/����
��� ���� + � 91.3 kΩ + 30 kΩ
� ��� = = = = 1.735 kΩ
��� ��� ���� + 1 0.755 mA/V × 91.3 kΩ + 1

The output resistance ‫ݎ‬௢௨௧ is found by applying a voltage ‫ݒ‬௫ to the output with the input
current ݅௜௡ = 0 and calculating the current ݅௫ flowing into the output. With ݅௜௡ = 0, we
find ‫ݒ‬௚ଶ = 0, resulting in:

�� ���� 91.3 kΩ
�� = ��� �� + �� /���� � ���� = = = = 1.306 kΩ
�� 1 + ��� ���� 1 + 0.755 mA/V × 91.3 kΩ

Alternatively, the small-signal transresistance, input resistance and output resistance may
found by LTspice using a ‘.tf ’ simulation shown as a comment in the LTspice schematic
from Question 2. From the output file, we find a transresistance of 29.6 kΩ, an input
resistance of 1737 Ω and an output resistance of 1307 Ω, all results matching the analytically
calculated values very well.

Question 5:
With a positive input current, the current through ܴ decreases (with the same amount as
the change in input current), so the drain voltage of M1 increases. In order to have a voltage
across ‫ܫ‬஻ଷ of at least 0.2 V, the drain voltage of M1 cannot be increased to more than 4.8
V. Since the quiescent value of the drain voltage is 3.5 V, this corresponds to a change in
the voltage across ܴ of 1.3 V, corresponding to a change in the current through ܴ (and,
hence, in the input current) of 1.3 V/30 kΩ = 43.3 μA . Thus, the maximum (positive) value
of the input current is 43.3 μA.

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94
CMOS ANALOG IC DESIGN Solution to Problem 3

With a negative input current, the current through ܴ increases (with the same amount as
the change in input current), so the drain voltage of M1 decreases. In order to keep M1 in
the active region, the drain voltage of M1 must not fall below the gate voltage minus the
threshold voltage, i.e., 2 V − 0.6 V = 1.4 V .

Also, the gate voltage of M2 (equal to the drain voltage of M1) must not fall below the value
required to maintain a voltage of at least 0.2 V across ‫ܫ‬஻ଶ. With the source voltage of M2
equal to 0.2 V, the drain-source voltage of M2 is 4.8 V and we find a gate-source voltage of

2‫ܫ‬஽ଶ 2 × 0.25 mA
‫ீݒ‬ௌଶ = ඨ + ܸ௧ = ඨ + 0.6 V
ߤ௡ ‫ܥ‬௢௫ (ܹ/‫()ܮ‬1 + ߣܸ஽ௌଶ ) 1 mA/V × (1 + 0.05 V ିଵ × 4.8 V)
ଶ

= 1.235 V

This implies that the drain voltage of M1 must not fall below ܸீௌଶ + 0.2 V = 1.435 V ,
corresponding to a change in the voltage across ܴ of 3.50 V − 1.435 V = 2.065 V. This
corresponds to a change in the current through ܴ (and, hence, in the input current) of
2.065 V/30 kΩ = 68.8 μA. Thus, the minimum (negative) value of the input current is
−68.8 μA.

The limitations described above may also be illustrated by a ‘.dc’ simulation in LTspice. With
the ‘.dc’ simulation directive shown as a comment in the LTspice schematic from Question
2, we can obtain a plot showing the voltages across the current sources ‫ܫ‬஻ଵ , ‫ܫ‬஻ଶ and ‫ܫ‬஻ଷ
and also the drain voltage of M1 which must be larger than the gate voltage minus the
threshold voltage to keep M1 in the active region. Transistor M2 has a drain voltage which
is larger than the gate voltage, so it is in the active region. The following figure shows the
plot from the ‘.dc’ simulation.

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95
CMOS ANALOG IC DESIGN Solution to Problem 3

The green trace shows the voltage across ‫ܫ‬஻ଷ. For this to be larger than 0.2 V, ݅ூே must be
smaller than 43.3 µA.

The cyan trace shows ‫ݒ‬஽ଵ which must be larger ‫ீݒ‬ଵ െ ܸ௧ = 1.4 V for M1 to be in the active
region. We see that this requires ݅ூே to be larger than −70 µA.

The red trace shows the voltage across ‫ܫ‬஻ଶ. For this to be larger than 0.2 V, ݅ூே must be
larger than −68.8 µA.

The blue trace shows the voltage across ‫ܫ‬஻ଵ. We notice that this is larger than 0.2 V for the
relevant range of ݅ூே.

From the limitations found from the simulation, we find −68.8 μA ≤ ��� ≤ 43.3 μA. This
is the same range as found from the analytically calculated limits.

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96
CMOS ANALOG IC DESIGN Solution to Problem 4

SOLUTION TO PROBLEM 4

Question 1:
For symmetry reasons, the bias currents in M1 and M2 are equal, and ‫ܫ‬஽ଵ = ‫ܫ‬஽ଷ and ‫ܫ‬஽ଶ = ‫ܫ‬஽ସ .
Also, M6 and M3/M4 form current mirrors ensuring ‫ܫ‬஽ଷ = ‫ܫ‬஽ସ = ‫ܫ‬஽଺ when the channel-length
modulation is neglected. The bias current of M7 is ‫ܫ‬஽଻ = ‫ܫ‬஽ଵ + ‫ܫ‬஽ଶ = 0.4 mA and with the
scaling factor between M5 and M7 (forming a current mirror), we find ‫ܫ‬஽ହ = ‫ܫ‬஽଻ /2 = 0.2 mA
when the channel-length modulation is neglected.

Neglecting the channel-length modulation, we have from the Shichman-Hodges model

1
‫ܫ‬஽ = ߤ‫ܥ‬௢௫ (ܹ/‫ீܸ()ܮ‬ௌ െ ܸ௧ )ଶ
2

For the NMOS transistors, we find

2‫ܫ‬஽ 2 × 0.2 mA
ܸீௌ = ܸ௧ + ඨ = 0.5 V + ඨ = 0.947 V
ߤ௡ ‫ܥ‬௢௫ (ܹ/‫)ܮ‬ 2 mA/V ଶ

For the PMOS transistors, we find

2�� 2 × 0.2 mA
��� = �� − � = −0.5 V − � = −0.947 V
�� ��� (�/�) 2 mA/V �

The current in ܴ஻ே is equal to ‫ܫ‬஽ହ = 0.2 mA and the voltage across
��� is ��� − ���� = 1.5 V − 0.947 V = 0.553 V, so ��� = 0.553 V/0.2 mA = 2.765 kΩ.

Likewise, the current in ܴ஻௉ is equal to ‫ܫ‬஽଺ = 0.2 mA and the voltage across ܴ஻௉ is ��� −
|���� | = 1.5 V − 0.947 V = 0.553 V , so ��� = 0.553 V/0.2 mA = 2.765 kΩ.

Question 2:
For the PMOS transistors M3 and M4, the drain voltage is specified to be 0 V and the source
voltage is the supply voltage ܸ஽஽ . Thus, we have |ܸ஽ௌ | = ܸ஽஽ = 1.5 V and ��� = −0.947 V,
so |ܸ஽ௌ | > |ܸீௌ െ ܸ௧ | = 0.447 V,, implying that the transistors are in the active region.

For M6, we have ܸ஽଺ = ܸீ଺ , so |ܸ஽ௌ଺ | > |ܸீௌ଺ െ ܸ௧ |, implying that M6 is in the active region.

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CMOS ANALOG IC DESIGN Solution to Problem 4

For M1, M2 and M5, we have ܸ஽ = ܸீ , so ܸ஽ௌ > ܸீௌ െ ܸ௧ , implying that the transistors are
in the active region.

For M7, we have ܸீௌ଻ = 0.947 V and ܸ஽ௌ଻ = ܸௌௌ െ ܸீௌଵ = 0.553 V , so ܸ஽ௌ଻ > ܸீௌ଻ െ ܸ௧ =
0.447 V, implying that M7 is in the active region.

Question 3:
The following figure shows a small-signal diagram of the amplifier. This is achieved by
replacing the transistors with their small-signal models and resetting the supply voltages.
Also, for the differential half-circuit, only ܼ௅ /2 = ܴ௅ /2 is connected as the load to the
half-circuit, and the source node of M1 is connected to ground, see ‘CMOS Analog IC
Design: Fundamentals’.

Using the bias point found in Questions 1 and 2, the small-signal parameters are as follows:

��� = 2��� /(���� � �� ) = 0.4 mA/0.447 V = 0.895 mA/V

���� = (1 + ����� )/(���� ) = (1 + 0.1 V �� × 0.947 V)/(0.1 V �� × 0.2 mA) = 54.7 kΩ
���� = (1 + ����� )/(���� ) = (1 + 0.1 V �� × 1.5 V)/(0.1 V �� × 0.2 mA) = 57.5 kΩ
���� � ���� = 28.0 kΩ
���� + ���� = 0.2 pF
�� /2 = 5 kΩ

Question 4:
With ܼ௅ ൌ ܴ௅ ൌ ͳͲȳ , we have ܼ௅ Ȁʹ ൌ ܴ௅ Ȁʹ ൌ ͷȳ and ሺሺܴ௅ Ȁʹሻ ‫ݎ צ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଷ ሻ ൌ ͶǤʹͶȳ.

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98
CMOS ANALOG IC DESIGN Solution to Problem 4

The low-frequency gain is ‫ܣ‬ௗ ൌ െ݃௠ଵ ൫ሺܴ௅ Ȁʹሻ ‫ݎ צ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଷ ൯ ൌ െͲǤͺͻͷȀ ൈ ͶǤʹͶȳ ൌ
െ͵ǤͺͲȀ (equivalent to 11.6 dB).

Question 5:
Whenn ܼ௅ is a parallel connection of ‫ܮ‬௅ and ‫ܥ‬௅ , we find ܼ௅ Ȁʹ as a parallel connection
of a capacitor with a value of ʹ‫ܥ‬௅ and an inductor with a value of ‫ܮ‬௅ Ȁʹ as shown in the
following small-signal diagram where the capacitor ʹ‫ܥ‬௅ is added to the transistor drain-
bulk capacitances.

Denoting ‫ ˆˆ‡ܮ‬ൌ ‫ܮ‬௅ Ȁʹ and ‫ ˆˆ‡ܥ‬ൌ ‫ܥ‬ௗ௕ଵ ൅ ‫ܥ‬ௗ௕ଷ ൅ ʹ‫ܥ‬௅ , we find the resonance frequency

ͳ ͳ ͳ ͳ ͳ ͳ
݂଴ ൌ ඨ ൌ ඨ ൌ ඨ ൌ ͳǤͳͻ œǤ
ʹԜɎ ‫ ˆˆ‡ܮ‬Ԝ‫ʹ ˆˆ‡ܥ‬ԜɎ ሺ‫ܥ‬ௗ௕ଵ ൅ ‫ܥ‬ௗ௕ଷ ൅ ʹ‫ܥ‬௅ ሻ‫ܮ‬௅ Ȁʹ ʹԜɎ ͳǤͺ’ ൈ ͳͲ

With ܴeff = (‫ݎ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଷ ), the quality factor is

‡ˆˆ ‫ܥ‬ௗ௕ଵ ൅ ‫ܥ‬ௗ௕ଷ ൅ ʹ‫ܥ‬௅ ͳǤͺ pF

ܳ ൌ  ‡ˆˆ ඨ ൌ ሺ‫ݎ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଷ ሻඨ ൌ ʹͺǤͲ kΩඨ ൌ ͵͹͸Ǥ
‡ˆˆ ‫ܮ‬௅ Ȁʹ ͳͲ nH

Question 6:
The maximum passband gain occurs at the resonance frequency where the impedance of
the parallel connection of the capacitance ‫ܥ‬ௗ௕ଵ ൅ ‫ܥ‬ௗ௕ଷ ൅ ʹ‫ܥ‬௅ and the inductance ‫ܮ‬௅ Ȁʹ is
infinite. The maximum gain is

ȁ‫ܣ‬ௗ ȁmax ൌ ݃௠ଵ ሺ‫ݎ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଷ ሻ ൌ ͲǤͺͻͷ mA/V ൈ ʹͺǤͲ kΩ ൌ ʹͷǤͳ V/V ‫ʹ ׽‬ͺǤͲ dBǤ

The −3 dB bandwidth is BW ൌ ݂଴ Ȁܳ ൌ ͵Ǥͳ͸ MHz.

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99
CMOS ANALOG IC DESIGN Solution to Problem 4

Question 7:
Shown below is an LTspice schematic for the circuit. For the transistors, we have selected
the geometries and the parameter ‘Kp’ such that ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ ൌ ʹǤͲͲȀ ଶ for transistors
M1 - M6 and ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ ൌ ͶǤͲͲȀ ଶ for M7. The resistor ܴ஻௉ has been specified as a
parameter ‘RBP’.

We may start by running a ‘.op’ simulation with ܴ஻௉ ൌ ʹǤ͹͸ͷȳ as found in Question 1.
From this, we find a bias point with ܸ஽ଵ ൌ ܸ஽ଶ ൌ ͲǤͻͳ. Although all transistors are in the
active region for this bias point, we may adjust the bias point to provide an output voltage
of ܸ஽ଵ ൌ ܸ஽ଶ ൌ Ͳ. This may be achieved by increasing the value of ܴ஻௉ . This reduces the
current in M6, causing transistors M3 and M4 to provide a weaker pull-up for the output
nodes. In order to find the new value of ܴ஻௉ , we step the parameter ‘RBP’ through an
interval from 2.5 kΩ to 3.5 kΩ by the ‘.step’ directive shown in the schematic. The ‘.op’
simulation now results in a plot window where we can display ܸ஽ଵ versus ܴ஻௉ as shown
below. From the plot, we can find the value of ܴ஻௉ resulting in ܸ஽ଵ ൌ Ͳ. Alternatively,
we may use the ‘.meas’ directive shown in the LTspice schematic. From the error log file,
we find ܴ஻௉ ൌ ͵ǤͳͲ͸͸͵ȳ.

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100
CMOS ANALOG IC DESIGN Solution to Problem 4

With this value of ܴ஻௉ , we re-run the ‘.op’ simulation with the ‘.step’ directive changed
into a comment in order to find the bias point and the small-signal parameters from the
error log file. From the error log file, we find the following results:

Error log file

We notice that the channel-length modulation causes the gate-source voltages to be slightly
smaller than the values found when neglecting the channel-length modulation. Hence, ݃௠ଵ is
slightly larger than the calculated value. The values of ‫ݎ‬ௗ௦ଵ and ‫ݎ‬ௗ௦ଷ are 55.2 kΩ and 58.1 kΩ,
respectively, i.e., slightly larger than the calculated values. Thus, we would expect the simulated
low-frequency gain to be slightly larger than the value calculated in Question 4. With the
simulated small-signal parameters, we find ‫ܣ‬ௗ ൌ െ݃௠ଵ ሺሺܴ௅ Ȁʹሻ ‫ݎ צ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଷ ሻ ൌ െͲǤͻ͵ͳȀ ൈ
ͶǤʹͷȳ ൌ െ͵Ǥͻ͸Ȁ (equivalent to 12.0 dB). The gain may be simulated directly by the
‘.tf ’ simulation shown as a comment in the LTspice schematic. From the output file, we
find ‫ܣ‬ௗ ൌ െ͵ǤͻͷȀ.

For verifying the results for Questions 5 and 6, we modify the LTspice schematic as shown
in the following figure. The load resistor is replaced by the parallel connection of ‫ܮ‬௅ and
‫ܥ‬௅ and an ac amplitude of 1 V is specified for ܸ௜௡ . The simulation directive is changed
to a ‘.ac’ directive, and because the circuit is a narrow-bandwidth filter, a large number
of points per octave is specified. Also three ‘.meas’ directives are included. The first one
finds the resonance frequency as the frequency where the phase of the output voltage

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CMOS ANALOG IC DESIGN Solution to Problem 4

ܸ௢ ሺ݆߱ሻ ൌ ܸௗଵ ሺ݆߱ሻ െ ܸௗଶ ሺ݆߱ሻ is 180° or ߨ. The second finds the maximum magnitude of
the gain and the third directive finds the −3 dB bandwidth. From the error log file, we find
a resonance frequency of 1.19 GHz, a maximum gain of 28.2 dB and a bandwidth of 3.3
MHz, all of which provide a good match to the analytically calculated results.

An alternative ‘.meas’ directive for finding the resonance frequency is ‘.meas fres when
mag(v(Vd1,Vd2))=peak’. Notice that both this directive and the directive for finding the
bandwidth use the result from the directive for finding the peak, so as the ‘.meas’ directives
are executed in the sequence in which they are inserted in the schematic, the directive for
finding the peak must be inserted first.

From the simulation, we can also obtain a plot of ܸ௢ ሺ݆߱ሻ as shown in the following figure.
The values of resonance frequency, gain and bandwidth may be found from a close-up of
this plot around the resonance frequency as also shown in the following figure.

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102
CMOS ANALOG IC DESIGN Solution to Problem 4

Question 8:
For simulating the circuit with a resistance ܴௌ ൌ ʹǤͷȳ in series with ‫ܮ‬௅ , we insert a resistor
with a value of ʹǤͷȳ in the previous LTspice schematic and run the ‘.ac’ simulation again.
This results in the output plots shown below.

From the close-up plot and from the error log file with the results of the ‘.meas’ directives,
we find a maximum gain of 11.1 dB ¾ 3.57 V/V and a −3 dB bandwidth of 23 MHz.

We notice that even a rather small series resistance has a very large impact on the performance
of the bandpass amplifier. The maximum gain is slightly smaller than the gain found with
a resistive load of 10 kΩ so for this circuit, a small series resistance of 2.5 Ω is equivalent
to a parallel resistance of about 10 kΩ.

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103
CMOS ANALOG IC DESIGN Solution to Problem 5

SOLUTION TO PROBLEM 5

Question 1:
The small-signal diagram is shown below. The current source ‫ܫ‬஻ is modeled by a resistor
‫ݎ‬௢஻ connected in parallel with the small-signal output resistance of M4. The output is
connected to a voltage source ‫ݒ‬ை which is delivering a current ݅ into the output of the
current mirror, i.e., the drain of M3. For details on how to create the small-signal diagram
from the schematic, you may turn to Appendix A in this book.

For finding the output resistance ‫ݎ‬௢௨௧, the input current ݅௜௡ is reset, i.e., ݅௜௡ ൌ Ͳ, and the
output resistance is found as ‫ݎ‬௢௨௧ ൌ ‫ݒ‬௢ Ȁ݅. With ݅௜௡ ൌ Ͳ, we also find ‫ݒ‬௜௡ ൌ Ͳ and ‫ݒ‬௚௦ଶ ൌ Ͳ.
Thus, also the voltage-controlled current source ݃௠ଶ ‫ݒ‬௚௦ଶ ൌ Ͳ and the current ݅ flows
through ‫ݎ‬ௗ௦ଶ , causing ‫ݒ‬௚௦ସ to be ‫ݒ‬௚௦ସ ൌ ‫ݒ‬௦ଷ ൌ ݅Ԝ‫ݎ‬ௗ௦ଶ .

We note that the current through ‫ݎ‬ௗ௦ଷ is ൫݅ െ ݃௠ଷ ‫ݒ‬௚௦ଷ ൯, so using Kirchhoff ’s voltage law
and Ohm’s law, we find

‫ݒ‬௢ ൌ ൫݅ െ ݃௠ଷ ‫ݒ‬௚௦ଷ ൯‫ݎ‬ௗ௦ଷ ൅ ݅Ԝ‫ݎ‬ௗ௦ଶ

where ‫ݒ‬௚௦ଷ ൌ ‫ݒ‬௚ଷ െ ‫ݒ‬௦ଷ ൌ െ݃௠ସ ‫ݒ‬௚௦ସ ሺ‫ݎ‬ௗ௦ସ ‫ݎ צ‬௢஻ ሻ െ ‫ݒ‬௦ଷ ൌ െ݅Ԝ‫ݎ‬ௗ௦ଶ ሺ݃௠ସ ሺ‫ݎ‬ௗ௦ସ ‫ݎ צ‬௢஻ ሻ ൅ ͳሻ.

Inserting in the expression for ‫ݒ‬ை, we find

‫ݒ‬௢ ൌ ൫݅ ൅ ݅Ԝ݃௠ଷ ‫ݎ‬ௗ௦ଶ ሺ݃௠ସ ሺ‫ݎ‬ௗ௦ସ ‫ݎ צ‬௢஻ ሻ ൅ ͳሻ൯‫ݎ‬ௗ௦ଷ ൅ ݅Ԝ‫ݎ‬ௗ௦ଶ

֜ ‫ݎ‬௢௨௧ ൌ ‫ݒ‬௢ Ȁ݅ ൌ ൫ͳ ൅ ݃௠ଷ ‫ݎ‬ௗ௦ଶ ሺ݃௠ସ ሺ‫ݎ‬ௗ௦ସ ‫ݎ צ‬௢஻ ሻ ൅ ͳሻ൯‫ݎ‬ௗ௦ଷ ൅ ‫ݎ‬ௗ௦ଶ

ൌ ‫ݎ‬ௗ௦ଶ ൅ ‫ݎ‬ௗ௦ଷ ൅ ‫ݎ‬ௗ௦ଶ ݃௠ଷ ‫ݎ‬ௗ௦ଷ ሺ݃௠ସ ሺ‫ݎ‬ௗ௦ସ ‫ݎ צ‬௢஻ ሻ ൅ ͳሻ

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104
CMOS ANALOG IC DESIGN Solution to Problem 5

With all transistors in the active region, we would normally find ‫ݎ‬ௗ௦ଶ ݃௠ଷ ‫ݎ‬ௗ௦ଷ ‫ݎ ب‬ௗ௦ଷ ൅ ‫ݎ‬ௗ௦ଶ
and ݃௠ସ ሺ‫ݎ‬ௗ௦ସ ‫ݎ צ‬௢஻ ሻ ‫ͳ ب‬ǡ so the expression for may be simplified to ‫ݎ‬௢௨௧ ؄
‫ݎ‬ௗ௦ଶ ݃௠ଷ ‫ݎ‬ௗ௦ଷ ݃௠ସ ሺ‫ݎ‬ௗ௦ସ ‫ݎ צ‬௢஻ ሻ.This may be interpreted as the output resistance ‫ݎ‬ௗ௦ଶ of the
current mirror output transistor M2 multiplied by the gain of the cascode transistor M3
and the gain of the amplifier stage M4.

Question 2:
For finding the numerical value of the output resistance, we need numerical values for ݃௠ଷ,
݃௠ସ , ‫ݎ‬ௗ௦ଶ, ‫ݎ‬ௗ௦ଷ and ‫ݎ‬ௗ௦ସ .

The transconductances ݃௠ଷ and ݃௠ସ can be calculated from

݃௠ ൌ ඥʹԜߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ‫ܫ‬஽ ሺͳ ൅ ߣܸ஽ௌ ሻ ؄ ඥʹԜߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ‫ܫ‬஽

where we assume ߣܸ஽ௌ ‫ ͳ ا‬.

With ‫ܫ‬஽ଷ ൌ ‫ܫ‬஽ଶ ؄ ‫ܫ‬ூே ൌ ͳͲͲɊ and ‫ܫ‬஽ସ ൌ ‫ܫ‬஻ ൌ ʹͷɊ , we find

݃௠ଷ ؄ ඥʹ ൈ ͳͺͲɊȀ ଶ ൈ ͳͲ ൈ ͳͲͲɊ ൌ ͲǤ͸ͲȀ

and

݃௠ସ ؄ ඥʹ ൈ ͳͺͲɊȀ ଶ ൈ ͳͲ ൈ ʹͷɊ ൌ ͲǤ͵ͲȀ

The output resistances ‫ݎ‬ௗ௦ଶ , ‫ݎ‬ௗ௦ଷ and ‫ݎ‬ௗ௦ସ can be calculated from

ͳ ൅ ߣܸ஽ௌ ͳ
‫ݎ‬ௗ௦ ൌ ؄
ߣ‫ܫ‬஽ ߣ‫ܫ‬஽

where we assume ߣܸ஽ௌ ‫ͳ ا‬.

With ‫ܫ‬஽ଷ ൌ ‫ܫ‬஽ଶ ؄ ‫ܫ‬ூே ൌ ͳͲͲɊ and ‫ܫ‬஽ସ ൌ ‫ܫ‬஻ ൌ ʹͷɊ, we find

ͳ
‫ݎ‬ௗ௦ଶ ؄ ‫ݎ‬ௗ௦ଷ ؄ ൌ ͳͲͲȳ
ͲǤͳ ିଵ ൈ ͲǤͳͲ

and

ͳ
‫ݎ‬ௗ௦ସ ؄ ൌ ͶͲͲȳ
ͲǤͳ ିଵ ൈ ͲǤͲʹͷ

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105
CMOS ANALOG IC DESIGN Solution to Problem 5

Inserting these values and ‫ݎ‬௢஻ ൌ ͶͲͲȳ in the expression for ‫ݎ‬௢௨௧ , we find

‫ݎ‬௢௨௧ ؄ ‫ݎ‬ௗ௦ଶ ݃௠ଷ ‫ݎ‬ௗ௦ଷ ݃௠ସ ሺ‫ݎ‬ௗ௦ସ ‫ݎ צ‬௢஻ ሻ

ൌ ͳͲͲȳ ൈ ͲǤ͸ͲȀ ൈ ͳͲͲȳ ൈ ͲǤ͵ͲȀ ൈ ሺͶͲͲȳ ‫ צ‬ͶͲͲȳሻ ൌ ͵͸Ͳȳ

Question 3:
For an NMOS transistor to be in the active region, we require ܸ஽ௌ ൒ ܸீௌ െ ܸ௧ ֜ ܸ஽ ൒ ܸீ െ ܸ௧ .

For M1, we have ܸ஽ଵ ൌ ܸீଵ , so ܸ஽ଵ ൐ ܸீଵ െ ܸ௧ , implying that M1 is in the active region.

For M4, we have ܸ஽ସ ൌ ܸீସ ൅ ܸீௌଷ , so ܸ஽ସ ൐ ܸீସ െ ܸ௧ , implying that M4 is in the active
region.

In order to investigate M2 and M3, we use the Shichman-Hodges transistor model to

find the gate-source voltages. With ߣܸ஽ௌ ‫ ͳ ا‬and the transistor in the active region, the
Shichman-Hodges model yields

ͳ
‫ܫ‬஽ ൌ ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻሺܸீௌ െ ܸ௧ ሻଶ ሺͳ ൅ ߣܸ஽ௌ ሻ
ʹ
ʹԜ‫ܫ‬஽ ʹԜ‫ܫ‬஽
֜ ܸீௌ ൌ ܸ௧ ൅ ඨ ؄ ܸ௧ ൅ ඨ
ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻሺͳ ൅ ߣܸ஽ௌ ሻ ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ

Introducing

ʹԜ‫ܫ‬஽
ܸ‡ˆˆ ൌ ܸீௌ െ ܸ௧ ൌ ඨ
ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ

we find

ʹ ൈ ͳͲͲɊ
ܸ‡ˆˆԜʹ ൌ ඨ ൌ ͲǤ͵͵͵
ͳͺͲɊȀ ଶ ൈ ͳͲ

and

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106
CMOS ANALOG IC DESIGN Solution to Problem 5

ʹ ൈ ʹͷɊ
ܸ‡ˆˆԜͶ ൌ ඨ ൌ ͲǤͳ͸͹
ͳͺͲɊȀ ଶ ൈ ͳͲ

For transistor M2, we find ܸீௌଶ ൌ ܸ௧ ൅ ܸ‡ˆˆԜʹ ൌ ͲǤͶ ൅ ͲǤ͵͵͵ ൌ ͲǤ͹͵͵ and ܸ஽ௌଶ ൌ ܸீௌସ ൌ
ܸ௧ ൅ ܸ‡ˆˆԜͶ ൌ ͲǤͶ ൅ ͲǤͳ͸͹ ൌ ͲǤͷ͸͹. Thus, ܸ஽ௌଶ ൌ ͲǤͷ͸͹ ൐ ܸீௌଶ െ ܸ௧ ൌ ܸ‡ˆˆԜʹ ൌ ͲǤ͵͵͵,,
so M2 is in the active region.

For transistor M3, we have ܸ‡ˆˆԜ͵ ൌ ܸ‡ˆˆԜʹ since ‫ܫ‬஽ଷ ൌ ‫ܫ‬஽ଶ and ܹଷ Ȁ‫ܮ‬ଷ ൌ ܹଶ Ȁ‫ܮ‬ଶ. Also,
ܸ஽ௌଷ ൌ ܸை െ ܸீௌସ ൌ ܸை െ ሺܸ௧ ൅ ܸ‡ˆˆԜͶ ሻ. Thus, for M3, we must require

ܸ஽ௌଷ ൒ ܸீௌଷ െ ܸ௧ ൌ ܸ‡ˆˆԜ͵

֜ ܸை െ ሺܸ௧ ൅ ܸ‡ˆˆԜͶ ሻ ൒ ܸ‡ˆˆԜ͵ ൌ ܸ‡ˆˆԜʹ
֜ ܸை ൒ ܸ௧ ൅ ܸ‡ˆˆԜͶ ൅ ܸ‡ˆˆԜʹ ൌ ͲǤͶ ൅ ͲǤͳ͸͹ ൅ ͲǤ͵͵͵ ൌ ͲǤͻͲ

Question 4:
The following figure shows the LTspice schematic for the current mirror. The bias current
source ‫ܫ‬஻ is modeled as a dc current source with a value of ʹͷɊ in parallel with a resistor
with a value of ͶͲͲȳ , representing the output resistance ‫ݎ‬௢஻ .

The output of the current mirror is connected to a voltage ܸை with a value of 1.3 V which
ensures that all transistors are in the active region, compare to Question 3.

We start by running a ‘.op’ simulation. From the output file, we find an output current
of ͻͺǤͷɊ, i.e., very close to the ideal value of ͳͲͲɊ. The difference is caused by the
different drain-source voltages for M1 and M2 with ܸ஽ௌଶ being smaller than ܸ஽ௌଵ .

We also notice that the drain current ‫ܫ‬஽ସ is somewhat larger than ʹͷɊ because the current
in the output resistor ‘Ro’ is added to the dc current ‘IB’.

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107
CMOS ANALOG IC DESIGN Solution to Problem 5

From the error log file, we may find the bias point for each transistor, and we also find the
small-signal parameters. The error log file is shown below.

Error log file

For finding the output resistance, we run the ‘.tf ’ simulation shown in the schematic. With
ܸ௢ as the source, the input resistance found by the ‘.tf ’ simulation is the output resistance
of the current mirror. From the output file, we find ‫ݎ‬௢௨௧ ൌ Ͷͻͷ MΩ . This is somewhat
larger than the value calculated in Question 2. The reason for this is the approximation
ͳ ൅ ߣܸ஽ௌ ؄ ͳ. This approximation causes the calculated values of transconductances and
output resistances to be somewhat smaller than the simulated values. With drain-source
voltages in the range of 0.5 V to 1.3 V, omitting the factor ሺͳ ൅ ߣܸ஽ௌ ሻǡ an average error
of about 7% is introduced in each of the calculated values of the small-signal parameters,
and since the factors are multiplied in the expression for ‫ݎ‬௢௨௧ , the total error is on the
order of 35%.

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108
CMOS ANALOG IC DESIGN Solution to Problem 5

From the error log file, we find ݃ௗ௦ଶ ൌ ͻǤ͵͵ɊȀ , ݃௠ଷ ൌ ͸ͳ͹ɊȀ , ݃ௗ௦ଷ ൌ ͻǤͳ͹ɊȀ,,
݃௠ସ ൌ ͵ʹ͹ɊȀ and ݃ௗ௦ଷ ൌ ʹǤ͵͵ɊȀ . Inserting these values and ͳȀ‫ݎ‬௢஻ ൌ ʹǤͷͲɊȀ
in the expression for ‫ݎ‬௢௨௧ , we find

‫ݎ‬௢௨௧ ؄ ‫ݎ‬ௗ௦ଶ ݃௠ଷ ‫ݎ‬ௗ௦ଷ ݃௠ସ ሺ‫ݎ‬ௗ௦ସ ‫ݎ צ‬௢஻ ሻ

ͳ ݃௠ଷ ݃௠ସ
ൌ Ԝ൬ ൰൬ ൰
݃ௗ௦ଶ ݃ௗ௦ଷ ݃ௗ௦ସ ൅ ͳȀ‫ݎ‬௢஻
ͳ ͸ͳ͹ ͵ʹ͹
ൌ ൈ ൈ ൌ Ͷͺͺȳ
ͻǤ͵͵ɊȀ ͻǤͳ͹ ʹǤ͵͵ ൅ ʹǤͷͲ

i.e., a very good match to the simulated value.

For finding the minimum output voltage with all transistors in the active region, we may
note that the minimum output voltage is the sum of the drain-source voltage of M2 and the
drain-source saturation voltage ܸ஽ௌ•ƒ– of M3. From the error log file, we find ܸ஽ௌଶ ൌ ͲǤͷ͸ͳ
and ܸ஽ௌsatଷ ൌ ͲǤ͵ͳͻ V,, so ܸைmin ൌ ͲǤͺͺ V. This is a close match to the calculated value. We
find a close match even when omitting the factor ሺͳ ൅ ߣܸ஽ௌ ሻ because in the calculation of
the gate-source voltages, the factor ሺͳ ൅ ߣܸ஽ௌ ሻ appears only as a factor ͳȀඥͳ ൅ ߣܸ஽ௌ , so it
has only a minor impact on the accuracy of the result. We do not have the accumulative
effect of several error factors as we observed for ‫ݎ‬௢௨௧ .

We may also find the minimum output voltage from a ‘.dc’ simulation. For M3 to be in
the active region, we require ܸ஽ௌଷ ൒ ܸீௌଷ െ ܸ௧ ֜ ܸ஽ଷ ൒ ܸீଷ െ ܸ௧ . As ܸ஽ଷ ൌ ܸை , we may
plot ‘V(vo)’ and ‘V(vg3)-0.4’ from the ‘.dc’ simulation and find the output voltage where
ܸை ൌ ܸீଷ െ ͲǤͶ. From the plot below, we find ܸை‹ ൌ ͲǤͺͺ͸. Alternatively, we may
use the ‘.meas’ directive shown in the LTspice schematic. From the error log file, we find
ܸை‹ ൌ ͲǤͺͺ͸.

We may observe in the plot below that ‘V(vg3)-0.4’ assumes unrealistically high values,
larger than ܸ஽஽ , for small values of ܸை . This happens because the ideal current source ‘IB’
used in the schematic may drive the gate voltage of M3 to a value larger than ܸ஽஽ . In a
real circuit implementation, ‫ܫ‬஻ and ‫ݎ‬௢஻ would be a PMOS transistor with an appropriate
dc gate voltage to provide the dc current ‫ܫ‬஻ , and this PMOS transistor would not be able
to drive the gate voltage of M3 to a value larger than ܸ஽஽ .

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109
CMOS ANALOG IC DESIGN Solution to Problem 5

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110
CMOS ANALOG IC DESIGN Solution to Problem 6

SOLUTION TO PROBLEM 6

Question 1:
The figure below shows the Bode plot. The amplitude plot starts at 100 dB corresponding
to a gain of ͳͲହ Ȁ at very low frequencies. The first breakpoint appears at ݂௣ଵ ൌ ͳͲଷ  œ
where the slope of the amplitude plot changes to −20 dB/dec. The second breakpoint appears
݂௣ଶ ൌ ͳͲହ  œ at where the slope of the amplitude plot changes to −40 dB/dec, and finally
at ݂௭ଵ ൌ ͳͲ଻  œ , the slope of the amplitude plot changes back to −20 dB/dec.

The phase plot (black plot) is the sum of the red, green and blue plots corresponding to
the phase shifts from ݂௣ଵ , ݂௣ଶ and ݂௭ଵ, respectively.

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111
CMOS ANALOG IC DESIGN Solution to Problem 6

Question 2:
From the Bode plot, we find a phase shift of −180° at ݂ ൌ ͳͲ଺  œ. Verifying, we find

݂ ݂ ݂
‫ܣס‬ௗ ሺ݆݂ሻ ൌ െ ƒ” –ƒ ൬ ൰ െ ƒ” –ƒ ቆ ቇ െ ƒ” –ƒ ቆ ቇ
݂௭ଵ ݂௣ଵ ݂௣ଶ
ͳͲ଺ ͳͲ଺ ͳͲ଺
ൌ െ ƒ” –ƒ ቆ ଻
ቇ െ ƒ” –ƒ ቆ ଷ ቇ െ ƒ” –ƒ ቆ ହ ቇ ൌ െͷǤ͹ι െ ͻͲι െ ͺͶǤ͵ι ൌ െͳͺͲι
ͳͲ ͳͲ ͳͲ

Alternatively, solve the equation ƒ” –ƒሺ݂ȀͳͲ଻ ሻ ൅ ƒ” –ƒሺ݂ȀͳͲଷ ሻ ൅ ƒ” –ƒሺ݂ȀͳͲହ ሻ

ሺ݂ȀͳͲହ ሻ ൌ ͳͺͲι to find ݂ ൌ ͳͲ଺  œ.

Question 3:
We find

ͳͲ଺
ͳͲହ ൈ ൬ͳ ൅ ݆ ൰ ͳͲହ ൈ ξͳ ൅ ͲǤͳଶ
ͳͲ଻
ȁୢሺŒ‫œ ଺Ͳͳڄ‬ሻȁൌተ ተ ൌ  ൌ ͳͲ ‫†Ͳʹ ׽‬
ͳͲ଺ ͳͲ଺ ξͳ ൅ ͳͲͲͲଶ ൈ ξͳ ൅ ͳͲଶ
൬ͳ ൅ ݆ ଷ ൰ ൬ͳ ൅ ݆ ହ ൰
ͳͲ ͳͲ

Question 4:
With ܴଵ ൌ ͳͲ kΩ and ܴଶ ൌ ʹ kΩ,, we find the feedback factor

ܴଶ ͳ
ߚൌ ൌ ൌ ͲǤͳ͸͹ ‫ ׽‬െͳͷǤ͸ dB
ܴଵ ൅ ܴଶ ͸

This gives a loop gain of ‫ ܮ‬ൌ ʹͲ dB െ ͳͷǤ͸ dB ൌ ͶǤͶ dB when the phase is shifted 180°,
i.e., the gain margin is െͶǤͶ dB, so the amplifier is not stable.

Question 5:
With the compensation inserted, the loop gain is

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112
CMOS ANALOG IC DESIGN Solution to Problem 6

݆݂
ͳ ͳͲହ ൬ͳ െ ଻ ൰
ͳͲ  œ
‫ܮ‬ሺ݆݂ሻ ൌ ߚ‫ܣ‬ௗ ሺ݆݂ሻ ൌ ൈ
͸ ݆݂ ݆݂
ቆͳ ൅ ᇱ ቇ ቆͳ ൅ ᇱ ቇ
݂௣ଵ ݂௣ଶ

ᇱ and ݂ ᇱ are the new locations of the poles.

where ݂௣ଵ ௣ଶ

ᇱ
Since we can assume ݂௣ଶ ‫ œ  ଻Ͳͳ ب‬, the expression above can be simplified to

ହ ݆݂
ͳ ͳͲ ൬ͳ െ ͳͲ଻  œ൰
‫ܮ‬ሺ݆݂ሻ ൌ ߚ‫ܣ‬ௗ ሺ݆݂ሻ ൌ ൈ
͸ ݆݂
ቆͳ ൅ ᇱ ቇ
݂௣ଵ

ᇱ ) to be ͳͲହ Ȁ͸ ‫׽‬
From this expression, we find the loop gain at very low frequencies (݂ ‫݂ ا‬௣ଵ
ͺͶǤͶͶ†. The loop gain amplitude response is sketched in the following figure.

At the frequency where the loop gain is 0 dB (the unity-gain frequency ݂௧), the phase shift from
ᇱ
݂௣ଵ is −90°.Therefore, at ݂௧, the phase shift from the zero must be −30° in order to give a phase
margin of 60°. From ‫ס‬ሺͳ െ ݆݂௧ ȀͳͲ଻ Hzሻ ൌ െ͵Ͳι , we find ƒ” –ƒሺ݂௧ ȀͳͲ଻ Hzሻ ൌ ͵Ͳι ֜ ݂௧ ൌ
ͷǤ͹͹ ൈ ͳͲ଺ Hz.

Inserting in the expression for the loop gain we find

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113
CMOS ANALOG IC DESIGN Solution to Problem 6

ହ ᇱ
ተ ͳͲହ ൈ ሺͳ െ ݆ ‫Ͳ ڄ‬Ǥͷ͹͹ሻ ተ ൌ ͳ ֜ ͳͲ ൈ ͳǤͳͷͷ ൈ ݂௣ଵ ൌ ͳ ֜ ݂ ᇱ ൌ ͵ͲͲ œ
ተ ͷǤ͹͹ ൈ ͳͲ଺  œ ተ ͸ ൈ ͷǤ͹͹ ൈ ͳͲ଺  œ ௣ଵ
͸ ൈ ቆͳ ൅ ݆ ᇱ ቇ
݂௣ଵ

Verifying, we find ȁ‫ܮ‬ሺ݆ ‫ ڄ‬ͷǤ͹͹ MHzሻȁ ൌ ȁͳͲହ ൈ ሺͳ െ ݆ ‫Ͳ ڄ‬Ǥͷ͹͹ሻȁȀȁ͸ ൈ ሺͳ ൅ ݆ ‫͵͵ʹͻͳ ڄ‬ሻȁ ൌ ͳ.

We may also analyze the loop gain using LTspice. The schematic shown above models
the gain function ‫ܣ‬ௗ ሺ݆݂ሻ ൌ ͳͲହ ሺͳ െ ݆݂ȀͳͲ଻ HzሻȀ൫ͳ ൅ ݆݂Ȁ݂௣ଵ ൯ and the ߚ-network is
implemented by the resistors ܴଵ and ܴଶ.The gain function is implemented using filter
blocks similar to those described in Example 5.3 in ‘CMOS Integrated Circuit Simulation
with LTspice’. The zero is defined by the parameter ‘fz1’ and since it is a right-half-plane
zero, it is defined with a negative value, i.e., ‘.param fz1=-10Meg’. The pole is defined
by the parameter ‘fp1’ which is stepped from 100 Hz to 500 Hz with steps of 100 Hz.

From a ‘.ac’ simulation, we plot the loop gain as ‘v(Vf )’. The plot has five traces corresponding
to the five different values of ‘fp1’.

From the plot corresponding to ݂௣ଵ = 300 Hz , we find that when the loop gain is 0 dB,
the phase of the loop gain is −120°, corresponding to a phase margin of 60°.

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114
CMOS ANALOG IC DESIGN Solution to Problem 6

The phase margin may also be found using the ‘.meas’ directive shown in the LTspice schematic.
The phase margin is PM ൌ ͳͺͲιԛ െ ‫ס‬൫െ‫ܮ‬ሺ݆݂௧ ሻ൯ ൌ ͳͺͲιԛ ൅ ‫ס‬൫‫ܮ‬ሺ݆݂௧ ሻ൯ ൌ ‫ס‬൫െ‫ܮ‬ሺ݆݂௧ ሻ൯. Thus, the
phase of ‘-v(Vf )’ is equal to the phase margin when the magnitude of ‘v(Vf )’ is equal to 1.

The error log file lists the phase margin for each value of ‘fp1’.

The results from the error log file may also be shown graphically. A right-click in the error
log file opens a dialogue box where you can select ‘Plot .step’ed .meas data’ by a left-click.
This opens a new plot showing the phase margin versus ‘fp1’. From this plot, we verify the
ᇱ
phase margin of 60° when ݂௣ଵ ൌ ͵ͲͲ Hz..

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115
CMOS ANALOG IC DESIGN Solution to Problem 7

SOLUTION TO PROBLEM 7

Question 1:
The small-signal diagram is shown below. The amplifier is modeled as a voltage-controlled
voltage source with gain ‫ܣ‬଴. The output is connected to a voltage source ‫ݒ‬ை which is
delivering a current ݅ into the output of the current mirror, i.e., the drain of M3. For details
on how to create the small-signal diagram from the schematic, you may turn to Appendix
A in this book.

For finding the output resistance ‫ݎ‬௢௨௧ , the input current ݅௜௡ ൌ
is Ͳreset, i.e., ݅௜௡ ൌ Ͳ, and the
output resistance is found as ‫ݎ‬௢௨௧ ൌ ‫ݒ‬௢ Ȁ݅ . With ݅௜௡ ൌ Ͳ, we also find ‫ݒ‬௜௡ ൌ Ͳ and ‫ݒ‬௚௦ଶ ൌ Ͳ.
Thus, also the voltage-controlled current source ݃௠ଶ ‫ݒ‬௚௦ଶ ൌ Ͳ and the current flows through
‫ݎ‬ௗ௦ଶ , causing ‫ݒ‬ௗ௦ଶ to be ‫ݒ‬ௗ௦ଶ ൌ ‫ݒ‬௦ଷ ൌ ݅Ԝ‫ݎ‬ௗ௦ଶ .

We note that the current through ‫ݎ‬ௗ௦ଷ is ൫݅ െ ݃௠ଷ ‫ݒ‬௚௦ଷ ൯, so using Kirchhoff ’s voltage law
and Ohm’s law, we find

‫ݒ‬௢ ൌ ൫݅ െ ݃௠ଷ ‫ݒ‬௚௦ଷ ൯‫ݎ‬ௗ௦ଷ ൅ ݅Ԝ‫ݎ‬ௗ௦ଶ

where ‫ݒ‬௚௦ଷ ൌ ‫ݒ‬௚ଷ െ ‫ݒ‬௦ଷ ൌ െ‫ܣ‬଴ ‫ݒ‬ௗ௦ଶ െ ‫ݒ‬௦ଷ ൌ െ݅Ԝ‫ݎ‬ௗ௦ଶ ሺ‫ܣ‬଴ ൅ ͳሻ.

Inserting in the expression for ‫ݒ‬ை, we find

‫ݒ‬௢ ൌ ൫݅ ൅ ݅Ԝ݃௠ଷ ‫ݎ‬ௗ௦ଶ ሺ‫ܣ‬଴ ൅ ͳሻ൯‫ݎ‬ௗ௦ଷ ൅ ݅Ԝ‫ݎ‬ௗ௦ଶ

֜ ‫ݎ‬௢௨௧ ൌ ‫ݒ‬௢ Ȁ݅ ൌ ൫ͳ ൅ ݃௠ଷ ‫ݎ‬ௗ௦ଶ ሺ‫ܣ‬଴ ൅ ͳሻ൯‫ݎ‬ௗ௦ଷ ൅ ‫ݎ‬ௗ௦ଶ

ൌ ‫ݎ‬ௗ௦ଶ ൅ ‫ݎ‬ௗ௦ଷ ൅ ‫ݎ‬ௗ௦ଶ ݃௠ଷ ‫ݎ‬ௗ௦ଷ ሺ‫ܣ‬଴ ൅ ͳሻ

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116
CMOS ANALOG IC DESIGN Solution to Problem 7

With all transistors in the active region, we would normally find ‫ݎ‬ௗ௦ଶ ݃௠ଷ ‫ݎ‬ௗ௦ଷ ‫ݎ ب‬ௗ௦ଷ ൅ ‫ݎ‬ௗ௦ଶ
and ‫ܣ‬଴ ‫ͳ ب‬, so the expression for ‫ݎ‬௢௨௧ may be simplified to ‫ݎ‬௢௨௧ ؄ ‫ݎ‬ௗ௦ଶ ݃௠ଷ ‫ݎ‬ௗ௦ଷ ‫ܣ‬଴ . This
may be interpreted as the output resistance ‫ݎ‬ௗ௦ଶ of the current mirror output transistor
M2 multiplied by the gain of the cascode transistor M3 and the gain ‫ܣ‬଴ of the amplifier.

Question 2:
For finding the numerical value of the output resistance, we need numerical values for ݃௠ଷ,
‫ݎ‬ௗ௦ଶ and ‫ݎ‬ௗ௦ଷ . The transconductances ݃௠ଷ and ݃௠ସ can be calculated from

݃௠ ൌ ඥʹԜߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ‫ܫ‬஽ ሺͳ ൅ ߣܸ஽ௌ ሻ ؄ ඥʹԜߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ‫ܫ‬஽

where we assume ߣܸ஽ௌ ‫ ͳ ا‬.

With ‫ܫ‬஽ଷ ൌ ‫ܫ‬஽ଶ ؄ ‫ܫ‬ூே୫ୟ୶ ൌ ʹͲͲ μA, we find

݃௠ଷ ؄ ටʹ ൈ ͳͺͲ μA/Vଶ ൈ ͳͲ ൈ ʹͲͲ μA ൌ ͲǤͺͷ mA/V

With ‫ܫ‬஽ଷ ൌ ‫ܫ‬஽ଶ ؄ ‫ܫ‬ூே୫ୟ୶ Ȁʹ ൌ ͳͲͲ μA, we find

݃௠ଷ ؄ ටʹ ൈ ͳͺͲ μA/Vଶ ൈ ͳͲ ൈ ͳͲͲ μA ൌ ͲǤ͸Ͳ mA/V

The output resistances ‫ݎ‬ௗ௦ଶ and ‫ݎ‬ௗ௦ଷ can be calculated from

ͳ ൅ ߣܸ஽ௌ ͳ
‫ݎ‬ௗ௦ ൌ ؄
ߣ‫ܫ‬஽ ߣ‫ܫ‬஽

where we assume ߣܸ஽ௌ ‫ ͳ ا‬.

With ‫ܫ‬஽ଷ ൌ ‫ܫ‬஽ଶ ؄ ‫ܫ‬ூே୫ୟ୶ ൌ ʹͲͲ μA, we find

ͳ
‫ݎ‬ௗ௦ଶ ؄ ‫ݎ‬ௗ௦ଷ ؄ ିଵ ൌ ͷͲ kΩ
ͲǤͳ V ൈ ͲǤʹͲ mA

With ‫ܫ‬஽ଷ ൌ ‫ܫ‬஽ଶ ؄ ‫ܫ‬ூே୫ୟ୶ Ȁʹ ൌ ͳͲͲ μA, we find

ͳ
‫ݎ‬ௗ௦ଶ ؄ ‫ݎ‬ௗ௦ଷ ؄ ିଵ ൌ ͳͲͲ kΩ
ͲǤͳ V ൈ ͲǤͳͲ mA

Inserting these values in the expression for ‫ݎ‬௢௨௧ , we find for ݅ூே ൌ ‫ܫ‬ூேmax ൌ ʹͲͲ μA:

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117
CMOS ANALOG IC DESIGN Solution to Problem 7

‫ݎ‬௢௨௧ ؄ ‫ݎ‬ௗ௦ଶ ݃௠ଷ ‫ݎ‬ௗ௦ଷ ‫ܣ‬଴ ൌ ͷͲ kΩ ൈ ͲǤͺͷ mA/V ൈ ͷͲ kΩ ൈ ͷͲ V/V ൌ ͳͲ͸ MΩ

For ݅ூே ൌ ‫ܫ‬ூேmax Ȁʹ ൌ ͳͲͲ μA,, we find:

‫ݎ‬௢௨௧ ؄ ‫ݎ‬ௗ௦ଶ ݃௠ଷ ‫ݎ‬ௗ௦ଷ ‫ܣ‬଴ ൌ ͳͲͲ kΩ ൈ ͲǤ͸Ͳ mA/V ൈ ͳͲͲ kΩ ൈ ͷͲ V/V ൌ ͵ͲͲ MΩ

Question 3:
For an NMOS transistor to be in the active region, we require ܸ஽ௌ ൒ ܸீௌ െ ܸ௧ ൌ ܸ஽ௌ•ƒ– .
We notice that M1 is in the active region since ܸ஽ௌଵ ൌ ܸீௌଵ ൐ ܸீௌଵ െ ܸ௧ .
For the active region, we find from the Shichman-Hodges model with ߣܸ஽ௌ ‫ͳ ا‬

ͳ
‫ܫ‬஽ ൌ ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻሺܸீௌ െ ܸ௧ ሻଶ ሺͳ ൅ ߣܸ஽ௌ ሻ
ʹ
ʹԜ‫ܫ‬஽
֜ ܸீௌ  ൌ  ܸ௧ ൅ ඨ
ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻሺͳ ൅ ߣܸ஽ௌ ሻ

ʹԜ‫ܫ‬஽ ʹԜ‫ܫ‬஽
֜ ܸ஽ௌ•ƒ–  ൌ  ඨ ؄ඨ
ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻሺͳ ൅ ߣܸ஽ௌ ሻ ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ

For transistor M2, we must require ܸ஽ௌଶ ൒ ܸ஽ௌଶ•ƒ– for the maximum value of ݅ூே, i.e., with
‫ܫ‬஽ଶ ؄ ‫ܫ‬஽ଵ ൌ ‫ܫ‬ூே୫ୟ୶

ʹԜ‫ܫ‬஽ଶ ʹ ൈ ʹͲͲ μA
ܸ஽ௌଶsat ؄ ඨ ൌඨ ൌ ͲǤͶ͹ͳ V
ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ ͳͺͲ μA/Vଶ ൈ ͳͲ

Thus, the inverting input to the amplifier should be at least ܸ஽ௌଶ•ƒ– ൌ ͲǤͶ͹ͳ. The output voltage
of the amplifier is ܸீଷ ൌ ܸ஽ௌଶ•ƒ– ൅ ܸீௌଷ where ܸீௌଷ ൌ ܸ௧ ൅ ܸ஽ௌଷ•ƒ– ൌ ܸ௧ ൅ ܸ஽ௌଶ•ƒ– ൌ ͲǤͺ͹ͳ
since with ‫ܫ‬஽ଷ ൌ ‫ܫ‬஽ଶ and ܹଷ Ȁ‫ܮ‬ଷ ൌ ܹଶ Ȁ‫ܮ‬ଶ , we find ܸ஽ௌଷ•ƒ– ൌ ܸ஽ௌଶ•ƒ– . Thus, ܸீଷ ൌ ͳǤ͵Ͷʹ and
with ‫ܣ‬଴ ൌ ͷͲȀ,, we find a differential input voltage ܸ௜ௗ to the amplifier of ܸ௜ௗ ൌ ܸீଷ Ȁ‫ܣ‬଴ ൌ
ͲǤͲʹ͹, so the noninverting input voltage ܸ஻ should be at least ܸ஻‹ ൌ ܸ஽ௌଶ•ƒ– ൅ ܸீଷ Ȁ‫ܣ‬଴ ൌ
ͲǤͶ͹ͳ ൅ ͲǤͲʹ͹ ൌ ͲǤͶͻͺ ؄ ͲǤͷ..

In order to ensure that also M3 is in the active region, we require ܸ஽ௌଷ ൒ ܸ஽ௌଷ•ƒ– ֜ ‫ݒ‬ை ൒ ܸீଷ െ
ܸ௧ ൌ ͳǤ͵Ͷʹ െ ͲǤͶ ൌ ͲǤͻͶʹ.

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118
CMOS ANALOG IC DESIGN Solution to Problem 7

If ܸ஻ is selected to be larger than ܸ஻‹ ,ൌ ܸ஽ௌଶ•ƒ–

the ൅ ܸீଷ Ȁ‫ܣ‬for
requirement ଴ ൌM3 is modified. We still require
‫ݒ‬ை ൒ ܸீଷ െ ܸ௧ but ܸீଷ െ
is ܸfound
௧ from

ܸீଷ ൌ ‫ܣ‬଴ ሺܸ஻ െ ܸௌଷ ሻ ൌ ‫ܣ‬଴ ሺܸ஻ ൅ ܸீௌଷ െ ܸீଷ ሻ

‫ܣ‬଴ ‫ܣ‬଴
֜ ܸீଷ ൌ ሺܸ஻ ൅ ܸீௌଷ ሻ ൌ ሺܸ஻ ൅ ܸ௧ ൅ ܸ஽ௌଷ•ƒ– ሻ
‫ܣ‬଴ ൅ ͳ ‫ܣ‬଴ ൅ ͳ

Thus, we find

‫ܣ‬଴ ‫ܣ‬଴
‫ݒ‬ை ൒ ܸீଷ െ ܸ௧ ൌ ሺܸ஻ ൅ ܸ௧ ൅ ܸ஽ௌଷsat ሻ െ ܸ௧ ൌ ሺܸ஻ ൅ ܸ஽ௌଷsat ሻ െ ܸ௧ Ȁሺ‫ܣ‬଴ ൅ ͳሻ
‫ܣ‬଴ ൅ ͳ ‫ܣ‬଴ ൅ ͳ

With ‫ܣ‬଴ ‫ͳ ب‬, this expression may be simplified to

ʹԜ‫ܫ‬ூேƒš
‫ݒ‬ை ൒ ܸ஻ ൅ ܸ஽ௌଷ•ƒ– ؄ ܸ஻ ൅ ඨ
ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ

Question 4:
Shown below is the LTspice schematic for the current mirror. The bias voltage ܸ஻ is selected
to ܸ஻ ൌ ͲǤͷ, i.e., the minimum value found in Question 3. The output of the current
mirror is connected to a voltage ܸை with a value of 1.3 V which ensures that all transistors
are in the active region, compare to Question 3.

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119
CMOS ANALOG IC DESIGN Solution to Problem 7

We start by running a ‘.op’ simulation with ݅ூே ൌ ʹͲͲɊ . From the output file, we find
an output current of 193 µA, i.e., very close to the ideal value of 200 µA. The difference is
caused by the different drain-source voltages for M1 and M2 with ܸ஽ௌଶ being smaller than
ܸ஽ௌଵ .ൌFrom
ܸீௌଵ the
൐ ܸீௌଵ െ log
error ܸ௧ file, we find the bias point for each transistor, and we also find
the small-signal parameters listed in the following table. The ‘.op’ simulation is repeated
with ݅ூே ൌ ͳͲͲɊ, resulting in the bias values and small-signal parameters also shown in
the following table.

Error log files, ��� = 200 μA and ��� = 100 μA

For finding the output resistance, we run the ‘.tf ’ simulation shown in the schematic. With ܸை
as the source, the input resistance found by the ‘.tf ’ simulation is the output resistance of the
current mirror. The ‘.tf ’ simulation is run both with ݅ூே ൌ ʹͲͲɊ and with ݅ூே ൌ ͳͲͲɊ.
From the output files, we find ‫ݎ‬௢௨௧ ൌ ͳ͵ͷȳ when ݅ூே ൌ ʹͲͲɊ and ‫ݎ‬௢௨௧ ൌ ͵͹Ͷȳ
when ݅ூே ൌ ͳͲͲɊ. These values are somewhat larger than the values calculated in Question
2. The reason for this is the approximation ͳ ൅ ߣܸ஽ௌ ؄ ͳ . This approximation causes the
calculated values of transconductances and output resistances to be somewhat smaller than
the simulated values. With drain-source voltages in the region 0.45 V to 0.83 V, omitting
the factor ሺͳ ൅ ߣܸ஽ௌ ሻ introduces an average error of about 7% in each of the calculated
values of the small-signal parameters, and since the factors are multiplied in the expression
for ‫ݎ‬௢௨௧ , the total error is on the order of 25%.

From the error log file, we find ݃ௗ௦ଶ ൌ ͳͺǤͶɊȀ , ݃௠ଷ ൌ ͺ͸͹ɊȀ and ݃ௗ௦ଷ ൌ ͳ͹ǤͺɊȀ
when ݅ூே ൌ ʹͲͲɊ. Inserting these values in the expression for ‫ݎ‬௢௨௧ , we find

ͳ ݃௠ଷ ͳ ͺ͸͹
‫ݎ‬௢௨௧ ؄ ‫ݎ‬ௗ௦ଶ ݃௠ଷ ‫ݎ‬ௗ௦ଷ ‫ܣ‬଴ ൌ Ԝ൬ ൰ ‫ܣ‬଴ ൌ ൈ ൈ ͷͲ ൌ ͳ͵ʹȳ
݃ௗ௦ଶ ݃ௗ௦ଷ ͳͺǤͶɊȀ ͳ͹Ǥͺ

i.e., a very good match to the simulated value.

For ݅ூே ൌ ͳͲͲɊ, we find ݃ௗ௦ଶ ൌ ͻǤ͵͵ɊȀ, ݃௠ଷ ൌ ͸ͳ͹ɊȀ and ݃ௗ௦ଷ ൌ ͻǤͲ͵ɊȀ . Inserting
these values in the expression for ‫ݎ‬௢௨௧ , we find

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120
CMOS ANALOG IC DESIGN Solution to Problem 7

ͳ ݃௠ଷ ͳ ͸ͳ͹
‫ݎ‬௢௨௧ ؄ ‫ݎ‬ௗ௦ଶ ݃௠ଷ ‫ݎ‬ௗ௦ଷ ‫ܣ‬଴ ൌ Ԝ൬ ൰ ‫ܣ‬଴ ൌ ൈ ൈ ͷͲ ൌ ͵͸͸ȳ
݃ௗ௦ଶ ݃ௗ௦ଷ ͻǤ͵͵ɊȀ ͻǤͲ͵

i.e., again a very good match to the simulated value.

For finding the minimum value of ܸ஻ which ensures M2 in the active region, we run a ‘.dc’
simulation with a sweep of ܸ஻ . We must require ܸ஽ଶ ൌ ܸௌଷ ൒ ܸீଶ െ ܸ௧ ൌ ܸூே െ ܸ௧ . Hence,
we plot ‘v(Vin)-0.4’ and ‘v(Vs3)’ as shown below. From the plot, we find ܸ஻min ൌ ͲǤͶ͹ͺ V
which is slightly lower than the calculated value because the calculated value of ܸ஽ௌଶsat is
slightly larger than the simulated value due to the approximation ͳ ൅ ߣܸ஽ௌ ؄ ͳ .

The minimum value of ܸ஻ may also be found using the ‘.meas’ directive shown in the
schematic. From the error log file, we find ܸ஻min ൌ ͲǤͶ͹ͺ V .

The minimum value of the output voltage with both M2 and M3 in the active region and
ܸ஻ ൌ ܸ஻‹ is ܸை‹ ൌ ܸ஽ௌଷ•ƒ– ൅ ܸ஽ௌଶ•ƒ– ൌ ͲǤͶͶͷ ൅ ͲǤͶͷ͵ ൌ ͲǤͺͻͺ, again a value which
is slightly lower than the calculated value because the calculated values of the saturation
voltages are slightly larger than the simulated values.

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121
CMOS ANALOG IC DESIGN Solution to Problem 8

SOLUTION TO PROBLEM 8

Question 1:
With ܸூே ൌ ܸை ൌ Ͳ V, both transistors have ܸ஽ௌ ൌ ܸீௌ , i.e., ȁܸ஽ௌ ȁ ൐ ȁܸீௌ െ ܸ௧ ȁ so they are
in the active region and ‫ܫ‬஽ଵ ൌ ‫ܫ‬஽ଶ . Thus, we find the quiescent current from

ͳ ܹ
‫ܫ‬஽ ൌ ߤ‫ܥ‬௢௫ ൬ ൰ ሺܸீௌଵ െ ܸ௧௡ ሻଶ ሺͳ ൅ ߣܸ஽ௌଵ ሻ
ʹ ‫ܮ‬

where ܸீௌଵ ൌ ܸ஽ௌଵ ൌ ͳǤͷ V . Inserting numerical values, we find

‫ܫ‬஽ ൌ ͲǤͷ ൈ ͵ͲͲ μA/Vଶ ൈ ሺͳǤͷ V െ ͲǤ͹ Vሻଶ ൈ ൫ͳ ൅ ͲǤͳ Vିଵ ൈ ͳǤͷ V൯ ൌ ͳͳͲǤͶ μA

Question 2:
The small-signal diagram is shown below. Notice that both ܸ஽஽ and ܸௌௌ are reset, implying
that in the small-signal diagram, M1 and M2 are connected in parallel. For details on how
to create the small-signal diagram from the schematic, you may turn to Appendix A in
this book.

The transconductances ݃௠ and output resistances ‫ݎ‬ௗ௦ are the same for the two transistors.
The transconductances are calculated from

ʹԜ‫ܫ‬஽ ʹ ൈ ͳͳͲǤͶ μA
݃௠ଶ ൌ ݃௠ଵ ൌ ൌ ൌ ʹ͹͸ μA/V
ܸீௌଵ െ ܸ௧௡ ͳǤͷ V െ ͲǤ͹ V

The output resistances are calculated from

ͳ ൅ ߣܸ஽ௌଵ ͳ ൅ ͲǤͳ Vିଵ ൈ ͳǤͷ V

‫ݎ‬ௗ௦ଶ ൌ ‫ݎ‬ௗ௦ଵ ൌ ൌ ൌ ͳͲͶ kΩ
ߣ‫ܫ‬஽ ͲǤͳ Vିଵ ൈ ͳͳͲǤͶ Ɋ

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122
CMOS ANALOG IC DESIGN Solution to Problem 8

Question 3:
A node equation at the output gives ሺ݃௠ଵ ൅ ݃௠ଶ ሻ‫ݒ‬௜௡ ൅ ‫ݒ‬௢ Ȁሺ‫ݎ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଶ ሻ ൌ Ͳ from which
we find the small-signal voltage gain

‫ܣ‬௩଴ ൌ െሺ݃௠ଵ ൅ ݃௠ଶ ሻሺ‫ݎ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଶ ሻ ൌ െͷͷʹ μA/V ൈ ͷʹ kΩ ൌ െʹͺǤ͹ V/V ‫ͻʹ ׽‬Ǥʹ dB

The input resistance is infinite, and with the input voltage reset (‫ݒ‬௜௡ ൌ Ͳ), the two voltage-
controlled current sources are reset, so we see that the output resistance is ‫ݎ‬௢௨௧ ൌ ‫ݎ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଶ ൌ
ͷʹ kΩ..

Question 4:
The small-signal diagram is now:

Assuming that the dominant pole is caused by ܴ௦ and ‫ܥ‬௉ , we can use the Miller transformation,
giving an input capacitance ‫ܥ‬௉ ሺͳ ൅ ȁ‫ܣ‬௩଴ ȁሻ of and the −3 dB frequency

ͳ ͳ ͳ
݂௣ ൌ ൬ ൰൬ ൰ൌ ൌ ͳͲǤͷ œ
ʹߨ ܴ௦ ‫ܥ‬௉ ሺͳ ൅ ȁ‫ܣ‬௩଴ ȁሻ ʹ ൈ ߨ ൈ ͳͲͲȳ ൈ ͷ’ ൈ ሺͳ ൅ ʹͺǤ͹ሻ

Question 5:
Shown below is an LTspice schematic for the circuit. For the transistors, we have selected
the geometries and the parameter ‘Kp’ such that ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ ൌ ͵ͲͲ μA/Vଶ for both M1 and
M2. In the schematic, we have included ܴ௦ and ‫ܥ‬௉ ,. They do not influence the bias point
of the circuit, so the results for Questions 1 and 2 can be verified from a ‘.op’ simulation.
Also specified is a ‘.tf ’ simulation and a ‘.ac’ simulation.

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123
CMOS ANALOG IC DESIGN Solution to Problem 8

From the error log file from the ‘.op’ simulation, we find ‫ܫ‬஽ଵ ൌ ‫ܫ‬஽ଶ ൌ ͳͳͲɊ, and we
find the small-signal parameters ݃௠ଵ ൌ ݃௠ଶ ൌ ʹ͹͸ɊȀ and ݃ௗ௦ଵ ൌ ݃ௗ௦ଶ ൌ ͻǤ͸ͲɊȀ ,
corresponding to ‫ݎ‬ௗ௦ଵ ൌ ‫ݎ‬ௗ௦ଶ ൌ ͳͲͶȳ . The simulation results are identical to the calculated
results.

From the output file from the ‘.tf ’ simulation, we find a gain of −28.75 V/V, an infinite input
resistance and an output resistance of 52 kΩ, also results matching the calculated results.

From the ‘.ac’ simulation, we find the plot of ܸை shown below where the −3 dB frequency
may be found using the cursors. Again, we find a perfect match to the calculated results.

Alternatively, the low-frequency gain and −3 dB frequency may be found using the ‘.meas’
directives shown in the schematic. The results are given in the error log file, and again a
perfect match to the calculated results is found.

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124
CMOS ANALOG IC DESIGN Solution to Problem 9

SOLUTION TO PROBLEM 9

Question 1:
With an ideal opamp, the closed loop transfer function ܸ௢ ሺ‫ݏ‬ሻȀܸ௜௡ ሺ‫ݏ‬ሻ is equal to the reciprocal
of the feedback factor E which is the voltage-divider ratio between the impedance ܼଶ and
the resistor ܴଵ where ܼଶ is the series connection of ܴଶ and ‫ܥ‬. Thus, we find

ܸ௢ ሺ‫ݏ‬ሻ ͳ ܼଶ ൅ ܴଵ ܴଵ ൅ ܴଶ ൅ ͳȀሺ‫ܥݏ‬ሻ ሺܴଵ ൅ ܴଶ ሻ‫ ݏܥ‬൅ ͳ

‫ܣ‬௙ ൌ ൌ ൌ ൌ ൌ
ܸ௜௡ ሺ‫ݏ‬ሻ ߚ ܼଶ ܴଶ ൅ ͳȀሺ‫ܥݏ‬ሻ ܴଶ ‫ ݏܥ‬൅ ͳ

The pole frequency is ݂௣ ൌ ሺʹߨሻିଵ ൈ ͳȀሺܴଶ ‫ܥ‬ሻ ൌ ͳͲ œ .

The zero frequency is ݂௭ ൌ ሺʹߨሻିଵ ൈ ͳȀ൫ሺܴ
൫ ଵ ൅ ܴଶ ሻ‫ܥ‬൯൯ ൌ ͳ œ.
The gain at low frequencies (݂ ‫ ا‬1 kHz or ݂ ՜ 0) is 1 V/V.
The gain at high frequencies (݂ ‫ ب‬10 kHz or ݂ ՜ λ) is 1 + ܴଵ /ܴଶ = 10 V/V .

A Bode plot (piecewise-linear approximation) of ȁܸ௢ ሺ݆݂ሻȀܸ௜௡ ሺ݆݂ሻȁ is shown below.

Question 2:
The loop gain is the product of the feedback factor and the transfer function of the opamp,
i.e.,
ܸ௢ ሺ݆݂ሻ ʹߨԜܴଶ ‫ ݂݆ܥ‬൅ ͳ ‫ܣ‬଴
‫ܮ‬ሺ݆݂ሻ ൌ ߚ ൌ൬ ൰ቆ ቇ
ܸ௜ௗ ሺ݆݂ሻ ʹߨԜሺܴଵ ൅ ܴଶ ሻ‫ ݂݆ܥ‬൅ ͳ ൫ͳ ൅ ݆݂Ȁ݂௣ଵ ൯൫ͳ ൅ ݆݂Ȁ݂௣ଶ ൯

The loop gain has a zero at 10 kHz and poles at 1 kHz, 10 kHz and 20 MHz. The pole
and the zero at 10 kHz cancel, so the loop gain simplifies to a transfer function with a
pole at 1 kHz and a pole at 20 MHz. The loop gain at very low frequencies (݂ ‫))œ ͳ ا‬
is ‫ܣ‬଴ , i.e., 80 dB.

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125
CMOS ANALOG IC DESIGN Solution to Problem 9

The following figure shows a Bode plot (piecewise-linear approximation) of ܸ௢ ሺ݆݂ሻȀܸ௜௡ ሺ݆݂ሻ.
The amplitude plot starts at 80 dB at very low frequencies. The first breakpoint appears at the
pole frequency of 1 kHz where the slope of the amplitude plot changes to −20 dB/dec. The
second breakpoint appears at the pole frequency of 20 MHz where the slope of the amplitude
plot changes to −40 dB/dec.

The phase plot (black plot) is the sum of the red plot and the green plot corresponding to
the phase shifts from the poles at 1 kHz and 20 MHz, respectively.

From the Bode plot, the phase margin is estimated to be 60°.

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126
CMOS ANALOG IC DESIGN Solution to Problem 9

A more accurate estimate may be obtained using Fig. 6.35 in ‘CMOS Analog IC Design:
Fundamentals’. The gain-bandwidth product of the loop gain is ݂௧௟ ൌ ͳͲସ ൈ ͳ œ ൌ ͳͲ œ
and with the second pole at ݂௣ଶ ൌ ʹͲ œ, we find ݂௣ଶ Ȁ݂௧௟ ൌ ʹ. From Fig. 6.35(a) or the
corresponding table in Chapter 9.9, we find a phase margin of 65.5°.

Analytically, the phase margin may also be calculated as follows:

The frequency ݂௧ for which the loop gain is 0 dB is found from

ͳͲସ
ቤ ቤ ൌ ͳ ֜ ݂௧ ൌ ͻǤͳ œ
ሺͳ ൅ ݆Ԝ݂௧ ȀͲǤͲͲͳ œሻሺͳ ൅ ݆Ԝ݂௧ ȀʹͲ œሻ

At ݂௧ ൌ ͻǤͳ œ, we find:

‫ܮס‬ሺ݆݂௧ ሻ ൌ െ ƒ” –ƒሺͻǤͳ œȀͳ œሻ െ ƒ” –ƒሺͻǤͳ œȀʹͲ œሻ ൌ െͻͲι െ ʹͶǤͷι ൌ −114.5° .

From this, we find a phase margin of ͳͺͲι െ ͳͳͶǤͷι ൌ ͸ͷǤͷι .

Question 3:
For simulating the circuit with LTspice, we model the opamp using two lowpass RC-filters
separated by voltage-controlled voltage sources to model the poles in the transfer function and
a voltage-controlled voltage source to model the low-frequency gain ‫ܣ‬଴. For the RC-filters,
we use a value of ‘1’ for the resistors and values of ‘{1/(2*pi*10k)}’ and ‘{1/(2*pi*10Meg)}
for the capacitors as shown in the LTspice schematic below. Notice that LTspice recognizes
‘pi’ as the value of ߨ and remember to include the curly brackets in the specifications of
the capacitors.

By running the ‘.ac’ simulation specified in the schematic, we obtain the Bode plot of Vo
shown below. The match to the piecewise-linear approximation from Question 1 is apparent.

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127
CMOS ANALOG IC DESIGN Solution to Problem 9

Question 4:
For simulating the loop gain, we reset the input signal, break the feedback loop at the
inverting input of the opamp, i.e., at the inverting input of the voltage-controlled voltage
source ‘E1’, and apply a test voltage ‘Vt’ with an ac amplitude of 1 to the inverting input
of ‘E1’ as shown in the LTspice schematic below. The loop gain is ‫ܮ‬ሺ݆݂ሻ ൌ െܸ௙ ሺ݆݂ሻȀܸ௧ ሺ݆݂ሻ
where ܸ௙ is the feedback voltage from the E -network.

From a ‘.ac’ simulation, we obtain the loop gain shown below. From the plot, we find a
phase margin of 180° − 114.5° = 65.5°, closely matching the value found from the exact
analytical calculation.

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128
CMOS ANALOG IC DESIGN Solution to Problem 9

The LTspice schematic also includes a ‘.meas’ directive to find the phase margin. The phase
margin is:

 ൌ ͳͺͲιԛ െ ‫ס‬൫െ‫ܮ‬ሺ݆݂௧ ሻ൯ ൌ ͳͺͲιԛ ൅ ‫ס‬൫‫ܮ‬ሺ݆݂௧ ሻ൯ ൌ ‫ס‬൫െ‫ܮ‬ሺ݆݂௧ ሻ൯ ൌ ‫ ס‬ቀܸ௙ ሺ݆݂௧ ሻȀܸ௧ ሺ݆݂௧ ሻቁ.

Thus, the phase of ‘v(Vf )’ is equal to the phase margin when the magnitude of ‘v(Vf )’
is equal to 1. From the error log file, we find ‘pm: v(vf )=(-0.000573381dB,65.5443°) at
9.10981e+06’, i.e., a phase margin of 65.5° and a unity-gain frequency of 9.1 MHz for the
loop gain. These results closely match the results from the plot.

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129
 CMOS ANALOG IC DESIGN Solution to Problem 10

SOLUTION TO PROBLEM 10

Question 1:
The current in M6 is the sum of the current in M1 and M2, i.e., ‫ܫ‬஽଺ ൌ ‫ܫ‬஽ଵ ൅ ‫ܫ‬஽ଶ ൌ ͲǤʹ.
The current in M4 is half the current in M6 since ߤ௡ ‫ܥ‬௢௫ ሺܹସ Ȁ‫ܮ‬ସ ሻ ൌ ߤ௡ ‫ܥ‬௢௫ ሺܹ଺ Ȁ‫ ଺ܮ‬ሻȀʹ (current
mirror), so the current in M4 is 0.1 mA. The current in ܴ஻ , M4 and M5 is the same, so the
current in ܴ஻ is ‫ܫ‬ோಳ ൌ ͲǤͳ. The voltage across ܴ஻ is ܸோಳ ൌ ܸ஽஽ ൅ ܸௌௌ െ ܸீௌସ െ ȁܸீௌହ ȁ
ܸோಳܸோൌಳ ܸ
ൌ஽஽ܸ஽஽
൅where
ܸ൅ௌௌܸെ
ௌௌ ܸ
െீௌସ
ܸீௌସ
െ ȁܸ ȁܸீௌହ
െீௌହ
and ȁ ȁ are found from the Shichman-Hodges model for a MOS transistor
without channel-length modulation:

ͳ
‫ܫ‬஽ ൌ ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻሺܸீௌ െ ܸ௧ ሻଶ
ʹ

For M4, this gives:

ʹ‫ܫ‬஽ ʹ ൈ ͲǤͳ
ܸீௌସ ൌ ܸ௧ ൅ ඨ ൌ ͲǤͷ ൅ ඨ ൌ ͲǤ͹ʹͶ
ߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ ͶǤͲͲȀ ଶ

For M5, we find

ʹ‫ܫ‬஽ ʹ ൈ ͲǤͳ
ȁܸீௌହ ȁ ൌ ȁܸ௧ ȁ ൅ ඨ ൌ ͲǤͷ ൅ ඨ ൌ ͳǤͳ͵ʹ
ߤ௣ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ ͲǤͷͲȀ ଶ

Inserting these values in the expression for ܸோಳ ,ൌweܸ஽஽ ൅ ܸܸோௌௌಳ െ

find ൌܸ ீௌସ െ ȁܸ
ͳǤͷͲ ൅ீௌହ ȁ െ ͲǤ͹ʹͶ െ
ͳǤͷͲ
ͳǤͳ͵ʹ ൌ ͳǤͳͶͶ.. From this, we find ܴ஻ ൌ ܸோಳ Ȁ‫ܫ‬ோಳ ൌ ͳǤͳͶͶȀͲǤͳ ൌ ͳͳǤͶͶȳ.

Question 2:
The following small-signal diagram is shown with a purely differential input voltage ܸ௜௡ ሺ‫ݏ‬ሻ .
With M3 and M6 considered as ideal dc current sources, they are open circuits in the small-
signal diagram, i.e., they are omitted from the small-signal diagram.

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130
CMOS ANALOG IC DESIGN Solution to Problem 10

The small-signal parameters ݃௠ଵ and ݃௠ଶ can be calculated from ݃௠ ൌ ʹԜ‫ܫ‬஽ Ȁሺܸீௌ െ ܸ௧ ሻ
and with ‫ܫ‬஽ଵ ൌ ‫ܫ‬஽ଶ ൌ ‫ܫ‬஽ସ , we find ܸீௌଵ ൌ ܸீௌଶ ൌ ܸீௌସ , so ݃௠ଶ ൌ ݃௠ଵ ൌ ʹԜ‫ܫ‬஽ସ Ȁሺܸீௌସ െ ܸ௧ ሻ ൌ
ͲǤʹȀሺͲǤ͹ʹͶ െ ͲǤͷͲሻ ൌ ͲǤͺͻ͵Ȁ.

Question 3:
In order to find the differential gain, a differential voltage is applied, i.e., ܸ௚ଵ ൌ െܸ௚ଶ ൌ ܸ௜௡ Ȁʹ.
With ݃௠ଵ ൌ ݃௠ଶ , a node equation at the source of M1 and M2 yields

݃௠ଵ ܸ௚௦ଵ ൅ ݃௠ଶ ܸ௚௦ଶ ൌ Ͳ ֜ ܸ௚ଵ െ ܸ௦ଵ ൅ ܸ௚ଶ െ ܸ௦ଶ ൌ Ͳ ֜ ܸ௦ଵ ൌ ܸ௦ଶ ൌ Ͳ

With ܸ௦ଵ ൌ ܸ௦ଶ ൌ Ͳ, we find

ͳ
ܸ௚௦ଶ ൌ െܸ௜௡ Ȁʹ ֜ ܸ௢ ൌ ܸௗଶ ൌ െܼ௅ ݃௠ଶ ܸ௚௦ଶ ൌ െ ൬ܴ௅ ‫צ‬ ൰ ݃ ሺെܸ௜௡ Ȁʹሻ
‫ܥݏ‬௅ ௠ଶ
ܴ௅ ݃௠ଶ Ȁʹ
֜ ‫ܣ‬ௗ ሺ‫ݏ‬ሻ ൌ
ͳ ൅ ‫ܴݏ‬௅ ‫ܥ‬௅

At very low frequencies, we find ‫ܣ‬଴ ൌ ܴ௅ ݃௠ଶ Ȁʹ ൌ ͶͶǤ͹ V/V.

From the expression for ‫ܣ‬ௗ , we find the −3 dB bandwidth as the pole frequency ݂௣ ൌ
ͳȀሺʹߨܴ௅ ‫ܥ‬௅ ሻ, so the gain-bandwidth product is
ͳ ݃௠ଶ
 ൌ ܴ௅ ݃௠ଶ Ȁʹ ൌ 
ʹߨܴ௅ ‫ܥ‬௅ Ͷߨ‫ܥ‬௅

With  ൌ ͳͲͲ œ, we find ‫ܥ‬௅ ൌ ݃௠ଶ ȀሺͶߨ ሻ ൌ ͲǤ͹ͳ’ .

Question 4:
We now have ‫ܫ‬஽ଵ ൌ ͲǤͳ, ‫ܫ‬஽଺ ൌ ͲǤʹ and ‫ܫ‬஽ଷ ൌ ͲǤͳͲͳ . Since ‫ܫ‬஽ଵ ൅ ‫ܫ‬஽ଶ ൌ ‫ܫ‬஽଺,
we still find ‫ܫ‬஽ଶ ൌ ‫ܫ‬஽ଵ ൌ ͲǤͳ. The difference between ‫ܫ‬஽ଷ and ‫ܫ‬஽ଶ must flow into
ܴ௅ , so the current in ܴ௅ is ‫ܫ‬஽ଷ െ ‫ܫ‬஽ଶ ൌ ͲǤͲͲͳ . With ܴ௅ ൌ ͳͲͲȳ , we find an
output voltage ܸை ൌ ሺ‫ܫ‬஽ଷ െ ‫ܫ‬஽ଶ ሻܴ௅ ൌ ͲǤͳ, corresponding to an input offset voltage of
ܸ‘ˆˆ ൌ െܸை Ȁ‫ܣ‬ௗ ൌ െʹǤʹͶ.. Notice that the input offset voltage is defined as the input
voltage required to bring the output voltage to 0 V.

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131
CMOS ANALOG IC DESIGN Solution to Problem 10

Question 5:
The following figure shows an LTspice schematic for the circuit. For the transistors, we have
selected the geometries and the parameter ‘Kp’ such that ߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ ൌ ͶǤͲͲȀ ଶ for
M1, M2 and M4, while ߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ ൌ ͺǤͲͲȀ ଶ for M6 and ߤ௣ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ ൌ ͲǤͷͲȀ ଶ
for M3 and M5.

From a ‘.op’ simulation, we find the following results from the error log file:

Error log file

We notice ‫ܫ‬஽ ൌ ͲǤͳ for all transistors except M6 where ‫ܫ‬஽଺ ൌ ͲǤʹ. This is as expected
and confirms the result from Question 1. We also note that the simulated and calculated
values of the gate-source voltages are the same and the simulated value of ݃௠ଵ ൌ ݃௠ଶ is
0.894 mA/V, closely matching the calculated value of 0.893 mA/V found in Question 2.

For verifying the results from Question 3, we run a ‘.ac’ simulation. From the plot of ܸ௢,
we find a low-frequency gain of 33 dB ¾ 44.7 V/V, i.e., the same as the calculated value.
The −3 dB frequency is 2.23 MHz, giving a gain-bandwidth product of 99.7 MHz which
is a close match to the specified value of 100 MHz. Thus, the value of ‫ܥ‬௅ is verified.

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132
CMOS ANALOG IC DESIGN Solution to Problem 10

For verifying the result from Question 4, we change the channel width of M3 to 10.1 µm.
This increases the current in M3 by 1%. From a ‘.dc’ simulation with ‘Vid’ as the input,
we find the following plot of ܸை versus ܸூ஽ .

From this plot, we find an output voltage of 100 mV for a differential input voltage of 0 V,
i.e., the same as the calculated value, and we find that an input voltage of ܸ‘ˆˆ ൌ െʹǤʹͶ
is required for an output voltage of 0 V as also calculated in Question 4.

Question 6:
For simulating the circuit with different values of h , we introduce ‘lambda’ as a parameter
in the model specifications for both the NMOS transistors and the PMOS transistors as
shown in the following LTspice schematic. Also, we remove the resistor ܴ௅. For finding a

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133
CMOS ANALOG IC DESIGN Solution to Problem 10

value of h resulting in an output resistance of 100 kΩ, we run the ‘.tf ’ simulation shown
in the schematic and we step ‘lambda’ through the range from 0 to 0.1 by a ‘.step’ directive.
After having run the ‘.tf ’ simulation, it is a good idea to run a ‘.op’ simulation to verify
that all transistors are biased in the active region.

From the ‘.tf ’ simulation, we may plot the ‘output_impedance_at_V(vo)’ versus ‘lambda’
as shown below, and we find that ߣ ൌ ͲǤͲ͹ͳ ିଵ results in an output resistance of 100
kΩ. Alternatively, the value of h can be found using the ‘.meas tf ’ directive shown in the
schematic.

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134
CMOS ANALOG IC DESIGN Solution to Problem 10

Question 7:
For finding the frequency response, we run the ‘.ac’ simulation with the ‘.step’ directive
shown as a comment in the LTspice schematic. The resulting plot of ܸ௢ is shown in the
following figure.

We notice that the phase shift at high frequencies is only −90° so the response has only a
single pole, implying that the gain-bandwidth product is equal to the unity-gain frequency.
The unity-gain frequency is found using the ‘.meas ac’ directive shown in the schematic. Also
the low-frequency gain is found using a ‘.meas’ directive. From the error log file, we find:

ߣ ൌ ͲǤͲͳ ିଵ: ‫ܣ‬଴ ൌ ͶͻǤ͹† ‫Ͳ͵ ׽‬ͶȀ,  ൌ ͳͲͳ œ.

ߣ ൌ ͲǤͲ͹ ିଵ: ‫ܣ‬଴ ൌ ͵͵Ǥ͹† ‫ ׽‬ͶͺǤͷȀ,  ൌ ͳͲͺ œ .

ߣ ൌ ͲǤͳ͵ ିଵ : ‫ܣ‬଴ ൌ ʹͻǤʹ† ‫ʹ ׽‬ͺǤͻȀ,  ൌ ͳͳ͵ œ.

We notice that even though the low-frequency gain depends strongly on h , the gain-
bandwidth product shows only a small variation as also expected from the expression for
GBW found in Question 3, showing that GBW depends only on ݃௠ଶ and ‫ܥ‬௅ where ݃௠ଶ
shows only a weak dependence on h .

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135
 CMOS ANALOG IC DESIGN Solution to Problem 11

SOLUTION TO PROBLEM 11

Question 1:

ூே ൌ ܸை ൌ Ͳ ,Vthe current in ܴ௅ is 0, so ‫ܫ‬஽ଶ ൌ ‫ܫ‬஽ଵ . Since M2 and M3 are identical and both
ܸWith
in the active region, ‫ܫ‬஽ଷ ൌ ‫ܫ‬஽ଶ . The current in ܴ஻ is ‫ܫ‬஽ଷ .ൌThe
ͲǤͳͲͳ
voltage across ܴ஻ is

ܸோ஻ ൌ ܸ஽஽ ൅ ܸௌௌ െ ȁܸீௌଷ ȁ

ܸோ஻ ൌ ܸThe
஽஽ ൅ ܸௌௌ െ ȁܸீௌଷ ȁ is found from the Shichman-Hodges model for a MOS transistor in the
voltage
active region:

ͳ
‫ܫ‬஽ ൌ ߤ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻሺܸீௌ െ ܸ௧ ሻଶ
ʹ

For M3, this gives:

ʹԜ‫ܫ‬஽ଷ ʹ ൈ ͳͲɊ
ȁܸீௌଷ ȁ ൌ หܸ௧௣ ห ൅ ඨ ൌ ͲǤͷ ൅ ඨ ൌ ͲǤͻ͹
ߤ௣ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ ͵ͲɊȀ ଶ ൈ ሺʹǤͳȀͲǤ͹ሻ

Bewareܸோ஻ ൌ ܸ஽஽
of the ൅ ܸௌௌ
signs: െ ȁܸீௌଷ ȁand ܸ௧௣ are negative.
both

Thus,

ܸ஽஽ ൅ ܸௌௌ െ ȁܸீௌଷ ȁ ͳǤͷ ൅ ͳǤͷ െ ͲǤͻ͹

ܴ஻ ൌ ൌ ൌ ʹͲ͵ȳ
‫ܫ‬஽ଷ ͳͲԛɊ

For the input transistor M1, we find:

ʹԜ‫ܫ‬஽ଵ ʹ ൈ ͳͲɊ
ܸீௌଵ ൌ ܸ௧ ൅ ඨ ൌ ͲǤͷ ൅ ඨ ൌ ͲǤ͹͹
ߤ௣ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ ͻͲɊȀ ଶ ൈ ሺʹǤͳȀͲǤ͹ሻ

From this, we get ܸூே ൌ െܸௌௌ ൅ ܸீௌଵ ൌ െͳǤͷ ൅ ͲǤ͹͹ ൌ െͲǤ͹͵.

Question 2:
For ‫ݒ‬ூே ൌ െͳ V, we find ‫ீݒ‬ௌଵ ൌ ͲǤͷ V, i.e., ‫ீݒ‬ௌଵ ൌ ܸ௧௡ , so the current in M1 is 0. This
implies that the drain current from M2 must flow in ܴ௅ . With ݅஽ଶ ൌ ͳͲ μA, we find
‫ݒ‬ை ൌ ͳͲ μA ൈ ͳͲͲ kΩ ൌ ͳ V .

With ‫ݒ‬ை ൌ ͳ V , we find ȁ‫ݒ‬஽ௌଶ ȁ ൌ ͲǤͷ V which is larger than ห‫ீݒ‬ௌଶ െ ܸ௧௣ ห ൌ ห‫ீݒ‬ௌଷ െ ܸ௧௣ ห ൌ
ͲǤͻ͹ V െ ͲǤͷ V ൌ ͲǤͶ͹ V. Thus, M2 is in the active region and ‫ݒ‬ை ൌ ͳ V for ‫ݒ‬ூே ൌ െͳ V.

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136
CMOS ANALOG IC DESIGN Solution to Problem 11

For ‫ݒ‬ூே ൌ ͲǤͷ V, we have ‫ீݒ‬ௌଵ ൌ ʹ V. Assuming that M1 is in the active region, this results
in ݅஽ଵ ൌ ሺͳȀʹሻߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻሺܸீௌଵ െ ܸ௧௡ ሻଶ ൌ ͲǤͷ ൈ ͻͲɊȀ ଶ ൈ ሺʹǤͳȀͲǤ͹ሻ ൈ ሺʹ െ ͲǤͷሻଶ ൌ ͵ͲͶɊ
which clearly cannot be obtained through M2 and ܴ௅ . Thus, M1 is in the linear region, i.e.,

ܹ ͳ ଶ
݅஽ଵ ൌ ߤ௡ ‫ܥ‬௢௫ ቆሺ‫ீݒ‬ௌଵ െ ܸ௧௡ ሻ‫ݒ‬஽ௌଵ െ ‫ݒ‬஽ௌଵ ቇ
‫ܮ‬ ʹ
ܹ ͳ
ൌ ߤ௡ ‫ܥ‬௢௫ ቆሺ‫ீݒ‬ௌଵ െ ܸ௧௡ ሻሺ‫ݒ‬ை ൅ ܸௌௌ ሻ െ ሺ‫ݒ‬ை ൅ ܸௌௌ ሻଶ ቇ
‫ܮ‬ ʹ

From a node equation at the output node, we also have ݅஽ଵ ൌ ‫ܫ‬஽ଶ െ ‫ݒ‬ை Ȁܴ௅ , so

ܹ ͳ
ߤ௡ ‫ܥ‬௢௫ ቆሺ‫ீݒ‬ௌଵ െ ܸ௧௡ ሻሺ‫ݒ‬ை ൅ ܸௌௌ ሻ െ ሺ‫ݒ‬ை ൅ ܸௌௌ ሻଶ ቇ ൌ ‫ܫ‬஽ଶ െ ‫ݒ‬ை Ȁܴ௅
‫ܮ‬ ʹ

Re-writing the right-hand side of this equation to ‫ܫ‬஽ଶ െ ሺ‫ݒ‬ை ൅ ܸௌௌ ሻȀܴ௅ ൅ ܸௌௌ Ȁܴ௅ , we obtain
a quadratic equation which can be solved for ‫ݒ‬ை ൅ ܸௌௌ .

Inserting numerical values, we find

ʹǤͳ ͳ ‫ݒ‬ை ൅ ܸௌௌ ͳǤͷ

ͻͲɊȀ ଶ ൈ ൈ ൬ͳǤͷ ൈ ሺ‫ݒ‬ை ൅ ܸௌௌ ሻ െ ൈ ሺ‫ݒ‬ை ൅ ܸௌௌ ሻଶ ൰ ൌ ͳͲɊ െ ൅
ͲǤ͹ ʹ ͳͲͲȳ ͳͲͲȳ
ൌ ʹͷɊ െ ͳͲɊȀ ൈ ሺ‫ݒ‬ை ൅ ܸௌௌ ሻ

This quadratic equation in ሺ‫ݒ‬ை ൅ ܸௌௌ ሻhas the solution ሺ‫ݒ‬ை ൅ ܸௌௌ ሻ ൌ ͲǤͲ͸͵, so ‫ݒ‬ை ൌ െͳǤͶ͵͹
for ‫ݒ‬ூே ൌ ͲǤͷ V. The quadratic equation also has a solution for ሺ‫ݒ‬ை ൅ ܸௌௌ ሻ which is larger
than ‫ீݒ‬ௌଵ െ ܸ௧௡ but this is rejected as it does not correspond to M1 being in the linear
region.

In conclusion, for an input voltage range from −1 V to +0.5 V, we find an output voltage
range from +1 V to −1.437 V.

Question 3:
Transistors M2 and M3 are bias transistors forming a constant-current source. Thus, they
are not included in the small-signal diagram which is shown below

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137
CMOS ANALOG IC DESIGN Solution to Problem 11

The transconductance ݃௠ଵ ൌ

is ݃
calculated
௠ଶ from

ܹ
݃௠ଵ ൌ ඨʹߤ௡ ‫ܥ‬௢௫ ‫ ܫ‬ൌ ඥʹ ൈ ͻͲɊȀ ଶ ൈ ሺʹǤͳȀͲǤ͹ሻ ൈ ͳͲɊ ൌ ͹͵ǤͷɊȀ
‫ ܮ‬஽ଵ

The small-signal voltage gain is

‫ܣ‬௩ ൌ െܴ௅ ݃௠ଵ ൌ െͳͲͲȳ ൈ ͹͵ǤͷɊȀ ൌ െ͹Ǥ͵ͷȀ

Question 4:
The input capacitance is the Miller capacitance, i.e.,

‫ܥ‬௜௡ ൌ ‫ܥ‬ெ ൌ ‫ܥ‬௉ ሺͳ െ ‫ܣ‬௩ ሻ ൌ ʹ’ ൈ ሺͳ ൅ ͹Ǥ͵ͷȀሻ ൌ ͳ͸Ǥ͹’

Instead of using the Miller transformation, the input impedance can be calculated directly
from ܸ௜௡ Ȁ‫ܫ‬௜௡ when an input voltage ܸ௜௡ is applied. A node equation at the output gives

ܸ௢
ሺܸ௜௡ െ ܸ௢ ሻ‫ܥݏ‬௉ ൌ ݃௠ଵ ܸ௜௡ ൅
ܴ௅
‫ܥݏ‬௉ െ ݃௠ଵ ͳ െ ‫ܥݏ‬௉ Ȁ݃௠ଵ
֜ ܸ௢ ൌ ܸ௜௡ ൌ െܴ௅ ݃௠ଵ ܸ
‫ܥݏ‬௉ ൅ ͳȀܴ௅ ͳ ൅ ‫ܥݏ‬௉ ܴ௅ ௜௡

With ߱ ‫ͳ ا‬Ȁሺܴ௅ ‫ܥ‬௉ ሻ ൏ ݃௠ଵ Ȁ‫ܥ‬௉ , the expression for ܸ௢ reduces to ܸ௢ ൌ െ݃௠ଵ ܴ௅ ܸ௜௡ , so
ͳȀܼ௜௡ ൌ ‫ܫ‬௜௡ Ȁܸ௜௡ ൌ ‫ܥݏ‬௉ ሺܸ௜௡ െ ܸ௢ ሻȀܸ௜௡ ൌ ‫ܥݏ‬௉ ሺܸ௜௡ ൅ ݃௠ଵ ܴ௅ ܸ௜௡ ሻȀܸ௜௡ ൌ ‫ܥݏ‬௉ ሺͳ ൅ ݃௠ଵ ܴ௅ ሻ from
which we see that for frequencies ‫ͳ ا‬Ȁሺʹߨܴ௅ ‫ܥ‬௉ ሻ ‫Ͳ ׽‬Ǥͺ œ, the input is capacitive with
an input capacitance of ‫ܥ‬௜௡ ൌ ‫ܥ‬௉ ሺͳ ൅ ݃௠ଵ ܴ௅ ሻ as also found from the Miller transformation.

Question 5:
With �� = 500 k٠and an input capacitance of 16.7 pF, we find a time constant from the
input of the amplifier of ߬௜௡ ൌ ܴௌ Ԝ‫ܥ‬௜௡ ൌ ͷͲͲȳ ൈ ͳ͸Ǥ͹’ ൌ ͺǤ͵ͷɊ•. This corresponds to
a −3 dB bandwidth of ݂Ǧ͵ԛ† ൌ ͳȀሺʹԜߨ߬௜௡ ሻ ൌ ͳͻǤͳ œ..

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138
CMOS ANALOG IC DESIGN Solution to Problem 11

Question 6:
The small-signal diagram including ܴௌ and ‫ܥ‬௉ is shown below.

A node equation at the gate of M1 results in

൫ܸ௜௡ െ ܸ௚௦ଵ ൯Ȁܴௌ ൌ ൫ܸ௚௦ଵ െ ܸ௢ ൯‫ܥݏ‬௉ ֜ ܸ௚௦ଵ ሺͳȀܴௌ ൅ ‫ܥݏ‬௉ ሻ െ ܸ௢ ‫ܥݏ‬௉ ൌ ܸ௜௡ Ȁܴௌ

and a node equation at the output node results in

ܸ௢ Ȁܴ௅ ൅ ݃௠ଵ ܸ௚௦ଵ ൌ ൫ܸ௚௦ଵ െ ܸ௢ ൯‫ܥݏ‬௉ ֜ ܸ௚௦ଵ ሺ݃௠ଵ െ ‫ܥݏ‬௉ ሻ ൅ ܸ௢ ሺͳȀܴ௅ ൅ ‫ܥݏ‬௉ ሻ ൌ Ͳ

Solving these equations for ܸ௢ results in

ܸ௢ ͳ ݃௠ଵ െ ‫ܥݏ‬௉
ൌ െ൬ ൰൬ ൰
ܸ௜௡ ܴௌ ‫ܥݏ‬௉ ሺ݃௠ଵ ൅ ͳȀܴ௅ ൅ ͳȀܴௌ ሻ ൅ ͳȀሺܴௌ ܴ௅ ሻ
െܴ௅ ሺ݃௠ଵ െ ‫ܥݏ‬௉ ሻ
ൌ
ͳ ൅ ‫ܥݏ‬௉ ൫ሺ݃௠ଵ ܴ௅ ൅ ͳሻܴௌ ൅ ܴ௅ ൯

Question 7:
From the transfer function, we find a low-frequency gain of ‫ܣ‬଴ ൌ െ݃௠ଵ ܴ௅ . The low-frequency
gain is independent of ܴௌ , and with ܴ௅ ൌ ͳͲͲȳ and ݃௠ଵ ൌ ͹͵ǤͷɊȀ, we find ‫ܣ‬଴ ൌ
െ͹Ǥ͵ͷȀ, compare to Question 3.

We notice that the transfer function has a right-half-plane zero at the frequency ݂௭ ൌ
݃௠ଵ ȀሺʹԜߨԜ‫ܥ‬௉ ሻ ൌ ͷǤͺͷ œ, independent of ܴௌ .

From the transfer function, we also find the pole frequency

ͳ
݂௣ ൌ
ʹԜߨ‫ܥ‬௉ ൫ሺ݃௠ଵ ܴ௅ ൅ ͳሻܴௌ ൅ ܴ௅ ൯

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139
CMOS ANALOG IC DESIGN Solution to Problem 11

For ܴௌ ൌ Ͳ, we find ݂௣ ൌ ͹ͻ͸ œ .

For ܴௌ ൌ ͳͲȳ,, we find ݂௣ ൌ Ͷ͵Ͷ œ.
For ܴௌ ൌ ͳͲͲȳ , we find ݂௣ ൌ ͺͷǤͳ œ..
For ܴௌ ൌ ͷͲͲȳ, we find ݂௣ ൌ ͳͺǤ͸ œ.

Except for ܴௌ ൌ Ͳ, we find ݂௣ ‫݂ ا‬௭ , so the pole frequencies are good approximations to
the −3 dB bandwidth. For ܴௌ ൌ Ͳ, we can expect a −3 dB bandwidth which is somewhat
higher than the pole frequency. The exact value can be found from the equation

ଶ
ͳ െ ݆݂Ȁ݂௭ ‫ܣ‬ଶ଴
ቤ‫ܣ‬଴ ቤ ൌ
ͳ ൅ ݆݂Ȁ݂௣ ʹ

ͳ ൅ ሺ݂Ȁ݂௭ ሻଶ ͳ
֜ ଶ ൌ
ͳ ൅ ൫݂Ȁ݂௣ ൯ ʹ

ͳ ͳ
݂֜ൌඨ ൌ ݂௣ ݂௭ ඨ ଶ
ͳȀ݂௣ଶ െ ʹȀ݂௭ଶ ݂௭ െ ʹ݂௣ଶ

Inserting the pole frequencies and the zero frequency, we find the following bandwidths:

ܴௌ ൌ Ͳ: BW=811 kHz
ܴௌ ൌ ͳͲȳ: BW=436 kHz
ܴௌ ൌ ͳͲͲȳ: BW=85.1 kHz
ܴௌ ൌ ͷͲͲȳ: BW=18.6 kHz

Question 8:
Shown below is an LTspice schematic for the circuit. Resistor ܴ஻ has the value found in
Question 1. Also the dc value of ‫ݒ‬ூே ൌ theV value found in Question 1. The resistor ܴௌ in
hasͲǤͷ
series with the input voltage is inserted with the value defined as a parameter ‘RS’. For the
first questions, we use ‘RS=0.1’ since LTspice does not accept a value of 0. The capacitor
‫ܥ‬௉ , is inserted with a value of 2 pF. It does not affect the simulation results for the first
three questions but it is needed for the following questions.

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140
CMOS ANALOG IC DESIGN Solution to Problem 11

For verifying the answer to Question 1, we run a ‘.op’ simulation. From the output, we
find ܸ௢ ൌ െ݃ ௠ଵ ܴ௅and
ͳͷ ܸ௜௡ ‫ܫ‬஽ଵ ൌ ͻͺǤͶɊ, closely matching the values specified in Question 1.
The main source of inaccuracy in the calculated results is the rounding off of ܸீௌଵ to 0.77
V rather than 0.7722 V.

For verifying the answer to Question 2, we run the ‘.dc’ simulation shown as a comment in
the schematic. The plot of ‫ݒ‬ை versus ‫ݒ‬ூே is shown below. We find an output voltage range
from 1 V to −1.438 V for ‫ݒ‬ூே in the range from −1 V to +0.5 V. This closely matches the
calculated range but we notice that the useful input voltage range is only from −1 V to
about −0.6 V.

For verifying the answers to Questions 3 - 5, we run a ‘.ac’ simulation with ܴௌ ൌ ͷͲͲȳ.

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141
CMOS ANALOG IC DESIGN Solution to Problem 11

The ‘.ac’ simulation results in the following plot of ܸ௢. We find a low-frequency gain of 17.2
dB ¾ −7.28 V/V, confirming the result from Question 3. We also find a −3 dB frequency
of 18.7 kHz which is close to the calculated approximate value from Question 5.

Assuming a capacitive input, we notice that ‫ܫ‬௜௡ ൌ ܸ௜௡ ‫ܥݏ‬௜௡ ֜ ‫ܥ‬௜௡ ൌ ‫ܫ‬௜௡ Ȁሺ‫ܸݏ‬௜௡ ሻ. With ܸ௜௡ Ȁ‫ܫ‬௜௡
real and ‫ ݏ‬ൌ ݆߱, we find ‫ܥ‬௜௡ ൌ ‫ܫ‬௜௡ Ȁሺ݆ܸ߱௜௡ ሻ ൌ െ݆‫ܫ‬௜௡ Ȁሺܸ௜௡ ߱ሻ. Thus, in order for ‫ܥ‬௜௡ to be
real, ‫ܫ‬௜௡ is imaginary and ‫ܥ‬௜௡ can be found from ‫ܥ‬௜௡ ൌ ȁ‫ܫ‬௜௡ ȁȀሺܸ௜௡ ߱ሻ. With the amplitude
of ‘Vin’ equal to 1, ‫ܥ‬௜௡ can be found from a plot of ‘abs(v(Vin))/(2*pi*frequency)’ when
ܴௌ ൌ Ͳ. From the plot shown below, we find ‫ܥ‬௜௡ ൌ ͳ͸Ǥ͸’ , confirming the value calculated
in Question 4.

Finally, for verifying the calculated results from Question 7, we run a ‘.ac’ simulation with
ܴௌ stepped between the four specified values. For this simulation, we also include ‘.meas’
directives to find the low-frequency gain and the bandwidth.

The ‘.ac’ simulation results in the following plot of ܸ௢.

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142
CMOS ANALOG IC DESIGN Solution to Problem 11

From the error log file, we find the results of the ‘.meas’ directives. We find a gain of 17.2
dB and the following values of the bandwidth:

ܴௌ ൌ Ͳ: BW=811 kHz
ܴௌ ൌ ͳͲȳ: BW=438 kHz
ܴௌ ൌ ͳͲͲȳ: BW=85.7 kHz
ܴௌ ൌ ͷͲͲȳ: BW=18.8 kHz

These values are all very close to the calculated values, thus confirming the calculated results.

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143
CMOS ANALOG IC DESIGN Solution to Problem 12

SOLUTION TO PROBLEM 12

Question 1:
We assume that all transistors are in the active region, and neglecting the channel-length
modulation, we find

ͳ
‫ܫ‬஽ହ ൌ ߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ௡ ሺܸீௌହ െ ܸ௧௡ ሻଶ
ʹ
ʹԜ‫ܫ‬஽ହ ʹ ൈ ʹͲɊ
֜ ܸீௌହ ൌ ܸ௧௡ ൅ ඨ ൌ ͲǤ͹ ൅ ඨ ൌ ͳǤͲ͹
ߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ௡ ͵ͲͲɊȀ ଶ

From this, we find ܸ஻ ൌ െܸௌௌ ൅ ܸீௌହ ൌ െͲǤͶ͵ . We also note that ܸ஽ௌହ•ƒ– ൌ ܸீௌହ െ ܸ௧௡ ൌ
ͲǤ͵͹.. Further, with ܸூேశ ൌ ܸூேష and ‫ܫ‬஽ଵ ൌ ‫ܫ‬஽ଶ ൌ ‫ܫ‬஽ହ Ȁʹ, we find

ʹԜ‫ܫ‬஽ଵ ʹ ൈ ͳͲɊ
ܸ஽ௌଵ•ƒ– ൌ ඨ ൌඨ ൌ ͲǤʹ͸
ߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ௡ ͵ͲͲɊȀ ଶ

and with ܸூேశ ൌ ܸூேష ൌ Ͳ, we find ܸ஽ହ ൌ ܸௌଵ ൌ െܸீௌଵ ൌ െሺܸ஽ௌଵ•ƒ– ൅ ܸ௧௡ ሻ ൌ െሺͲǤʹ͸ ൅
ͲǤ͹ሻ ൌ െͲǤͻ͸. Thus, ܸ஽ௌହ ൌ ܸ஽ହ ൅ ܸௌௌ ൌ െͲǤͻ͸ ൅ ͳǤͷͲ ൌ ͲǤͷͶ which is larger than
ܸ஽ௌହ•ƒ– ൌ ͲǤ͵͹. This implies that the assumption of M5 being in the active region is correct.

Question 2:
Shown below is an LTspice schematic of the amplifier stage.
The transistors have been specified with geometries and parameters giving
ߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ௡ ൌ ͵ͲͲɊȀ ଶ  and ߤ௣ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ௣ ൌ ͳͲͲɊȀ ଶ .

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144
CMOS ANALOG IC DESIGN Solution to Problem 12

For finding the value of ܸ஻ ൌresulting

െܸௌௌ ൅ in
ܸீௌହ ൌ െͲǤͶ͵
a drain current in M5 of 20 µA, we run a ‘.dc’
simulation with a sweep of ܸ஻ ൌ െܸௌௌ
from ൅ ܸV
−0.5 ீௌହtoൌ−0.3 V. This result in the plot of ‫ܫ‬஽ହ shown
െͲǤͶ͵
below.

From the plot, we find ‫ܫ‬஽ହ ൌ ʹͲɊ for ܸ஻ ൌ െͲǤͶͶͶ͸. Alternatively, the value of ܸ஻ ൌ െܸௌௌ ൅ ܸீௌହ ൌ െ
may
be found using the ‘.meas VB’ directive shown in the schematic. The result of the ‘.meas’
directive is found in the error log file.

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145
CMOS ANALOG IC DESIGN Solution to Problem 12

Question 3:
The lower limit is given by

ܸூே‹ ൌ െܸௌௌ ൅ ܸ஽ௌହ•ƒ– ൅ ܸீௌଵ ൌ െܸௌௌ ൅ ሺܸீௌହ െ ܸ௧௡ ሻ ൅ ܸீௌଵ

ൌ െͳǤͷ ൅ ሺͳǤͲ͹ െ ͲǤ͹ሻ ൅ ͲǤͻ͸ ൌ െͲǤͳ͹

where ܸீௌଵ ൌ ͲǤͻ͸ was found in Question 1.

The upper limit is given by

ܸூேƒš ൌ ܸ஽஽ െ ȁܸீௌଷ ȁ െ ܸ஽ௌଵ•ƒ– ൅ ܸீௌଵ ൌ ܸ஽஽ െ ȁܸீௌଷ ȁ െ ሺܸீௌଵ െ ܸ௧௡ ሻ ൅ ܸீௌଵ
ൌ ܸ஽஽ െ ȁܸீௌଷ ȁ ൅ ܸ௧௡

where

ʹԜ‫ܫ‬஽ଷ
ȁܸீௌଷ ȁ ൌ หܸ௧௣ ห ൅ ඨ ൌ ͳǤͳͷ
Ɋ௣ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ௡

ܸூேƒš
Be careful with the signs. െ ȁܸீௌଷ
M3ൌisܸa஽஽PMOS ȁ െ ܸ஽ௌଵ•ƒ–
transistor and൅ ܸீௌଵmust
ൌ ܸ஽஽ ȁܸீௌଷnegative
beെmore ȁ െ ሺܸீௌଵthan ܸ௧௣ሻ ,൅ ܸீௌଵ
െ ܸ௧௡
i.e., ܸௌீ ൌ ȁܸீௌ ȁ must be moreൌpositive
ܸ஽஽ െ ȁܸthat
ீௌଷ ȁ ൅ From this, we find ܸூேƒš ൌ ͳǤͷ െ ͳǤͳͷ ൅
หܸ௧௣ หܸ.௧௡
ͲǤ͹ ൌ ͳǤͲͷ.

Question 4:
For simulating the limits of the common-mode input voltage range, we run a ‘.dc’ simulation
with ‘VICM’ as the input.

The lower limit is caused by M5 where we require ܸ஽ௌହ ൒ ܸீௌହ െ ܸ௧௡ ֜ ܸ஽ହ ൒ ܸீହ െ ܸ௧௡ ൌ ܸ஻ െ
ܸ௧௡. Hence, we plot ‘V(vd5)’ and ‘V(Vb)-0.7’ and find the intersection between the two
curves.

The upper limit is caused by M1, requiring ܸ஽ௌଵ ൒ ܸீௌଵ െ ܸ௧௡ ֜ ܸ஽ଵ ൒ ܸீଵ െ ܸ௧௡ ֜ ܸீଷ ൒
ܸூ஼ெ െ ܸ௧௡ . Hence, we plot ‘V(vg3)’ and ‘V(vicm)-0.7’ and find the intersection between
the two curves.

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146
CMOS ANALOG IC DESIGN Solution to Problem 12

From the following plot, we find ܸூே‹ ൌ െͲǤʹͲ͸ and ܸூேƒš ൌ ͳǤͲ͸. Both values are
reasonably close to the calculated values. The difference between calculated and simulated
values appears because the channel-length modulation is neglected for the calculated values.

Alternatively, the limits may be found using the ‘.meas’ directives shown in the LTspice
schematic.

Question 5:
The gain is ‫ܣ‬ௗ ൌ ݃௠ଵ ሺ‫ݎ‬ௗ௦ଶ ‫ݎ צ‬ௗ௦ସ ሻ. The transconductance ݃௠ଵ ൌ ݃௠ଶ from ݃௠ଵ ൌ ʹԜ‫ܫ‬஽ଵ Ȁ
is found
ሺܸீௌଵ െ ܸ௧௡ ሻ. From Question 1, we have ‫ܫ‬஽ଵ ൌ ͳͲɊ and ܸீௌଵ ൌ ͲǤͻ͸, giving ݃௠ଵ ൌ
ʹͲɊȀͲǤʹ͸ ൌ ͹͸ǤͻɊȀ..

The output resistances may be calculated from ‫ݎ‬ௗ௦ ൌ ሺͳ ൅ ߣȁܸ஽ௌ ȁሻȀሺߣ‫ܫ‬஽ ሻ . For both
M2 and M4, we have ‫ܫ‬஽ ൌ ͳͲɊ. For symmetry reasons, the bias value of the output
voltage is the same as ܸீௌଷ , and from Question 3, we have ȁܸீௌଷ ȁ ൌ ͳǤͳͷ, resulting in
an output voltage ܸை ൌ ܸ஽஽ െ ȁܸீௌଷ ȁ ൌ ͲǤ͵ͷ . Thus, ȁܸ஽ௌସ ȁ ൌ ܸ஽஽ െ ܸை ൌ ͳǤͳͷ and
ܸ஽ௌଶ ൌ ܸை െ ܸௌଶ ൌ ܸை െ ሺെܸீௌଵ ሻ ൌ ͳǤ͵ͳ when ܸூேశ ൌ ܸூேష ൌ Ͳ.

Inserting in the expression for ‫ݎ‬ௗ௦, we find ‫ݎ‬ௗ௦ଶ ൌ ሺͳ ൅ ͲǤͳ ିଵ ൈ ͳǤ͵ͳሻȀሺͲǤͳ ିଵ ൈ ͳͲɊሻ ൌ
ͳǤͳ͵ͳȳ and ‫ݎ‬ௗ௦ସ ൌ ሺͳ ൅ ͲǤͳ ିଵ ൈ ͳǤͳͷሻȀሺͲǤͳ ିଵ ൈ ͳͲɊሻ ൌ ͳǤͳͳͷȳ, giving ሺ‫ݎ‬ௗ௦ଶ ‫צ‬
‫ݎ‬ௗ௦ସ ሻ ൌ ͷ͸ͳȳ.

Inserting in the expression for ‫ܣ‬ௗ , ൌwe

݃௠ଵ ሺ‫ݎ‬ௗ௦ଶ
find ‫ܣ‬ௗ‫ צ‬ൌ
‫ݎ‬ௗ௦ସ ሻ
͹͸ǤͻɊȀ ൈ ͷ͸ͳȳ ൌ Ͷ͵ǤʹȀ. The
output resistance is ‫ݎ‬௢௨௧ ൌ ‫ݎ‬ௗ௦ଶ ‫ݎ צ‬ௗ௦ସ ൌ ͷ͸ͳȳ..

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147
CMOS ANALOG IC DESIGN Solution to Problem 12

Question 6:
The results for Question 5 may be verified by the ‘.tf ‘ simulation shown as a comment
in the LTspice schematic. From the output file, we find a gain of 45.8 V/V and an output
resistance of 566 kΩ. These values are close to the calculated values. The difference is caused
mainly by the neglection of the channel-length modulation in the calculation of ܸீௌଵ .ൌByͲǤͻͶ͵
running a ‘.op’ simulation, we find ܸீௌଵ ൌ ͲǤͻͶ͵ giving ݃௠ଵ ൌ ͺʹǤ͵ɊȀ which results
in ‫ܣ‬ௗ ൌ Ͷ͸ǤͳȀ, i.e., very close to the simulated value.

Question 7:
With the bulk of M1 and M2 connected to െܸௌௌ ൌ െͳǤͷ, the threshold voltage of M1
and M2 is changed to

ܸ௧ ൌ ܸ௧௢ ൅ ߛ ቆටܸௌ஻ ൅ หʹȰ௙ ห െ ටหʹȰ௙ หቇ

where ܸ௧௢ ൌ ͲǤ͹, ߛ ൌ ͲǤͷԛξ and ȁʹȰி ȁ ൌ ͲǤ͹.

Concerning Question 1:

With ܸூேశ ൌ ܸூேష ൌ Ͳ, the source voltage of M1 and M2 is about െͳǤͷ V,, so ܸ஻ ൌ െܸௌௌ ൅
is about 0.5ܸீௌହ ൌ െͲǤͶ͵
V, causing the threshold voltage of M1 and M2 to be about ܸ௧ ൌ ͲǤ͹ ൅ ͲǤͷԛξ ൈ ൫ξͲǤͷ ൅ ͲǤ͹ െ
ξͲǤ͹൯ ൌ ͲǤ͹ ൅ ͲǤͳ͵ ൌ ͲǤͺ͵. This reduces the drain-source voltage of M5 to about
0.41 V which is still larger than ܸீௌହ െ ܸ௧௡ ൌ ͲǤ͵͹ found in Question 1, implying that
M5 is in the active region. Thus, the calculation of ܸ஻ ൌ െܸௌௌneglecting
when ൅ ܸீௌହ ൌ the
െͲǤͶ͵
channel-length
modulation remains the same as for Question 1, i.e., ܸ஻ ൌ െͲǤͶ͵ .

Concerning Question 2:

The slightly reduced value of ܸ஽ௌହ implies that ܸீௌହ should be increased in order to obtain
a current of 20 µA for M5. Repeating the simulation from Question 2 with the bulk of M1
and M2 connected to െܸௌௌ , we find ܸ஻ ൌ െͲǤͶͶʹ͹ for ‫ܫ‬஽ହ ൌ ʹͲɊ.

Concerning Question 3:

In the calculation of the lower limit for ‫ݒ‬ூே ,ൌthe V of ܸீௌଵ ൌ

ͲǤͷvalue is ͲǤͻ͸
increased by the bulk
effect. For the calculation of ܸ஻ ,ൌwe
െܸestimated
ௌௌ ൅ ܸீௌହ ൌ to be about 0.41 V and ܸ஽ௌହ•ƒ– to
െͲǤͶ͵
ܸ஽ௌହ
be about 0.37 V for ܸூேశ ൌ ܸூேష ൌ Ͳ. Thus, the input voltage may be reduced by about
40 mV with M5 still in the active region. As this also reduces ܸௌ஻ଵ, the body effect is also
reduced slightly, so an estimate for ܸூே‹ is ܸூே‹ ؄ െͲǤͲͷ..
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148
 CMOS ANALOG IC DESIGN Solution to Problem 12

In the calculation of the upper limit for ‫ݒ‬ூே ,ൌweͲǤͷ V ܸூேƒš ൌ ܸ஽஽
have െ ȁܸൌ
ܸூேƒš ܸȁ஽஽
ீௌଷ ൅െܸ௧௡ȁܸwhere
ீௌଷ ȁ ൅ ܸ௧௡

is the threshold voltage of M1, taking the body effect into account. The increased value of
ܸ஽஽ െ ȁܸீௌଷ ȁ ൅ ܸ௧௡ implies a larger value of ܸூேƒš .ൌWith െௌଵȁܸൌ
ܸ஽஽ ܸ ܸȁ஽஽൅െ
ீௌଷ ܸ௧௡
ȁܸீௌଷ ȁ െ ܸ஽ௌଵ•ƒ– ൌ ͳǤͷ െ ͳǤͳͷ െ
ͲǤʹ͸ ൌ ͲǤͲͻ , we find ܸௌ஻ଵ ൌ ͳǤͷͻ , resulting in ܸ௧௡ ൌ ͲǤ͹ ൅ ͲǤͷԛξ ൈ
ௌ஻ଵ
൫ξͳǤͷͻ ൅ ͲǤ͹ െ ξͲǤ͹൯ ൌ ͲǤ͹ ൅ ͲǤ͵Ͷ ൌ ͳǤͲͶ.
ܸூேƒš ൌ ܸthis
With ȁܸீௌଷ ȁof൅ ܸ௧௡ , we find
஽஽ െvalue
ܸூேƒš ൌ ͳǤͷ െ ͳǤͳͷ ൅ ͳǤͲͶ ൌ ͳǤ͵ͻ .

Concerning Question 4:

For simulating the limits of the common-mode input voltage range, we repeat the ‘.dc’
simulation with ‘VICM’ as the input.

The lower limit is caused by M5 where we still require ܸ஽ହ ൒ ܸீହ െ ܸ௧௡ ൌ ܸ஻ െ ܸ௧௡ and
ܸ஽஽ െ ȁܸீௌଷ ȁ ൅ ܸ௧௡ is the threshold voltage of M5 which is not affected by the bulk effect. Hence, we plot
‘V(vd5)’ and ‘V(Vb)-0.7’ and find the intersection betwee n the two curves. This results
in ܸூே‹ ൌ െͲǤͳͲ. As for the case with no bulk effect, this value is slightly lower than
the calculated lower limit. The main reason for the difference is that the neglection of the
channel-length modulation causes the calculated values of both ܸ஽ௌହ•ƒ– and ܸீௌଵ ൌ toͲǤͻ͸
be
slightly larger than the simulated values.

The upper limit is caused by M1 where we still require ܸ஽ௌଵ ൒ ܸீௌଵ െ ܸ௧௡ ֜ ܸீଷ ൒ ܸூ஼ெ െ ܸ௧௡.
ܸூேƒš ܸ஽஽ െ ȁܸீௌଷ
ൌ However, nowȁ ൅ ܸ௧௡ depends on the bulk effect and is given by

ܸ௧௡ ൌ ܸ௧௢ ൅ ߛ ቆට‫ݒ‬ௌ஻ ൅ หʹȰ௙ ห െ ටหʹȰ௙ หቇ ൌ ͲǤ͹ ൅ ͲǤͷԛξ ൈ ൫ඥ‫ݒ‬஽ହ ൅ ܸௌௌ ൅ ͲǤ͹ െ ξͲǤ͹൯

Hence, we plot ‘V(vg3)’ and ‘V(vicm)-0.7-0.5*(sqrt(v(VD5)+2.2)-sqrt(0.7))’ and find the

intersection between the two curves. This results in ܸூேmax = 1.39 V, closely matching the
calculated value.

Alternatively, the limits may be found using ‘.meas VINmin’ and ‘.meas VINmax’ directives.
The ‘.meas VINmin’ directive is as for Question 4. The ‘.meas VINmax’ directive is changed
into ‘.meas VINmax find v(VICM) when v(VG3)=V(VICM)-0.7-0.5*(sqrt(v(VD5)+2.2)-
sqrt(0.7))’ in order to take the body effect into account.

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CMOS ANALOG IC DESIGN Solution to Problem 12

Concerning Question 5:

The gain is ‫ܣ‬ௗ = ݃௠ଵ (‫ݎ‬ௗ௦ଶ ‫ݎ צ‬ௗ௦ସ ) . The transconductance ݃௠ଵ is found from ݃௠ଵ = 2Ԝ‫ܫ‬஽ଵ /
(ܸீௌଵ െ ܸ௧௡ ).ܸThe ൌ ܸeffect
bulk
ூேƒš ȁܸீௌଷ ȁ ൅ ܸ௧௡ but also ܸீௌଵ is
஽஽ െincreases ͲǤͻ͸ so ݃௠ଵ remains the same ,
ൌincreased,
i.e., ��� = 76.9 μA/V. The output resistances may be calculated from ‫ݎ‬ௗ௦ = (1 + ߣ|ܸ஽ௌ |)/(ߣ‫ܫ‬஽ ).
For both M2 and M4, we have �� = 10 μA. The bulk effect does not affect M4, so ‫ݎ‬ௗ௦ସ remains
unchanged, i.e., ���� = 1.115 MΩ. For M2, the bulk effect causes an increase in drain-source
voltage of about 0.13 V to about 1.44 V, so ‫ݎ‬ௗ௦ is increased to ‫ݎ‬ௗ௦ଶ = (1 + 0.1 V ିଵ × 1.44 V)/
(0.1 V �� × 10 μA) = 1.144 MΩ, giving (���� � ���� ) = 565 kΩ. Inserting in the expression
for ‫ܣ‬ௗ , ൌwe݃௠ଵ ሺ‫ݎ‬ௗ௦ଶ
find �� ‫ݎ=צ‬ௗ௦ସ
76.9ሻ μA/V × 565 kΩ = 43.4 V/V..

The output resistance is ���� = ���� � ���� = 565 kΩ.

Thus, the bulk effect has only a marginal effect on the gain and output resistance.

Concerning Question 6:

Repeating the ‘.tf ’ simulation with the bulk of M1 and M2 connected to െܸௌௌ , we find a
gain of 46.2 V/V and an output resistance of 569 , i.e., values which are marginally larger
than the simulated values without body effect. As for the calculated results, the simulated
results show that the bulk effect has only a marginal effect on the gain and output resistance.

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CMOS ANALOG IC DESIGN Solution to Problem 13

SOLUTION TO PROBLEM 13

Question 1:
The feedback factor is found as the voltage-divider ratio between the impedances ܴଶ and
ܼଵ where ܼଵ is the parallel connection of ܴଵ and ‫ܥ‬ଵ. Thus,

ܴଶ ܴଶ ܴଶ
ߚ= = =
ܴଶ + ܼଵ ܴଶ + ܴଵ ‫ צ‬൫1/(‫ܥݏ‬ଵ )൯ ܴଵ /(‫ܥݏ‬ଵ )
ܴଶ +
ܴଵ + 1/(‫ܥݏ‬ଵ )

ܴଶ ‫ܥݏ‬ଵ ܴଵ + 1 ܴଶ ‫ܥݏ‬ଵ ܴଵ + 1
=൬ ൰൬ ൰=൬ ൰൬ ൰
ܴଵ + ܴଶ 1 + ‫ܥݏ‬ଵ ܴଵ ܴଶ /(ܴଵ + ܴଶ ) ܴଵ + ܴଶ 1 + ‫ܥݏ‬ଵ (ܴଵ ‫ܴ צ‬ଶ )

Question 2:
With an ideal opamp, the closed loop transfer function ܸ௢ (‫)ݏ‬/ܸ௜௡ (‫ )ݏ‬is equal to 1/ߚ, so

ܸ௢ (‫)ݏ‬ 1 ܴଵ 1 + ܴଵ ‫ܥ‬ଵ ‫ݏ‬/(1 + ܴଵ /ܴଶ ) ܴଵ 1 + (ܴଵ ‫ܴ צ‬ଶ )‫ܥ‬ଵ ‫ݏ‬

‫ܣ‬௙ = = = ൬1 + ൰ ቆ ቇ = ൬1 + ൰ ቆ ቇ
ܸ௜௡ (‫ߚ )ݏ‬ ܴଶ 1 + ܴଵ ‫ܥ‬ଵ ‫ݏ‬ ܴଶ 1 + ܴଵ ‫ܥ‬ଵ ‫ݏ‬

The pole frequency is �� = 1/(2���� �� ) = 1/(2 × � × 45 kΩ × 35.4 nF) = 100 Hz.

The zero frequency is �� = 1/(2��(�� ∥ �� )�� ) = 1/(2 × � × (45 kΩ ∥ 5 kΩ) × 35.4 nF) =
1 kHz.

The gain at low frequencies (݂ ‫ ا‬100 Hz or ݂ ՜ 0) is 1 + ܴଵ /ܴଶ = 10 V/V..

The gain at high frequencies (݂ ‫ ب‬1 kHz or ݂ ՜ λ) is 1 V/V .

A Bode plot of |ܸ௢ (݆݂)/ܸ௜௡ (݆݂)| is shown below.

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151
CMOS ANALOG IC DESIGN Solution to Problem 13

Question 3:
The loop gain is

ܸ௢ (݆݂) ܴଶ 1 + 2ߨԜ݆݂Ԝܴଵ ‫ܥ‬ଵ ‫ܣ‬଴

‫ߚ = )݂݆(ܮ‬ =൬ ൰൬ ൰ቆ ቇ
ܸ௜ௗ (݆݂) ܴଵ + ܴଶ 1 + 2ߨԜ݆݂Ԝ(ܴଵ ‫ܴ צ‬ଶ )‫ܥ‬ଵ ൫1 + ݆݂/݂௣ଵ ൯൫1 + ݆݂/݂௣ଶ ൯

From ߚ(݆݂), the loop gain has a zero at 100 Hz and a pole at 1 kHz. From the opamp
transfer function, the loop gain has poles at 100 kHz and 200 MHz.

The loop gain at very low frequencies (݂ ‫ ا‬100 Hz) is ‫ܣ‬଴ ܴଶ /(ܴଵ + ܴଶ ) = 100 V/V.

The following figure shows the Bode plot. The amplitude plot starts at 40 dB corresponding
to a gain of 100 V/V at low frequencies. The first breakpoint appears at the zero frequency of
100 Hz where the slope of the amplitude plot changes to 20 dB/dec. The second breakpoint
appears at the pole frequency of 1 kHz where the slope of the amplitude plot changes back
to 0 dB/dec. The third breakpoint appears at the pole frequency of 100 kHz where the
slope of the amplitude plot changes to −20 dB/dec, and finally at the pole frequency of
200 MHz, the slope of the amplitude plot changes to −40 dB/dec.

The phase plot (black plot) is the sum of the red, green, blue and magenta plots corresponding
to the phase shifts from the zero at 100 Hz and the poles at 1 kHz, 100 kHz and 200
MHz, respectively.

From the Bode plot, the phase margin is estimated to be 60°.

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152
CMOS ANALOG IC DESIGN Solution to Problem 13

Question 4:
A more accurate value may be found as follows:

At high frequencies, ݂ ‫ ب‬1 kHz , the feedback factor ߚ is approximately 1, so the expression
for the loop gain simplifies to
‫ܣ‬଴
‫= )݂݆(ܮ‬
൫1 + ݆݂/݂௣ଵ ൯൫1 + ݆݂/݂௣ଶ ൯

This is a second-order loop gain function with a gain-bandwidth product ݂௧௟ = ‫ܣ‬଴ ݂௣ଵ = 100 MHz
and a ratio between the non-dominant pole and the gain-bandwidth product of ݂௣ଶ /݂௧௟ = 2 .
From Fig. 6.35(a) or the corresponding table in Chapter 9.9 in ‘CMOS Analog IC Design:
Fundamentals’, we find that this corresponds to a phase margin of 65.5°.

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153
CMOS ANALOG IC DESIGN Solution to Problem 13

Alternatively, the frequency ݂௧ for which the loop gain is 1 V/V ¾ 0 dB is found from

10ଷ
ቤ ቤ = 1 ֜ ݂௧ = 91 MHz
(1 + ݆Ԝ݂௧ /0.1 MHz)(1 + ݆Ԝ݂௧ /200 MHz)

At ݂௧ = 91 MHz, we find

91 MHz 91 MHz 91 MHz 91 MHz

��(��� ) = arctan � � − arctan � � − arctan � � − arctan � �
0.1 kHz 1 kHz 100 kHz 200 MHz
= 90° − 90° − 89.9° − 24.5° = −114.4°

From this, we find a phase margin of 180° − 114.4° = 65.6°.

For analyzing the circuit with LTspice, we model the opamp using two lowpass RC-filters
separated by voltage-controlled voltage sources to model the poles in the transfer function
and a voltage-controlled voltage source to model the low-frequency gain ‫ܣ‬଴. For the RC-
filters, we use a value of ‘1’ for the resistors and values of ‘{1/(2*pi*100k)}’ and ‘{1/
(2*pi*200Meg)}’ for the capacitors as shown in the LTspice schematic below. Notice that
LTspice recognizes ‘pi’ as the value of π and remember to include the curly brackets in the
specifications of the capacitors.

By running the ‘.ac’ simulation specified in the schematic, we obtain the following Bode
plot of the closed-loop response ܸ௢. The match to the piecewise-linear approximation from
Question 2 is apparent.

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154
CMOS ANALOG IC DESIGN Solution to Problem 13

In order to find the phase margin, we must simulate the loop gain. For this simulation, we
reset the input signal, break the feedback loop at the inverting input of the opamp, i.e., at
the inverting input of the voltage-controlled voltage source ‘E1’, and apply a test voltage ‘Vt’
with an ac amplitude of 1 to the inverting input of ‘E1’ as shown in the LTspice schematic
below. The loop gain is ‫ = )݂݆(ܮ‬െܸ௙ (݆݂)/ܸ௧ (݆݂) where ܸ௙ is the feedback voltage from the
ߚ-network.

From a ‘.ac’ simulation, we obtain the following plot. From the plot, we find a phase
margin of PM = 180° − 114.4° = 65.6°, closely matching the value found from the exact
analytical calculation.

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155
CMOS ANALOG IC DESIGN Solution to Problem 13

The LTspice schematic also includes a `.meas’ directive to find the phase margin. The phase
margin is

PM = 180° � ����(��� )� = 180° + ���(��� )� = ����(��� )� = � ��� (��� )/�� (��� )�

so the phase of ‘v(Vf )’ is equal to the phase margin when the magnitude of ‘v(Vf )’ is equal
to 1.
From the error log file, we find ‘pm: v(vf )=(-0.00071279dB,65.6033°) at 9.11196e+007’,
i.e., a phase margin of 65.6° and a unity gain frequency of 91.1 MHz for the loop gain.
These results closely match the results from the plot and from the analytical calculation.

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156
CMOS ANALOG IC DESIGN Solution to Problem 14

SOLUTION TO PROBLEM 14

Question 1:
For the common-source stage, we have the output resistance ���� = ���� = 200 k٠.

The small-signal gain at low frequencies is �� = −��� ���� = −0.4 mA/V × 200 kΩ =
−80 V/V ∼ 38.0 dB.

The −3 dB bandwidth is ��� �� = 1/(2� ���� �� ) = (2 × � × 200 kΩ × 5 pF)�� = 159 kHz..

The gain-bandwidth product is GBW = |‫ܣ‬௩ |݂ିଷ ୢ୆ = 80 × 159 kHz = 12.7 MHz.

Question 2:
For the cascode amplifier, we have the output resistance ���� ≃ (��� + ���� )���� ���� =
(0.4 mA/V + 0.1 mA/V) × 200 kΩ × 200 kΩ = 20 MΩ (see ‘CMOS Analog IC Design:
Fundamentals’, Eq. (4.27)).

The small-signal gain at low frequencies is �� = −��� ���� = −0.4 mA/V × 20 MΩ = −8.0 ×
10� V/V ∼ 78.0 dB.

The −3 dB bandwidth is ��� �� = 1/(2� ���� �� ) = (2 × � × 20 MΩ × 5 pF)�� = 1.59 kHz .

The gain-bandwidth product is GBW = |‫ܣ‬௩ |݂ିଷ ୢ୆ = 8.0 × 10ଷ × 1.59 kHz = 12.7 MHz ,
i.e., the same as for the common-source stage.

Question 3:
For the cascade amplifier, the values of the small-signal parameters change because the
quiescent current is changed.

From �� ≃ �2�� ��� (�/�)�� , we see that when the current is multiplied by a factor of
0.5, the transconductance is multiplied by a factor of √0.5 = 0.707 so the new value of
݃௠ is ݃௠ = 0.283 mA/V.

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157
CMOS ANALOG IC DESIGN Solution to Problem 14

From ��� ≃ 1/(��� ) , we see that when the current is multiplied by a factor of 0.5, the output
resistance is multiplied by a factor of 1/0.5 = 2 so the new value of ‫ݎ‬ௗ௦ is ��� = 400 kΩ.

So, for the cascade amplifier, we have the output resistance ���� = ���� = 400 kΩ.

The small-signal gain at low frequencies is ‫ܣ‬௩ = (െ݃௠ଵ ‫ݎ‬ௗ௦ଵ )(െ݃௠ଶ ‫ݎ‬ௗ௦ଶ ) = (0.283 mA/V ×
400 kΩ)� = 12.8 × 10� V/V ∼ 82.1 dB.

The −3 dB bandwidth is ��� �� = 1/(2� ���� �� ) = (2 × � × 400 kΩ × 5 pF)�� = 79.6 kHz.

The gain-bandwidth product is GBW = |‫ܣ‬௩ |݂ିଷ ୢ୆ = 12.8 × 10ଷ × 79.6 kHz = 1.019 GHz,
i.e., much larger than for the common-source stage and the cascode stage.

Question 4:

From ݃௠ = 2Ԝ‫ܫ‬஽ /(ܸீௌ െ ܸ௧ ), we find ��� � �� = 2��� /�� = 2 × 50 μA/0.4 mA/V = 0.25 V .
From the Shichman-Hodges model, we then find with 1 + ���� ≃ 1

1 � 2��� 2 × 50 μA
�� ≃ �� ��� (�/�)(��� � �� )� ⇒ = = =8
2 � �� ��� (��� � �� ) � 200 μA/V � × (0.25 V)�

From ��� ≃ 1/(��� ) when 1 + ���� ≃ 1 , we find � � 1/(�� ���� ) = 1/(50 μA × 200 kΩ) =
0.1 V ିଵ.

From �� = �� = 0.1 μm/V, we find � = �/�� = 1 μm.

Thus, for the simulations, we use ߣ = 0.1 V ିଵ , � = 1 μm and � = 8� = 8 μm.

Shown below is the LTspice schematic for simulating the common-source amplifier. The
current source ‫ܫ‬஻ is inserted between ground and ‫ݒ‬ை. In an actual circuit implementation,
the upper terminal of the current source would be connected to a supply voltage which
for the transistor parameters selected for the simulation would have a value of about 2 V
but for the purpose of this simulation, the upper terminal just has to be connected to an
arbitrary dc voltage which can provide the current ‫ܫ‬஻.

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158
CMOS ANALOG IC DESIGN Solution to Problem 14

The first simulation is a ‘.dc’ simulation for finding the input voltage required to get an
output voltage in the useful output voltage range of the amplifier. By running the ‘.dc’
simulation shown in the schematic, we get the following plot of the output voltage. Here
we observe that the y-axis extends from 0 to 27 MV which is obviously not physically
reasonable for the circuit. The reason for this is the ideal dc current source ‫ܫ‬஻. This is not
a realistic model for a real physical current source where the output voltage cannot exceed
the supply voltage.

In order to see ‫ݒ‬ை in a realistic range of output voltages, we set the range of the y-axis to 2
V as shown in the following plot. We see that the output voltage changes abruptly for an
input voltage of about 0.65 V. In order to find a reasonable value of the input bias voltage,
we use the ‘.meas’ directive shown in the LTspice schematic. This finds the value of ‫ݒ‬ூே
resulting in ‫ݒ‬ை = 0.8 V. From the error log file, we find ܸூே = 0.640563 V and we insert
this value as the dc value for ‘VIN’.

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159
CMOS ANALOG IC DESIGN Solution to Problem 14

Next, we may run a ‘.op’ simulation. From this, we may verify that a dc value of 0.640563
V for ‘VI’ results in an output voltage of 0.8 V, and from the error log file, we find
݃௠ଵ = 0.416 mA/V and ���� = 4.63 μA/V corresponding to ���� = 1/���� = 216 kΩ .
These values are close to the values specified for the circuit. The difference is caused by the
neglection of the factor (1 + ߣܸ஽ௌ ) in the expressions for ‫ܫ‬஽ and ‫ݎ‬ௗ௦.

With the simulated small-signal parameters, we expect an output resistance of ‫ݎ‬௢௨௧ = ‫ݎ‬ௗ௦ଵ =
216 kΩ , a low-frequency gain of �� = −��� ���� = −0.416 mA/V × 216 kΩ = −90 V/V ∼
39.1 dB and a bandwidth of ��� �� = 1/(2� ���� �� ) = (2 × � × 216 kΩ × 5 pF)�� =
147.4 kHz.

We may verify gain and output resistance by a ‘.tf ’ simulation. From this, we find a gain
of −89.789 V/V and an output resistance of 215.999 kΩ.

Finally, by running a ‘.ac’ simulation, we verify the −3 dB bandwidth. From the plot below,
we find ݂ିଷ ୢ୆ = 146 kHz, matching the calculated value very well. We may also note that
with a phase shift of 90° at high frequencies, the amplifier has only a single pole, so the gain-
bandwidth product is equal to the unity-gain frequency of 13.4 MHz as indicated in the plot.

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160
CMOS ANALOG IC DESIGN Solution to Problem 14

Next, we repeat the simulations for the cascode amplifier. For this, we need to determine a
value for ܸ஻. This bias voltage should be large enough to keep M1 in the active region. For M1,
we have ����sat = ��� � �� ≃ 0.25 V so the source voltage of M2 should be larger than 0.25 V.
Leaving some margin, we may assume ��� ≃ 0.35 V.. The bulk effect causes an increase of the

threshold voltage of M2. With ܸௌ஻ଶ = 0.35 V , we find ��� = ��� + � ����� + |2Φ� | − ��2Φ� �� =

0.4 V + 0.5 √V × �√0.35 V + 0.7 V − √0.7 V� = 0.494 V . This causes ܸீௌଶ to be ܸீௌଶ =

����sat + ��� = 0.25 V + 0.494 V ≃ 0.75 V, and with ��� ≃ 0.35 V, we find ܸ஻ = ܸௌଶ + ܸீௌଶ =
1.1 V. The bulk transconductance is given by

� 0.5 √V
���� = ��� = 0.4 mA/V × = 0.098 mA/V
2���� + |2Φ� | 2 × √0.35 V + 0.7 V

i.e., a value very close to the specified value of 0.1 mA/V.

The following figure shows the LTspice schematic for simulating the cascode amplifier.

We start by running a ‘.dc’ simulation in order to find the bias value of the input voltage.
As for the common-source stage, this results in an output plot of ‘v(Vo)’ with a very abrupt
change of ‘v(Vo)’ for an input voltage of about 0.65 V. The plot is not shown here. For
finding a reasonable value of the input bias voltage, we use the ‘.meas’ directive shown in
the LTspice schematic. This finds the value of ‫ݒ‬ூே resulting in ‫ݒ‬ை = 1.0 V . The value has

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161
CMOS ANALOG IC DESIGN Solution to Problem 14

been selected slightly higher than for the common-source stage because the cascode transistor
shifts the output voltage range to higher voltage levels. Because of the very high gain in
the cascode stage, the step size for the ‘.dc’ simulation has been selected to be very small,
10 µV. From the error log file, we find ܸூே = 0.645607 V and we insert this value as the
dc value for ‘VIN’.

Next, we may run a ‘.op’ simulation. From this, we may verify that a dc value of 0.645607
V for ‘VIN’ results in an output voltage of 1.0 V, and from the error log file, we find ݃௠ଵ =
0.407 mA/V and ���� = 4.83 μA/V corresponding to ���� = 1/���� = 207 kΩ. For M2,
we find ݃௠ଶ = 0.413 mA/V , ݃௠௕ଶ = 0.100 mA/V and ���� = 4.70 μA/V corresponding
to ‫ݎ‬ௗ௦ଶ = 213 kΩ. These values are close to the values specified for the circuit. From the
error log file, we also verify that both transistors are in the active region with ‘Vds>Vdsat’.

With the simulated small-signal parameters, we expect an output resistance of ���� ≃

(��� + ���� )���� ���� = (0.413 mA/V + 0.1 mA/V) × 213 kΩ × 207 kΩ = 22.6 MΩ . The
expected low-frequency gain is �� = −��� ���� = −0.407 mA/V × 22.6 MΩ = −9.2 ×
10� V/V ∼ 79.3 dB and the bandwidth is ��� �� = 1/(2� ���� �� ) = (2 × � × 22.6 MΩ ×
5 pF)ିଵ = 1.408 kHz.

We may verify gain and output resistance by a ‘.tf ’ simulation. From this, we find a gain
of −9286.01 V/V and an output resistance of 23.0198 MΩ.

Finally, by running a ‘.ac’ simulation, we verify the −3 dB bandwidth. From the following
plot, we find ݂ିଷ ୢ୆ = 1.41 kHz , matching the calculated value very well. We may also note
that with a phase shift of 90° at high frequencies, the amplifier has only a single pole, so
the gain-bandwidth product is equal to the unity-gain frequency of 13 MHz as indicated
in the plot.

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162
CMOS ANALOG IC DESIGN Solution to Problem 14

Finally, we repeat the simulations for the cascade of two common-source stages. Shown
below is the LTspice schematic.

As for the other amplifiers, we start by running a ‘.dc’ simulation in order to find the bias
value of the input voltage. This results in an output plot of ‘v(Vo)’ with a very abrupt change
of ‘v(Vo)’ for an input voltage of about 0.57 V. The following plot shows ‘v(Vo)’ versus
‘v(Vin)’ for an output voltage range of 2 V. We notice that the amplifier is noninverting
because it is a cascade of two inverting gain stages.

From the ‘.meas’ directive, we find that ܸூே = 0.571943 V results in an output voltage
of 0.8 V. The bias value of the input voltage has changed compared to the bias value
for the common source stage and the cascode stage because the bias current for each
transistor has been reduced. This also changes the small-signal parameters. From a ‘.op’

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163
CMOS ANALOG IC DESIGN Solution to Problem 14

simulation, we find ݃௠ଵ = 0.291 mA/V, ���� = 2.37 μA/V corresponding to ���� = 422 kΩ,
݃௠ଶ = 0.294 mA/V and ���� = 2.32 μA/V corresponding to ���� = 431 kΩ. These values
are close to the values calculated in Question 3. From the ‘.op’ simulation, you may also
verify that the gate-source voltage of M2 is 0.57 V, confirming that both M1 and M2 are
in the active region.

With the simulated small-signal parameters, we expect an output resistance of ‫ݎ‬௢௨௧ = ‫ݎ‬ௗ௦ଶ =
431 kΩ. The expected low-frequency gain is �� = ��� ���� ��� ���� = 0.291 mA/V × 422 kΩ ×
0.294 mA/V × 431 kΩ = 15.6 × 10� V/V ∼ 83.8 dB and the bandwidth is ݂ିଷ ୢ୆ = 1/
(2� ���� �� ) = (2 × � × 431 kΩ × 5 pF)�� = 73.9 kHz . We may verify gain and output
resistance by a ‘.tf ’ simulation. From this, we find a gain of 15600.5 V/V and an output
resistance of 431.782 kΩ.

Finally, by running a ‘.ac’ simulation, we verify the −3 dB bandwidth. From the following
plot, we find ݂ିଷ ୢ୆ = 73.7 kHz , matching the calculated value very well. We may also note
that with a phase shift of 90° at high frequencies, the amplifier has only a single pole, so
the gain-bandwidth product is equal to the unity-gain frequency of 1.15 GHz as indicated
in the plot.

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164
CMOS ANALOG IC DESIGN Solution to Problem 15

SOLUTION TO PROBLEM 15

Question 1:
With ܸை = 0 V, the bias current in M1 is equal to the bias current in M3 (and M2) since
the current in ܴ௅ is 0 and M2 - M3 form a current mirror. From this, we find

1
��� = �� ��� (�/�)(��� + ��� − ��� )� = 20 μA
2
� ��� + ��� − ��� = �2 × 20 μA/300 μA/V � = 0.365 V
� ��� = 0.365 V − 1.5 V + 0.5 V = −0.635 V

The voltage ܸோ across ܴ஻ is ܸோ = ܸ஽஽ െ ܸீଶ = 1.5 V + 0.635 V = 2.135 V , resulting in ܴ஻ =

�� /��� = 2.135 V/20 μA = 106.8 kΩ.

Question 2:
The lower limit for the output voltage is found when ݅஽ଵ = 0. For ݅஽ଵ = 0, the current in ܴ௅ is
equal to ‫ܫ‬஽ଷ, i.e., 20 µA. This gives an output voltage of ��min = −�� ��� = −50 kΩ × 20 μA =
−1 V.

For this output voltage, the drain-source voltage of M3 is 0.5 V which is larger than
ܸீௌଷ െ ܸ௧௢ = ܸீଶ + ܸௌௌ െ ܸ௧௢ = 0.365 V, so M3 is in the active region as required.

Note that the source follower only works for input voltages down to ��min + ��� ≃ −0.4 V
(assuming ��� ≃ 0.6 V). For lower values of the input voltage, M1 is no longer in the active
region but in the cut-off region and the output voltage is clamped to −1 V.

The upper limit for the output voltage is reached for ‫ݒ‬ூே = ܸ஽஽ = 1.5 V . In this case
‫ݒ‬ை
݅஽ଵ = ‫ܫ‬஽ଷ +
ܴ௅

and

1
݅஽ଵ = ߤ௡ ‫ܥ‬௢௫ (ܹ/‫ܸ()ܮ‬஽஽ െ ‫ݒ‬ை െ ܸ௧ଵ )ଶ
2

where ܸ௧ଵ = 0.8 V

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165
CMOS ANALOG IC DESIGN Solution to Problem 15

Thus, we have

‫ݒ‬ை 1
‫ܫ‬஽ଷ + = ߤ ‫ܹ( ܥ‬/‫ܸ()ܮ‬஽஽ െ ‫ݒ‬ை െ ܸ௧ଵ )ଶ
ܴ௅ 2 ௡ ௢௫

Inserting numerical values, we get a quadratic equation for ‫ݒ‬ை. The equation has two solutions
for ‫ݒ‬ை, either ‫ݒ‬ை = 1.247 V or ‫ݒ‬ை = 0.286 V. The correct solution is ‫ݒ‬ை = 0.286 V since
only this solution gives a positive value for ‫ீݒ‬ௌଵ െ ܸ௧ଵ. Thus, ܸைmax = 0.286 V.

Question 3:
The following figure shows the low-frequency small-signal diagram for the source follower.
Only transistor M1 appears in the small-signal diagram. Transistors M2 and M3 serve only
to provide the dc bias current for M1 and are thus omitted from the diagram. You may
compare the small-signal diagram to Fig. 4.11 in ‘CMOS Analog IC Design: Fundamentals’.

The small-signal parameters are calculated as follows:

��� = �2�� ��� (�/�)��� = �2 × 300 μA/V � × 20 μA = 109.5 μA/V

���� = ���� = 0.137 × 109.5 μA/V = 15.0 μA/V

The small-signal gain is calculated as follows using a node equation at the output:

��� (��� � �� ) = ���� �� + �� /��

� ��� ��� = (��� + ���� + 1/�� )��
� �� /��� = ��� /(��� + ���� + 1/�� )
= 109.5 μA/V/(109.5 μA/V + 15.0 μA/V + 1/50 kΩ) = 0.758 V/V

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166
CMOS ANALOG IC DESIGN Solution to Problem 15

Question 4:

Shown above is an LTspice schematic corresponding to the source follower. For the transistor
model, we use ‘Kp=150u’ with ‘W=2u’ and ‘L=1u’. This results in �� ��� (�/�) = 300 μA/V �
as specified.

Also, we use ‘Vto=0.5’ and ‘Phi=0.7’ as specified.

The value of ‘Gamma’ is found from ��� = ��� + ������ + |2Φ� | − �|2�� |�.

For ‫ݒ‬ை = ܸைmax = 0.286 V ֜ ‫ݒ‬ௌ஻ = ܸைmax + ܸௌௌ = 1.786 V, we have ܸ௧ଵ = 0.8 V.

This results in � = (��� − ��� )/����� + |2Φ� | − �|2Φ� |� = (0.8 V − 0.5 V)/
�√1.786 V + 0.7 V − √0.7 V� = 0.405 √V .

First, we run a ‘.dc’ simulation with the input voltage swept from െܸௌௌ to ܸ஽஽ . From this
simulation, we plot ‫ݒ‬ை and ݅஽ଵ, see below. We notice that ‫ݒ‬ை = 0 for ‫ݒ‬ூே = 1.127 V and
for this value of ‫ݒ‬ூே, the current ݅஽ଵ is 20 µA as requested. This confirms the calculation
of ܴ஻ in Question 1.

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167
CMOS ANALOG IC DESIGN Solution to Problem 15

From the plot, we also see that the output range of ‫ݒ‬ை is from −1 V to 0.286 V, confirming
the calculations of ܸைmin and ܸைmax in Question 2.

Next, we run a ‘.op’ simulation with the dc value of ‫ݒ‬ூே specified to 1.127 V. From the error
log file from this simulation, we find ��� = 110 μA/V and ���� = 15 μA/V , confirming
the calculations of the small-signal parameters in Question 3.

Finally, we run a ‘.tf ’ simulation for finding the low-frequency gain. From the output file,
we find ‫ݒ‬௢ /‫ݒ‬௜௡ = 0.758071 V/V, confirming the calculation in Question 3.

We may also run a ‘.op’ simulation with ‫ݒ‬ூே = 1.5 V in order to verify the value of the
threshold voltage when ‫ݒ‬ை = ܸைmax . From the error log file from this simulation, we find
ܸ௧ଵ = 0.800 V, confirming the calculation of ߛ for the transistor model.

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168
CMOS ANALOG IC DESIGN Solution to Problem 16

SOLUTION TO PROBLEM 16

Question 1:
From ‫ܫ‬஽ = (1/2)ߤ‫ܥ‬௢௫ (ܹ/‫ீܸ()ܮ‬ௌ െ ܸ௧ )ଶ , we find

2���� 2 × 18 μA
�� = � � = 1 μm × = 8 μm
�� ��� ����� − ��� � 50 μA/V � (−0.3 V)�

Question 2:
For M1 and M2 we have

1 ܹଵ
‫ܫ‬஽ଵ = ߤ௡ ‫ܥ‬௢௫ (ܸீௌଵ െ ܸ௧௡ )ଶ (1 + ߣܸ஽ௌଵ )
2 ‫ܮ‬

and

1 ܹଶ ଶ
‫ܫ‬஽ଶ = ߤ௣ ‫ܥ‬௢௫ ൫ܸீௌଶ െ ܸ௧௣ ൯ (1 + ߣ|ܸ஽ௌଶ |)
2 ‫ܮ‬

From the schematic, we see that ‫ܫ‬஽ଵ = ‫ܫ‬஽ଶ . Also, ���� − ��� = �� − ��� = 0.9 V − 0.6 V =
0.3 V and ���� − ��� = ���� − ��� = −0.3 V. Furthermore, ܸ஽ௌଵ = |ܸ஽ௌଶ | = ܸ஽஽ /2.

Consequently, we find

��� �� ��� �� �� ��� 50 μA/V �

=1=� � � � � �� = � � �� = � � × 8 μm = 2.5 μm
��� �� ��� �� �� ��� 160 μA/V �

Question 3:
The transconductance is given by ݃௠ଵ = 2‫ܫ‬஽ଵ /(ܸீௌଵ െ ܸ௧௡ ) where ‫ܫ‬஽ଵ ؄ ‫ܫ‬஽ହ (neglecting
the channel-length modulation). From this, we find ��� = (2 × 18 μA)/0.3 V = 120 μA/V.

The small-signal gain at low frequencies is given by |‫ܣ‬

|‫ܣ‬௩௩|| = ௠ଵ(‫ݎ‬
= ݃݃௠ଵ (‫ݎ‬ௗ௦ଵ ௗ௦ଶ)) where
ௗ௦ଵ ‫ݎݎ צצ‬ௗ௦ଶ where ‫ݎݎ‬ௗ௦ଵ
where ௗ௦ଵ =
=
���� ≃ 1/(���� ) ≥ 1/(0.1 V �� × 18 μA) = 556 kΩ..

From this, we find |�� | ≥ 0.12 mA/V × 556 kΩ/2 = 33.3 V/V .

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169
 CMOS ANALOG IC DESIGN Solution to Problem 16

Question 4:
The bandwidth of the amplifier is

1
݂଴ =
2ߨ‫ܥ‬௅ (‫ݎ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଶ )

The gain-bandwidth product is

1 ��� 120 μA/V

GBW = |�� |�� = ��� (���� � ���� ) � �= = = 38.2 MHz
2��� (���� � ���� ) 2��� 2 × � × 0.5 pF

Question 5:
From ‫ܫ‬஽ = (1/2)ߤ௡ ‫ܥ‬௢௫ (ܹ/‫ீܸ()ܮ‬ௌ െ ܸ௧௡ )ଶ , we see that with ܹସ = 4Ԝܹଷ, the effective gate
voltage ܸீௌ െ ܸ௧௡ for M4 must be half the effective gate voltage for M3. With M1 identical
in size to M3, we find ܸீௌସ െ ܸ௧௡ = (ܸீௌଷ െ ܸ௧௡ )/2 = (ܸீௌଵ െ ܸ௧௡ )/2 = 0.15 V.

Question 6:

The voltage across ܴ஻ is ܸீௌଷ െ ܸீௌସ = 0.15 V and the current in ܴ஻ is equal to ��� = 18 μA,
so �� = 0.15 V/18 μA = 8.33 kΩ .

Question 7:
Shown below is an LTspice schematic corresponding to the amplifier. For M1 and M2,
(�/�) = 800 μA/V �
, ���models
transistor and � = 0.1 V �� are used while the other transistors are modeled with
= 0.6 Vwith
ߣ = 0. A very large resistor ܴଵ is inserted to ensure that the correct bias point is found for
the bias circuit. If ܴଵ is not included, LTspice finds a bias point where all currents in the
bias circuit are zero, see ‘CMOS Analog IC Design: Fundamentals’, Chapter 8. The resistor
should be inserted between two nodes where a bias point with zero current in all transistors
will result in a voltage across the resistor such that current in the resistor forces the circuit
away from a bias point where the current in all branches is zero.

The supply voltage ܸ஽஽ has (somewhat arbitrarily) been selected to 2.2 V. The exact value
is not important as the value of ܸ஽஽ is not used in the calculations in Questions 1 - 6.

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170
CMOS ANALOG IC DESIGN Solution to Problem 16

From a ‘.op’ simulation, we find the bias point for the circuit. The output file shows
‫ܫ‬஽ହ = 18.0146 μA and ܸை = 1.1045 V, confirming the calculations for Questions 1 and
2, respectively.

The error log file shows ��� = 133 μA/V and ���� = ���� = 1/1.80 μA/V = 555.6 kΩ . The
value of ݃௠ଵ is slightly larger than the value calculated in Question 3 because the channel-
length modulation in M1 and M2 causes the drain current of M1 and M2 to be slightly
larger than 18 µA. With ��� = 133 μA/V and ���� = ���� = 1/1.80 μA/V = 555.6 kΩ , we
expect a low-frequency gain of |�� | = 0.133 mA/V × 555.6 kΩ/2 = 36.9 V/V, showing a
reasonable match to the calculated value.

The error log file also shows ܸீௌସ = 0.75 V as calculated in Question 5, and with ��� = 18.0 μA,,
also the calculation of ܴ஻ in Question 6 is confirmed.

For finding the gain-bandwidth product, we run a ‘.ac’ simulation. The output of this
simulation is shown below.

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171
CMOS ANALOG IC DESIGN Solution to Problem 16

From the plot, we find a low-frequency gain of 31.3 dB corresponding to 36.7 V/V and a
bandwidth of 1.1599 MHz, giving a gain-bandwidth product of 42.6 MHz. Again, we note
a reasonable match to the calculated value from Question 4, the difference being caused
by the slightly larger simulated value of ݃௠ଵ. From the frequency response, we may also
note that the system has only a single pole so the gain-bandwidth product is equal to the
unity-gain frequency found to be 42.5 MHz in the plot of ܸ௢.

Also from Question 4, we notice that the gain-bandwidth product does not depend on the output
resistances ‫ݎ‬ௗ௦ଵ and ‫ݎ‬ௗ௦ଶ . Thus, the gain-bandwidth will show only a weak dependence on ߣ
through the transconductance ݃௠ଵ, depending on ߣ by the relation ��� = �� ��� (�� /�)(�� −
ܸ௧௡ )(1 + ߣܸ஽ௌଵ ) = ߤ௡ ‫ܥ‬௢௫ (ܹଵ /‫ܸ()ܮ‬஻ െ ܸ௧௡ )(1 + ߣܸ஽஽ /2). This may be verified by a simulation
with different values of ߣ but this is an exercise left for the reader.

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172
CMOS ANALOG IC DESIGN Solution to Problem 17

SOLUTION TO PROBLEM 17

Question 1:
We find the voltage ܸோ஻ across ܴ஻ as the bandgap voltage ܸ஻ீ minus the gate-source ܸீௌଵ
of transistor M1.

ܸீௌଵ is found from

1 ܹ
‫ܫ‬஽ଵ = ߤ௡ ‫ܥ‬௢௫ (ܸீௌଵ െ ܸ௧௡ )ଶ
2 ‫ܮ‬

where ‫ܫ‬஽ଵ = ‫ܫ‬஽ଶ = ‫ܫ‬஽ଷ = ‫ܫ‬஻ூ஺ௌ .

2������ 2 × 20 μA
���� = ��� + � = 0.6 V + � = 0.916 V
�� ��� (�/�) 160 μA/V � × 2.5

��� = ��� − ���� = 1.24 V − 0.916 V = 0.324 V

�� = ��� /����� = 0.324 V/20 μA = 16.2 kΩ

Question 2:
To ensure M2 and M1 in the active region, we have ܸ஽஽min = |ܸீௌଶ | + ܸ஽ௌଵmin + ܸோ஻ where
����min = ����sat = ���� − ��� = 0.916 V − 0.6 V = 0.316 V .

|ܸீௌଶ | is found from

1 ܹ ଶ
‫ܫ‬஽ଶ = ߤ௣ ‫ܥ‬௢௫ ൫ܸீௌଶ െ ܸ௧௣ ൯
2 ‫ܮ‬

2������ 2 × 20 μA
⇒ |���� | = ���� � + � = 0.6 V + � = 1.166 V
�� ��� (�/�) 50 μA/V� × 2.5

Hence, ܸ஽஽min = 1.166 V + 0.316 V + 0.324 V = 1.806 V.

Also M3 should be in the active region. This requires |���� | ≥ |���� | � ���� � = |���� | � ���� � =
0.566 V . With ܸ௅ = 1.0 V and ܸ஽஽ = 1.806 V, we find |���� | = 1.806 V − 1.0 V = 0.806 V >
0.566 V , so the condition for active region for M3 is fulfilled with ܸ஽஽ = 1.806 V .

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173
CMOS ANALOG IC DESIGN Solution to Problem 17

Question 3:
The maximum value of ܸ௅ is ��� − |����min | = ��� − �|���� | − ���� �� = 3.0 V − 0.566 V =
2.434 V. Transistors M1 and M2 are in the active region since ܸ஽஽ is larger than the minimum
value of ܸ஽஽ calculated in the previous question.

Question 4:

Shown above is an LTspice schematic corresponding to the bias circuit. From a ‘.op’
simulation, we find the current ‫ܫ‬஻ூ஺ௌ from the output file as the current ‘I(Vl)’ = 19.9906
µA as required, thus confirming the calculation of ܴ஻. From the error log file, we verify
that all transistors have ‘|Vds|>|Vdsat|’ so they are all in the active region.

Running a ‘.dc’ simulation with ܸ஽஽ swept from 1 V to 3 V, we obtain the plot of ‫ܫ‬஻ூ஺ௌ
shown below. From this, we see that the minimum value of ܸ஽஽ required for ����� = 20 μA
is 1.806 V as also found in Question 2.

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174
CMOS ANALOG IC DESIGN Solution to Problem 17

Running a ‘.dc’ simulation with ܸ௅ swept from 1 V to 3 V, we obtain the plot of ‫ܫ‬஻ூ஺ௌ
shown below. From this, we see that the maximum value of ܸ௅ for which ����� = 20 μA is
2.434 V as also found in Question 3.

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175
CMOS ANALOG IC DESIGN Solution to Problem 18

SOLUTION TO PROBLEM 18

Question 1:
We find the feedback factor ߚ = ܴଶ /(ܴଵ + ܴଶ ) = 0.1 and we have the amplifier gain at
low frequencies as ‫ܣ‬଴ = 50 V/V (corresponding to 34 dB).

The low-frequency closed-loop gain is found from

‫ܣ‬଴ 50 V/V
‫ܣ‬஼௅ = = = 8.33 V/V
1 + ߚ‫ܣ‬଴ 1 + 0.1 × 50 V/V

This corresponds to 18.4 dB.

Question 2:
The −3 dB bandwidth of the amplifier with feedback is the −3 dB bandwidth of the basic
amplifier multiplied by the amount of feedback which is 1 + ߚ‫ܣ‬଴ = 6.

The −3 dB bandwidth of the basic amplifier is given by the pole frequency of 2 MHz, so
the −3 dB bandwidth of the amplifier with feedback is 6 × 2 MHz = 12 MHz.

This can also be found from the relation

‫)݂݆(ܣ‬ ‫ܣ‬଴ /൫1 + ݆݂/݂௣ଵ ൯ ‫ܣ‬଴ 1

‫ܣ‬஼௅ (݆݂) = = =൬ ൰ቌ ቍ
1 + ߚ‫ )݂݆(ܣ‬1 + ߚ‫ܣ‬଴ /൫1 + ݆݂/݂௣ଵ ൯ 1 + ߚ‫ܣ‬଴ 1 + ݆݂/ ቀ݂ (1 + ߚ‫) ܣ‬ቁ
௣ଵ ଴

giving a bandwidth with feedback of ݂௣ଵ (1 + ߚ‫ܣ‬଴ ) = 12 MHz.

Question 3:
The loop gain is

ܴଶ ‫ܣ‬଴ (1 െ ݆݂/݂௭ )
‫ = )݂݆(ܣߚ = )݂݆(ܮ‬൬ ൰ቆ ቇ
ܴଵ + ܴଶ ൫1 + ݆݂/݂௣ଵ ൯൫1 + ݆݂/݂௣ଶ ൯

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176
CMOS ANALOG IC DESIGN Solution to Problem 18

The following figure shows the Bode plot. The amplitude plot starts at 14 dB corresponding
to a loop gain of ‫ܮ‬଴ = ‫ܣ‬଴ ߚ = 5 V/V at very low frequencies. The first breakpoint appears
at the pole frequency ݂௣ଵ = 2 MHz where the slope of the amplitude plot changes to −20
dB/dec. The second breakpoint appears at the zero frequency ݂௭ = 20 MHz where the slope
of the amplitude plot changes back to 0 dB/dec. The third breakpoint appears at the pole
frequency ݂௣ଶ = 200 MHz where the slope of the amplitude plot changes to −20 dB/dec.

The phase plot (black plot) is the sum of the red, green and blue plots corresponding to
the phase shifts from ݂௣ଵ, ݂௭ and ݂௣ଶ, respectively.

From the Bode plot, we estimate a phase margin of 72°.

A more accurate analytical calculation gives the following: The frequency ݂௧ for which the
loop gain is 0 dB is found from

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177
CMOS ANALOG IC DESIGN Solution to Problem 18

݂௧
0.1 × 50 × ൬1 െ ݆ 20 MHz൰
ተ ተ = 1 ֜ ݂௧ = 11.3 MHz
݂௧ ݂௧
൬1 + ݆ 2 MHz൰ ൬1 + ݆ 200 MHz൰

At ݂௧ = 11.3 MHz, we find:

�� �� ��
��(��� ) = − arctan � � − arctan � � − arctan � �
�� ��� ���
11.3 MHz 11.3 MHz 11.3 MHz
= − arctan � � − arctan � � − arctan � �
20 MHz 2 MHz 200 MHz
= −29.5° − 80.0° − 3.2° = −112.7°

From this, we find a phase margin of 180° − 112.7° = 67.3°.

Question 4:
The LTspice schematic shown below models the gain function
ܸ௢ (݆݂) ‫ܣ‬଴ (1 െ ݆݂/݂௭ )
‫= )݂݆(ܣ‬ =
ܸ௜ௗ (݆݂) ൫1 + ݆݂/݂௣ଵ ൯൫1 + ݆݂/݂௣ଶ ൯

and the ߚ-network is implemented by the resistors ܴଵ and ܴଶ. The gain function is implemented
using filter blocks similar to those described in Example 5.3 in ‘CMOS Integrated Circuit
Simulation with LTspice’. The zero is defined by the parameter ‘fz1’ and since it is a right-
half-plane zero, it is defined with a negative value, i.e., ‘.param fz1=-20Meg’. The poles are
defined by the parameters ‘fp1’ and ‘fp2’.

From a ‘.ac’ simulation, we plot the loop gain as ‘v(Vf )’. We find a phase shift of −112.5°
when the loop gain is 0 dB, corresponding to a phase margin of 67.5°.

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178
CMOS ANALOG IC DESIGN Solution to Problem 18

The phase margin may also be found using the ‘.meas’ directive shown in the LTspice
schematic.

The phase margin is PM = 180° � ����(��� )� = 180° + ���(��� )� = ����(��� )� where

‫ )݂݆(ܮ‬is the loop gain and ݂௧ is the frequency where |‫ |)݂݆(ܮ‬has dropped to a value of 1.

Thus, the phase of ‘-v(Vf )’ is equal to the phase margin when the magnitude of ‘v(Vf )’ is
equal to 1. The result of the ‘.meas’ directive is found in the error log file which shows a
phase margin of 67.3751°. Thus, the simulated results match the exact calculation of the
phase margin very well.

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179
CMOS ANALOG IC DESIGN Solution to Problem 19

SOLUTION TO PROBLEM 19

Question 1:
For finding a relationship between the small-signal gain and the bias current, we examine
the small-signal diagram for the amplifier. The small-signal diagram is shown below.

With the capacitor ‫ ܥ‬being so large that it can be treated as a short circuit and the resistor ܴ
being so large that it does not affect the small-signal gain, we have ‫ݒ‬௚௦ଵ = ‫ݒ‬௜௡. At low frequencies
where ‫ܥ‬௅ can be treated as an open circuit, we find ‫ݒ‬௢ = െ݃௠ଵ ‫ݒ‬௚௦ଵ ‫ݎ‬ௗ௦ଵ ֜ ‫ܣ‬଴ = െ݃௠ଵ ‫ݎ‬ௗ௦ଵ .

Assuming 1 + ����� ≃ 1, we have

��� ≃ �2�� ��� (�/�)��

and

1
���� ≃
���

From this, we find

1 1 2�� ��� (�/�)

�� = −��� ���� ≃ − ��2�� ��� (�/�)�� �� � � = −� ��
��� � ��
1 � 1 �
� �� ≃ 2 � � �� ��� (�/�) = 2 × � � × 800 μA/V � = 25 μA
�|�� | 0.1 V �� × 80

Question 2:
As there is no dc current flowing in ‫ ܥ‬and no dc current flowing into the gate of M1, a
node equation at the gate of M1 shows that also the dc current in ܴ is zero. Hence, the
voltage across ܴ is zero and the quiescent value of the drain voltage of M1 is equal to the
quiescent value of the gate voltage of M1, leading to
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180
CMOS ANALOG IC DESIGN Solution to Problem 19

2�� 2 × 25 μA
�� = ���� = ���� = ��� + � = 0.6 V + � = 0.85 V
�� ��� (�/�) 800 μA/V �

Question 3:
Neglecting the transistor capacitances, the bandwidth ݂௣ of the amplifier is given by ‫ܥ‬௅ and
‫ݎ‬ௗ௦ଵ, i.e., ݂௣ = 1/(2ԜߨԜ‫ݎ‬ௗ௦ଵ ‫ܥ‬௅ ). Thus, the gain-bandwidth product is
|‫ܣ‬଴ | ݃௠ଵ ‫ݎ‬ௗ௦ଵ ݃௠ଵ
GBW = = =
2ԜߨԜ‫ݎ‬ௗ௦ଵ ‫ܥ‬௅ 2ԜߨԜ‫ݎ‬ௗ௦ଵ ‫ܥ‬௅ 2ԜߨԜ‫ܥ‬௅

From this, we find

��� �2�� ��� (�/�)�� �2 × 800 μA/V � × 25 μA

�� = ≃ = = 0.106 pF
2���GBW 2���GBW 2 × � × 300 MHz

Question 4:
In the small-signal diagram, a load resistor from the current source appears in parallel with
‫ݎ‬ௗ௦ଵ. The load resistor from the current source is approximately 1/(ߣ‫ܫ‬஻ ), so when ߣ for the
current source has the same value as ߣ for M1, the load resistor from the current source
is approximately equal to ‫ݎ‬ௗ௦ଵ. This causes the low-frequency gain to be halved and the
bandwidth to be doubled. The gain-bandwidth product remains unchanged.

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181
CMOS ANALOG IC DESIGN Solution to Problem 20

SOLUTION TO PROBLEM 20

Question 1:
The bias current of M1 is

��� − �� 3V−2V
��� = �� + = 100 μA + = 110 μA
�� 100 kΩ

From

1 ܹଵ
‫ܫ‬஽ଵ = ߤ௡ ‫ܥ‬௢௫ (ܸ െ ܸ௧௡ )ଶ
2 ‫ீ ܮ‬ௌଵ

we find with ܸீௌଵ = ܸீீ :

2���� �� 2 × 110 μA × 1 μm
�� = = = 5.5 μm
�� ��� (��� − ��� ) � 160 μA/V � × (1 V − 0.5 V)�

The question can also be solved by LTspice:

Shown below is an LTspice schematic for the circuit where the channel width ܹଵ has been
defined as a parameter. By running a ‘.op’ simulation with ܹଵ stepped from 3 µm to 8
µm, we can obtain a plot of ܸை versus ܹଵ as also shown below. From the plot, we find
��==22VVfor
�� for�
for ���==5.5
5.5μm
μm.

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182
CMOS ANALOG IC DESIGN Solution to Problem 20

Question 2:
The small-signal diagram is shown below.

For calculating the gain, we need the transconductance ݃௠ଵ:

2���� 2 × 100 μA
��� = = = 0.44 mA/V
���� − ��� 1 V − 0.5 V

At low frequencies, the capacitor ‫ܥ‬௖ is treated as an open circuit, so a node equation at the
output node results in ݃௠ଵ ‫ݒ‬௚௦ = ‫ݒ‬௢ /‫ݎ‬௢ . Also, ‫ݒ‬௚௦ = ‫ݒ‬௦ since the dc current through ܴ௦ is
0. From this, we find the small-signal gain at low frequencies as:

��� = �� /�� = −��� �� = −0.44 mA/V × 100 kΩ = −44 V/V

Question 3:
The capacitor ‫ܥ‬௖ between input and output gives rise to an input capacitance which is found
from the Miller transformation:

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183
CMOS ANALOG IC DESIGN Solution to Problem 20

‫ܥ‬௜௡ = (1 + |‫ܣ‬௩௦ |)‫ܥ‬௖ = (1 + 44) × 1.2 pF = 54 pF

Together with ܴ௦, the input capacitance creates a pole which defines the −3 dB bandwidth:

1 1
��� �� = = = 5.89 kHz
2���� ��� 2 × � × 500 kΩ × 54 pF

The bandwidth may also be found using a ‘.ac’ simulation (shown as a comment in the
previous LTspice schematic). For this simulation, the ‘.step param’ directive should be
turned into a comment. Also remember to define the ac amplitude of ‘Vs’. From the
simulation, we find the following plot. From this, we find a low-frequency gain of 32.9
dB corresponding to −44.2 V/V and we find a bandwidth of 5.9 kHz. Both values match
the calculated values very well.

Question 4:
We have

ͳ ܹଶ ଶ
‫ܫ‬஽ଵ ൌ ‫ܫ‬஽ଶ ൌ ߤ௣ ‫ܥ‬௢௫ ൫ܸீௌଶ െ ܸ௧௣ ൯ ሺͳ ൅ ߣȁܸ஽ௌଶ ȁሻ
ʹ ‫ܮ‬

ͳ ܹଶ ଶ ͳ ܹଶ ଶ
ൌ ߤ௣ ‫ܥ‬௢௫ ൫ܸீௌଶ െ ܸ௧௣ ൯ ൅ ߤ௣ ‫ܥ‬௢௫ ൫ܸீௌଶ െ ܸ௧௣ ൯ ߣȁܸ஽ௌଶ ȁ
ʹ ‫ܮ‬ ʹ ‫ܮ‬

In this expression, the first term is constant (independent of ȁܸ஽ௌଶ ȁ) and the second term
is proportional to ȁܸ஽ௌଶ ȁ.

We also have

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184
CMOS ANALOG IC DESIGN Solution to Problem 20

ܸ஽஽ െ ܸை ȁܸ஽ௌଶ ȁ
‫ܫ‬஽ଵ ൌ ‫ܫ‬஻ ൅ ൌ ‫ܫ‬஻ ൅
‫ݎ‬௢ ‫ݎ‬௢

This expression also has a first term which is constant (independent of ȁܸ஽ௌଶ ȁ) and a second
term which is proportional to ȁܸ஽ௌଶ ȁ.

By equating the terms which are independent of ȁܸ஽ௌଶ ȁ and using หܸீௌଶ െ ܸ௧௣ ห ൌ ͲǤͷ,
we find

ͳ ܹଶ ଶ
‫ܫ‬஻ ൌ ߤ௣ ‫ܥ‬௢௫ ൫ܸீௌଶ െ ܸ௧௣ ൯
ʹ ‫ܮ‬

ʹԜ‫ܫ‬஻ Ԝ‫ܮ‬ ʹ ൈ ͳͲͲɊ ൈ ͳɊ

֜ ܹଶ ൌ ଶ ൌ ൌ ͳ͸Ɋ
ߤ௣ ‫ܥ‬௢௫ ൫ܸீௌଶ െ ܸ௧௣ ൯ ͷͲɊȀ ଶ ൈ ሺͲǤͷሻଶ

Questi on 5:
By equating the terms in the expressions for ‫ܫ‬஽ଵ which are proportional to ȁܸ஽ௌଶ ȁ, we find:

ȁܸ஽ௌଶ ȁ ͳ ܹଶ ଶ
ൌ ߤ௣ ‫ܥ‬௢௫ ൫ܸீௌଶ െ ܸ௧௣ ൯ Ԝߣȁܸ஽ௌଶ ȁ ൌ ‫ܫ‬஻ ߣȁܸ஽ௌଶ ȁ
‫ݎ‬௢ ʹ ‫ܮ‬
ͳ ͳ
֜ߣൌ ൌ ൌ ͲǤͳ ିଵ
‫ݎ‬௢ ‫ܫ‬஻ ͳͲͲȳ ൈ ͳͲͲɊ

Question 6:

For M2, we have ‫ܫ‬஽ଶ ൌ ‫ܫ‬஽ଵ ൌ ͳͳͲɊ and ܸ஽ௌଶ ൌ ܸை െ ܸ஽஽ ൌ ʹ െ ͵ ൌ െͳ . Since M3
- M2 form a current mirror, we also have ‫ܫ‬஽ଷ ൌ ‫ܫ‬஽ଶ ൌ ͳͳͲɊ and ܸ஽ௌଷ ൌ ܸ஽ௌଶ ൌ െͳ.
Thus, the voltage across ܴ஻ is ܸோ஻ ൌ ܸ஽஽ ൅ ܸ஽ௌଷ ൌ ʹ and the current in ܴ஻ is equal to
‫ܫ‬஽ଷ ൌ ͳͳͲɊ , so ܴ஻ ൌ ܸோ஻ Ȁ‫ܫ‬஽ଷ ൌ ʹȀͳͳͲɊ ൌ ͳͺǤͳͺȳ.

The results for Questions 4 - 6 may be verified by an LTspice simulation. The following
figure shows the LTspice schematic. From the error log file shown below, we may verify all
bias values, and we may verify the value of ‫ݎ‬௢ as ‘1/Gds’ for M2. The error log file shows
݃ௗ௦ଶ ൌ ͳͲɊȀ ֜ ‫ݎ‬௢ ൌ ͳͲͲȳ as specified.

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185
CMOS ANALOG IC DESIGN Solution to Problem 20

Error log file

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186
CMOS ANALOG IC DESIGN Solution to Problem 21

SOLUTION TO PROBLEM 21

Question 1:
We find the feedback factor ߚ ൌ ܴଶ Ȁሺܴଵ ൅ ܴଶ ሻ ൌ ͲǤͳͳͳ and we have the amplifier gain at
low frequencies as ‫ܣ‬଴ ൌ ʹͲͲȀ (corresponding to 46 dB).

The low-frequency closed-loop gain is found from

‫ܣ‬଴ ʹͲͲ
‫ܣ‬஼௅ ൌ ൌ ൌ ͺǤ͸ͳȀ
ͳ ൅ ߚ‫ܣ‬଴ ͳ ൅ ͲǤͳͳͳ ൈ ʹͲͲ

This corresponds to 18.7 dB.

Using LTspice, see schematic below, the gain can be simulated by a ’.tf ’ simulation.

From the output file, we see ‫ܣ‬஼௅ ൌ ͺǤ͸ͳʹͶͶȀ.

Question 2:
The −3 dB bandwidth of the amplifier with feedback is the −3 dB bandwidth of the basic
amplifier multiplied by the amount of feedback which is ͳ ൅ ߚ‫ܣ‬଴ ൌ ͳ ൅ ͲǤͳͳͳ ൈ ʹͲͲ ൌ ʹ͵Ǥʹʹ.

The −3 dB bandwidth of the basic amplifier is given by the pole frequency which is 270 kHz,
so the −3 dB bandwidth of the amplifier with feedback is 23.22 × 270 kHz = 6.27 MHz.

This can also be found from the relation

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187
CMOS ANALOG IC DESIGN Solution to Problem 21

‫ܣ‬ሺ݆݂ሻ ‫ܣ‬଴ Ȁ൫ͳ ൅ ݆݂Ȁ݂௣ଵ ൯ ‫ܣ‬଴ ͳ

‫ܣ‬஼௅ ሺ݆݂ሻ ൌ ൌ ൌ൬ ൰ቌ ቍ
ͳ ൅ ߚ‫ܣ‬ሺ݆݂ሻ ͳ ൅ ߚ‫ܣ‬଴ Ȁ൫ͳ ൅ ݆݂Ȁ݂௣ଵ ൯ ͳ ൅ ߚ‫ܣ‬଴ ͳ ൅ ݆݂Ȁ ቀ݂ ሺͳ ൅ ߚ‫ ܣ‬ሻቁ
௣ଵ ଴

giving a bandwidth with feedback of ݂௣ଵ ሺͳ ൅ ߚ‫ܣ‬଴ ሻ ൌ ͸Ǥʹ͹ œ .

Using LTspice, the frequency response can be simulated by a ‘.ac’ simulation. The transfer
function for ‫ܣ‬ሺ݆݂ሻ is implemented by introducing a low-pass RC network comprising ‫ܥ‬ଵ
and ܴଷ as shown in the following figure. From the output plot, we find a bandwidth of
6.3 MHz.

Question 3:
The loop gain at low frequencies is ‫ܮ‬଴ ൌ ‫ܣ‬௢ Ԝܴଶ Ȁሺܴଵ ൅ ܴଶ ሻ ൌ ʹʹǤʹʹȀ, i.e., the unity-gain
frequency for the loop gain is much larger than the pole frequency. Thus, the phase shift
of the loop gain at the unity-gain frequency is approximately 90°, so the phase margin is
(approximately) 180° − 90° = 90°.

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188
CMOS ANALOG IC DESIGN Solution to Problem 21

A more accurate calculation is the following: The loop gain is

ܴଶ ‫ܣ‬଴ ‫ܮ‬଴
‫ܮ‬ሺ݆݂ሻ ൌ ൬ ൰ቆ ቇൌ
ܴଵ ൅ ܴଶ ͳ ൅ ݆݂Ȁ݂௣ଵ ͳ ൅ ݆݂Ȁ݂௣ଵ

where ‫ܮ‬଴ ൌ ‫ܣ‬௢ Ԝܴଶ Ȁሺܴଵ ൅ ܴଶ ሻ ൌ ʹʹǤʹʹȀ, corresponding to 26.9 dB.

The frequency ݂௧ for which the loop gain has dropped to 0 dB is found from ‫ܮ‬ଶ଴ ൌ ͳ ൅
ଶ
൫݂௧ Ȁ݂௣ଵ ൯ ֜ ݂௧ ൌ ݂௣ଵ ඥ‫ܮ‬ଶ଴ െ ͳ ൌ ʹ͹Ͳ œ ൈ ξʹʹǤʹʹଶ െ ͳ ൌ ͷǤͻͻ œ . At this frequency,
‫ܮס‬ሺ݆݂ሻ ൌ െ ƒ” –ƒሺͷǤͻͻ œȀʹ͹Ͳ œሻ ൌ െͺ͹ǤͶι,, so the phase margin is 180° − 87.4°
= 92.6°.

The phase margin may be verified by an LTspice simulation. Shown in the following figure
is a schematic for simulating the loop gain. From the simulation, we find a phase shift of
−87.4° when the loop gain has dropped to 0 dB, so the phase margin is 180° − 87.4° = 92.6°.

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189
CMOS ANALOG IC DESIGN Solution to Problem 21

Question 4:
With ‫ܥ‬௣ included, the feedback factor is

ିଵ ିଵ
ܴଶ ‫ צ‬൫݆ʹߨ݂‫ܥ‬௣ ൯ ൫݆ʹߨ݂‫ܥ‬௣ ൅ ͳȀܴଶ ൯
ߚሺ݆݂ሻ ൌ ିଵ ൌ ିଵ
ܴଵ ൅ ቀܴଶ ‫ צ‬൫ʹߨ݂‫ܥ‬௣ ൯ ቁ ܴଵ ൅ ൫݆ʹߨ݂‫ܥ‬௣ ൅ ͳȀܴଶ ൯
ͳ ܴଶ ܴଶ ͳ
ൌ ൌ ൌ൬ ൰ቆ ቇ
ܴଵ ൫݆ʹߨ݂‫ܥ‬௣ ൅ ͳȀܴଶ ൯ ൅ ͳ ܴଵ ൅ ܴଶ ൅ ݆ʹߨ݂‫ܥ‬௣ ܴଵ ܴଶ ܴଵ ൅ ܴଶ ͳ ൅ ݆ʹߨ݂‫ܥ‬௣ ሺܴଵ ‫ܴ צ‬ଶ ሻ

The loop gain is

ܴଶ ͳ ‫ܣ‬଴
‫ܮ‬ሺ݆݂ሻ ൌ ߚሺ݆݂ሻ‫ܣ‬ሺ݆݂ሻ ൌ ൬ ൰ቆ ቇቆ ቇ
ܴଵ ൅ ܴଶ ͳ ൅ ݆ʹߨ݂‫ܥ‬௣ ሺܴଵ ‫ܴ צ‬ଶ ሻ ͳ ൅ ݆݂Ȁ݂௣ଵ
‫ܮ‬଴
ൌ
൫ͳ ൅ ݆݂Ȁ݂௣ଵ ൯൫ͳ ൅ ݆݂Ȁ݂௣ଶ ൯

where ‫ܮ‬଴ ൌ ‫ܣ‬௢ Ԝܴଶ Ȁሺܴଵ ൅ ܴଶ ሻ ൌ ʹʹǤʹʹȀ ‫ʹ ׽‬͸Ǥͻ†, ݂௣ଵ ൌ ʹ͹Ͳ œ and

݂௣ଶ ൌ ͳȀ ቀʹߨ‫ܥ‬௣ ሺܴଵ ‫ܴ צ‬ଶ ሻቁ ൌ ͷǤͻ͹ œ..

The following figure shows the Bode plot. The amplitude plot starts at 26.9 dB. The first
breakpoint appears at the pole frequency ݂௣ଵ ൌ ʹ͹Ͳ œ where the slope of the amplitude plot
changes to −20 dB/dec. The second breakpoint appears at the pole frequency ݂௣ଶ ൌ ͷǤͻ͹ œ
where the slope of the amplitude plot changes to −40 dB/dec.

The phase plot (black plot) is the sum of the red plot and the green plot corresponding to
the phase shifts from ݂௣ଵ and ݂௣ଶ , respectively.

From the Bode plot, the phase margin is estimated to 45°.

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190
CMOS ANALOG IC DESIGN Solution to Problem 21

Question 5:
A better estimate of the phase margin can be found by observing that the feedback amplifier
is a second-order system with a gain-bandwidth product of the loop gain of ݂௧௟ ൌ ‫ܮ‬଴ ݂௣ଵ ൌ
ʹʹǤʹʹȀ ൈ ʹ͹Ͳ œ ൌ ͸ǤͲ œ and a non-dominant pole ݂௣ଶ ൌ ͷǤͻ͹ œ . Thus,
݂௣ଶ Ȁ݂௧௟ ؄ ͳ and from Fig. 6.35(a) in ‘CMOS Analog IC Design: Fundamentals’, we find
that the phase margin is  ؄ ͷʹι when assuming that the phase shift from the dominant
pole is 90°. In Question 4, we found a phase shift of about 87.4° at a frequency of 6 MHz,
so about 2.6° can be added to the phase margin estimated from Fig. 6.35(a), resulting in
an estimate for the phase margin of  ؄ ͷͶǤ͸ι.

The phase margin may also be found using a analytical approach. We find the unity-
gain frequency ݂௧ of the loop gain and find the phase of the loop gain at the unity-gain
frequency as follows:

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191
CMOS ANALOG IC DESIGN Solution to Problem 21

ʹʹǤʹʹ
ฬ ฬ ൌ ͳ ֜ ݂௧ ൌ ͶǤ͹Ͳ œ
ሺͳ ൅ ݆݂௧ Ȁʹ͹Ͳ œሻሺͳ ൅ ݆݂௧ ȀͷǤͻ͹ œሻ

With ݂ ൌ ݂௧ , we find

䌴‫ܮ‬ሺ݆݂௧ ሻ ൌ െ ƒ” –ƒ൫݂௧ Ȁ݂௣ଵ ൯ െ ƒ” –ƒ൫݂௧ Ȁ݂௣ଶ ൯

ൌ െ ƒ” –ƒሺͶǤ͹Ͳ œȀʹ͹Ͳ œሻ െ ƒ” –ƒሺͶǤ͹Ͳ œȀͷǤͻ͹ œሻ

ൌ െͺ͸Ǥ͹ι െ ͵ͺǤʹι ൌ െͳʹͶǤͻι

From this, we find a phase margin of  ൌ ͳͺͲι ൅ ‫ܮס‬ሺ݆݂௧ ሻ ൌ ͳͺͲι െ ͳʹͶǤͻι ൌ ͷͷǤͳιǤ

Alternatively, we may use LTspice to simulate the loop gain. We modify the previous
LTspice schematic by inserting ‫ܥ‬௣ and run a ‘.ac’ simulation, resulting in the simulation
plot shown below. From the plot, we find a phase shift of 125.1° when the loop gain is 0
dB, corresponding to a phase margin of 54.9°, i.e., a value very close to the calculated value.

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192
CMOS ANALOG IC DESIGN Solution to Problem 22

SOLUTION TO PROBLEM 22

Question 1:
With ߣ ൌ Ͳ ିଵ for M1, the bias current of M1 is

ͳ ܹଵ
‫ܫ‬஽ଵ ൌ ߤ௡ ‫ܥ‬௢௫ ሺܸ െ ܸ௧௡ ሻଶ
ʹ ‫ܮ‬ଵ ூே

which results in

ʹԜ‫ܫ‬஽ଵ ʹ ൈ ʹͷͲɊ
ܸூே ൌ ܸ௧௡ ൅ ඨ ൌ ͲǤ͸ ൅ ඨ ൌ ͳǤͳͲ
ߤ௡ ‫ܥ‬௢௫ ሺܹଵ Ȁ‫ܮ‬ଵ ሻ ʹͲͲɊȀ ଶ ൈ ሺͳͲɊȀͳɊሻ

Question 2:
For the PMOS transistor M2, the current is given by

ͳ ܹଶ ଶ
‫ܫ‬஽ଶ ൌ ߤ௣ ‫ܥ‬௢௫ ൫ܸ஽஽ െ ܸ஻ଵ െ หܸ௧௣ ห൯ ቀͳ ൅ ߣ௣ ሺܸ஽஽ െ ܸை ሻቁ
ʹ ‫ܮ‬ଶ

With ‫ܫ‬஽ଵ ൌ ‫ܫ‬஽ଶ , this results in

ʹԜ‫ܫ‬஽ଵ
ܸ஻ଵ ൌ ܸ஽஽ െ หܸ௧௣ ห െ ඨ
ߤ௣ ‫ܥ‬௢௫ ሺܹଶ Ȁ‫ܮ‬ଶ ሻ ቀͳ ൅ ߣ௣ ሺܸ஽஽ െ ܸை ሻቁ

ʹ ൈ ʹͷͲɊ
ൌ ͵Ǥ͵ െ ͲǤ͸ െ ඨ
͸ͲɊȀ ଶ ൈ ሺͳͲɊȀͲǤ͵ͷɊሻ ൈ ൫ͳ ൅ ͲǤͳ ିଵ ൈ ሺ͵Ǥ͵ െ ͳǤͺሻ൯

ൌ ʹǤͳͻ͸Ͷ

The value of ܸ஻ଵ has been calculated with high precision because the output voltage is very
sensitive to even small variations in ܸ஻ଵ . The small-signal gain from ܸ஻ଵ to the output is
about the same as the small-signal gain from the input voltage to the output. This may be
illustrated by an LTspice simulation. The following figure shows an LTspice schematic with
simulation directives for a dc sweep of the bias voltage ܸ஻ଵ , a ‘.op’ simulation for finding

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193
CMOS ANALOG IC DESIGN Solution to Problem 22

the bias point and the small-signal parameters, a ‘.tf ’ simulation for finding the small-signal
gain and output impedance at low frequencies (Question 3) and a ‘.ac’ simulation for finding
the input capacitance (Question 4).

Also included is a ‘.tf ’ simulation directive for finding the small-signal gain from ܸ஻ଵ to
the output.

The plot of the output voltage versus the bias voltage ܸ஻ଵ is shown below. From the plot,
we find that ܸ஻ଵ ൌ ʹǤͳͻ͸Ͷ results in ܸை ൌ ͳǤͺ and we also see that the curve showing
the output voltage versus the bias voltage is very steep, so even a small error in ܸ஻ଵ causes
a large error in ܸை . The ‘.tf ’ simulation with ܸ஻ଵ as the input shows a small-signal gain of
−45.7 V/V from ܸ஻ଵ to the output.

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194
CMOS ANALOG IC DESIGN Solution to Problem 22

Question 3:
In the small-signal diagram, ‫ݎ‬ௗ௦ଵ is infinite because the channel-length modulation is neglected
for M1, and for M2, only ‫ݎ‬ௗ௦ଶ appears because the gate voltage to M2 is a dc voltage. The
following figure shows the small-signal diagram.

At low frequencies, both capacitors are treated as open circuits, so a node equation at the
output gives ݃௠ଵ ‫ݒ‬௜௡ ൅ ‫ݒ‬௢ Ȁ‫ݎ‬ௗ௦ଶ ൌ Ͳ. From this, we find the low-frequency gain ‫ܣ‬௩ ൌ ‫ݒ‬௢ Ȁ‫ݒ‬௜௡ ൌ
െ݃௠ଵ Ԝ‫ݎ‬ௗ௦ଶ ൌ െ݃௠ଵ Ȁ݃ௗ௦ଶ .

We find the small-signal parameters ݃௠ଵ and ݃ௗ௦ଶ from

݃௠ଵ ൌ ߤ௡ ‫ܥ‬௢௫ ሺܹଵ Ȁ‫ܮ‬ଵ ሻሺܸூே െ ܸ௧௡ ሻ ൌ ʹͲͲɊȀ ଶ ൈ ሺͳͲɊȀͳɊሻ ൈ ሺͳǤͳͲ െ ͲǤ͸Ͳሻ
ൌ ͳǤͲͲȀ
and

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195
CMOS ANALOG IC DESIGN Solution to Problem 22

ͳ ଶ ͳ ଶ
݃ௗ௦ଶ ൌ Ԝߤ௣ ‫ܥ‬௢௫ ሺܹଶ Ȁ‫ܮ‬ଶ ሻ൫ȁܸீௌଶ ȁ െ หܸ௧௣ ห൯ Ԝߣ ൌ Ԝߤ௣ ‫ܥ‬௢௫ ሺܹଶ Ȁ‫ܮ‬ଶ ሻ൫ܸ஽஽ െ ܸ஻ଵ െ หܸ௧௣ ห൯ ԜߣԜ
ʹ ʹ
ൌ ͲǤͷ ൈ ͸ͲɊȀ ଶ ൈ ሺͳͲɊȀͲǤ͵ͷɊሻ ൈ ሺ͵Ǥ͵ െ ʹǤͳͻ͸Ͷ െ ͲǤ͸ሻଶ ൈ ͲǤͳ ିଵ
ൌ ʹͳǤ͹ͶɊȀ

Inserting the values for ݃௠ଵ and ݃ௗ௦ଶ , we find ‫ܣ‬௩ ൌ െͳͲͲͲɊȀȀʹͳǤ͹ͶɊȀ ൌ െͶ͸ǤͲȀ .

The output resistance is ‫ݎ‬௢ ൌ ‫ݎ‬ௗ௦ଶ ൌ ͳȀ݃ௗ௦ଶ ൌ ͳȀʹͳǤ͹ͶɊȀ ൌ Ͷ͸ǤͲȳ.

These results may be verified by a ‘.op’ simulation and a ‘.tf ’ simulation shown as comments
in the LTspice schematic.

From the error log file shown below from the ‘.op’ simulation, we notice that ܸ஽ௌଵ ൌ ͳǤͺͲ,,
confirming the bias value of the output voltage, and we notice ݃௠ଵ ൌ ͳǤͲͲȀ and
݃ௗ௦ଶ ൌ ʹͳǤ͹ɊȀ, confirming the calculated values of small-signal parameters.

Error log file

From the output file from the ‘.tf ’ simulation shown below, we find the small-signal gain
to be −46.0 V/V and the output resistance to be 46 kΩ as also found from the calculations
above.

Output file

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196
CMOS ANALOG IC DESIGN Solution to Problem 22

Question 4:
The capacitor ‫ܥ‬ଶ between input and output gives rise to an input capacitance which is
found from the Miller transformation:

‫ܥ‬௜௡ǡଶ ൌ ሺͳ ൅ ȁ‫ܣ‬௩ ȁሻ‫ܥ‬ଶ ൌ ሺͳ ൅ Ͷ͸ǤͲሻ ൈ ͲǤͲͷ’ ൌ ʹǤ͵ͷ’ Ǥ

This adds to the capacitance ‫ܥ‬ଵ , so the total input capacitance is ‫ܥ‬௜௡ ൌ ‫ܥ‬ଵ ൅ ‫ܥ‬௜௡ǡଶ ൌ ͲǤͳ’ ൅
ʹǤ͵ͷ’ ൌ ʹǤͶͷ’ .

Using LTspice, we can run a ‘.ac’ simulation shown as a comment in the LTspice schematic.
Assuming a purely capacitive input, we have ‫ܫ‬௜௡ Ȁܸ௜௡ ൌ ݆߱‫ܥ‬௜௡ ֜ ‫ܥ‬௜௡ ൌ ‫ܫ‬௜௡ Ȁሺ݆ܸ߱௜௡ ሻ. Thus,
with an input ac amplitude of 1, we find ‫ܥ‬௜௡ as ‘abs(i(Vin))/(2*pi*frequency)’.

From the plot of ‘abs(i(Vin))/(2*pi*frequency)’ shown below, we find ‫ܥ‬௜௡ ൌ ʹǤͶͷ’ ,

confirming the calculated result. Note that in the plot below, linear axes have been used.

Question 5:
In the small-signal diagram, M3 is modeled only by a voltage-controlled current source since
‫ݎ‬ௗ௦ଷ is infinite because the channel-length modulation is neglected for M3. The direction
of the current source is from source to drain since the controlling voltage is ‫ݒ‬௚௦ଷ ൌ Ͳ െ ‫ݒ‬௫ .
The small-signal diagram is shown below. You may compare the small-signal diagram to
Fig. 4.24 in ‘CMOS Analog IC Design: Fundamentals’.

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197
CMOS ANALOG IC DESIGN Solution to Problem 22

At low frequencies, both capacitors are treated as open circuits.

For finding the output resistance, we reset the input voltage. When resetting ‫ݒ‬௜௡ , both of the
controlled current sources are reset, so the output resistance is ‫ݎ‬௢ ൌ ‫ݎ‬ௗ௦ଶ ൌ ͳȀ݃ௗ௦ଶ ൌ Ͷ͸ǤͲȳ.
Notice that the bias conditions for M2 are unchanged from Question 3, so ݃ௗ௦ଶ is also
unchanged.

A loop equation for the loop comprising ݃௠ଵ ‫ݒ‬௜௡ , ݃௠ଷ ‫ݒ‬௫ and ‫ݎ‬ௗ௦ଶ shows that the current
݃௠ଵ ‫ݒ‬௜௡ flows through ‫ݎ‬ௗ௦ଶ , so the low-frequency gain is ‫ܣ‬௩ ൌ ‫ݒ‬௢ Ȁ‫ݒ‬௜௡ ൌ െ݃௠ଵ ‫ݎ‬ௗ௦ଶ where
the transconductance ݃௠ଵ ൌ ߤ௡ ‫ܥ‬௢௫ ሺܹଵ Ȁ‫ܮ‬ଵ ሻሺܸூே െ ܸ௧௡ ሻ ൌ ͳǤͲͲȀ is also unchanged
from Question 2.

Inserting the values for ݃௠ଵ and ‫ݎ‬ௗ௦ଶ , we find ‫ܣ‬௩ ൌ െͳǤͲͲȀ ൈ Ͷ͸ǤͲȳ ൌ െͶ͸ǤͲȀ.

Both gain and output resistance are unchanged compared to the simple common-source
stage from Question 3.

Question 6:
A node equation at ‫ݒ‬௫ results in ݃௠ଵ ‫ݒ‬௜௡ ൅ ݃௠ଷ ‫ݒ‬௫ ൌ Ͳ ֜ ‫ܣ‬௩ଵ ൌ ‫ݒ‬௫ Ȁ‫ݒ‬௜௡ ൌ െ݃௠ଵ Ȁ݃௠ଷ .

As M1 and M3 have the same dimensions, no channel-length modulation and ‫ܫ‬஽ଵ ൌ ‫ܫ‬஽ଷ , they
have the same value of ܸீௌ െ ܸ௧௡ . Hence, ݃௠ ൌ ʹԜ‫ܫ‬஽ Ȁሺܸீௌ െ ܸ௧௡ ሻ ֜ ݃௠ଵ ൌ ݃௠ଷ ֜ ‫ܣ‬௩ଵ ൌ
െͳȀ.

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198
CMOS ANALOG IC DESIGN Solution to Problem 22

Question 7:
The capacitor ‫ܥ‬ଶ between input and output gives rise to an input capacitance which is
found from the Miller transformation:

‫ܥ‬௜௡ǡଶ ൌ ሺͳ ൅ ȁ‫ܣ‬௩ଵ ȁሻ‫ܥ‬ଶ ൌ ሺͳ ൅ ͳሻ ൈ ͲǤͲͷ’ ൌ ͲǤͳ’ Ǥ

This adds to the capacitance C1, so the total input capacitance is ‫ܥ‬௜௡ ൌ ‫ܥ‬ଵ ൅ ‫ܥ‬௜௡ǡଶ ൌ ͲǤʹ’ .

We notice that the input capacitance is significantly smaller than for the simple common-
source stage from Question 4. For this reason, the cascode configuration is often useful in
circuits designed for high-speed operation.

The results for the cascode amplifier may also be verified using LTspice. Shown below is an
LTspice schematic including the cascode transistor M3.

From the ‘.op’ simulation, we may verify that ܸை , ݃௠ଵ and ݃ௗ௦ଶ remain unchanged. The
results from the error log file are shown below.

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199
CMOS ANALOG IC DESIGN Solution to Problem 22

Error log file

From the ‘.tf ’ simulation with ‘v(Vo)’ as the output, we may verify that the low-frequency
small-signal gain and output resistance remain unchanged, see the following output file.

Output file

From the ‘.tf ’ simulation with ‘v(Vx)’ as the output, we may verify that the low-frequency
small-signal gain ‫ݒ‬௫ Ȁ‫ݒ‬௜௡ is −1 , see output file below.

Output file

From the ‘.ac’ simulation, we may obtain the following plot, verifying that the input
capacitance is 0.2 pF.

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200
CMOS ANALOG IC DESIGN Solution to Problem 23

SOLUTION TO PROBLEM 23

Question 1:

The low-frequency closed-loop gain is given by ‫ܣ‬஼௅ǡ଴ ൌ ‫ܣ‬଴ Ȁሺͳ ൅ ߚ‫ܣ‬଴ ሻ where ‫ܣ‬଴ is the low-
frequency open-loop gain. With a low-frequency gain of 46 dB, we find ‫ܣ‬଴ ൌ ʹͲͲȀ ,
and using ߚ ൌ ͲǤͳ, we find the closed-loop low-frequency gain ‫ܣ‬஼௅ǡ଴ ൌ ‫ܣ‬଴ Ȁሺͳ ൅ ߚ‫ܣ‬଴ ሻ ൌ
ʹͲͲȀȀሺͳ ൅ ͲǤͳ ൈ ʹͲͲሻ ൌ ͻǤͷʹȀ.

Using LTspice, the gain can be simulated by a ‘.tf ’ simulation with ‘v(Vo)’ as the output
and ‘Vin’ as the source. From the output file, we find ‫ܣ‬஼௅ǡ଴ ൌ ͻǤͷʹ͵ͺͳȀ.

Question 2:
With the feedback factor ߚ, the low-frequency gain ‫ܣ‬଴ and the pole frequencies ݂௣ଵ and
݂௣ଶ , the loop gain expression is as follows:

‫ܣ‬଴ ߚ
‫ܮ‬ሺ݆݂ሻ ൌ
൫ͳ ൅ ݆݂Ȁ݂௣ଵ ൯൫ͳ ൅ ݆݂Ȁ݂௣ଶ ൯

The following figure shows the Bode plot using asymptotic piecewise-linear approximations.
The amplitude plot starts at 26 dB corresponding to a loop gain of 20 V/V a 26 dB at
very low frequencies. The first breakpoint appears at ݂௣ଵ ൌ ͳͲͲ œ where the slope of the
amplitude plot changes to −20 dB/dec. The second breakpoint appears at ݂௣ଶ ൌ ͳ œ
where the slope of the amplitude plot changes to −40 dB/dec. The phase plot (black plot)
is the sum of the red and green plots corresponding to the phase shifts from ݂௣ଵ and ݂௣ଶ ,
respectively.

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201
CMOS ANALOG IC DESIGN Solution to Problem 23

Question 3:
From the asymptotic piecewise-linear approximations to the Bode plot shown above, we
estimate a unity-gain frequency of ݂௧ ؄ ͳǤͶ œ and a phase margin of 40°.

Analytically, a more precise value for the phase margin may be found as follows:

From the expression for the loop gain, we find the unity-gain frequency ݂௧ from

‫ܣ‬଴ ߚ
ȁ‫ܮ‬ሺ݆݂ሻȁ ൌ ͳԛ ֜ ԛ ൌ ͳ ֜ ݂௧ ൌ ͳǤʹͷ œ
ଶ ଶ
ቆටͳ ൅ ൫݂௧ Ȁ݂௣ଵ ൯ Ԝቇ ቆටͳ ൅ ൫݂௧ Ȁ݂௣ଶ ൯ Ԝቇ

With ݂ ൌ ݂௧ , we find

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202
CMOS ANALOG IC DESIGN Solution to Problem 23

‫ܮס‬ሺ݆݂௧ ሻ ൌ െ ƒ” –ƒ൫݂௧ Ȁ݂௣ଵ ൯ െ ƒ” –ƒ൫݂௧ Ȁ݂௣ଶ ൯

ൌ െ ƒ” –ƒሺͳǤʹͷ œȀͳͲͲ œሻ െ ƒ” –ƒሺͳǤʹͷ œȀͳ œሻ ൌ െͺͷǤͶι െ ͷͳǤ͵ι ൌ െͳ͵͸Ǥ͹ι

From this, we find the phase margin  ൌ ͳͺͲι ൅ ‫ܮס‬ሺ݆݂௧ ሻ ൌ Ͷ͵Ǥ͵ι .

The Bode plot and the phase margin may also be found using LTspice. The loop gain can
be plotted from a ‘.ac’ simulation using the schematic below where two RC networks have
ିଵ
been inserted, providing a time constant ߬ଵ ൌ ൫ʹߨ݂௣ଵ ൯ ൌ ܴଵ ‫ܥ‬ଵ ൌ ͳǤͷͻͳɊ• and a time
ିଵ
constant ߬ଶ ൌ ൫ʹߨ݂௣ଶ ൯ ൌ ܴଶ ‫ܥ‬ଶ ൌ ͲǤͳͷͻͳɊ•. The low-frequency open-loop gain is modeled
by the voltage-controlled voltage source ‘E1’ and the feedback factor ߚ is modeled by the
voltage-controlled voltage source ‘E2’. The Bode plot is also shown below.

From the plot of the feedback voltage ܸ௙ , we find a phase margin of 43.4° as shown above.

The phase margin may also be found using the ‘.meas’ directive shown in the LTspice
schematic.

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203
CMOS ANALOG IC DESIGN Solution to Problem 23

The phase margin is  ൌ ͳͺͲιԛ െ ‫ס‬൫െ‫ܮ‬ሺ݆݂௧ ሻ൯ ൌ ͳͺͲιԛ ൅ ‫ס‬൫‫ܮ‬ሺ݆݂௧ ሻ൯ ൌ ‫ס‬൫െ‫ܮ‬ሺ݆݂௧ ሻ൯ where
‫ܮ‬ሺ݆݂ሻ is the loop gain and ݂௧ is the frequency where ȁ‫ܮ‬ሺ݆݂ሻȁ has dropped to a value of 1.
Thus, the phase of ‘-v(Vf )’ is equal to the phase margin when the magnitude of ‘v(Vf )’ is
equal to 1.

The result of the ‘.meas’ directive is found in the error log file which shows a phase margin
of 43.3309°. We notice that there is a good match between the analytically calculated phase
margin and the simulated phase margin.

Question 4:
A Bode plot using asymptotic piecewise-linear approximations is shown below, resulting in
a phase margin of 60°. From the Bode plot, we find ݂௣ଵ ൌ ʹͶ œ.

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204
CMOS ANALOG IC DESIGN Solution to Problem 23

The plot is constructed as follows:

1. Draw the phase response at high frequencies. This can easily be done since the
pole frequency ݂௣ଶ , remains unchanged, line segments a and b.
2. Find the frequency where ‫ܮס‬ሺ݆݂ሻ ൌ ͳʹͲι, giving a phase margin of 60°. This is
also the unity-gain frequency ݂௧ of the loop gain.
3. Draw line segment c in the amplitude response as a line through 0 dB at the
unity-gain frequency and with a slope of −20 dB/decade.
4. Draw line segment d in the amplitude response as a line with a slope of −40
dB/decade, starting from line segment c at the frequency ݂௣ଶ ൌ ͳ œ .
5. Draw line segment e in the amplitude response as a horizontal line at 26 dB
(the low-frequency loop gain). The intersection between segment e and segment
c is the frequency ݂௣ଵ which may be read from the Bode plot as 24 kHz.
6. Draw line segment f in the phase response as a line from 0° at
݂௣ଵ ȀͳͲ ൌ ʹǤͶ œ to −90° at ͳͲԜ݂௣ଵ ൌ ʹͶͲ œ, i.e., a slope of −45°/decade.
7. Draw line segment g in the phase response with a slope of −90°/decade, starting
from line segment f at a frequency of ݂௣ଶ ȀͳͲ ൌ ͲǤͳ œ.

Analytically, a more precise value for the phase margin with ݂௣ଵ ൌ ʹͶ œ may be found
as follows:

Using ݂௣ଵ ൌ ʹͶ œ in

‫ܣ‬଴ ߚ
ൌͳ
ଶ ଶ
ቆටͳ ൅ ൫݂௧ Ȁ݂௣ଵ ൯ Ԝቇ ቆටͳ ൅ ൫݂௧ Ȁ݂௣ଶ ൯ Ԝቇ

we find a unity-gain frequency ݂௧ ൌ Ͷ͵ͻ œ.

With this value of ݂௧ , we find

‫ܮס‬ሺ݆݂௧ ሻ ൌ െ ƒ” –ƒ൫݂௧ Ȁ݂௣ଵ ൯ െ ƒ” –ƒ൫݂௧ Ȁ݂௣ଶ ൯

ൌ െ ƒ” –ƒሺͶ͵ͻ œȀʹͶ œሻ െ ƒ” –ƒሺͶ͵ͻ œȀͳ œሻ ൌ െͺ͸Ǥͻι െ ʹ͵Ǥ͹ι ൌ െͳͳͲǤ͸ι

corresponding to a phase margin of 69.4°.

A somewhat better estimate of ݂௣ଵ may be obtained by noting that for a second-order system
with ݂௣ଶ ‫݂ ب‬௣ଵ , a phase margin of 60° requires that the frequency ݂௣ଶ , of the second pole
is 1.5 times the gain-bandwidth product ݂௧௟ of the loop gain, see Fig. 6.35(a) in ‘CMOS

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205
CMOS ANALOG IC DESIGN Solution to Problem 23

Analog IC Design: Fundamentals’. Thus, we find ݂௧௟ ൌ ݂௣ଶ ȀͳǤͷ ൌ ͳ œȀͳǤͷ ൌ ͸͸͹ œ.
With a low-frequency loop gain ‫ܮ‬଴ ൌ ‫ܣ‬଴ ߚ ൌ ʹͲȀ, we find ݂௣ଵ ൌ ͸͸͹ œȀʹͲ ൌ ͵͵Ǥ͵ œ.
According to Fig. 6.35(b) in ‘CMOS Analog IC Design: Fundamentals’, the unity-gain
frequency for the loop gain is approximate ݂௧ ؄ ͲǤͺ͹Ԝ݂௧௟ ൌ ͷͺͲ œ . Using ݂௣ଵ ൌ ͵͵Ǥ͵ œ
and ݂௧ ൌ ͷͺͲ œ, we find

‫ܮס‬ሺ݆݂௧ ሻ ൌ െ ƒ” –ƒ൫݂௧ Ȁ݂௣ଵ ൯ െ ƒ” –ƒ൫݂௧ Ȁ݂௣ଶ ൯

ൌ െ ƒ” –ƒሺͷͺͲ œȀ͵͵Ǥ͵ œሻ െ ƒ” –ƒሺͷͺͲ œȀͳ œሻ ൌ െͺ͸Ǥ͹ι െ ͵ͲǤͳι ൌ െͳͳ͸Ǥͺι

corresponding to a phase margin of 63.2°. The extra 3.2° of phase margin appears because
the phase shift from the dominant pole is not 90° but only about 87° at the unity-gain
frequency for the loop gain.

Obviously, using an accurate calculation of unity-gain frequency and phase margin, a

somewhat larger value of ݂௣ଵ may be determined. Analytically, the equations to be solved
with respect to ݂௧ and ݂௣ଵ are

‫ܣ‬଴ ߚ
ൌͳ
ଶ ଶ
ቆටͳ ൅ ൫݂௧ Ȁ݂௣ଵ ൯ Ԝቇ ቆටͳ ൅ ൫݂௧ Ȁ݂௣ଶ ൯ Ԝቇ

and ‫ܮס‬ሺ݆݂ሻ ൌ െ ƒ” –ƒ൫݂௧ Ȁ݂௣ଵ ൯ െ ƒ” –ƒ൫݂௧ Ȁ݂௣ଶ ൯ ൌ െͳʹͲι.

This set of equations may be solved to yield ݂௧ ൌ ͸͸ͳ œ and ݂௣ଵ ൌ ͵ͻǤ͹ œ,, i.e., a phase
margin of 60° is obtained with the dominant pole moved from 100 kHz to 39.7 kHz.

Using LTspice, the dominant-pole frequency may be defined as a parameter ‘fp1’ which can
be stepped through a range of values as shown in the schematic below.

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206
CMOS ANALOG IC DESIGN Solution to Problem 23

The schematic includes a ‘.meas’ directive which calculates the phase margin. The result of
this calculation is given in the error log file and a right-click in the error log file lets you
plot the phase margin versus the dominant pole frequency ݂௣ଵ as shown in the figure below.
From this, we find ݂௣ଵ ൌ ͵ͻǤ͹ œ,.

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207
CMOS ANALOG IC DESIGN Solution to Problem 24

SOLUTION TO PROBLEM 24

Question 1:
The bias current ‫ܫ‬஽ହ in M5 is the sum of the bias currents for M1 and M2, and since M1
and M2 are matched, ‫ܫ‬஽ଵ ൌ ‫ܫ‬஽ଶ , so ‫ܫ‬஽ହ ൌ ‫ܫ‬஽ଵ ൅ ‫ܫ‬஽ଶ ൌ ʹͷɊ.

With ߣ ൌ Ͳ ିଵ , the bias current of M5 is

ͳ ܹହ
‫ܫ‬஽ହ ൌ ߤ௡ ‫ܥ‬௢௫ ሺܸ െ ܸ௧௡ ሻଶ
ʹ ‫ܮ‬ହ ஻

which results in

ʹԜ‫ܫ‬஽ହ ʹ ൈ ʹͷɊ
ܹହ ൌ ‫ܮ‬ହ ൬ ൰ ൌ ͲǤͷɊ ൈ ൬ ൰ ൌ ʹɊǤ
ߤ௡ ‫ܥ‬௢௫ ሺܸ஻ െ ܸ௧௡ ሻ ଶ ʹͲͲɊȀ ൈ ሺͲǤ͹ͷ െ ͲǤͷͲሻଶ
ଶ

Question 2:
When ‫ܥ‬௅ is the only capacitor to be considered, the gain-bandwidth product GBW of the
differential stage is given by

ͳ ݃௠ଵ
 ൌ ݃௠ଵ ‫ݎ‬௢௨௧ ൬ ൰ൌ
ʹԜߨ‫ݎ‬௢௨௧ ‫ܥ‬௅ ʹԜߨ‫ܥ‬௅

where ‫ݎ‬௢௨௧ is the output resistance of the differential stage (see Eqs. (4.71) and (4.107) in
‘CMOS Analog IC Design: Fundamentals’).

From this, we find

݃௠ଵ ൌ ݃௠ଶ ൌ ʹԜߨԜ‫ܥ‬௅ ԜԜ  ൌ ʹ ൈ ߨ ൈ ͲǤͳ͸’ ൈ ͳͲͲ œ ൌ ͲǤͳȀǤ

We may note that with the specification of ߣ ൌ Ͳ ିଵ , the output resistance is infinite, so
there is a pole at ݂ ൌ Ͳ and the gain-bandwidth product is equal to the unity-gain frequency.

Question 3:
From ݃௠ଵ ൌ ʹԜ‫ܫ‬஽ଵ Ȁሺܸீௌଵ െ ܸ௧௡ ሻ, we find ܸீௌଵ െ ܸ௧௡ ൌ ʹԜ‫ܫ‬஽ଵ Ȁ݃௠ଵ ൌ ʹ ൈ ͳʹǤͷɊȀͲǤͳȀ ൌ
ͲǤʹͷǤ

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208
CMOS ANALOG IC DESIGN Solution to Problem 24

From

ͳ ܹଵ
‫ܫ‬஽ଵ ൌ ߤ௡ ‫ܥ‬௢௫ ሺܸ െ ܸ௧௡ ሻଶ
ʹ ‫ܮ‬ଵ ீௌଵ

we find
ʹԜ‫ܫ‬஽ଵ ʹ ൈ ͳʹǤͷɊ
ܹଵ ൌ ‫ܮ‬ଵ ൬ ൰ ൌ ͲǤͷɊ ൈ ൬ ൰ ൌ ͳɊǤ
ߤ௡ ‫ܥ‬௢௫ ሺܸீௌଵ െ ܸ௧௡ ሻ ଶ ʹͲͲɊȀ ଶ ൈ ሺͲǤʹͷሻଶ

Question 4:
The minimum common-mode input voltage is limited by the requirement that M5 should
remain in the active region, i.e., have a drain-source voltage of at least ܸ஻ െ ܸ௧௡ ൌ ͲǤʹͷ.
With ܸ஽ହ ൌ ܸௌଵ ൌ ͲǤʹͷ , we find ܸூ஼ெ‹ ൌ ܸ஻ െ ܸ௧௡ ൅ ܸீௌଵ ൌ ܸ஻ ൅ ሺܸீௌଵ െ ܸ௧௡ ሻ ൌ ͲǤ͹ͷ ൅
ͲǤʹͷ ൌ ͳǤͲ where the value of ܸீௌଵ െ ܸ௧௡ is taken from Question 3.

Question 5:
The maximum common-mode input voltage is limited by the requirement that M1 should remain
in the active region, i.e., have a drain-source voltage of at least ܸீௌଵ െ ܸ௧௡ . With ܸ஽ௌଵ ൌ ܸீௌଵ െ
ܸ௧௡ ֜ ܸ஽ଵ ൌ ܸீଵ െ ܸ௧௡ and ܸீଵ ൌ ܸூ஼ெƒš , we find ܸ஽ଵ ൌ ܸூ஼ெƒš െ ܸ௧௡ ൌ ʹǤ͹Ͳ െ ͲǤͷͲ ൌ
ʹǤʹͲ..

For M3, we have ܸீଷ ൌ ܸ஽ଷ ൌ ܸ஽ଵ ൌ ʹǤʹͲ and ܸௌଷ ൌ ܸ஽஽ ൌ ͵ǤͲ, so ȁܸீௌଷ ȁ ൌ ͲǤͺ.. From

ͳ ܹଷ ଶ
‫ܫ‬஽ଷ ൌ ߤ௣ ‫ܥ‬௢௫ ൫ȁܸீௌଷ ȁ െ หܸ௧௣ ห൯
ʹ ‫ܮ‬ଷ

we find (with ‫ܫ‬஽ଷ ൌ ‫ܫ‬஽ଵ ൌ ͳʹǤͷɊ))

ʹԜ‫ܫ‬஽ଷ ʹ ൈ ͳʹǤͷɊ
ܹଷ ൌ ‫ܮ‬ଷ ൭ ଶ൱ ൌ ͲǤͷɊ ൈ ൬ ൰ ൌ ͵ɊǤ
ߤ௣ ‫ܥ‬௢௫ ൫ȁܸீௌଷ ȁ െ หܸ௧௣ ห൯ ͸ʹɊȀ ଶ ൈ ሺͲǤͺͲ െ ͲǤͷͶሻଶ

As M3 and M4 are matched, ܹସ ൌ ܹଷ ൌ ͵Ɋ .

Question 6:
The small-signal output resistance is ‫ݎ‬௢௨௧ ൌ ‫ݎ‬ௗ௦ଶ ‫ݎ צ‬ௗ௦ସ (see Eq. (4.70) in ‘CMOS Analog
IC Design: Fundamentals’).

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209
CMOS ANALOG IC DESIGN Solution to Problem 24

The small-signal parameters ‫ݎ‬ௗ௦ଶ and ‫ݎ‬ௗ௦ସ are calculated from

ͳ ൅ ߣܸ஽ௌଶ ͳ ͳ
‫ݎ‬ௗ௦ଶ ൌ ؄ ൌ ିଵ
ൌ ͷͲͲȳ
ߣ‫ܫ‬஽ଶ ߣ‫ܫ‬஽ଶ ͲǤͳ͸ ൈ ͳʹǤͷɊ

and

ͳ ൅ ߣȁܸ஽ௌସ ȁ ͳ ͳ
‫ݎ‬ௗ௦ସ ൌ ؄ ൌ ିଵ
ൌ ͷͲͲȳ
ߣ‫ܫ‬஽ସ ߣ‫ܫ‬஽ସ ͲǤͳ͸ ൈ ͳʹǤͷɊ

From this, we find ‫ݎ‬௢௨௧ ൌ ͷͲͲ kΩ ‫ צ‬ͷͲͲ kΩ ൌ ʹͷͲ kΩ..

A slightly more accurate calculation takes the drain-source voltages of M2 and M4 into account.
For M2 and M4 we find ܸௌଶ ൌ ܸீଶ െ ܸீௌଶ ൌ ܸூ஼ெ െ ܸீௌଶ ൌ ʹǤͲ െ ͲǤ͹ͷ ൌ ͳǤʹͷ, where
we have used ܸீௌଶ ൌ ܸீௌଵ ൌ ͲǤ͹ͷ , compare to Question 3. Also, ܸ஽ଶ ൌ ܸ஽ସ ൌ ܸ஽ଷ ൌ ʹǤʹ
(compare to Question 5) and ܸௌସ ൌ ܸ஽஽ ൌ ͵ǤͲ.

Inserting in the expressions for ‫ݎ‬ௗ௦ , we find

ͳ ൅ ߣܸ஽ௌଶ ͳ ൅ ͲǤͳ͸ ିଵ ൈ ሺʹǤʹ െ ͳǤʹͷሻ
‫ݎ‬ௗ௦ଶ ൌ ൌ ൌ ͷ͹͸ȳ
ߣ‫ܫ‬஽ଵ ͲǤͳ͸ ିଵ ൈ ͳʹǤͷɊ

and
ͳ ൅ ߣȁܸ஽ௌସ ȁ ͳ ൅ ͲǤͳ͸ ିଵ ൈ ȁʹǤʹ െ ͵ǤͲȁ
‫ݎ‬ௗ௦ସ ൌ ൌ ൌ ͷ͸ͶȳǤ
ߣ‫ܫ‬஽ଵ ͲǤͳ͸ ିଵ ൈ ͳʹǤͷɊ

From this, we find ‫ݎ‬௢௨௧ ൌ ͷ͹͸ kΩ ‫ צ‬ͷ͸Ͷ kΩ ൌ ʹͺͷ kΩ.

Question 7:
The small-signal gain at low frequencies is given by ‫ܣ‬ௗ ൌ ݃௠ଵ Ԝ‫ݎ‬௢௨௧ . The transconductance
݃௠ଵ was calculated in Question 2, and using the approximate value for ‫ݎ‬௢௨௧ from Question
6, we find ‫ܣ‬௩ ൌ ͲǤͳȀ ൈ ʹͷͲȳ ൌ ʹͷȀ.

With the more accurate value for ‫ݎ‬௢௨௧ from Question 6, we find ‫ܣ‬௩ ൌ ͲǤͳȀ ൈ ʹͺͷȳ ൌ
ʹͺǤͷȀ.

Question 8:
For verifying the answers to Questions 1 - 5, we use the LTspice schematic shown below
with the transistor models specified in the problem and the transistor geometries calculated
in Questions 1, 3 and 5.

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210
CMOS ANALOG IC DESIGN Solution to Problem 24

Running a ‘.op’ simulation, the result of Question 1 (‫ܫ‬஽ଵ ൌ ‫ܫ‬஽ଶ ൌ ͳʹǤͷɊ) is verified
from the error log file. Also, the error log file shows ݃௠ଵ ൌ ݃௠ଶ ൌ ͲǤͳȀ as found in
Question 2 and used in Question 3.

Running a ‘.ac’ simulation, we obtain the following plot. The gain-bandwidth product is
found as the unity-gain frequency which from the plot is found to be 100 MHz, i.e., a
perfect match to the specified gain-bandwidth product.

Running a ‘.dc’ simulation with a sweep of ܸூ஼ெ, the common-mode range specified in
Questions 4 and 5 is verified by examining the common-mode voltage range for which ‫ܫ‬஽ହ
is 25 µA (Question 4) and examining the common-mode voltage range for which ܸீௌଵ is
equal to 750 mV (Question 5). When ܸீௌଵ increases above 750 mV for high values of the
common-mode input voltage, it is an indication that M1 enters the triode region. From the
plot shown below, we see a perfect match to the calculated common-mode range.

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211
CMOS ANALOG IC DESIGN Solution to Problem 24

For verifying the answers to Questions 6 and 7, the schematic is modified by introducing
ߣ ൌ ͲǤͳ͸ ିଵ in both transistors models, and M5 is replaced by a dc current source ensuring
that the bias currents in the differential pair remains unchanged, see the following schematic.

For finding the small-signal output resistance and low-frequency small-signal gain, we run a
‘.tf ’ simulation with ‘v(Vo)’ as the output and ‘Vid’ as the source. From the output file, we
find an output resistance of 286.995 kΩ and a gain of 30.285 V/V, both values matching
the calculated results from Questions 6 and 7 reasonably well. The discrepancies are due
to slightly altered bias voltage conditions because of the channel-length modulation. This
causes ݃௠ଵ and ݃௠ଶ to be slightly larger than 0.1 mA/V. The error log file from a ‘.op’
simulation shows ݃௠ଵ ൌ ݃௠ଶ ൌ ͲǤͳͲ͹Ȁ.

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212
CMOS ANALOG IC DESIGN Solution to Problem 25

SOLUTION TO PROBLEM 25

Question 1:
The small-signal diagram is shown below. Notice that ‫ݒ‬௚௦ଶ ൌ െ‫ݒ‬௦ଶ since the gate of M2 is
connected to a dc bias voltage. Hence, the voltage-controlled current source representing
M2 is pointing from source to drain with ‫ݒ‬௦ଶ as the controlling voltage. Also note that M3
has a constant gate-source voltage, so the small-signal equivalent of M3 is reduced to the
small-signal output resistance ‫ݎ‬ௗ௦ଷ.

The small-signal parameters ݃௠ଵ and ݃௠ଶ can be calculated from

݃௠ ൌ ඥʹߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ‫ܫ‬஽ ሺͳ ൅ ߣܸ஽ௌ ሻ

With ‫ܫ‬஽ଵ ؄ ‫ܫ‬஽ଶ ؄ ‫ܫ‬஻ ൌ ʹͷͲɊ and ߣܸ஽ௌ ‫ͳ ا‬, we find

݃௠ଵ ؄ ݃௠ଶ ؄ ඥʹߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ‫ܫ‬஽ ൌ ඥʹ ൈ ʹǤͲͲȀ ଶ ൈ ͲǤʹͷ ൌ ͳǤͲͲȀ

The small-signal parameters ‫ݎ‬ௗ௦ଵ , ‫ݎ‬ௗ௦ଶ , and ‫ݎ‬ௗ௦ଷ can be calculated from

ͳ ൅ ߣܸ஽ௌ
‫ݎ‬ௗ௦ ൌ
ߣ‫ܫ‬஽

With ‫ܫ‬஽ଵ ؄ ‫ܫ‬஽ଶ ൌ ‫ܫ‬஽ଷ ؄ ‫ܫ‬஻ ൌ ʹͷͲɊ and ߣܸ஽ௌ ‫ͳ ا‬, we find

ͳ ͳ
‫ݎ‬ௗ௦ଵ ؄ ‫ݎ‬ௗ௦ଶ ؄ ‫ݎ‬ௗ௦ଷ ؄ ൌ ିଵ
ൌ ͳͲͲȳ
ߣ‫ܫ‬஻ ͲǤͲͶ ൈ ͲǤʹͷ

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213
CMOS ANALOG IC DESIGN Solution to Problem 25

Question 2:
For the common-drain stage (M1), the voltage gain is
‫ݒ‬௦ ݃௠ଵ
‫ܣ‬ଵ ൌ ൌ
‫ݒ‬௜௡ ݃௠ଵ ൅ ݃ௗ௦ଵ ൅ ͳȀ‫ݎ‬௅ଵ

where ݃ௗ௦ଵ ൌ ͳȀ‫ݎ‬ௗ௦ଵ and ‫ݎ‬௅ଵ is the load resistance of the common-drain stage, i.e., the
input resistance of the common-gate stage.

The input resistance of the common-gate stage is found using Eq. (4.23) in ‘CMOS Analog
IC Design: Fundamentals’:
‫ݎ‬ௗ௦ଶ + ‫ݎ‬ௗ௦ଷ
‫ݎ‬௅ଵ =
1 + ݃௠ଶ ‫ݎ‬ௗ௦ଶ

Using ݃௠ଵ ؄ ݃௠ଶ ؄ ݃௠ , ‫ݎ‬ௗ௦ଵ ؄ ‫ݎ‬ௗ௦ଶ ؄ ‫ݎ‬ௗ௦ଷ ؄ ‫ݎ‬ௗ௦ , and �� ��� ≫ 1, we find

2���� 2
��� ≃ =
�� ��� ��

and
��
�� ≃ = 2/3 = 0.67
�� + �� /2

Question 3:
The gain in the common-gate stage is found using Eq. (4.22) in ‘CMOS Analog IC Design:
Fundamentals’:

1
‫ܣ‬ଶ = ൬݃௠ଶ + ൰ (‫ݎ‬ௗ௦ଶ ‫ݎ צ‬ௗ௦ଷ )
‫ݎ‬ௗ௦ଶ

Using ����
���������� ���and
��������� and���
and �������
��≫≫1/�
1/�
���� , we find

‫ܣ‬ଶ ؄ ݃௠ ‫ݎ‬ௗ௦ /2

and ‫ܣ‬௩ = ‫ܣ‬ଵ ‫ܣ‬ଶ = ݃௠ ‫ݎ‬ௗ௦ /3.

With �� ≃ 1.00 mA/V and ��� ≃ 100 kΩ , we find �� ≃ 50 V/V and ‫ܣ‬௩ = 33 V/V.

Question 4:
The output resistance is the output resistance of a common-gate stage which is found using
Eq. (4.26) in ‘CMOS Analog IC Design: Fundamentals’:
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214
CMOS ANALOG IC DESIGN Solution to Problem 25

���� � ���� ∥ (���� + ��� ���� ��� )

where ܴௌଵ is the signal source resistance to the common-gate stage, i.e., the output resistance
of the common-drain stage. From Eq. (4.16) in ‘CMOS Analog IC Design: Fundamentals’,
we find
1 1
��� = � ���� ≃
��� ��

From this, we find using ‫ݎ‬ௗ௦ଶ ؄ ‫ݎ‬ௗ௦ଷ ؄ ‫ݎ‬ௗ௦ and ݃௠ଶ ؄ ݃௠ଵ ؄ ݃௠

���� � ��� ∥ (��� + �� ��� /�� ) = ��� ∥ (2���� ) = 2���� /3

With ��� = 100 kΩ, we find ���� ≃ 67 kΩ.

Question 5:
Shown below is the LTspice schematic for the circuit. The transistor models and geometries
have been selected to provide ߤ‫ܥ‬௢௫ (ܹ/‫ = )ܮ‬2.00 mA/V ଶ for both the NMOS transistors
and the PMOS transistors.

For verifying the small-signal parameters, we run a ‘.op’ simulation and open the error log
file to find the simulated values of the small-signal parameters.

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215
CMOS ANALOG IC DESIGN Solution to Problem 25

The error log file lists the following small-signal parameters: ݃௠ଵ = 1.05 mA/V , ݃௠ଶ =
1.03 mA/V , ���� = ���� = 9.21 μA/V � ���� = ���� = 109 kΩ, and ���� = 9.62 μA/V ⇒
���� = 104 k٠. From the error log file, we also verify that all transistors are biased in the
active region, i.e., ‘|Vds|>|Vdsat|’.

The simulated small-signal parameters are slightly larger than the calculated parameters
because the factor (1 + ߣܸ஽ௌ ) has been neglected in the calculations.

For finding the gain ‫ܣ‬ଵ, we run a ‘.tf ’ simulation with ‘v(Vs)’ as the output and ‘Vin’ as
the input. The output file from this simulation shows a transfer function of 0.661549 V/V,
i.e., very close to the calculated value.

For finding the total gain ‫ܣ‬௩ , we run a ‘.tf ’ simulation with ‘v(Vo)’ as the output and ‘Vin’
as the input. The output file from this simulation shows a transfer function of 36.4832
V/V, i.e., slightly larger than the calculated value. This is caused mainly by the slightly
larger values of ‫ݎ‬ௗ௦ଶ and ‫ݎ‬ௗ௦ଷ. The gain ‫ܣ‬ଶ may be found from the simulation results as
‫ܣ‬ଶ = ‫ܣ‬௩ /‫ܣ‬ଵ = 55.1481 V/V,, again slightly larger than the calculated value.

The output resistance is found from the ‘.tf ’ simulation with ‘v(Vo)’ as the output and ‘Vin’
as the input. The output file lists an output impedance of 70.0272 kΩ, again slightly larger
than the calculated value due to the larger values of ‫ݎ‬ௗ௦ଶ and ‫ݎ‬ௗ௦ଷ.

Question 6:
The input capacitance is found using the Miller transformation. This results in ‫ܥ‬௜௡ = ‫ܥ‬௚ௗ +
(1 − �� )��� = 3 fF + (1 − 0.66) × 50 fF = 20 fF.

Question 7:

For a common-source stage with a gain of �� = −36 V/V and ‫ܥ‬௚௦ = 50 fF and ‫ܥ‬௚ௗ = 3 fF,
we find ‫ܥ‬௜௡ = ‫ܥ‬௚௦ + (1 െ ‫ܣ‬௩ )‫ܥ‬௚ௗ = 50 fF + (1 + 36) × 3 fF = 161 fF.

Thus, the two-stage common-drain/common-gate amplifier provides a major reduction of

the input capacitance compared to a single-stage common-source amplifier.

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216
CMOS ANALOG IC DESIGN Solution to Problem 26

SOLUTION TO PROBLEM 26

Question 1:
With an ideal opamp, ܸ௜ௗ = 0 , so a node equation at the inverting input of the opamp
results in

��� − 0 0 − �� �� (��) −1 �
= � ��� (��) = = =
� 1/(2������) ��� (��) 2������� 2������

Question 2:
The loop gain may be found by resetting ܸ௜௡ and breaking the feedback loop at the inverting
input of the opamp, applying a test voltage ܸ௧ at the inverting input and calculating the
returned voltage ܸ௥ across the resistor ܴ.

With ݂ோ஼ = 1/(2ߨԜܴ‫)ܥ‬, this results in

�� (��) �
�(��) = − = �(��) � �
�� (��) � + 1/(2������)
��� 2������� ��� /���
=� �� �= , q.e.d.
����1 + ��/�� � 1 + 2������� (1 + ��/��� )�1 + ��/�� �

Question 3:
At low frequencies, the loop gain approaches the value ‫ܮ‬଴ = ݂௧௔ /݂ோ஼ , so for a loop gain of 40
dB ¾100 V/V, we find ��� = 100���� = 100/(2����) = 100/(2 × � × 10 kΩ × 15.9 pF) =
100 MHz .

Question 4:
With the unity-gain frequency ݂௧ for |‫ |)݂݆(ܮ‬much larger than ݂ோ஼ , the loop gain at high
frequencies can be approximated by
݂௧௔
‫= )݂݆(ܮ‬
݆݂Ԝ൫1 + ݆݂/݂௣ ൯

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217
CMOS ANALOG IC DESIGN Solution to Problem 26

From this, ��(��) = −90° − arctan��/�� �, so for a phase margin of 60°, arctan൫݂/݂௣ ൯ = 30°
at the frequency ݂ = ݂௧ . From this, �� /�� = tan(30°) = 1/√3 � �� = √3�� . The unity-gain
frequency ݂௧ is found from

��� 1
|�(��� )| = � �⎛ ⎞=1
�� �
�
⎝ 1 + ��� /�� � ⎠
��� 1 √3
⇒1=� �� � ⇒ �� = � � ���
�� �1 + 1/3 2

Inserting in �� = √3�� , we find ݂௣ = (3/2)݂௧௔ = (3/2) × 100 MHz = 150 MHz.

A Bode plot using asymptotic piecewise-linear approximations to the loop gain

��� /��� 100

�(��) = =
(1 + ��/��� )�1 + ��/�� � (1 + ��/1 MHz)(1 + ��/150 MHz)

is shown below. The amplitude plot starts at 40 dB, corresponding to a loop gain of 100
V/V at very low frequencies. The first breakpoint appears at the pole frequency ݂ோ஼ = 1 MHz
where the slope of the amplitude changes to −20 dB/dec. The second breakpoint appears at
the pole frequency ݂௣ = 150 MHz where the slope of the amplitude changes to −40 dB/dec.
The phase plot (black plot) is the sum of the red plot and the green plot, corresponding to
the phase shifts from the poles at 1 MHz and 150 MHz, respectively.

Notice that due to the piecewise-linear approximations, the phase margin appears somewhat
smaller than found from the calculations.

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218
CMOS ANALOG IC DESIGN Solution to Problem 26

Using LTspice, the answers to Questions 2 - 4 may be verified. The LTspice schematic in
the following figure shows a circuit where the opamp is modeled by the voltage-controlled
current source ‘G1’, the capacitors ‘C1’ and ‘C2’, the voltage-controlled voltage sources
‘E1’ and ‘E2’, and the resistor ‘R1’ (compare to Table 5.3 in ‘CMOS Integrated Circuit
Simulation with LTspice’). The loop gain is found from a ‘.ac’ simulation with the test
voltage ‘Vt’ as the input and the input voltage ‘Vin’ reset. The returned voltage is ‘Vr’, so
the loop gain ‫ = )݂݆(ܮ‬െܸ௥ /ܸ௧ is shown by plotting ‘-Vr’ as shown below. A ‘.ic’ directive
is inserted to define the bias voltage of the node ‘V1’ which is a floating node. If this ‘.ic’
directive is omitted, the error log file opens automatically with a message that the node
is floating but the simulation still runs and gives correct simulation results. With the ‘.ic’
directive included, the error log file does not open automatically. It can be opened with
‘Ctrl-L’ and it will inform you that node ‘V1’ is floating and the bias value is defined solely
by the ‘.ic’ directive.

From the plot, we see that the low-frequency loop gain is 40 dB as requested, and we find a
phase margin of 60.7°. The reason for the additional 0.7° of phase margin is that the phase
shift from the factor 1/(1 + ݆݂/݂ோ஼ ) was approximated to be −90°. With ݂௧ = 86.3 MHz
and ݂ோ஼ = 1 MHz, the phase shift is only −arctan(86.3) = 89.3°, corresponding to the
additional phase margin of 0.7°.

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CMOS ANALOG IC DESIGN Solution to Problem 26

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CMOS ANALOG IC DESIGN Solution to Problem 27

SOLUTION TO PROBLEM 27

Question 1:
For M1, we have the Shichman-Hodges model for a MOS transistor without channel-length
modulation:

1
‫ܫ‬஽ଵ = ߤ௡ ‫ܥ‬௢௫ (ܹଵ /‫ܮ‬ଵ )(ܸீௌଵ െ ܸ௧௡ )ଶ
2

As there is no dc current flowing through ܴௌ , we have ���� = ��� − (−��� ) = 0 V − (−1 V) =

1 V . With ܹଵ /‫ܮ‬ଵ = 50, we find ��� = (1/2) × 100 μA/V � × 50 × (1 V − 0.8 V)� = 100 μA.

Using Kirchhoff’s voltage law and Ohm’s law, we find ��� = ��� − �� ��� = 1 V − 10 kΩ ×
100 μA = 0 V, q.e.d.

Similarly for M2, we find

1
��� = �� ��� (�� /�� )(|���� | − |��� |)�
2

where |���� | = |��� − ��� | = |0 V − 1 V| = 1 V. With ܹଶ /‫ܮ‬ଶ = 125, we find ‫ܫ‬஽ଶ = (1/2) ×
40 μA/V � × 125 × (1 V − 0.8 V)� = 100 μA .

Using Kirchhoff’s voltage law and Ohm’s law, we find ��� = −��� + �� �� = −1 V + 10 kΩ ×
100 μA = 0 V , q.e.d.

Question 2:
The low-frequency small-signal diagram is shown below.

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221
CMOS ANALOG IC DESIGN Solution to Problem 27

Using a node equation at the output of the first stage, we find

݃௠ଵ ‫ݒ‬௚௦ଵ = ݃௠ଵ ‫ݒ‬௜௡ = െ‫ݒ‬௢ଵ /ܴଵ ֜ ‫ܣ‬௩ଵ = ‫ݒ‬௢ଵ /‫ݒ‬௜௡ = െ݃௠ଵ ܴଵ

The transconductance is found from ��� = 2���� /(���� − ��� ) = 2 × 100 μA/(1 V −
0.8 V) = 1 mA/V. From this, we find ��� = −��� �� = −1 mA/V × 10 kΩ = −10 V/V.

Using a node equation at the output of the second stage, we find

݃௠ଶ ‫ݒ‬௢ଵ = െ‫ݒ‬௢ଶ /ܴଶ െ ‫ݒ‬௢ଶ /ܴ௅ ֜ ‫ܣ‬௩ଶ = ‫ݒ‬௢ଶ /‫ݒ‬௢ଵ = െ݃௠ଶ (ܴଶ ‫ܴ צ‬௅ )

The transconductance ݃௠ଶ is found from ��� = 2���� /�|���� | − ���� �� = 2 × 100 μA/(1 V −
0.8 V) = 1 mA/V. From this, we find ��� = −��� (�� ∥ �� ) = −1 mA/V × (10 kΩ ∥ 40 kΩ) =
−1 mA/V × 8 kΩ = −8 V/V.

The total gain is �� = ��� ��� = (−10 V/V) × (−8 V/V) = 80 V/V .

Question 3:
Using the small-signal gain to calculate the input amplitude, we find ܸ௜௡ = ܸ௢ଶ /‫ܣ‬௩ =
100 mV/80 = 1.25 mV. The linear small-signal approximation can be used when ��� ≪
2(ܸீௌ െ ܸ௧ ), see Eq. (3.43) in ‘CMOS Analog IC Design: Fundamentals’. With ܸ௜௡ = 1.25 mV,
this is clearly the case for M1 where 2(ܸீௌଵ െ ܸ௧௡ ) = 400 mV . The amplitude of the output
voltage from the first stage is ܸ௢ଵ = |‫ܣ‬௩ଵ |ܸ௜௡ = 10 × 1.25 mV = 12.5 mV . For M2, we find
2൫|ܸீௌ | െ หܸ௧௣ ห൯ = 400 mV which is much larger than 12.5 mV, so also for M2, the small-
signal approximation is reasonable.

We note that with an output amplitude of 100 mV, |‫ݒ‬஽ௌଶ | is larger than 900 mV, i.e.,
larger than |ܸ஽ௌଶsat | = |ܸீௌଶ | െ หܸ௧௣ ห = 200 mV,, so M2 is in the active region. Likewise,
with an amplitude of 12.5 mV for the drain voltage of M1, ‫ݒ‬஽ௌଵ is larger than 987.5 mV,
i.e., larger than ܸ஽ௌଵsat = ܸீௌଵ െ ܸ௧௡ = 200 mV, so M1 is in the active region.

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222
CMOS ANALOG IC DESIGN Solution to Problem 27

Question 4:
For finding the dominant pole, we estimate the equivalent time constants to ground for
the gate of M1, the gate of M2 and the output node.

For the gate of M1, the time constant ߬ଵ is the product of the resistor �� = 1 kΩ and the
input capacitance of the first stage which can be found using the Miller approximation (see
Eq. (4.80) in ‘CMOS Analog IC Design: Fundamentals’), i.e.

‫ܥ‬௜௡ଵ ؄ ‫ܥ‬௚௦ଵ + (1 + |‫ܣ‬௩ଵ |)‫ܥ‬௚ௗଵ = 100 fF + (1 + 10) × 20 fF = 320 fF, so

�� ≃ 1 kΩ × 320 fF = 320 ps.

For the gate of M2, the time constant ߬ଶ is the product of the resistor �� = 10 kΩ and the
input capacitance of the second stage which can be found using the Miller approximation,
i.e., ‫ܥ‬௜௡ଶ ؄ ‫ܥ‬௚௦ଶ + (1 + |‫ܣ‬௩ଶ |)൫‫ܥ‬௚ௗଶ + ‫ܥ‬௙௕ ൯ = 250 fF + (1 + 8) × (50 fF + 200 fF) = 2.5 pF,,
so �� ≃ 10 kΩ × 2.5 pF = 25 ns

For the output node, the time constant ߬ଷ may be estimated as the product of (�� � �� ) = 8 kΩ
and ‫ܥ‬௚ௗଶ + ‫ܥ‬௙௕ = 250 fF (see Eq. (4.82) in ‘CMOS Analog IC Design: Fundamentals’),
i.e., �� ≃ 2 ns.

Apparently, the dominant pole originates from the gate of M2, and we may estimate the −3
dB frequency to be �-3 dB ≃ 1/(2���� ) = 1/(2 × � × 25 ns) = 6.4 MHz.

Question 5:
Shown below is an LTspice schematic for the amplifier. The channel lengths have (somewhat
arbitrarily) been selected to �� = �� = 1 μm and the channel widths have been specified
according to the specified ܹ/‫ ܮ‬ratios. The capacitor ‘C3’ is the sum of ‫ܥ‬௚ௗଶ and ‫ܥ‬௙௕.

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223
CMOS ANALOG IC DESIGN Solution to Problem 27

For verifying the results from Question 1, we run a ‘.op’ simulation. From the output file,
we find ��� = −20.1 nV and ܸைଶ = 176.88 nV . Both values are sufficiently close to 0 V to
confirm that ܸைଵ = ܸைଶ = 0 V as requested. We may also open the error log file (‘Ctrl-L’)
from which we verify that ��� = ��� = 100 μA and ݃௠ଵ = ݃௠ଶ = 1 mA/V as used for the
calculations in Question 2.

For verifying the results from Question 2, we run the two ‘.tf ’ simulations shown (as
comments) in the LTspice schematic. For the simulation with ‘v(Vo1)’ as the output, we
find a transfer function of −10, i.e., ��� = −10 V/V. For the simulation with ‘v(Vo2)’ as
the output, we find a transfer function of 80, i.e., ‫ܣ‬௩ = 80 V/V . As ‫ܣ‬௩ = ‫ܣ‬௩ଵ ‫ܣ‬௩ଶ, we find
��� = �� /��� = −8 V/V. These results are identical to the results calculated in Question 2.

For verifying the results from Question 3, we run the ‘.dc’ simulation shown (as a comment)
in the LTspice schematic. This results in the following plot. From the plot, we see that an
output swing of ±100 mV corresponds to an input swing from −1.29 mV to +1.21 mV.
This is fairly close to the input swing of ±1.25 mV expected from the linear small-signal
calculation used in Question 2 but the simulation shows that the nonlinearities in the circuit
are visible for input signal amplitudes on the order of a few mV.

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224
CMOS ANALOG IC DESIGN Solution to Problem 27

The ‘.meas’ directives shown in the schematic finds the exact input voltages for an output
voltage of ±100 mV. These results are given in the error log file which reports ‘vin+:
v(vo2)=100m AT 0.00120954’ and ‘vin-: v(vo2)=-100m AT -0.00129591’.

For verifying the results from Question 4, we run the ‘.ac’ simulation shown (as a comment)
in the LTspice schematic. This results in the following plot.

From the plot, we find �-3 dB = 5.84 MHz which is somewhat smaller than the −3 dB
frequency found using the dominant-pole approximation. This is not surprising. The
additional non-dominant poles slightly reduce the −3 dB frequency.

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225
CMOS ANALOG IC DESIGN Solution to Problem 28

SOLUTION TO PROBLEM 28

Question 1:
At low frequencies, the capacitor ‫ܥ‬௖ is treated as an open circuit.

A node equation at the output (node B) gives ‫ݒ‬௢ /ܴଶ + ݃௠ଶ ‫ݒ‬௔ = 0 ֜ ‫ݒ‬௢ = െ݃௠ଶ ܴଶ ‫ݒ‬௔ .

A node equation at node A gives �� /�� + ��� (���� − ���� ) = 0 � �� = −��� �� (���� −
‫ݒ‬௜௡ష ) = െ݃௠ଵ ܴଵ ‫ݒ‬௜ௗ.

Inserting, we find ‫ݒ‬௢ = െ݃௠ଶ ܴଶ ‫ݒ‬௔ = ݃௠ଶ ܴଶ ݃௠ଵ ܴଵ ‫ݒ‬௜ௗ ֜ ‫ܣ‬଴ = ‫ݒ‬௢ /‫ݒ‬௜ௗ = ݃௠ଵ ܴଵ ݃௠ଶ ܴଶ ..

Question 2:
When including the capacitor ‫ܥ‬௖ , node equations at node A and node B gives:

Node A: ��� ��� + �� /�� + (�� � �� )����� = 0= 0

Node B: (�� � �� )����� + ��� ��� + �� /�� = 0= 0

Rearranging, we find

Node A: �� (1/�� + �����)� (1/� � +� ���=� ) ���

� �� ���� = =
��������
���� ���� ���

Node B: �� (��� � ���� ) + �� (1/�� + ���� ) = =0 0

From this, we find the transfer function

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226
CMOS ANALOG IC DESIGN Solution to Problem 28

ܸ௢ (‫)ݏ‬ ݃௠ଵ (݃௠ଶ െ ‫ݏ‬Ԝ‫ܥ‬௖ )

‫ܣ‬ௗ (‫= )ݏ‬ =
ܸ௜ௗ (‫( )ݏ‬1/ܴଵ + ‫ݏ‬Ԝ‫ܥ‬௖ )(1/ܴଶ + ‫ݏ‬Ԝ‫ܥ‬௖ ) + ‫ݏ‬Ԝ‫ܥ‬௖ (݃௠ଶ െ ‫ݏ‬Ԝ‫ܥ‬௖ )

݃௠ଵ (݃௠ଶ െ ‫ݏ‬Ԝ‫ܥ‬௖ )

=
1/(ܴଵ ܴଶ ) + ‫ݏ‬Ԝ‫ܥ‬௖ (1/ܴଵ + 1/ܴଶ + ݃௠ଶ )

1 െ ‫ݏ‬Ԝ‫ܥ‬௖ /݃௠ଶ
= ‫ܣ‬଴ ൬ ൰ q.e.d.
1 + ‫ݏ‬Ԝ‫ܥ‬௖ (ܴଵ + ܴଶ + ܴଵ ܴଶ ݃௠ଶ )

From this expression, we see that the transfer function has a right-half-plane zero at the frequency
߱Ԝ௭ = ݃௠ଶ /‫ܥ‬௖ and a left-half-plane pole at the frequency ߱௣ = 1/൫‫ܥ‬௖ (ܴଵ + ܴଶ + ܴଵ ܴଶ ݃௠ଶ )൯.

Question 3:
With ����
��≫ 1/���and
≫1/� and����
and ��≫
≫1/�
1/��� , we find �� ≃ 1/(�� �� ��� �� ), so

��� �� ��� �� ���

��� = �� ��� /(2��) ≃ = q.e.d.
2����� �� ��� �� 2����

Question 4:
The transfer function ‫ܣ‬ௗ (‫ )ݏ‬may be written as ‫ܣ‬ௗ (‫ܣ = )ݏ‬଴ (1 െ ‫ݏ‬/߱Ԝ௭ )/൫1 + ‫ݏ‬/߱௣ ൯.

For the amplifier with feedback, the transfer function is

‫ܣ‬ௗ (‫)ݏ‬
‫ܣ‬஼௅ (‫= )ݏ‬
1 + ߚ‫ܣ‬ௗ (‫)ݏ‬
‫ܣ‬଴ (1 െ ‫ݏ‬/߱Ԝ௭ )
=
൫1 + ‫ݏ‬/߱௣ ൯ ቀ1 + ߚ‫ܣ‬଴ (1 െ ‫ݏ‬/߱Ԝ௭ )/൫1 + ‫ݏ‬/߱௣ ൯ቁ
‫ܣ‬଴ (1 െ ‫ݏ‬/߱Ԝ௭ )
=
1 + ߚ‫ܣ‬଴ + ‫ݏ‬൫1/߱௣ െ ߚ‫ܣ‬଴ /߱Ԝ௭ ൯
1 െ ‫ݏ‬/߱Ԝ௭
= ‫ܣ‬଴஼௅ ቆ ቇ
1 + ‫ݏ‬/߱௣஼௅

where ߱Ԝ௭ = ݃௠ଶ /‫ܥ‬௖ was found in Question 2 and ‫ܣ‬଴஼௅ and ߱௣஼௅ are given by

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227
CMOS ANALOG IC DESIGN Solution to Problem 28

‫ܣ‬଴
‫ܣ‬଴஼௅ =
1 + ߚ‫ܣ‬଴
1 + ߚ‫ܣ‬଴ 1
߱௣஼௅ = = (1 + ߚ‫ܣ‬଴ )߱௣ ቆ ቇ
1/߱௣ െ ߚ‫ܣ‬଴ /߱Ԝ௭ 1 െ ߚ‫ܣ‬଴ ߱௣ /߱Ԝ௭

Question 5:
With ��� ≫ 1 , we find ���� ≃ 1/� and ߱௣஼௅ ؄ ߚ‫ܣ‬଴ ߱௣ /൫1 െ ߚ‫ܣ‬଴ ߱௣ /߱Ԝ௭ ൯. Using ݂௭ =
߱Ԝ௭ /(2Ԝߨ) and ‫ܣ‬଴ ߱௣ = ݃௠ଵ /‫ܥ‬௖ , we find

݃௠ଵ 1
߱௣஼௅ ؄ ߚ ൬ ൰൬ ൰
‫ܥ‬௖ 1 െ ߚ݂௧௔ /݂௭

Using ߱Ԝ௭ = ݃௠ଶ /‫ܥ‬௖ , we then find the gain-bandwidth product

1 1
GBW = ‫ܣ‬଴஼௅ ߱௣஼௅ /(2Ԝߨ) ؄ ݂௧௔ ൬ ൰ ؄ ݂௧௔ ൬ ൰
1 െ ߚ݂௧௔ /݂௭ 1 െ ߚ݃௠ଵ /݃௠ଶ

We notice that the zero causes the gain-bandwidth product of the feedback amplifier to be
larger than the gain-bandwidth product ݂௧௔ of the basic amplifier. For a feedback amplifier
using a basic amplifier with a single pole and no zero, the bandwidth ݂௣ is the bandwidth
of the basic amplifier multiplied by the factor (1 + ߚ‫ܣ‬଴ ) ؄ ߚ‫ܣ‬଴ . Introducing a right-half-
plane zero at the frequency ݂௭ increases the bandwidth by an extra factor (1 െ ߚ݂௧௔ /݂௭ )ିଵ .

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228
CMOS ANALOG IC DESIGN Solution to Problem 29

SOLUTION TO PROBLEM 29

Question 1:
Using Kirchhoff’s voltage law, we find that the voltage ܸ஻ across ܴ஻ is �� = ��� − |���� | −
|ܸீௌଶ |. Also, since ܴ஻, M1 and M2 are connected in series, the current is the same in these
devices, i.e., �� = ��� = ��� = 20 μA where ‫ܫ‬஻ is the current through ܴ஻.

For M1, we have the Shichman-Hodges model for a MOS transistor without channel-length
modulation:

1 ଶ
‫ܫ‬஽ଵ = ߤ௣ ‫ܥ‬௢௫ (ܹଵ /‫ܮ‬ଵ )൫|ܸீௌଵ | െ หܸ௧௣ ห൯
2

Notice that since M1 is a PMOS transistor, we use absolute values of the gate-source voltage
and the threshold voltage, and from the equation above, we find

2���� 2 × 20 μA
|���� | = ���� � + � = 0.7 V + � = 0.9 V
�� ��� (�� /�� ) 100 μA/V � × (5 μm/0.5 μm)

Since ‫ܫ‬஽ଵ = ‫ܫ‬஽ଶ and ܹଵ /‫ܮ‬ଵ = ܹଶ /‫ܮ‬ଶ, we find |ܸீௌଶ | = |ܸீௌଵ | = 0.9 V, so �� = ��� − |���� | −
|���� | = 3 V − 0.9 V − 0.9 V = 1.2 V.. From Ohm’s law, we find �� = �� /�� = 1.2 V/20 μA =
60 kΩ.

Transistors M1 and M3 form a current mirror, so

�� /��
��� = � � � = 20/10 × 20 μA = 40 μA
�� /�� ��

Likewise, M1 and M8 form a current mirror, so

�� /��
��� = � � � = 100/10 × 20 μA = 200 μA
�� /�� ��

Question 2:
The condition for a transistor to be in the active region is |��� | ≥ |��� | − |�� | .

For M1 and M2, we have |��� | = |��� | > |��� | − |�� | , so M1 and M2 are in the active region.

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229
CMOS ANALOG IC DESIGN Solution to Problem 29

For M3, we have |ܸீௌଷ | = |ܸீௌଵ | = 0.9 V. Also, ܸௌଷ = ܸ஽஽ = 3 V. From Kirchhoff’s voltage
law, we find |ܸ஽ଷ | = ܸூேష + |ܸீௌସ |. Using ‫ܫ‬஽ସ = ‫ܫ‬஽ଷ /2, we find |ܸீௌସ | from

��� 40 μA
|���� | = ���� � + � = 0.7 V + � = 0.8 V
�� ��� (�� /�� ) 100 μA/V � × (20 μm/0.5 μm)

Thus, ܸ஽ଷ = ܸூேష + |ܸீௌସ | = 1.5 V + 0.8 V = 2.3 V , resulting in |���� | = |2.3 V − 3.0 V| =
0.7 V > |���� | − ���� � = 0.9 V − 0.7 V = 0.2 V,, so M3 is in the active region.

For M4 and M5, we have |ܸீௌ | = 0.8 V and we find ܸ஽ସ = ܸ஽ହ = ܸீௌ଺ where (using
‫ܫ‬஽ହ = ‫ܫ‬஽଺ = ‫ܫ‬஽ଷ /2))

��� 40 μA
���� = ��� + � = 0.5 V + � = 0.641 V
�� ��� (�� /�� ) 200 μA/V × (5 μm/0.5 μm)
�

With ܸௌସ = ܸௌହ = ܸ஽ଷ = 2.3 V , we find |���� | = |���� | = |���� − ��� | = |0.641 V − 2.3 V| =

1.659 V > |���� | − ���� � = |���� | − ���� � = 0.8 V − 0.7 V = 0.1 V, so M4 and M5 are in
the active region.

For M6, we have ܸ஽ௌ଺ = ܸீௌ଺ > ܸீௌ଺ െ ܸ௧௡ , so M6 is in the active region.

For M7, we have for symmetry reasons ܸ஽ௌ଻ = ܸ஽ௌ଺ and since ܸீௌ଻ = ܸீௌ଺ = ܸ஽ௌ଺ , we find
ܸ஽ௌ଻ = ܸீௌ଻ > ܸீௌ଻ െ ܸ௧௡ , so M7 is in the active region.

For M8, we have |���� | = ��� − �� = 3.0 V − 1.5 V = 1.5 V and |���� | = |���� | = 0.9 V,,
i.e., |���� | > |���� | − ���� � = 0.9 V − 0.7 V = 0.2 V, so M8 is in the active region.

For M9, we have ܸ஽ௌଽ = ܸை = 1.5 V and ܸீௌଽ = ܸ஽ௌ଻ = ܸீௌ଺ = 0.641 V , i.e., ���� > ���� −
��� = 0.641 V − 0.5 V = 0.141 V , so M9 is in the active region.

Question 3:
The gain at low frequencies is the product of the gain of the differential stage with active
load and the gain of the common-source stage.

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230
CMOS ANALOG IC DESIGN Solution to Problem 29

The differential gain of the differential stage with active load is the transconductance of the
input transistors multiplied by the output resistance of the stage, i.e., ‫ܣ‬௩ଵ = െ݃௠ହ (‫ݎ‬ௗ௦ହ ‫ݎ צ‬ௗ௦଻ ).

For the common-source stage, the gain is the transconductance of M9 multiplied by the
output resistance of the stage, i.e., ‫ܣ‬௩ଶ = െ݃௠ଽ (‫ݎ‬ௗ௦଼ ‫ݎ צ‬ௗ௦ଽ ).

The total gain is ‫ܣ‬ௗ = ‫ܣ‬௩ଵ ‫ܣ‬௩ଶ = ݃௠ହ (‫ݎ‬ௗ௦ହ ‫ݎ צ‬ௗ௦଻ )݃௠ଽ (‫ݎ‬ௗ௦଼ ‫ݎ צ‬ௗ௦ଽ ), compare to Eq. (5.7) in
‘CMOS Analog IC Design: Fundamentals’.

Using ‫ܫ‬஽ଽ = ‫ܫ‬஽଼ and the approximation 1 + ���� ≃ 1, we find

2���� 2 × 20 μA
��� = = = 0.40 mA/V
|���� | − ���� � 0.8 V − 0.7 V

2���� 2 × 200 μA
��� = = = 2.83 mA/V
���� − ��� 0.641 V − 0.5 V

1 1
���� ≃ ���� ≃ = ��
= 500 kΩ
���� 0.1 V × 20 μA

1 1
���� ≃ ���� ≃ = = 50 kΩ
���� 0.1 V �� × 200 μA

Inserting in the expressions for the gain, we find ��� = −0.40 mA/V × (500 kΩ ∥ 500 kΩ) =
−100 V/V and ��� = −2.83 mA/V × (50 kΩ ∥ 50 kΩ) = −70.7 V/V giving a total gain of
�� = 7070 V/V ∼ 77 dB .

The small-signal output resistance is ���� = ���� ∥ ���� = 50 kΩ ∥ 50 kΩ = 25 kΩ, compare

to Eq. (5.8) in ‘CMOS Analog IC Design: Fundamentals’.

Question 4:
With the Miller capacitor being the only capacitor which must be taken into account, the −3 dB
bandwidth is given by the dominant pole caused by the output resistance (���� � ���� ) ≃ 250 kΩ
from the differential stage and the input capacitance to the second stage. This input capacitance
is found using the Miller approximation as ‫ܥ‬௜௡ଶ = ‫ܥ‬௖ (1 െ ‫ܣ‬௩ଶ ) = 1 pF × (1 + 70.7 V/V) =
71.7 pF. Thus, we find ��� �� = 1/(2���(���� � ���� )���� ) = 1/(2 × � × 250 kΩ × 71.7 pF) =
8.88 kHz.

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231
CMOS ANALOG IC DESIGN Solution to Problem 29

Question 5:
With the output connected back to the inverting input, we have a feedback amplifier with
a feedback factor ߚ = 1. From the feedback theory explained in Chapter 6 in ‘CMOS
Analog IC Design: Fundamentals’, we find that the output resistance of the amplifier with
feedback is ‫ݎ‬௢௨௧஼௅ = ‫ݎ‬௢௨௧ /(1 + ߚ‫ܣ‬଴ ) where ‫ܣ‬଴ is the low-frequency gain of the opamp, i.e.,
‫ܣ‬଴ = ‫ܣ‬ௗ = 7070 V/V. Thus, ������ = ���� /(1 + ��� ) = 25 kΩ/7071 = 3.54 Ω.

Also from the feedback theory, we find that the bandwidth of the amplifier with feedback
is found as the bandwidth of the amplifier without feedback multiplied by the factor
(1 + ߚ‫ܣ‬଴ ) (the amount of feedback). Thus, for the buffer, we find a −3 dB frequency of
8.88 kHz × 7071 = 62.8 MHz .

Question 6:
The following figure shows the LTspice schematic corresponding to the opamp. The transistor
models have been defined with ߣ = 0.1 V ିଵ , so for the simulated results, the channel-length
modulation is included in all question.

For verifying the answers for Questions 1 and 2, we run a ‘.op’ simulation. From the output
file, we note that ܸை = 1.46183 V , i.e., very close to the specified value of ܸை = ܸ஽஽ /2 = 1.5 V.

From the ‘.op’ simulation, we also find the results from the error log file shown after the
LTspice schematic. We notice that the bias currents are close to the anticipated values, thus
confirming the calculation of ܴ஻. Only ‫ܫ‬஽଼ = ‫ܫ‬஽ଽ is about 7% larger than the calculated values.

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232
CMOS ANALOG IC DESIGN Solution to Problem 29

Error log file

The error log file also lists ܸ஽ௌ and ܸீௌ െ ܸ௧ = ܸ஽ௌsat for each transistor, and we note that
|ܸ஽ௌ | > |ܸ஽ௌsat | for all transistors, confirming that all transistors are in the active region as
found in Question 2.

For verifying the results for Question 3, we may run the ‘.tf ’ simulations shown as comments
in the LTspice schematic. The directive ‘.tf v(Vo1) Vin+’ finds the gain in the first stage.
From the output file, we find the gain ��� = −120 V/V. The directive ‘.tf v(Vo) Vin+’ finds
the total gain and the output resistance. From the output file, we find ‫ܣ‬௩ = 10091 V/V and
���� = 26.819 kΩ. We notice that the values of gain and output resistance are somewhat
higher than the values calculated in Question 3. In these calculations, the approximation
1 + ���� ≃ 1 was used. This leads to smaller values of ݃௠ and ‫ݎ‬ௗ௦ than what is found from
the simulations. From the error log file shown above, we find

��� = 0.431 mA/V

��� = 3.14 mA/V
���� = 1/���� = 1/1.71 μA/V = 585 kΩ
���� = 1/���� = 1/1.87 μA/V = 535 kΩ
���� = 1/���� = 1/18.6 μA/V = 53.8 kΩ
���� = 1/���� = 1/18.7 μA/V = 53.5 kΩ

From the expressions for the gain, we find ��� = −0.431 mA/V × (585 kΩ ∥ 535 kΩ) =
−120.4 V/V and ��� = −3.14 mA/V × (53.8 kΩ ∥ 53.5 kΩ) = −84.18 V/V giving a total
gain of �� = 10135 V/V ∼ 80.1 dB..

The small-signal output resistance is ���� = ���� ∥ ���� = 53.8 kΩ ∥ 53.5 kΩ = 26.8 kΩ.

These values match the simulated values of gain and output resistance very closely.

For verifying the result for Question 4, we run the ‘.ac’ simulation shown as a comment
in the LTspice schematic. Notice the specification of the input voltage sources ‘Vin+’ and
‘Vin-’. The ac amplitude is specified to be 0.5 V and the ac phase for ‘Vin+’ is specified to
be 0° while the ac phase for ‘Vin-’ is specified to be 180°. This gives differential ac input
with an amplitude of 1 V.
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233
CMOS ANALOG IC DESIGN Solution to Problem 29

From the simulation, we find the following plot of ܸ௢, showing a −3 dB frequency of 6.67 kHz,
which is somewhat lower than the calculated result. Using the simulated values of gain and
small-signal parameters, we find ‫ܥ‬௜௡ଶ = ‫ܥ‬௖ (1 െ ‫ܣ‬௩ଶ ) = ‫ܥ‬௖ (1 െ ‫ܣ‬ௗ /‫ܣ‬௩ଵ ) = 1 pF × (1 + 10091/
120) = 85 pF and ��� �� = 1/(2���(���� ∥ ���� )���� ) = 1/(2 × � × (585 kΩ ∥ 535 kΩ) ×
85 pF) = 6.70 kHz which is a very close match to the simulated value.

The simulation also shows that ‫ܣ‬ௗ (݂) has a zero at a high frequency (between 100 MHz
and 1 GHz), so the gain function is not just a simple first-order lowpass function.

For verifying the results for the buffer amplifier, Question 5, we modify the LTspice schematic
as shown in the following figure.

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234
CMOS ANALOG IC DESIGN Solution to Problem 29

Using the directive ‘.tf v(Vo) Vin+’, we find from the ‘.tf ’ simulation a closed-loop output
resistance of 2.66 Ω which is somewhat lower than the value found in Question 5 but
an exact match to ������ = ���� /(1 + ��� ) = 26.819 kΩ/(1 + 10091) = 2.66 Ω with the
simulated values of ‫ݎ‬௢௨௧ and ‫ܣ‬଴.

With the ‘.ac’ simulation shown as a comment in the LTspice schematic, we find the plot of ܸ௢
shown below from which we find a −3 dB bandwidth of 79.4 MHz. This is somewhat higher
than the value calculated in Question 5 or calculated from the simulated values of ݂ିଷ ୢ୆ and
‫ܣ‬଴. From the simulated values, we find (1 + ߚ‫ܣ‬଴ )݂ିଷ ୢ୆ = (1 + 10091) × 6.67 kHz = 67.3 MHz .
However, we notice from the simulation plot that the frequency response is not a simple first-
order response with only a dominant pole, so in the buffer amplifier, the high-frequency zero
found from the simulation of ‫ܣ‬ௗ (݂) modifies the frequency response, leading to a somewhat
higher bandwidth. It can be shown (see Problem 28) that the frequency of the dominant
pole in the feedback amplifier is multiplied by an extra factor (1 − ���� /��� )�� = (1 − 1 ×
0.431 mA/V/3.14 mA/V)ିଵ = 1.159 , giving a dominant pole at 67.3 MHz × 1.159 = 78
MHz which matches the simulated bandwidth very well.

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CMOS ANALOG IC DESIGN Solution to Problem 30

SOLUTION TO PROBLEM 30

Question 1:
For the amplifier, the low-frequency gain is ‫ܣ‬଴ so the low-frequency loop gain is ‫ܮ‬଴ = ߚ‫ܣ‬଴ =
100 ∼ 40 dB. The magnitude of ‫ )݂݆(ܮ‬is

1 + (݂/݂Ԝ௭ )ଶ
|‫ܮ = |)݂݆(ܮ‬଴ ඨ ଶ ଶ
ቀ1 + ൫݂/݂௣ଵ ൯ ቁ ቀ1 + ൫݂/݂௣ଶ ൯ ቁ

With ݂Ԝ௭ = ݂௣ଶ, this expression can be simplified to

1
|‫ܮ = |)݂݆(ܮ‬଴ ඨ ଶ
ቀ1 + ൫݂/݂௣ଵ ൯ ቁ

This corresponds to an amplitude plot starting at 40 dB at very low frequencies and a

breakpoint at ݂௣ଵ = 1 kHz where the slope of the amplitude changes to −20 dB/dec as
shown in the Bode plot below.

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236
CMOS ANALOG IC DESIGN Solution to Problem 30

The phase of the loop gain is

��(��) = − arctan(�/��� ) − arctan��/��� � − arctan��/��� �

Thus, the phase plot (black plot) is the sum of the red, green and blue plots corresponding
to the phase shifts from ݂௣ଵ, ݂௣ଶ and ݂Ԝ௭, respectively. Since ݂௣ଶ = ݂Ԝ௭ , the green plot and the
blue plot overlap and each of them gives a phase shift of −45° at ݂ = 1 MHz as marked
by a dot in the phase plot.

Question 2:
From the Bode plot, we find the unity-gain frequency ݂௧ = 100 kHz and we can estimate
the phase margin to be about 90°. However, since a breakpoint in the phase plot appears
at the frequency ݂௧, the estimation of the phase margin is not very precise.

Using a more precise calculation, we find the unity-gain frequency ݂௧ for ‫ )݂݆(ܮ‬from

1
|�(��)| = 1 � �� � � =1
�1 + ��� /��� � �
�
� ��� = 1 + ��� /��� �

� �� = ��� ���� − 1 = 1 kHz × √9999 = 100 kHz

The phase margin is PM = 180° െ ൫െ‫݂݆(ܮס‬Ԝ௧ )൯ = 180° + ‫݂݆(ܮס‬Ԝ௧ ) where

��(��� ) = − arctan(�� /��� ) − arctan��� /��� � − arctan��� /��� �

= − arctan(100 kHz/1 MHz) − arctan(100 kHz/1 kHz) − arctan(100 kHz/1 MHz)
= −5.71° − 89.43° − 5.71° = −100.85°

From this, we find PM = 180° + ��(�\�� ) = 180° − 100.85° = 79.15° .

Question 3:
For a phase margin of 60°, we find ��(��� ) = −120° , i.e.,

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237
CMOS ANALOG IC DESIGN Solution to Problem 30

arctan(݂௧ /݂Ԝ௭ ) + arctan൫݂௧ /݂௣ଵ ൯ + arctan൫݂௧ /݂௣ଶ ൯ = 120°

With ݂Ԝ௭ = ݂௣ଶ = 1 MHz and �� � ��� ⇒ arctan��� /��� � ≃ 90° , this expression can be
simplified as follows:

arctan(�� /��� ) + arctan��� /��� � + arctan��� /��� � = 120°

⇒ 2 arctan(�� /1 MHz) + 90° ≃ 120°
⇒ arctan(�� /1 MHz) = 15° ⇒ �� ≃ 1 MHz × tan(15°) = 0.268 MHz

With �� = ��� ≫ 1 , we have ݂௧ ؄ ߚ‫ܣ‬଴ ݂௣ଵ ֜ ߚ ؄ ݂௧ /൫‫ܣ‬଴ ݂௣ଵ ൯ = 268 kHz/(1000 × 1 kHz) =
0.268. Thus, the maximum value of ߚ for PM ≥ 60° is ߚԜ୫ୟ୶ = 0.268.

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238
CMOS ANALOG IC DESIGN Solution to Problem 31

SOLUTION TO PROBLEM 31

Question 1:
With ܸ஽ = 1.2 V, we find the drain current �� = (��� − �� )/�� = (1.8 V − 1.2 V)/30 kΩ =
20 μA .

From ݃௠ = 2Ԝ‫ܫ‬஽ /(ܸீௌ െ ܸ௧ ), we find ��� � �� = �eff = 2��� /�� = 2 × 20 μA/0.2 mA/V =
0.2 V.

From ݃௠ = ߤ௡ ‫ܥ‬௢௫ (ܹ/‫ீܸ()ܮ‬ௌ െ ܸ௧ ) , we find

�� 0.2 mA/V
� = �� � = 0.9 μm × � � = 5 μm
�� ��� (��� � �� ) 180 μA/V � × 0.2 V

Question 2:
The bias value of ‫ݒ‬ௌ is found from Ohm’s law: ܸௌ = ܴௌ ‫ܫ‬ௌ = ܴௌ ‫ܫ‬஽ = 0.3 V .

The bias value of ‫ݒ‬ூே is found as ܸூே = ܸௌ + ܸீௌ = ܸௌ + ܸeff + ܸ௧ = 0.9 V..

Question 3:
The small-signal diagram is shown below.

A node equation at the source of the transistor gives ݃௠ ‫ݒ‬௚௦ = ݃௠ (‫ݒ‬௜௡ െ ‫ݒ‬௦ ) = ‫ݒ‬௦ /ܴௌ ..

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239
CMOS ANALOG IC DESIGN Solution to Problem 31

Rearranging, we find
1 �� �� ��
�� � + �� � = �� ��� ⇒ =
�� ��� 1 + �� ��

Inserting numerical values, we find

�� 15 kΩ × 0.2 mA/V
= = 0.75 V/V
��� 1 + 15 kΩ × 0.2 mA/V

The drain voltage is found from

�� �� �� ��
�� = −�� �� ��� = −�� �� (��� − �� ) = −�� �� ��� �1 − � = −��� � �
1 + �� �� 1 + �� ��
�� �� ��
⇒ =−
��� 1 + �� ��

Inserting numerical values, we find

�� 30 kΩ × 0.2 mA/V
=− = −1.5 V/V
��� 1 + 15 kΩ × 0.2 mA/V

Question 4:

We may find the output resistance at the drain by resetting ‫ݒ‬௜௡ , i.e., ‫ݒ‬௜௡ ൌ Ͳ, and applying
a test voltage ‫ –•‡–ݒ‬at the drain. The output resistance is then found as ‫ݎ‬௢௨௧ǡௗ ൌ ‫ –•‡–ݒ‬Ȁ݅–‡•–
where ݅–‡•– is the current delivered by ‫ –•‡–ݒ‬. The current flowing in ܴ஽ is ‫ –•‡–ݒ‬Ȁܴ஽ . The
current flowing into the drain is ݃௠ ‫ݒ‬௚௦ ൌ ‫ݒ‬௦ Ȁܴௌ . Since ‫ݒ‬௚௦ ൌ െ‫ݒ‬௦ for ‫ݒ‬௚ ൌ ‫ݒ‬௜௡ ൌ Ͳ, we
find െ݃௠ ‫ݒ‬௦ ൌ ‫ݒ‬௦ Ȁܴௌ , and this relation is only fulfilled for ‫ݒ‬௦ ൌ Ͳ, so the current flowing
into the drain is 0. Thus, ݅–‡•– ൌ ‫ –•‡–ݒ‬Ȁܴ஽ ֜ ‫ݎ‬௢௨௧ǡௗ ൌ ‫ –•‡–ݒ‬Ȁ݅–‡•– ൌ ܴ஽ ൌ ͵Ͳȳ.

Applying a test voltage to the source terminal, we find ‫ݒ‬௚௦ ൌ െ‫ –•‡–ݒ‬, so ݅–‡•– ൌ ‫ –•‡–ݒ‬Ȁܴௌ ൅

݃௠ ‫ݎ ֜ –•‡–ݒ‬௢௨௧ǡ௦ ൌ ‫ –•‡–ݒ‬Ȁ݅–‡•– ൌ ሺͳȀܴ௦ ൅ ݃௠ ሻିଵ ൌ ሺͳȀ݃௠ ሻ ‫ܴ צ‬ௌ ൌ ܴௌ Ȁሺͳ ൅ ܴௌ ݃௠ ሻ ൌ

ͳͷȳȀሺͳ ൅ ͳͷȳ ൈ ͲǤʹȀሻ ൌ ͵Ǥ͹ͷȳ.

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CMOS ANALOG IC DESIGN Solution to Problem 31

Question 5:
In the small-signal diagram, ‫ܥ‬௚௦ now appears as a capacitor from gate to source as shown
below.

A node equation at the source of the transistor now gives

݃௠ ሺܸ௜௡ െ ܸ௦ ሻ ൅ ‫ܥݏ‬௚௦ ሺܸ௜௡ െ ܸ௦ ሻ ൌ ܸ௦ Ȁܴௌ

֜ ܸ௦ ൫ͳȀܴௌ ൅ ݃௠ ൅ ‫ܥݏ‬௚௦ ൯ ൌ ൫݃௠ ൅ ‫ܥݏ‬௚௦ ൯ܸ௜௡

ܸ௦ ݃௠ ൅ ‫ܥݏ‬௚௦ ܴௌ ݃௠ ൅ ‫ܥݏ‬௚௦ ܴௌ
ൌ ൌ
ܸ௜௡ ͳȀܴௌ ൅ ݃௠ ൅ ‫ܥݏ‬௚௦ ͳ ൅ ܴௌ ݃௠ ൅ ‫ܥݏ‬௚௦ ܴௌ

From this expression, we find the frequency of the zero as

ͳ ݃௠ ͳ ͲǤʹ mA/V
݂௭ ൌ ൬ ൰ቆ ቇ ൌ ൬ ൰൬ ൰ ൌ ͳͲͲ MHz
ʹߨ ‫ܥ‬௚௦ ʹ ൈ ߨ ͲǤ͵ͳͺ pF

We also find the frequency of the pole as

ͳ ͳ ൅ ܴௌ ݃௠ ͳ ͳ ൅ ͳͷȳ ൈ ͲǤʹȀ
݂௣ ൌ ൬ ൰ቆ ቇൌ൬ ൰൬ ൰ ൌ ͳ͵͵ œ
ʹߨ ܴௌ ‫ܥ‬௚௦ ʹൈߨ ͳͷȳ ൈ ͲǤ͵ͳͺ’

Question 6:
The drain voltage is found from

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241
CMOS ANALOG IC DESIGN Solution to Problem 31

ܴௌ ݃௠ ൅ ‫ܥݏ‬௚௦ ܴௌ
ܸௗ ൌ െܴ஽ ݃௠ ܸ௚௦ ൌ െܴ஽ ݃௠ ሺܸ௜௡ െ ܸ௦ ሻ ൌ െܴ஽ ݃௠ ܸ௜௡ ቆͳ െ ቇ
ͳ ൅ ܴௌ ݃௠ ൅ ‫ܥݏ‬௚௦ ܴௌ
ͳ ܸௗ ܴ஽ ݃௠
ൌ െܴ஽ ݃௠ ܸ௜௡ ቆ ቇ֜ ൌെ
ͳ ൅ ܴௌ ݃௠ ൅ ‫ܥݏ‬௚௦ ܴௌ ܸ௜௡ ͳ ൅ ܴௌ ݃௠ ൅ ‫ܥݏ‬௚௦ ܴௌ

This is a first-order low-pass transfer function with a low-frequency gain of െܴ஽ ݃௠ Ȁሺͳ ൅
ܴௌ ݃௠ ሻ ൌ െͳǤͷȀ ‫͵ ׽‬Ǥͷʹ† as found in Question 3 and a −3 dB frequency corresponding
to the pole frequency ݂௣ ൌ ሺͳ ൅ ܴௌ ݃௠ ሻȀ൫ʹߨԜܴௌ ‫ܥ‬௚௦ ൯ ൌ ͳ͵͵ œ found in Question 5.

Question 7:
For verifying the results, we use the LTspice schematic shown below.

For verifying the results for Questions 1 and 2, we run a ‘.op’ simulation and check the
voltages ܸ஽ and ܸௌ . We find ܸ஽ ൌ ͳǤʹ and ܸௌ ൌ ͲǤ͵ as expected. From the error log
file, we find ݃௠ = 0.2 mA/V as expected.

For verifying the numerical values for Questions 3 and 4, we run the two different ‘.tf ’
simulations shown in the schematic and check the values of transfer function and output
impedance. From ‘.tf v(Vd) Vin’, we find a gain of −1.5 and an output impedance of 30
kΩ as expected and from ‘.tf v(Vs) Vin’, we find a gain of 0.75 and an output impedance
of 3.75 kΩ as expected.

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242
CMOS ANALOG IC DESIGN Solution to Problem 31

For verifying the result for Question 5, we run the ‘.ac’ simulation shown in the schematic.
From this, we may plot ܸ௦ as shown below. We notice that the gain changes from −2.5 dB
¾ 0.75 V/V to 0 dB ¾ 1 V/V at a frequency of slightly more than 100 MHz as expected
from the calculated values of pole frequency and zero frequency. As expected, the pole
frequency is higher than the zero frequency and the gain at very high frequencies is 0 dB
as the term ‫ܥݏ‬௚௦ ܴௌ becomes dominant in both the numerator and the denominator of the
transfer function. Essentially, the capacitor ‫ܥ‬௚௦ shorts the input node and the output node
at very high frequencies.

For verifying the result for Question 6, we plot ܸௗ from the ‘.ac’ simulation as shown
below. From the plot, we find a low-frequency gain of 3.52 dB and a −3 dB bandwidth of
133 MHz as expected.

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CMOS ANALOG IC DESIGN Solution to Problem 32

SOLUTION TO PROBLEM 32

Question 1:
Using Kirchhoff’s voltage law and Ohm’s law, we find ܸீௌଵ ൌ ܸீௌଶ ൅ ܴ஻ ‫ܫ‬ை .

From the Shichman-Hodges transistor model, we find

ʹ‫ܫ‬஽
ܸீௌ ൌ ܸ௧ ൅ ඨ
ߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ

For M1, we find with ‫ܫ‬஽ ൌ ‫ܫ‬ூே ൌ ͶͷɊ:

ʹ ൈ ͶͷɊ
ܸீௌଵ ൌ ͲǤͶͲ ൅ ඨ ൌ ͲǤͻͲͲ
ͳͺͲɊȀ ଶ ൈ ሺʹɊȀͳɊሻ

For M2, we find with ‫ܫ‬஽ ൌ ‫ܫ‬ை ൌ ͷɊ:

ʹ ൈ ͷɊ
ܸீௌଶ ൌ ͲǤͶͲ ൅ ඨ ൌ ͲǤͷ͸͹
ͳͺͲɊȀ ଶ ൈ ሺʹɊȀͳɊሻ

From this, we find ܴ஻ ൌ ሺܸீௌଵ െ ܸீௌଶ ሻȀ‫ܫ‬ை ൌ ሺͲǤͻͲͲ െ ͲǤͷ͸͹ሻȀͷɊ ൌ ͸͸Ǥ͹ȳ .

Question 2:
M1 is in the active region since ܸ஽ௌଵ ൌ ܸீௌଵ ൐ ܸீௌଵ െ ܸ௧ .

The maximum value of ܴ௅ is limited by the minimum output voltage ܸை‹ required to keep
M2 in the active region. This requires ܸ஽ௌଶ ൒ ܸீௌଶ െ ܸ௧ ֜ ܸ஽ଶ ൒ ܸீଶ െ ܸ௧ ֜ ܸை‹ ൌ ܸீଶ െ ܸ௧ ൌ
ܸீௌଵ െ ܸ௧ ൌ ͲǤͻ െ ͲǤͶ ൌ ͲǤͷ , resulting in ܴ௅Ԝƒš ൌ ሺܸ஽஽ െ ܸை‹ ሻȀ‫ܫ‬ை ൌ ሺͳǤͺ െ ͲǤͷሻȀ
ͷɊ ൌ ʹ͸Ͳȳ.

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CMOS ANALOG IC DESIGN Solution to Problem 32

Question 3:
The output resistance of the current source is the output resistance of a common-gate
configuration which is given by

‫ݎ‬௢௨௧ ൌ ܴ஻ ൅ ሺͳ ൅ ݃௠ଶ ܴ஻ ሻ‫ݎ‬ௗ௦ଶ ؄ ‫ݎ‬ௗ௦ଶ ൅ ݃௠ଶ ‫ݎ‬ௗ௦ଶ ܴ஻

see ‘CMOS Analog IC Design: Fundamentals’, Eq. (4.25).

From ‫ݎ‬ௗ௦ଶ ؄ ͳȀሺߣ‫ܫ‬ை ሻ and ݃௠ଶ ؄ ඥʹߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻ, we find

‫ݎ‬ௗ௦ଶ ؄ ͳȀሺͲǤͳ ିଵ ൈ ͷɊሻ ൌ ʹȳ

݃௠ଶ ؄ ඥʹ ൈ ͳͺͲɊȀ ଶ ൈ ሺʹɊȀͳɊሻ ൌ ͸ͲɊȀ
֜ ‫ݎ‬௢௨௧ ؄ ʹȳ ൅ ͸ͲɊȀ ൈ ʹȳ ൈ ͸͸Ǥ͹ȳ ൌ ͳͲȳ

From ‫ݎ‬ௗ௦ଶ ൌ ሺͳ ൅ ߣܸ஽ௌଶ ሻȀሺߣ‫ܫ‬ை ሻ,, we see that ‫ݎ‬ௗ௦ଶ is somewhat larger than 2 MΩ because
of the term ߣܸ஽ௌଶ. Also ݃௠ଶ is somewhat larger, ݃௠ଶ ൌ ඥʹߤ௡ ‫ܥ‬௢௫ ሺܹȀ‫ܮ‬ሻሺͳ ൅ ߣܸ஽ௌଶ ሻ . With
a value of about 1 V for ܸ஽ௌଶ, we find a value for ‫ݎ‬௢௨௧ which is about 10% higher than
the value found above.

Question 4:
With a doubling of both W and L for both transistors, the ratio ܹ/‫ ܮ‬is unchanged but the
channel-length modulation parameter h is reduced by a factor of 2, i.e., ߣ = 0.05 V ିଵ. This
causes a doubling of the transistor output resistances while the transconductances remain
unchanged when assuming ���� ≪ 1 . Thus, the output resistance ‫ݎ‬௢௨௧ ؄ ‫ݎ‬ௗ௦ଶ + ݃௠ଶ ‫ݎ‬ௗ௦ଶ ܴ஻
is doubled, i.e., ���� ≃ 20 MΩ.

Question 5:
Shown below is an LTspice schematic where ܴ஻ is specified to 66.7 kΩ and h is specified
to 0 V−1. The load resistor is specified to �� = 20 kΩ which ensures that M2 is in the active
region when verifying the answer to Question 1. From the error log file from a simulation
with ܴ௅ = 20 kΩ, we find ��� = 5.00 μA as requested, thus verifying the value of ܴ஻.

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245
CMOS ANALOG IC DESIGN Solution to Problem 32

For verifying the answer to Question 2, we run a ‘.op’ simulation with ܴ௅ stepped from 220
kΩ to 300 kΩ. This gives the following plot of ‫ܫ‬ை = ‫ܫ‬஽ଶ and we find that for �� = 260 kΩ,,
M2 is just at the border between the active region and the triode region.

For verifying the answer to Question 3, we modify the transistor model to include the
channel-length modulation parameter and we connect a dc voltage to the drain of M2 instead
of the load resistor ܴ௅. The dc value is selected to 0.9 V, ensuring M2 in the active region.
The new LTspice schematic is shown below. For finding the output resistance, we run a
‘.tf ’ simulation with ‘Vo’ as the source and ‘v(Vo)’ as the output. From this simulation, we
find the output resistance of the current source as ‘vo#Input_impedance’. A value of 11.2
MΩ is found which matches the calculated value reasonably well, taking the drain-source
voltage of M2 into consideration.

We may also run a ‘.op’ simulation to find the small-signal parameters. From this, we find
݃௠ଶ = 60.5 mA/V and ���� = 0.454 μA/V , corresponding to 2.20 MΩ. Again, considering
the channel-length modulation, these values match the calculated values reasonably well.

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246
 CMOS ANALOG IC DESIGN Solution to Problem 32

Finally, for verifying the answer to Question 4, we change ‘Lambda’ in the transistor model
specification to 0.05 and we change W and L for both transistors to 4 µm and 2 µm, respectively.
From the ‘.tf’ simulation, we now find the output resistance to be 21.1 MΩ which is as expected
�� ��� (�/�) = 800
about the� ,value
μA/V
twice ��� =found and � = 0.1 V �� , ܹ ൌ ʹɊ and � = 1 μm.
0.6 Vwith

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247
CMOS ANALOG IC DESIGN Solution to Problem 33

SOLUTION TO PROBLEM 33

Question 1:
The ‫ܣ‬-circuit consists of the gain stage ‫ )ݏ(ܩ‬and the transistor M1 with the load resistance
ܴଵ + ܴଶ. From this, we find

‫ܩ‬଴ Ԝ݃௠ଵ (ܴଵ + ܴଶ )

‫݃)ݏ(ܩ = )ݏ(ܣ‬௠ଵ (ܴଵ + ܴଶ ) =
൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯

The ߚ-circuit is the voltage divider consisting of ܴଵ and ܴଶ, i.e., ߚ = ܴଵ /(ܴଵ + ܴଶ ).

The loop gain is the product of ‫ )ݏ(ܣ‬and ߚ, i.e.,

‫ܩ‬଴ Ԝ݃௠ଵ ܴଵ
‫݃)ݏ(ܩ = )ݏ(ܮ‬௠ଵ ܴଵ = q.e.d.
൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯

At low-frequencies, we find �� = �� ���� (�� + �� ) = 1000 V/V × 0.1 mA/V × (1 kΩ +

9 kΩ) = 1000 V/V and � = �� /(�� + �� ) = 1 kΩ/(1 kΩ + 9 kΩ) = 0.1 V/V . This results
in ‫ܮ‬଴ = ‫ܣ‬଴ Ԝߚ = 1000 V/V × 0.1 V/V = 100 V/V.

The low-frequency value of ܸ௢ /ܸ௜௡ is ܸ௢ (0)/ܸ௜௡ = ‫ܣ‬଴ /(1 + ‫ܮ‬଴ ) = 1000 V/V/(1 + 100) =
9.90 V/V .

Question 2:
The gain-bandwidth product of the loop gain is ߱௧௟ = ‫ܮ‬଴ Ԝ߱௣ଵ = 100 × 20 × 10ଷ rad/s = 2 ×
10଺ rad/s .

Question 3:
For finding the phase margin, we may find the frequency ߱௧ where the magnitude of the
loop gain is 1, i.e.,

�� ���
� �=1⇒ � � =1
�1 + ��� /��� ��1 + ���� /��� � �1 + ��� /��� � � �1 + ��� /��� � �

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248
CMOS ANALOG IC DESIGN Solution to Problem 33

With ‫ܮ‬଴ = 100, we may assume ߱௧ ‫߱ ب‬௣ଵ, so the equation above may be modified as follows:

‫ܮ‬ଶ଴
ଶ ଶ =1
൫߱௧ /߱௣ଵ ൯ ቀ1 + ൫߱௧ /߱௣ଶ ൯ ቁ
ଶ ଶ
֜ ൫߱௧ /߱௣ଵ ൯ ቀ1 + ൫߱௧ /߱௣ଶ ൯ ቁ = ‫ܮ‬ଶ଴
ଶ ସ ଶ
֜ ൫߱௧ /߱௣ଵ ൯ + ൫߱௧ /߱௣ଵ ൯ ൫߱௣ଵ /߱௣ଶ ൯ = ‫ܮ‬ଶ଴

ଶ
This is a quadratic equation in ൫߱௧ /߱௣ଵ ൯ .

ଶ �
Inserting numerical values and solving for ൫߱௧ /߱௣ଵ ൯ , we find ��� /��� � = 8284 ⇒
߱௧ /߱௣ଵ = 91.0 ֜ ߱௧ = 91.0 × 20 × 10ଷ rad/s = 1.82 × 10଺ rad/s.

The phase margin PM is then calculated from

PM = 180° − arctan��� /��� � − arctan��� /��� �

1.82 × 10� rad/s 1.82 × 10� rad/s
= 180° − arctan � � − arctan � �
20 × 10� rad/s 4 × 10� rad/s

= 180° − 89.4° − 24.5°

= 66.1°

We may also find the phase margin by realizing that ߱௣ଶ = 2Ԝ߱௧௟ which gives a phase
margin of 65.5°, see ‘CMOS Analog IC Design: Fundamentals’, Fig. 6.35(a) or table in
Chapter 9.8. The difference between this value and the value calculated above is an extra
contribution of 0.6° because the phase shift from the dominant pole is not −90° as assumed
in Fig. 6.35(a) but only −89.4° as calculated above.

Question 4:
With �� � ��� ⇒ arctan��� /��� � � 90°, the expression for the phase margin can be
simplified to PM = 180° − arctan��� /��� � − arctan��� /��� � � 90° − arctan��� /��� �.

For PM = 76° , we find �� = ��� × tan(90° − PM) = 0.25 × ��� = 1 × 10� rad/s .

From ‫݆߱(ܮ‬௧ ) = 1, we then find, using ߱௧ ‫߱ ب‬௣ଵ:

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249
CMOS ANALOG IC DESIGN Solution to Problem 33

‫ܮ‬ଶ଴
ଶ ଶ =1
൫߱௧ /߱௣ଵ ൯ ቀ1 + ൫߱௧ /߱௣ଶ ൯ ቁ
ଶ
֜ ߱௣ଵ = (߱௧ /‫ܮ‬଴ )ට1 + ൫߱௧ /߱௣ଶ ൯
= (10଺ rad/s/100) × ඥ1 + 0.25ଶ = 10.3 × 10ଷ rad/s

We may also find the new value of ߱௣ଵ by realizing that a phase margin of 76° requires
߱௣ଶ = 4Ԝ߱௧௟ , see ‘CMOS Analog IC Design: Fundamentals’, Fig. 6.35(a) or table in Chapter
9.8. From this, we find ߱௣ଵ = ߱௧௟ /‫ܮ‬଴ = ߱௣ଶ /(4Ԝ‫ܮ‬଴ ) = 10 × 10ଷ sିଵ.

We may use LTspice to verify the phase-margin calculations. The following figure shows a
schematic for modeling the loop gain. Resistor ܴ௣ଵ and capacitor ‫ܥ‬௣ଵ model the dominant
pole, ��� = 1/(10 kΩ × 5 nF) = 20 × 10� rad/s , while ܴ௣ଶ and ‫ܥ‬௣ଶ model the non-
dominant pole, ��� = 1/(10 kΩ × 25 pF) = 4 × 10� rad/s. The gain in the controlled
voltage source is equal to ‫ܮ‬଴.

From a ‘.ac’ simulation, we can find the unity gain frequency ݂௧ and the phase of the loop
gain for ݂ = ݂௧ . We find ݂௧ = 290 kHz, corresponding to ߱௧ = 1.82 × 10଺ rad/s and we
find the phase to be −114°, corresponding to a phase margin of 66°.

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250
CMOS ANALOG IC DESIGN Solution to Problem 33

Reducing the dominant pole to 10.3 × 103 rad/s by increasing ‫ܥ‬௣ଵ to 9.71 nF, we find the
gain plot shown below. From this, we find a phase margin of 76.5°. Again, the approximation
arctan൫߱௧ /߱௣ଵ ൯ ؄ 90° causes a small difference between simulated and calculated phase
margin.

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251
CMOS ANALOG IC DESIGN Solution to Problem 34

SOLUTION TO PROBLEM 34

Question 1:
With ܸ௑ = 1 V, we have ���� = �� > ���� − ��� = ��� − ��� = 0.7 V − 0.6 V = 0.1 V, so
M1 is in the active region.

Thus, the bias current in M1 is given by

1
‫ܫ‬஽ଵ = ߤ௡ ‫ܥ‬௢௫ (ܹଵ /‫ܮ‬ଵ )(ܸீௌଵ െ ܸ௧௡ )ଶ (1 + ߣ௡ ܸ஽ௌଵ )
2
1
= ߤ௡ ‫ܥ‬௢௫ (ܹଵ /‫ܮ‬ଵ )(ܸூே െ ܸ௧௡ )ଶ (1 + ߣ௡ ܸ௑ )
2

From ��� = �� �� = 0.1 μm/V , we find �� = 0.1 μm/V/0.5 μm = 0.2 V �� and inserting in
the expression for ‫ܫ‬஽ଵ, we find
ͳ
‫ܫ‬஽ଵ ൌ ൈ ͵ͲͲɊȀ ଶ ൈ ሺͶɊȀͲǤͷɊሻ ൈ ሺͲǤ͹ െ ͲǤ͸ሻଶ ൈ ሺͳ ൅ ͲǤʹ ିଵ ൈ ͳǤͲሻ
ʹ
ൌ ͳͶǤͶɊ
Since the capacitor ‫ ܥ‬is an open circuit for dc voltages, Kirchhoff’s current law implies
‫ܫ‬஽ଶ = ��� = 14.4 μA .

Question 2:
With ܸ௑ = 1 V , we have |���� | = |�� − ��� | = |1.0 V − 2.0 V| = 1 V . Also, หܸீௌଶ െ ܸ௧௣ ห =
��� − ��� − ��� � = |1.1 V − 2.0 V − (−0.7 V)| = 0.2 V , so |ܸ஽ௌଶ | > หܸீௌଶ െ ܸ௧௣ ห , implying
that M2 is in the active region.

Thus, the bias current in M2 is given by

1 ଶ
‫ܫ‬஽ଶ = ߤ௣ ‫ܥ‬௢௫ (ܹଶ /‫ܮ‬ଶ )൫ܸீௌଶ െ ܸ௧௣ ൯ ൫1 + ߣ௣ |ܸ஽ௌଶ |൯
2
1 ଶ
= ߤ௣ ‫ܥ‬௢௫ (ܹଶ /‫ܮ‬ଶ )൫ܸ஻ െ ܸ஽஽ െ ܸ௧௣ ൯ ቀ1 + ߣ௣ (ܸ஽஽ െ ܸ௑ )ቁ
2
2Ԝ‫ܫ‬஽ଶ ‫ܮ‬ଶ
֜ ܹଶ = ଶ
ߤ௣ ‫ܥ‬௢௫ ൫ܸ஻ െ ܸ஽஽ െ ܸ௧௣ ൯ ቀ1 + ߣ௣ (ܸ஽஽ െ ܸ௑ )ቁ

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252
CMOS ANALOG IC DESIGN Solution to Problem 34

From ��� = �� �� = 0.2 μm/V,, we find �� = 0.2 μm/V/0.5 μm = 0.4 V �� and inserting in
the expression for ܹଶ, we find

2 × 14.4 μA × 0.5 μm
�� = � = 2.57 μm
100 μA/V � × �1.1 V − 2 V − (−0.7 V)� × �1 + 0.4 V �� × (2.0 V − 1.0 V)�

Question 3:
The transconductance ݃௠ଵ may be found as follows:

����
��� = � = �� ��� (�� /�� )(���� − ��� )(1 + �� ���� )
����� ���� �����

= �� ��� (�� /�� )(��� − ��� )(1 + �� �� )

= 300 μA/V � × (4 μm/0.5 μm) × (0.7 V − 0.6 V) × (1 + 0.2 V �� × 1.0 V)
= 288 μA/V

Question 4:
The small-signal output resistance ‫ݎ‬ௗ௦ଶ is the reciprocal of the small-signal output conductance
݃ௗ௦ଶ which may be found using Eq. (3.68) in ‘CMOS Analog IC Design: Fundamentals’:
‫ܫ‬஽ଶ ߣ௣
݃ௗ௦ଶ =
1 + ߣ௣ |ܸ஽ௌଶ |

From this expression, we find

1 + �� |���� | 1 + �� |�� − ��� |

���� = 1/���� = =
��� �� ��� ��
1 + 0.4 V �� × |1.0 V − 2.0 V|
= = 243 kΩ
14.4 μA × 0.4 V ��

Question 5:
For finding the small-signal gain, we derive the small-signal equivalent circuit shown below.
The gate-source voltage for M2 is a dc voltage, i.e., the small-signal voltage of ‫ீݒ‬ௌଶ is zero,
so the voltage-controlled current source ݃௠ଶ ܸ௚௦ଶ is omitted.

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253
CMOS ANALOG IC DESIGN Solution to Problem 34

With the capacitor ‫ ܥ‬being so large that it can be treated as a short circuit for signal
variations, we have ‫ݎ‬ௗ௦ଵ, ‫ݎ‬ௗ௦ଶ and ܴ௅ in parallel and a node equation at the output gives

݃௠ଵ ܸ௜௡ + ܸ௢ /(‫ݎ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଶ ‫ܴ צ‬௅ ) = 0 ֜ ‫ܣ‬௩ = ܸ௢ /ܸ௜௡ = െ݃௠ଵ (‫ݎ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଶ ‫ܴ צ‬௅ )

For finding the numerical value, we need the value of ‫ݎ‬ௗ௦ଵ. This is found using ‫ݎ‬ௗ௦ଵ =
(1 + ߣ௡ ܸ஽ௌଵ )/(‫ܫ‬஽ଵ ߣ௡ ), compare to Question 4. Inserting numerical values, we find

1 + �� �� 1 + 0.2 V �� × 1.0 V
���� = = = 416.7 kΩ
��� �� 14.4 μA × 0.2 V ��

We then find

�� = −��� (���� � ���� � �� ) = −��� (1/���� + 1/���� + 1/�� )��

= −288 μA /V × (1/243 kΩ + 1/416.7 kΩ + 1/200 kΩ)��
= −288 μA/V × 86.84 kΩ = −25.0 V/V

Question 6:
For a transistor to be in the active region, we require |��� | ≥ |��� | − |�� |. With a high
value of ‫ݒ‬௑, this condition is fulfilled for M1, but for M2, we must require

|���� | ≥ |���� | − ���� � � |�� − ��� | ≥ |�� − ��� | − ���� �

� ��� − �� ≥ ��� − �� + ��� � �� � �� − ���
� ��max = �� − ��� = 1.1 V − (−0.7 V) = 1.8 V

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254
CMOS ANALOG IC DESIGN Solution to Problem 34

Question 7:
For verifying the results for the previous questions, we may use the LTspice schematic shown
below. The coupling capacitor at the output has been specified to 1 F which is a very large
value ensuring that the capacitor appears as a short circuit for ac signals. The device values
have been specified as given in the problem and the value of ܹଶ has been specified to the
value found in Question 2.

By running a ‘.op’ simulation, the output file from the simulation shows the dc values ܸ௑ =
0.998771 V and ��� = ��� = 14.3971 μA , closely matching the value specified for ܸ௑ and
the value calculated for ‫ܫ‬஽ଵ and ‫ܫ‬஽ଶ, thus confirming the results of Questions 1 and 2.

From the error log file from the ‘.op’ simulation, we find ��� = 288 μA/V , confirming the
result from Question 3. We also find ���� = 4.11 μA/V , corresponding to ‫ݎ‬ௗ௦ଶ = 1/݃ௗ௦ଶ =
243.309 kΩ, confirming the result from Question 4.

For finding the small-signal gain ‫ܣ‬௩ = ܸ௢ /ܸ௜௡ at low frequencies, we run a ‘.ac’ simulation
with a frequency range from 1 kHz to 10 kHz. As shown in the output plot below, this gives a
gain of 27.963 dB ¾ 25.01 V/V, and the phase ܸ௢ of is −180°, so �� = �� /��� = −25.01 V/V ,
confirming the result from Question 5.

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255
CMOS ANALOG IC DESIGN Solution to Problem 34

Note that the low-frequency gain cannot be found by a simple ‘.tf ’ simulation because
of the coupling capacitor. A ‘.tf ’ simulation with ‘Vin’ as the source and ‘v(Vx)’ as the
output gives an output resistance of ���� = 153.563 kΩ and a gain of ��� = −44.217 V/V.
From these values, the gain ܸ௢ /ܸ௜௡ with a load resistor �� = 200 kΩ may be calculated as
‫ܣ‬௩ = ‫ܣ‬௩௫ Ԝܴ௅ /(ܴ௅ + ���� ) = −44.217 V/V × 200 kΩ/(200 kΩ + 153.563 kΩ) = −25.01 V/V
as also found from the ‘ac’ simulation.

For confirming the result from Question 6, we find from the error log file from the ‘.op’
simulation the saturation voltage for M2 to be ‘Vdsat: -2.00e-01’, implying that
��max = ��� − |����sat | = 2.0 V − 0.2 V = 1.8 V, confirming the result from Question 6.

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256
CMOS ANALOG IC DESIGN Solution to Problem 35

SOLUTION TO PROBLEM 35

Question 1:
The condition for a transistor to be in the active region is |��� | ≥ |��� � �� | = |����sat |. In
the error log file, we find both ܸ஽ௌԜsat and ܸ஽ௌ listed.

For M1, ܸ஽ௌ = 0.233 V and ܸ஽ௌԜsat = 0.100 V, i.e., ܸ஽ௌ > ܸ஽ௌԜsat , so M1 is in the active region.

For M2, ܸ஽ௌ = 1.27 V and ܸ஽ௌԜsat = 0.0674 V, i.e., ܸ஽ௌ > ܸ஽ௌԜsat , so M2 is in the active region.

For M3, ��� = −1.22 V and ����sat = −0.117 , i.e., |ܸ஽ௌ | > |ܸ஽ௌԜsat |, so M3 is in the active
region.

For M4, ��� = −0.283 V and ����sat = −0.200 V, i.e., |ܸ஽ௌ | > |ܸ஽ௌԜsat |, so M4 is in the
active region.

Question 2:
The small-signal output resistance is the parallel combination of the small-signal resistance
‫ݎ‬௨௣ଷ looking into the drain of M3 and the small-signal resistance ‫ݎ‬ௗ௢௪௡ଶ looking into the
drain of M2 as shown in the schematic below. Each of these resistances are found using
Eq. (4.23) from ‘CMOS Analog IC Design: Fundamentals’. In this equation, the bulk
transconductance is omitted since all transistors have their bulk and source terminal connected.

We find ���� � ��� ���� ���� = ��� /(���� ���� ) = 0.131 mA/V/(0.684 μA/V × 1.45 μA/V) =
132.08 MΩ and ������ � ��� ���� ���� = ��� /(���� ���� ) = 0.228 mA/V/(0.681 μA/V ×
0.750 μA/V) = 446.40 MΩ. From these values, we find ���� = ���� � ������ = 101.9 MΩ..

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257
CMOS ANALOG IC DESIGN Solution to Problem 35

Question 3:
The small-signal gain for the cascode stage is the transconductance of the common source
transistor M4 multiplied by the output resistance, and it is inverting, compare to Eq. (4.27)
in ‘CMOS Analog IC Design: Fundamentals’. Thus, �� = −��� ���� = −76.7 μA/V ×
101.9 MΩ = −7816 V/V ∼ 77.9 dB .

Question 4:
The small-signal gain of the common-source stage M4 is ‫ܣ‬௩,௖௦ = െ݃௠ସ (‫ݎ‬ௗ௦ସ ‫ݎ צ‬ௗ௢௪௡ଷ ) where
‫ݎ‬ௗ௢௪௡ଷ is the small-signal resistance looking into the source of M , compare to Eq. (4.5) in
3
‘CMOS Analog IC Design: Fundamentals’.

The resistance ‫ݎ‬ௗ௦ସ is ���� = 1/���� = 1/1.45 μA/V = 0.690 MΩ.

The resistance ‫ݎ‬ௗ௢௪௡ଷ is the input resistance of the common-gate gain stage M3, see the
schematic below. This is found using Eq. (4.19) in ‘CMOS Analog IC Design: Fundamentals’.
The load resistor for the common-gate stage M3 is the resistance ‫ݎ‬ௗ௢௪௡ଶ found in Question
2 looking down into the drain of M2, so Eq. (4.19) results in

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258
CMOS ANALOG IC DESIGN Solution to Problem 35

1 ������ 1 ������ ����

������ ≃ + = +
��� ��� ���� ��� ���
1 + ������ ���� 1 + 446.40 MΩ × 0.684 μA/V
= = = 2.338 MΩ
��� 0.131 mA/V

Finally, we find ��,�� = −��� (���� ∥ ������ ) = −76.7 μA/V × (0.690 MΩ ∥ 2.338 MΩ) =
−40.9 V/V ∼ 32.2 dB .

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259
CMOS ANALOG IC DESIGN Solution to Problem 36

SOLUTION TO PROBLEM 36

Question 1:
Assuming that both transistors are in the active region in the bias point, we find that
‫ܫ‬஽ଵ = ‫ܫ‬஽ଶ leads to

1
� � (� /� )(� � ��� )� (1 + �� �� )
2 � �� � � ��
1 �
= �� ��� (�� /�� )���� � �� � ���� �� �1 + �� (��� � �� )�
2
�
1 + �� (��� � �� ) �� �� /�� ��� � ���
⇒ = � �� �� �
1 + �� �� �� �� /�� ��� � �� � ���� �

From ��� = �� �� = 0.1 μm/V, we find ߣ௡ = ߣᇱ௡ /‫ܮ‬ଵ = 0.1 V ିଵ. From ��� = �� �� = 0.2 μm/V ,
we find ߣ௣ = ߣᇱ௣ /‫ܮ‬ଶ = 0.1 V ିଵ. Inserting numerical values in the equation above, we find

�
300 μA/V � 6 μm/1 μm 0.8 V − 0.6 V
� � × � � × � � =1
100 μA/V � 36 μm/2 μm 2.0 V − 1.1 V − 0.7 V

⇒ 1 + 0.1 V �� × (2.0 V − �� ) = 1 + 0.1 V �� × �� ⇒ �� = 1.0 V

Note that both M1 and M2 have |ܸ஽ௌ | > |ܸீௌ െ ܸ௧ | so they are in the active region.

The bias current in M1 and M2 is

1
��� = ��� = �� ��� (�� /�� )(��� − ��� )� (1 + �� �� )
2
= 0.5 × 300 μA/V � × (6 μm/1 μm) × (0.8 V − 0.6 V)� × (1 + 0.1 V �� × 1 V) = 39.6 μA

Question 2:
The small-signal diagram is shown below. Notice that both ܸ஽஽ and ܸ஻ are reset, implying
that in the small-signal diagram, M2 is reduced to the small-signal drain-source resistance
‫ݎ‬ௗ௦ଶ . For details on how to create the small-signal diagram from the schematic, you may
turn to Appendix A in this book.

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260
CMOS ANALOG IC DESIGN Solution to Problem 36

The small-signal parameters are:

��� = 2���� /(���� − ��� ) = 2 × 39.6 μA/(0.8 V − 0.6 V) = 396 μA/V

���� = (1 + �� ���� )/(�� ��� ) = (1 + �� �� )/(�� ��� )

= (1 + 0.1 V �� × 1 V)/(0.1 V �� × 39.6 μA) = 278 kΩ
���� = �1 + �� |���� |�/��� ��� � = �1 + �� (��� − �� )� /��� ��� �
= �1 + 0.1 V �� × (2 V − 1 V)�/(0.1 V �� × 39.6 μA) = 278 kΩ

Question 3:
From the small-signal diagram with ‫ݒ‬௜௡ = 0, we see that the small-signal output resistance at
low frequencies is the parallel combination of ‫ݎ‬ௗ௦ଵ and ‫ݎ‬ௗ௦ଶ , i.e., ���� = ���� ∥ ���� = 278 kΩ ∥
278 kΩ = 139 kΩ .

From a node equation at the output node, we find at low frequencies where all capacitors are
open circuits: ‫ݒ‬௢ /‫ݎ‬ௗ௦ଵ + ‫ݒ‬௢ /‫ݎ‬ௗ௦ଶ + ݃௠ଵ ‫ݒ‬௜௡ = 0 from which ‫ܣ‬௩ = ‫ݒ‬௢ /‫ݒ‬௜௡ = െ݃௠ଵ (‫ݎ‬ௗ௦ଵ ‫ݎ צ‬ௗ௦ଶ ) =
−396 μA/V × 139 kΩ = −55.0 V/V.

Question 4:
With ܴௌ > ‫ݎ‬௢௨௧ and a fairly large input capacitance due to the Miller effect on ‫ܥ‬ଵ, the dominant
pole is found from the input side. Using the Miller transformation, the time constant from
the input side is ��� � �� ��� = �� ��� + �� (1 � �� )� = 250 kΩ × �2 pF + 0.5 pF × (1 + 55)� =
�
ିଵ
7.50 μs. This corresponds to ݂௣ଵ ؄ ൫2Ԝߨ߬௣ଵ ൯ = 21.2 kHz.

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261
CMOS ANALOG IC DESIGN Solution to Problem 36

Question 5:
The amplifier may be recognized as the Miller-compensated gain stage in a two-stage opamp
which is analyzed in Chapter 6.6 in ‘CMOS Analog IC Design: Fundamentals’. Using Eq.
(6.59) from this chapter, we find ��� � ��� /�2���(�� + �� + �� �� /�� )� = 396 μA/V/�2 × � ×
(2.0 pF + 1.0 pF + 2.0 pF × 1.0 pF/0.5 pF)൯ = 9.0 MHz..

Question 6:
Shown below is an LTspice schematic for the amplifier.

From the output file from the ‘.op’ simulation, we find ܸை = 1.0 V and ��� = ��� = 39.6 μA
as calculated in Question 1. From the error log file from the ‘.op’ simulation, we find ݃௠ଵ =
396 μA/V as calculated in Question 2, and we find ���� = ���� = 3.60 μA/V, corresponding
to ���� = ���� = 1/���� = 1/3.60 μA/V = 278 kΩ as calculated in Question 2.

From the output file from the ‘.tf ’ simulation shown in the schematic, we find the low-
frequency gain to be �� = �� /��� = −55 V/V and we find the output resistance to be
���� = 138889 Ω ≃ 139 kΩ as calculated in Question 3.

For finding the pole frequencies of the amplifier, we run the ‘.ac’ simulation shown in the
schematic. Shown below is a plot of the output voltage. We notice that the low-frequency gain
is about 34.8 dB, corresponding to |‫ܣ‬௩ | = 55 V/V as also found from the ‘.tf ’ simulation.
We also find that there is a pole at a frequency about 20 kHz, another pole at a frequency
about 10 MHz and a zero at about 100 MHz.
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 CMOS ANALOG IC DESIGN Solution to Problem 36

The exact location is not easy to find from the plot but by plotting ‘V(vo)*frequency’, we
obtain a plot where the slopes of the line segments in the Bode plot are changed by 20 dB/
dec., compare to Fig. 6.54 in ‘CMOS Analog IC Design: Fundamentals’. This plot is shown
below. In the plot, a piecewise-linear approximation with line segments with slopes of 0 dB/
dec. and ±20 dB/dec. is also shown (in red), and from this, we may estimate ��� ≃ 21.3 kHz
and ��� ≃ 9.3 MHz , values which are close to the values calculated in Questions 4 and 5.
We may also estimate a zero frequency �� ≃ 126 MHz . From Eq. (6.54) in ‘CMOS Analog
IC Design: Fundamentals’, the zero frequency may be calculated as �� = ��� /(2���� ) = 396 μA/V/(
= ��� /(2���� ) = 396 μA/V/(2 × � × 0.5 pF) = 126 MHz,, exactly matching the simulated value.

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CMOS ANALOG IC DESIGN Solution to Problem 37

SOLUTION TO PROBLEM 37

Question 1:
The closed-loop gain is given by ‫ܣ‬஼௅ (‫)ݏ(ܣ = )ݏ‬/൫1 + ߚ(‫)ݏ(ܣ)ݏ‬൯. At very low frequencies,
we have ‫(ܣ‬0) = 1000 V/V and ߚ = 0.06 V/V , so we find the low-frequency closed-loop
gain to be ‫ܣ‬஼௅ (0) = 1000 V/V/(1 + 0.06 V/V × 1000 V/V) = 16.4 V/V .

Question 2:
Shown below is an LTspice schematic of the feedback amplifier. The two RC networks provide
�� ିଵ
a time constant �� = �2���� � = �� �� = 132.6 μs and a time constant ߬ଶ = ൫2ߨ݂௣ଶ ൯ =
�� �� = 0.5305 μs . The low-frequency open-loop gain is modeled by the voltage-controlled
voltage source ‘E1’ and the feedback factor ߚ is modeled by the voltage-controlled voltage
source ‘E4’.

From a ‘.ac’ simulation, we obtain the following plot of the output voltage from which
we find a low-frequency gain of 24.3 dB ¾ 16.4 V/V and a −3 dB frequency of 93.3 kHz,
resulting in a gain-bandwidth product of GBW = 1.53 MHz.

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CMOS ANALOG IC DESIGN Solution to Problem 37

Alternatively, the low-frequency gain and the bandwidth may be found using the ‘.meas’
directives shown in the schematic. From the error log file, we find the low-frequency gain
to be 24.293 dB ¾ 16.4 V/V and the bandwidth to be 93.2467 kHz, confirming GBW =
1.53 MHz.

Question 3:
The phase margin is determined by the loop gain

1000 V/V 60 V/V

‫ = )ݏ(ܣ)ݏ(ߚ = )ݏ(ܮ‬0.06 V/V × ቆ ቇ=
൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯ ൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯

It is found as PM = 180°ԛ െ ‫ס‬൫െ‫݂݆(ܮ‬௧ )൯ where ݂௧ is the unity-gain frequency of the loop

gain, i.e., the frequency where |‫ = |)݂݆(ܮ‬1.

The frequency ݂௧ is found from

60 V/V
= 1 ֜ ݂௧ = 70.2 kHz
ଶ ଶ
ቆට1 + ൫݂௧ /݂௣ଵ ൯ ቇ ቆට1 + ൫݂௧ /݂௣ଶ ൯ ቇ

With ݂ = ݂௧ , we find

��(��� ) = − arctan��� /��� � − arctan��� /��� �

= − arctan(70.2 kHz/1.2 kHz) − arctan(70.2 kHz/300 kHz) = −89.0° − 13.2° = −102.2°

From this, we find the phase margin PM = 180° + ‫݂݆(ܮס‬௧ ) = 77.8°.

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CMOS ANALOG IC DESIGN Solution to Problem 37

We may also estimate the phase margin by recognizing that the amplifier is a second-order system
with a gain-bandwidth product of the loop gain ݂௧௟ = ݂௣ଵ ߚ‫(ܣ‬0) = 1.2 kHz × 0.06 V/V ×
1000 V/V = 72 kHz and a second pole at ݂௣ଶ = 300 kHz. This gives the ratio ݂௣ଶ /݂௧௟ = 4.17
and from Fig. 6.35 in ‘CMOS Analog IC Design: Fundamentals’, we may estimate the
phase margin to be PM ≃ 77°.

The phase margin may also be found using LTspice. The loop gain can be plotted from a
‘.ac’ simulation using the schematic below where the feedback loop has been opened. Also
a plot of the loop gain is shown.

From the plot of the feedback voltage ܸ௙, we find a phase margin of 77.7° as shown above.

The phase margin may also be found using the ‘.meas’ directive shown in the LTspice
schematic.

The phase margin is PM = 180°ԛ െ ‫ס‬൫െ‫݂݆(ܮ‬௧ )൯ = 180° + ‫ס‬൫‫݂݆(ܮ‬௧ )൯ = ‫ס‬൫െ‫݂݆(ܮ‬௧ )൯ where

‫ )݂݆(ܮ‬is the loop gain and ݂௧ is the frequency where |‫ |)݂݆(ܮ‬has dropped to a value of 1.

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266
CMOS ANALOG IC DESIGN Solution to Problem 37

Thus, the phase of ‘-v(Vf )’ is equal to the phase margin when the magnitude of ‘v(Vf )’ is
equal to 1.

The result of the ‘.meas’ directive is found in the error log file which shows a phase margin
of 77.8289°. We notice that there is a good match between the analytically calculated phase
margin and the simulated phase margin.

Question 4:
The closed-loop gain is given by ‫ܣ‬஼௅ (‫)ݏ(ܣ = )ݏ‬/൫1 + ߚ(‫)ݏ(ܣ)ݏ‬൯. For the modified amplifier,
we have at very low frequencies ‫(ܣ‬0) = 100 V/V and ߚ(0) = 0.6 V/V , so we find the low-
frequency closed-loop gain to be ‫ܣ‬஼௅ (0) = 100 V/V/(1 + 0.6 V/V × 100 V/V) = 1.64 V/V..

Question 5:
Shown below is an LTspice schematic of the modified feedback amplifier.

From a ‘.ac’ simulation, we obtain the following plot of the output voltage from which
we find a low-frequency gain of 4.29 dB ¾ 1.64 V/V and a −3 dB frequency of 102 kHz,
resulting in a gain-bandwidth product of GBW = 167 kHz.

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267
CMOS ANALOG IC DESIGN Solution to Problem 37

Alternatively, the low-frequency gain and the bandwidth may be found using the ‘.meas’
directives shown in the schematic. From the error log file, we find the low-frequency gain
to be 4.29303 dB ¾ 1.64 V/V and the bandwidth to be 101.930 kHz, confirming GBW
= 167 kHz.

Question 6:
The phase margin is determined by the loop gain

0.6 V/V 100 V/V 60 V/V

‫ = )ݏ(ܣ)ݏ(ߚ = )ݏ(ܮ‬ቆ ቇቆ ቇ=
1 + ‫ݏ‬/߱௣ଵ 1 + ‫ݏ‬/߱௣ଶ ൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯

We notice that the expression for the loop gain of the modified amplifier is identical to the
expression for the loop gain of the original amplifier. Hence, the phase margin is the same
for the modified amplifier as for the original amplifier, i.e., PM ≃ 77.8° .

However, notice that the closed-loop gain given by ��� (�) = �(�)/�1 + β(�)�(�)� is
different for the two configurations. Even though the denominator ൫1 + ߚ(‫)ݏ(ܣ)ݏ‬൯ is the
same for the two configurations, the numerator ‫ )ݏ(ܣ‬is different.

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268
CMOS ANALOG IC DESIGN Solution to Problem 38

SOLUTION TO PROBLEM 38

Question 1:
For finding the loop gain, we open the feedback loop at the noninverting input to the
amplifier ‫ܣ‬ଵ and apply a test signal ܸ௧ to the noninverting input of ‫ܣ‬ଵ. The input voltage
ܸref to the inverting input of ‫ܣ‬ଵ is reset, i.e., ܸref = 0 and the returned voltage ܸ௥ is the
voltage at the node between the two resistors. The loop gain is found as

‫ = )ݏ(ܮ‬െܸ௥ (‫)ݏ‬/ܸ௧ (‫ = )ݏ‬െ‫ܣ‬ଵ (‫ܣ)ݏ‬௖௦ଵ ൫ܴଵ /(ܴଵ + ܴଶ )൯

where ‫ܣ‬௖௦ଵ is the small-signal gain of the common-source gain stage formed by transistor
M1 and the two resistors ܴଵ and ܴଶ. This gain is

���� ���� (�� + �� )

���� = ���� ����� ∥ (�� + �� )� =
���� + �� + ��

Inserting in the expression for ‫)ݏ(ܮ‬, we obtain

‫ܣ‬଴ ݃௠ଵ ‫ݎ‬ௗ௦ଵ (ܴଵ + ܴଶ ) ܴଵ

‫ = )ݏ(ܮ‬ቆ ቇቆ ቇ൬ ൰
1 + ‫ݏ‬/߱௣ ‫ݎ‬ௗ௦ଵ + ܴଵ + ܴଶ ܴଵ + ܴଶ
‫ܣ‬଴ ݃௠ଵ ‫ݎ‬ௗ௦ଵ ܴଵ
=ቆ ቇ൬ ൰
1 + ‫ݏ‬/߱௣ ‫ݎ‬ௗ௦ଵ + ܴଵ + ܴଶ

At very low frequencies, we find

�� ��� ���� �� 500 V/V × 10.0 mA/V × 5 kΩ × 20 kΩ

�� = = = 11111 V/V
���� + �� + �� 5 kΩ + 20 kΩ + 20 kΩ

The feedback factor is ߚ = ܴଵ /(ܴଵ + ܴଶ ) = 0.5 and with a loop gain which is much larger
than 1, we find an output voltage ܸை ؄ ܸref /ߚ = 2.50 V.

Question 2:
The line regulation ߲ܸை /߲ܸூே is the closed-loop gain ‫ܣ‬஼௅ from the input voltage ܸூே to the
output voltage ܸை, so it can be found as ‫ܣ‬஼௅ = ‫ܣ‬/(1 + ߚ‫ )ܣ‬؄ ‫ܣ‬/‫ ܮ‬where ‫ ܮ‬is the loop
gain found in Question 1 and ‫ ܣ‬is the open-loop gain from ܸூே to ܸை. When the feedback
loop is open, the gate voltage for M1 is a dc voltage and M1 is a common-gate stage so
the open-loop gain from ܸூே to ܸை is found as � � ��� ����� ∥ (�� + �� )�, compare to Eq.
(4.18) in ‘CMOS Analog IC Design: Fundamentals’.
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269
CMOS ANALOG IC DESIGN Solution to Problem 38

Using the expression for the low-frequency loop gain found for Question 1, we obtain

��� ��� ���� (�� + �� ) ���� + �� + ��

�� �� �
���� ���� + �� + �� �� ��� ���� ��
1 �� 1 20 kΩ
=� � �1 + � = � � �1 + � = 4 mV/V
�� �� 500 V/V 20 kΩ

Question 3:
The low-frequency open-loop output resistance may be found as the small-signal output
resistance ‫ݎ‬ௗ௦ଵ of transistor M1 in parallel with the resistor ܴଵ + ܴଶ . Thus, we find
���� = ���� ∥ (�� + �� ). The closed-loop output resistance at low frequencies is found using
Eq. (6.13) in ‘CMOS Analog IC Design: Fundamentals’, i.e.,

���� ���� ���� (�� + �� ) ���� + �� + ��

������� = ≃ =� �� �
1 + �� �� ���� + �� + �� �� ��� ���� ��
1 �� 1 20 kΩ
=� � �1 + � = � � �1 + � = 0.4 Ω
�� ���� �� 500 V/V × 10.0 mA/V 20 kΩ

Question 4:
For transistor M1, we have ‫ܫ‬஽ = ‫ܫ‬௅ + ܸை /(ܴଵ + ܴଶ ) = 2.0 mA + 2.5 V/(20 kΩ + 20 kΩ) =
2.0625 mA and |��� | = ��� − �� = 3.0 V − 2.5 V = 0.5 V..

Using Eq. (3.68) in ‘CMOS Analog IC Design: Fundamentals’, we find

1 + �|��� | 1 1
���� = ��= = = 0.102 V ��
��� ���� �� − |��� | 5.0 kΩ × 2.0625 mA − 0.5 V

Using Eq. (3.65) in ‘CMOS Analog IC Design: Fundamentals’, we find

2Ԝ‫ܫ‬஽ 2Ԝ‫ܫ‬஽ 2 × 2.0625 mA

݃௠ଵ = ֜ หܸீௌ െ ܸ௧௣ ห = = = 0.4125 V
หܸீௌ െ ܸ௧௣ ห ݃௠ଵ 10 mA/V

We notice that |ܸ஽ௌ | > หܸீௌ െ ܸ௧௣ ห , so M1 is in the active region.

Using Eq. (3.64) in ‘CMOS Analog IC Design: Fundamentals’, we then find

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270
CMOS ANALOG IC DESIGN Solution to Problem 38

��
��� = �� ��� � � ����� � ��� ��(1 + �|��� |)
��
���
� �� = �� � �
�� ��� ����� � ��� ��(1 + �|��� |)
10 mA/V
= 1 μm × � � = 230.66 μm
100 μA/V � × 0.4125 V × (1 + 0.102 V �� × 0.5 V)

Question 5:
The following figure shows an LTspice schematic of the voltage regulator. Transistor M1 is
modeled by the Shichman-Hodges transistor model with the model parameters and channel
dimensions found in Question 4. The opamp ‫ܣ‬ଵ is modeled by the voltage-controlled voltage
sources ‘E1’ and ‘E2’ and the RC network ‘Ra1’ and ‘Ca1’, providing a time constant
corresponding to the pole frequency ݂௣ = 100 kHz.

From the ‘.op’ simulation, we find the following results from the output file and the error
log file.

Output file Error log file

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271
CMOS ANALOG IC DESIGN Solution to Problem 38

We notice that the values of ݃௠ଵ and ݃ௗ௦ଵ are exactly matching the specifications given
in the problem. However, the value of ܸை is almost 9 mV larger than ܸref /ߚ even though
the loop gain is very high, on the order of 80 dB. The reason for this is that in the
feedback circuit consisting of the opamp ‫ܣ‬ଵ and the transistor M1, a dc bias voltage
ܸீଵ = 2.1873 V is needed for the gate of M1. This requires a dc input voltage to ‫ܣ‬ଵ of
ܸoff = 2.1873 V/‫ܣ‬଴ = 2.1873 V/500 = 4.3746 mV. Inserting this offset voltage in the
LTspice schematic as shown below and running a new ‘.op’ simulation, we find the following
results from the output file and the error log file.

Output file Error log file

From the ‘.tf ’ simulation shown (as a comment) in the schematic, we find the low-frequency
line regulation as the transfer function from ܸூே to ܸை to be 4.0797 mV/V and the output
resistance to be 0.399964 Ω, both results matching the calculated result from Questions
2 and 3 very well.

For finding the line regulation versus frequency, we run the ‘.ac’ simulation shown in the
schematic with the ac amplitude of ‘Vin’ specified to 1 and the ac amplitude of ‘IL’ specified
to 0. The resulting plot is shown below. A linear y-axis has been selected. At 2 MHz, we
find a line regulation of 81.3 mV/V.

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272
CMOS ANALOG IC DESIGN Solution to Problem 38

For finding the output impedance versus frequency, we run the ‘.ac’ simulation shown in
the schematic with the ac amplitude of ‘Vin’ specified to 0 and the ac amplitude of ‘IL’
specified to 1. The resulting plot is shown below. At 2 MHz, we find an output impedance
of 7.98 Ω.

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273
CMOS ANALOG IC DESIGN Solution to Problem 39

SOLUTION TO PROBLEM 39

Question 1:
The low-frequency closed-loop gain is calculated from
‫ܣ‬଴
‫ܣ‬஼௅଴ =
1 + ߚ‫ܣ‬଴

where the feedback factor at low frequencies is � = �� /(�� + �� ) = 200 kΩ/(200 kΩ +

200 kΩ) = 0.5. Inserting in the equation above, we find

�� 1000 V/V
���� = = = 1.996 V/V ∼ 6 dB
1 + ��� 1 + 0.5 × 1000 V/V

Question 2:
With ݂ ՜ λ, the parasitic capacitor from the inverting opamp input to ground creates a
short circuit for ܴଵ, so the closed-loop gain for ݂ ՜ λ is given by ‫ )ݏ(ܣ‬with ‫ ݏ‬՜ λ, i.e.

�� 20 kHz
���� = −�� � � = −1000 V/V × = −0.667 V/V ∼ −3.52 dB
�� 30 MHz

Question 3:
At high frequencies, the feedback factor is
ܴଵ ‫ צ‬൫1/‫ܥݏ‬௣ ൯ ܴଵ ܴଵ 1
ߚ= = =൬ ൰ቆ ቇ
ܴଵ ‫ צ‬൫1/‫ܥݏ‬௣ ൯ + ܴଶ ܴଵ + ܴଶ + ‫ܴݏ‬ଵ ܴଶ ‫ܥ‬௣ ܴଵ + ܴଶ 1 + ‫ܴ(ݏ‬ଵ ‫ܴ צ‬ଶ )‫ܥ‬௣

where ‫ܥ‬௉ is the parasitic capacitance from the inverting opamp input to ground. Thus, the
loop gain is

ܴଵ 1 1 െ ‫ݏ‬/߱௭
‫ = )ݏ(ܮ‬൬ ൰ቆ ቇ ‫ܣ‬଴ ቆ ቇ
ܴଵ + ܴଶ 1 + ‫ܴ(ݏ‬ଵ ‫ܴ צ‬ଶ )‫ܥ‬௣ 1 + ‫ݏ‬/߱௣

The loop gain has a low-frequency value of �� = �� ��� /(�� + �� ) = 500 V/V ∼ 54 dB, a
dominant pole at ݂௣ = 20 kHz , a right half-plane zero at ݂௭ = 30 MHz and a non-dominant
pole at ��� = 1/�2���(�� � �� )�� � = 1/(2 × � × 100 kΩ × 200 fF) = 7.96 MHz.

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274
CMOS ANALOG IC DESIGN Solution to Problem 39

The following figure shows the Bode plot. The amplitude plot starts at 54 dB corresponding
to a gain of 500 V/V at very low frequencies. The first breakpoint appears at ݂௣ = 20 kHz
where the slope of the amplitude plot changes to −20 dB/dec. The second breakpoint
appears at ݂௣ଶ = 7.96 MHz where the slope of the amplitude plot changes to −40 dB/dec,
and finally at ݂௭ = 30 MHz, the slope of the amplitude plot changes back to −20 dB/dec.

The phase plot (black plot) is the sum of the red, green and blue plots corresponding to
the phase shifts from ݂௣, ݂௣ଶ and ݂௭, respectively.

From the Bode plot, we estimate the phase margin to be PM ≃ 23°. However, with the
breakpoints in the piecewise linear approximations to the Bode plot close to the unity gain
frequency for the loop gain, this estimation is not very precise.

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CMOS ANALOG IC DESIGN Solution to Problem 39

Question 4:
For finding a more precise value for the phase margin, we may use LTspice to simulate
the loop gain. The following schematic models the loop gain ‫ )݂݆(ܮ‬. The gain function
is implemented using filter blocks similar to those described in Example 5.3 in ‘CMOS
Integrated Circuit Simulation with LTspice’. The zero is defined by the parameter ‘fz’ and
since it is a right-half-plane zero, it is defined with a negative value, i.e., ‘.param fz=−30Meg’.
The pole in the transfer function ‫ )ݏ(ܣ‬is defined by the parameter ‘fp’ and the pole caused
by the parasitic capacitance ‫ܥ‬௉ and the feedback resistors is modeled by ‘R1’, ‘R2’ and ‘Cp’.

From a ‘.ac’ simulation, we plot the loop gain as ‘v(Vf )’. From the plot, we find that when
the loop gain is 0 dB, the phase of the loop gain is −148°, corresponding to a phase margin
of 32°.

The phase margin may also be found using the ‘.meas’ directive shown in the LTspice
schematic. The phase margin PM = 180° � ����(��� )� = 180° + ���(��� )� = ����(��� )�
is where ݂௧ is the frequency |‫ |)݂݆(ܮ‬where has dropped to a value of 1. Thus, the phase of
‘-v(Vf )}’ is equal to the phase margin when the magnitude of ‘v(Vf )’ is equal to 1. From
the error log file, we find PM = 32.8°.

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CMOS ANALOG IC DESIGN Solution to Problem 40

SOLUTION TO PROBLEM 40

Question 1:
With ܸை = 0 V, the current in ܴ௅ is 0 and ‫ܫ‬஽ଵ = ‫ܫ‬஻ . Assuming that M1 is in the active
region, the current in M1 is found from the Shichman-Hodges model

1 ܹଵ
‫ܫ‬஽ଵ = ߤ௡ ‫ܥ‬௢௫ ൬ ൰ (ܸீௌଵ െ ܸ௧௡ )ଶ (1 + ߣ௡ ܸ஽ௌଵ )
2 ‫ܮ‬ଵ

where ܸீௌଵ = ܸூே െ ܸை = ܸூே , ܸ஽ௌଵ = ܸ஽஽ െ ܸை = ܸ஽஽ , and ߣ௡ = ߣᇱ௡ /‫ܮ‬ଵ = 0.16 V ିଵ .

From the equation above, we find

1 ��
�� = �� ��� � � (��� � ��� )� (1 + �� ��� )
2 ��

2���
� ��� = ��� + �
�� ��� (�� /�� )(1 + �� ��� )

2 × 100 μA
= 0.5 V + � = 558 mV
240 μA/V � × (100 μm/0.5 μm) × (1 + 0.16 V �� × 1.5 V)

We note that ܸ஽ௌଵ > ܸீௌଵ െ ܸ௧௡ so the assumption that M1 is in the active region is correct.

Question 2:
The transconductance is

��� = 2��� /(���� − ��� ) = 2�� /(��� − ��� ) = 2 × 100 μA/(0.558 V − 0.5 V) = 3.45 mA/V..

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CMOS ANALOG IC DESIGN Solution to Problem 40

Question 3:

The figure above shows a low-frequency small-signal diagram of the source follower. The
capacitor ‫ܥ‬௅ is omitted since it is an open circuit at low frequencies and also the current
source ‫ܫ‬஻ is omitted since it is an ideal dc current source, i.e., an open circuit in the small-
signal diagram.

A node equation at the output node gives

݃௠ଵ ‫ݒ‬௚௦ଵ = ݃௠ଵ (‫ݒ‬௜௡ െ ‫ݒ‬௢ ) = ‫ݒ‬௢ /‫ݎ‬ௗ௦ଵ + ‫ݒ‬௢ /ܴ௅

֜ ‫ݒ‬௢ (݃௠ଵ + 1/‫ݎ‬ௗ௦ଵ + 1/ܴ௅ ) = ݃௠ଵ ‫ݒ‬௜௡

‫ݒ‬௢ ݃௠ଵ
֜ ‫ܣ‬௩ = =
‫ݒ‬௜௡ ݃௠ଵ + 1/‫ݎ‬ௗ௦ଵ + 1/ܴ௅

The small-signal resistance ‫ݎ‬ௗ௦ଵ is found from

���� = (1 + �� ��� )/(�� �� ) = (1 + 0.16 V �� × 1.5 V)/(0.16 V �� × 100 μA) = 77.5 kΩ

Inserting in the expression for ‫ܣ‬௩, we find

��� 3.45 mA/V
�� = = = 0.773 V/V
��� + 1/���� + 1/�� 3.45 mA/V + 1/77.5 kΩ + 1/1 kΩ

Question 4:
We find the minimum output voltage for ��� = −��� = −1.5 V where ‫ீݒ‬ௌଵ is negative.
Hence, transistor M1 is in the off-region and ݅஽ଵ = 0 so the bias current ‫ܫ‬஻ flows in ܴ௅.

This results in ��,min = −�� ��� = −100 μA × 1 kΩ = −0.1 V .

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CMOS ANALOG IC DESIGN Solution to Problem 40

Question 5:
We find the maximum output voltage for ‫ݒ‬ூே = ܸ஽஽ = 1.5 V . Using a node equation at the
output, we find ‫ܫ‬஽ଵ = ‫ܫ‬஻ + ܸை,max /ܴ௅ . With ܸீௌଵ = ܸ஽ௌଵ = ܸ஽஽ െ ܸை,max , we find
1 ܹଵ ଶ ܸை,max
ߤ௡ ‫ܥ‬௢௫ ൬ ൰ ൫ܸ஽஽ െ ܸை,max െ ܸ௧௡ ൯ ቀ1 + ߣ௡ ൫ܸ஽஽ െ ܸை,max ൯ቁ = ‫ܫ‬஻ +
2 ‫ܮ‬ଵ ܴ௅

This is a cubic equation from which ܸை,max can be found. However, closed-form solutions
to a cubic equation are quite complicated and not suited for hand calculations, so assuming
that ߣ௡ ൫ܸ஽஽ െ ܸை,max ൯ ‫ ا‬1 , we can simplify the equation above as follows.
1 ܹଵ ଶ ܸை,max
ߤ௡ ‫ܥ‬௢௫ ൬ ൰ ൫ܸ஽஽ െ ܸை,max െ ܸ௧௡ ൯ = ‫ܫ‬஻ +
2 ‫ܮ‬ଵ ܴ௅

Inserting numerical values and solving for ܸை,max , we find ܸை,max = 1.24 V or ܸை,max = 0.806 V.
The solution ܸை,max = 1.24 V results in ܸூே െ ܸை,max < ܸ௧௡, so this solution is rejected and we find
ܸை,max = 0.806 V. With this value of ܸை,max , we find ߣ௡ ൫ܸ஽஽ െ ܸை,max ൯ = 0.111. We may find a
more exact solution to the cubic equation above by inserting ቀ1 + ߣ௡ ൫ܸ஽஽ െ ܸை,max ൯ቁ = 1.111,
resulting in

1 �� � ��,max
�� ��� � � 1.111 ���� � ��,max � ��� � = �� +
2 �� ��

Inserting numerical values and solving for ܸை,max , we find ܸை,max = 0.815 V.

Question 6:
The dominant pole can come either from the gate of M1 or from the output node.

At the gate of M1, both ‫ܥ‬௚ௗଵ and ‫ܥ‬௚௦ଵ contribute to the input capacitance. As the gate-
source capacitance is subject to the Miller effect, it appears smaller at the input by a factor
(1 െ ‫ܣ‬௩ ) and using Eq. (4.85) in ‘CMOS Analog IC Design: Fundamentals’, we find the
equivalent capacitance to ground

��,�� = ���� + ���� (1 − �� ) = 10 fF + 200 fF × (1 − 0.773 V/V) = 55.4 fF

With a signal source resistance �� = 20 kΩ, this results in a time constant of ߬௣,௜௡ = ܴௌ ‫ܥ‬௣,௜௡ =
20 kΩ × 55.4 fF = 1.11 ns , corresponding to a pole frequency of ݂௣,௜௡ = 1/൫2Ԝߨ߬௣,௜௡ ൯ =
144 MHz.

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CMOS ANALOG IC DESIGN Solution to Problem 40

At the output node, we note that ‫ܥ‬௅ is orders of magnitude larger than the other capacitors
in the circuit so the time constant at the output is approximately ߬௣,௢ = ‫ܥ‬௅ (ܴ௅ ‫ݎ צ‬௢௨௧ ) where
‫ݎ‬௢௨௧ is the output resistance of the source follower. From Eq. (4.12) in ‘CMOS Analog IC
Design: Fundamentals’, we find ���� = (1/��� ) ∥ ���� = (1/3.45 mA/V) ∥ 77.5 kΩ = 289 Ω,
giving an output time constant of ��,� = 1 nF × (1 kΩ ∥ 289 Ω) = 224 ns. This is much
larger than the time constant from the input side, so it corresponds to a dominant pole
frequency of ݂௣,௢ = 1/൫2Ԝߨ߬௣,௢ ൯ = 711 kHz.

Question 7:

The figure above shows an LTspice diagram including the capacitors ‫ܥ‬௅, ‫ܥ‬௚௦ଵ and ‫ܥ‬௚ௗଵ. For
verifying the bias point, we run a ‘.op’ simulation. From this, we find an output voltage
ܸை = 25.2319 μV ≃ 0 V as expected, and from the error log file, we find ݃௠ଵ = 3.45 mA/V
and ���� = 12.9 μA/V , corresponding to ���� = 77.5 kΩ as found in Questions 2 and 3.

By running a ‘.tf ’ simulation, we find the low-frequency small-signal gain to be 0.773072

V/V, closely matching the value found in Question 3.

By running a ‘.dc’ simulation, we find the following plot of the output voltage versus the
input voltage.

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CMOS ANALOG IC DESIGN Solution to Problem 40

From the plot, we verify both the bias value of ܸை and the values of ܸை,min and ܸை,max found
in Questions 4 and 5. We also note that the source follower only works for input voltages
in the range from 405 mV to 1.5 V.

Finally we run a ‘.ac’ simulation in order to estimate the frequency of the dominant pole.
The plot of ܸ௢ versus frequency is shown below.

From the plot, we find the dominant pole frequency to be about 712 kHz as calculated
in Question 6. We also note that there is a non-dominant pole at a frequency somewhat
below 100 MHz. This is lower than the pole frequency estimated from the input side.
However, this estimate was based on the Miller effect with a gain of 0.773 V/V. At
frequencies much higher than the dominant pole frequency, the gain is smaller, causing a
larger contribution from ‫ܥ‬௚௦ଵ to the input capacitance, hence a smaller value of the non-
dominant pole. Assuming a gain close to zero, the input capacitance is approximately
��,�� = ���� + (1 � �� )���� ≃ ���� + ���� = 210 fF with �� ≃ 0, so the non-dominant pole
frequency may be estimated to ��� ≃ 1/�2���� ��,�� � = 1/(2 × � × 20 kΩ × 210 fF) ≃ 38 MHz,,
matching the result shown in the Bode plot.

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281
CMOS ANALOG IC DESIGN Solution to Problem 41

SOLUTION TO PROBLEM 41

Question 1:
The low-frequency closed-loop gain is given by

�� 1000 V/V
���� = = = 4.975 V/V ∼ 13.94 dB
1 + ��� 1 + 0.2 V/V × 1000 V/V

Question 2:
The unity-gain frequency ݂௧ for the loop gain is found as follows:

��� (1 − ��� /�� )

|�(��� )| = 1 ⇒ � �=1
�1 + ��� /��� ��1 + ��� /��� �
��� ��� ���
⇒ �� ��� �1 + � = �1 + � � �1 + ��
��� ��� ���
(��� )� �
1 1 �� ���
⇒ � � + �� � � + � − � + 1 − �� ��� = 0
��� ��� ��� ��� ���
� �
��� ���
⇒ (��� )� + ��� ����
� �
+ ��� − �� ��� � �
� + (1 − �� ��� )��� ��� = 0
���

Introducing

� �
� �
��� ���
� = ���� + ��� − �� ��� �
���

� �
(0.02 MHz)� × (50 MHz)�
�
= (0.02 MHz) + (50 MHz) − (0.2 × 1000) × � �
(10 MHz)�

= −2100.0004 MHz � ≃ −2100 MHz �

and

� �
� = (1 − �� ��� )��� ��� = (1 − 40000) × (0.02 MHz)� × (50 MHz)� = −39999 (MHz � )�

we may re-write the equation above to

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282
CMOS ANALOG IC DESIGN Solution to Problem 41

(݂௧ଶ )ଶ + ‫݂(ܤ‬௧ଶ ) + ‫ = ܥ‬0

This is a quadratic equation from which we can calculate ݂௧ଶ. Selecting the positive solution,
we find

−� + √�� − 4� −2100 MHz � + �(2100 MHz � )� + 4 × 39999 (MHz � )�

��� = =
2 2
= 18.877 MHz �

from which we find the unity gain frequency for the loop gain to be �� = √18.877 MHz � =
4.34 MHz.

Question 3:
The phase margin is PM = 180° + ‫݂݆(ܮס‬௧ ), see Eq. (6.23) in ‘CMOS Analog IC Design:
Fundamentals’. With ݂௧ = 4.34 MHz , we find

�� �� ��
PM = 180° − arctan � � − arctan � � − arctan � �
�� ��� ���
4.34 MHz 4.34 MHz 4.34 MHz
= 180° − arctan � � − arctan � � − arctan � �
10 MHz 0.02 MHz 50 MHz
= 180° − 23.46° − 89.74° − 4.96° = 61.84°

Question 4:
The following figure shows an LTspice schematic of the amplifier with feedback. The
amplifier has been implemented using filter blocks similar to those described in Example
5.3 in ‘CMOS Integrated Circuit Simulation with LTspice’. The low-frequency gain ‫ܣ‬଴ is
specified as the gain in the voltage-controlled voltage source ‘E1’. The zero is specified by
the parameter ‘fz’. Since it is a right-half-plane zero, it is specified by a negative value. The
poles are specified by the parameters ‘fp1’ and ‘fp2’. The feedback factor ߚ is specified as a
parameter ‘beta’ for the gain in the voltage-controlled voltage source ‘E3’.

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283
CMOS ANALOG IC DESIGN Solution to Problem 41

Running a ‘.tf ’ simulation, we find the low-frequency gain to be 4.97512 V/V, confirming
the result from Question 1.

For finding the phase margin and the unity-gain frequency ݂௧ of the loop gain, we use the
following LTspice schematic where the feedback loop is open and a plot of ‘v(Vf )’ shows
the loop gain.

From the following plot of ‘v(Vf )’, we find a unity-gain frequency ݂௧ = 4.34 MHz for
the loop gain, confirming the result from Question 2. We also find ��(��� ) = −118.2°,
corresponding to a phase margin of 61.8°, closely matching the result from Question 3.

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284
CMOS ANALOG IC DESIGN Solution to Problem 41

The phase margin may also be found from the ‘.meas PM’ directive shown in the schematic.
Since PM = 180° + ‫݂݆(ܮס‬௧ ) = െ‫݂݆(ܮס‬௧ ), the phase of ‘-v(Vf )’ is equal to the phase margin
when the magnitude of ‘v(Vf )’ is equal to 1. From the error log file, we find a phase margin
of 61.8133° and a unity-gain frequency of 4.34487 MHz, both values closely matching the
results from Questions 2 and 3.

Question 5:
For finding the −3 dB bandwidth and unity-gain bandwidth ݂௧஼௅ for the closed-loop gain,
we run a ‘.ac’ simulation using the LTspice schematic for the amplifier with feedback. The
plot of the output voltage ‘v(Vo)’ is shown below. From the plot, we find a −3 dB bandwidth
of 20.1 MHz and a unity-gain bandwidth of 98 MHz. Thus, the unity-gain bandwidth
is close to the gain-bandwidth product GBW = 4.975 V/V × 20.1 MHz = 100 MHz but
much higher than the gain-bandwidth product ‫ܣ‬଴ ݂௣ଵ = 20 MHz of the amplifier without
feedback. This increase in bandwidth of the amplifier with feedback is caused by the zero
in the amplifier transfer function.

The unity-gain bandwidth ݂௧஼௅ may also be found using the ‘.meas’ directive shown in the
schematic. From the error log file, we find ݂௧஼௅ = 98.0521 MHz.

Question 6:
By repeating the simulation of the loop gain and phase margin with different values of
the feedback factor ߚ, we note that the phase margin is reduced when ߚ is increased. The
stability limit is reached when the phase margin reaches a value of 0°. In order to find
this limit, we run the simulation of the loop gain with the value of ‘beta’ stepped through
the range from 0.2 to 0.7 using the directive ‘.step param beta 0.2 0.7 0.01’ shown as a
comment in the LTspice schematic for simulation of the loop gain.

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285
CMOS ANALOG IC DESIGN Solution to Problem 41

The error log file from this simulation shows the phase margin versus ߚ in tabular form.
When right-clicking in the error log file, a dialogue box opens and you can select ‘Plot
.step’ed .meas data’ which opens a window in the waveform viewer showing the phase
margin versus ߚ. By default, the plot uses a logarithmic horizontal axis and it shows both
amplitude and phase of ‘PM’. You may select not to show the amplitude and to use a linear
horizontal axis by right-clicking on the axes and edit how ‘PM’ is plotted. The resulting
plot is shown below and using the cursor, we find that ߚ = 0.50 results in a phase margin
of 0°, i.e., ߚmax = 0.50 is the maximum value of ߚ for which the amplifier is stable.

The stability limit may also be calculated analytically. From the closed-loop transfer function
‫ܣ‬஼௅ (݆݂) = ‫)݂݆(ܣ‬/൫1 + ߚ‫)݂݆(ܣ‬൯, we see that the stability limit where ߚ = ߚmax may be found
by considering the situation �max �(��) = −1, causing the denominator in the closed-loop
transfer function to be 0 or the phase margin to be zero. This condition implies

�max �� (1 − ��/�� )
�max �(��) = = −1
�1 + ��/��� ��1 + ��/��� �
� �max �� (1 − ��/�� ) = −�1 + ��/��� ��1 + ��/��� �
� �max �� − ���max �� �/�� = −1 + � � /���� ��� � − ���/��� + �/��� �

By equating the imaginary terms in the equation above, we find

ߚmax ‫ܣ‬଴ ݂/݂௭ = ݂/݂௣ଵ + ݂/݂௣ଶ

֜ ߚmax = ൫݂௭ /݂௣ଵ + ݂௭ /݂௣ଶ ൯/‫ܣ‬଴ = (10 MHz/0.02 MHz + 10 MHz/50 MHz)/1000 = 0.5002

We see that the value found for ߚmax matches the simulated value very well.

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CMOS ANALOG IC DESIGN Solution to Problem 42

SOLUTION TO PROBLEM 42

Question 1:
From the schematic, we see that ‫ܫ‬஻ூ஺ௌ = |‫ܫ‬஽ଵ | and from the error log file, we find ‘Id1 =
-2.00e-05’, i.e., ����� = 20 μA. Notice that in the error log file, ‘ Id1’ appears with a negative
value since the drain current flows out of the drain for a PMOS transistor and the LTspice
convention is that a current is positive when flowing into the transistor.

For finding ܸ஽஽ , we apply a loop equation to the loop consisting of ܸ஽஽ , ܸ஽ௌଷ and ܸ஽ௌ଼.
The loop equation results in െܸ஽஽ െ ܸ஽ௌଷ + ܸ஽ௌ଼ = 0 ֜ ܸ஽஽ = ܸ஽ௌ଼ െ ܸ஽ௌଷ .

From the error log file, we find ‘vds3 = -1.63e+00’ and ‘vds8 = 1.67e+00’, i.e., ܸ஽஽ = 1.67 V +
1.63 V = 3.30 V .

Question 2:
For finding the input quiescent voltage ܸூேଵ, we apply a loop equation to the loop consisting of
ܸூேଵ , ܸீ஽ହ = ܸீௌହ െ ܸ஽ௌହ and ܸ஽ௌ଻. The loop equation results in െܸூேଵ + ܸீௌହ െ ܸ஽ௌହ + ܸ஽ௌ଻ =
0 ֜ ܸூேଵ = ܸீௌହ െ ܸ஽ௌହ + ܸ஽ௌ଻ . From the error log file, we find ‘vgs5 = -9.19e-01’, ‘vds5
= -1.80e+00’ and ‘vds7 = 7.73e-01’, i.e., ���� = −0.919 V + 1.80 V + 0.773 V = 1.654 V .

For finding the input quiescent voltage ܸூேଶ, we apply a loop equation to the loop consisting of
ܸூேଶ , ܸீ஽ସ = ܸீௌସ െ ܸ஽ௌସ and ܸ஽ௌ଺. The loop equation results in െܸூேଶ + ܸீௌସ െ ܸ஽ௌସ + ܸ஽ௌ଺ =
0 ֜ ܸூேଵ = ܸீௌସ െ ܸ஽ௌସ + ܸ஽ௌ଺ . From the error log file, we find ‘vgs4 = -9.19e-01’, ‘vds4 =
-1.80e+00’ and ‘vds6 = 7.73e-01’, i.e., ���� = −0.919 V + 1.80 V + 0.773 V = 1.654 V.

As expected, ܸூேଵ = ܸூேଶ .

For finding the output quiescent voltage ܸை, we note that ܸை = ܸ஽ௌ଼ . From the error log
file, we find ‘vds8 = 1.67e+00’, i.e., ܸை = 1.67 V .

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287
CMOS ANALOG IC DESIGN Solution to Problem 42

Question 3:
The low-frequency small-signal differential gain is the product of the small-signal gain in
the input differential stage and the small-signal gain in the output common-source stage.

The gain in the differential stage is ‫ܣ‬ௗ = ‫ݒ‬ௗ଻ /‫ݒ‬௜ௗ ؄ െ݃௠ସ (‫ݎ‬ௗ௦ହ ‫ݎ צ‬ௗ௦଻ ) = െ݃௠ସ /(݃ௗ௦ହ + ݃ௗ௦଻ ),
compare to Eq. (4.67) in ‘CMOS Analog IC Design: Fundamentals’. The gain in the common-
source stage is ‫ܣ‬௖௦ = ‫ݒ‬௢ /‫ݒ‬௚଼ = െ݃௠଼ (‫ݎ‬ௗ௦ଷ ‫ݎ צ‬ௗ௦଼ ) = െ݃௠଼ /(݃ௗ௦ଷ + ݃ௗ௦଼ ) , compare to Eq.
(4.5) in ‘CMOS Analog IC Design: Fundamentals’. Hence, the total gain is

݃௠ସ ݃௠଼
‫ܣ‬௩ = ‫ݒ‬௢ /‫ݒ‬௜ௗ = ‫ܣ‬ௗ ‫ܣ‬௖௦ = ൬ ൰൬ ൰
݃ௗ௦ହ + ݃ௗ௦଻ ݃ௗ௦ଷ + ݃ௗ௦଼

The error log file shows ‘Gm4 = 3.28e-04’, ‘Gds5 = 2.42e-06’, ‘Gds7 = 2.77e-06’, ‘Gm8
= 2.99e-03’, ‘Gds3 = 1.39e-05’ and ‘Gds8=1.38e-05’. Inserting in the expression for ‫ܣ‬௩,
we find

328 μA/V 2990 μA/V

�� = � �×� � = 63.2 × 107.9 = 6822 V/V
2.42 μA/V + 2.77 μA/V 13.9 μA/V + 13.8 μA/V
∼ 76.7 dB

Question 4:
Using the results from Section 7.2 in ‘CMOS Analog IC design: Fundamentals’, we find the
frequency ݂௣ଵ of the dominant pole from the time constant caused by the output resistance
‫ݎ‬௢௨௧ଵ = ‫ݎ‬ௗ௦଻ ‫ݎ צ‬ௗ௦ହ = 1/(݃ௗ௦଻ + ݃ௗ௦ହ ) of the differential stage and the input capacitance
‫ܥ‬௜௡,௖௦ to the common-source stage.

The output resistance is ����� = 1/(2.42 μA/V + 2.77 μA/V) = 192.7 kΩ..

Neglecting the small parasitic capacitances from M5 and M7, the input capacitance is the
sum of ‫ܥ‬௚ௗ଼ and the Miller capacitance caused by ‫ܥ‬௖ and ‫ܥ‬௚ௗ଼, i.e., ‫ܥ‬௜௡,௖௦ ؄ ‫ܥ‬௚௦଼ + (1 െ ‫ܣ‬௖௦ )൫‫ܥ‬௖ +
‫ܥ‬௚ௗ଼ ൯.

From the error log file, we find:

‫ܥ‬௚௦଼ = Cgs8 + Cgsov8 + Cgb8 + Cgbov8 = 50.4 fF + 10.0 fF + 0.00 fF + 0.07 fF=60.47fF

‫ܥ‬௚ௗ଼ = Cgd8 + Cgdov8 = 0.00 fF + 10.0 fF = 10.0 fF

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288
CMOS ANALOG IC DESIGN Solution to Problem 42

Using ��� = −107.9 from Question 3, we find:

‫ܥ‬௜௡,௖௦ = 60.47 fF + (1 + 107.9) × (0.2 pF + 10.0 fF) = 22.9 pF .

Thus, we find ��� ≃ 1/�2������� ���,�� � = 1/(2 × � × 192.7 kΩ × 22.9 pF) = 36.1 kHz.

Question 5:
Using the results from Section 7.2 in ‘CMOS Analog IC design: Fundamentals’, we find
the frequency ݂௣ଶ of the non-dominant pole from Eq. (7.6):

1 ݃௠଼
݂௣ଶ = ൬ ൰ቆ ቇ
2Ԝߨ ‫ܥ‬ଵ + ‫ܥ‬ଶ + ‫ܥ‬ଵ ‫ܥ‬ଶ /൫‫ܥ‬௖ + ‫ܥ‬௚ௗ଼ ൯

where ‫ܥ‬ଵ ؄ ‫ܥ‬௚௦଼ = 60.47 fF i is the capacitance to ground at the output of the differential
stage and �� = �� + ���� + ���� = 1.0 pF + 7.94 fF + 7.86 fF ≃ 1.02 pF is the capacitance
to ground from the output of the amplifier. As the numbering of the transistors is different
compared to Eq. (7.6) in ‘CMOS Analog IC design: Fundamentals’, the transconductance
in the numerator has been changed to ݃௠଼ (the transconductance of the common-source
transistor) and ‫ܥ‬௖ has been replaced by ‫ܥ‬௖ + ‫ܥ‬௚ௗ଼ in the equation above.

Inserting numerical values, we find:

1 2.99 mA/V
��� = � �� � ≃ 346 MHz
2 × � 60.47 fF + 1.02 pF + 60.47 fF × 1.02 pF/(0.2 pF + 10.0 fF)

Question 6:
Using the results from Section 7.2 in ‘CMOS Analog IC design: Fundamentals’, we find
the frequency ݂௭ of the zero from Eq. (7.7) with ݃௠଻ replaced by ݃௠଼ and ‫ܥ‬௖ replaced by
‫ܥ‬௖ + ‫ܥ‬௚ௗ଼ :

1 ��� 1 2.99 mA/V

�� = � �� �=� �� � ≃ 2.27 GHz
2�� �� + ���� 2 × � 0.2 pF + 10.0 fF

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CMOS ANALOG IC DESIGN Solution to Problem 42

Question 7:
From feedback theory, Eq. (6.13) in ‘CMOS Analog IC Design: Fundamentals’, we find
‫ݎ‬௢௨௧
‫ݎ‬௢௨௧஼௅ =
1 + ߚ‫ܣ‬௩

where ‫ݎ‬௢௨௧ is the output resistance of the opamp without feedback, ‫ܣ‬௩ is the open-loop
gain op the opamp ߚ and is the feedback factor. For a buffer where the output is connected
directly to the inverting input, the feedback factor is ߚ = 1. From Question 3, we have
‫ܣ‬௩ = 6822 V/V .

The open-loop output resistance of the opamp is

1 1
���� = ���� � ��� = = = 36.1 kΩ
���� + ���� 13.9 μA/V + 13.8 μA/V

Inserting in the expression for the closed-loop output resistance, we find

36.1 kΩ
������ = = 5.29 Ω
1 + 6822 V/V

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290
CMOS ANALOG IC DESIGN Solution to Problem 43

SOLUTION TO PROBLEM 43

Question 1:
The closed-loop gain is given by ‫ܣ‬஼௅ (‫)ݏ(ܣ = )ݏ‬/൫1 + ߚ(‫)ݏ(ܣ)ݏ‬൯. At very low frequencies,
we have �(�) = �� = 80 dB ∼ 10000 V/V and ߚ = 0.05 V/V, so we find the low-frequency
closed-loop gain to be ���� = 10000 V/V/(1 + 0.05 V/V × 10000 V/V) = 19.96 V/V ∼
26.0 dB.

Question 2:
For a first-order system, the bandwidth BW of the amplifier with feedback is equal to the
bandwidth ݂௣ଵ of the amplifier without feedback multiplied by the low-frequency amount
of feedback (1 + ߚ‫ܣ‬଴ ), see Eq. (6.11) in ‘CMOS Analog IC Design: Fundamentals’.

Thus, BW = ݂௣ଵ (1 + ߚ‫ܣ‬଴ ) = 1.2 kHz × (1 + 0.05 V/V × 10000 V/V) = 601.2 kHz.

The answers to Questions 1 and 2 may be verified by an LTspice simulation. Shown below
is an LTspice schematic of the feedback amplifier and a plot of from a ‘.ac’ simulation. The
ିଵ
ܴ‫ ܥ‬network provides a time constant ߬ଵ = ൫2ߨ݂௣ଵ ൯ .

The low-frequency open-loop gain is modeled by the voltage-controlled voltage source ‘E1’
and the feedback factor ߚ is modeled by the voltage-controlled voltage source ‘E2’.

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CMOS ANALOG IC DESIGN Solution to Problem 43

From the ‘.ac’ simulation, we find a low-frequency gain of 26.0 dB ¾ 20.0 V/V and a −3 dB
frequency of 600 kHz.

Alternatively, the low-frequency gain and the bandwidth may be found using the ‘.meas’
directives shown in the schematic. From the error log file, we find the low-frequency gain to
be 26.0032 dB ¾ 20.0 V/V and the bandwidth to be 601.363 kHz, matching the calculated
results very well.

Question 3:

The phase margin PM is calculated from Eq. (6.24) in ‘CMOS Analog IC Design: Fundamentals’,
i.e., PM = 90° + arctan(1/‫ܮ‬଴ ) where ‫ܮ‬଴ = ߚ‫ܣ‬଴ is the low-frequency loop gain.

Thus, PM = 90° + arctan൫1/(0.05 × 10000)൯ = 90.11°.

The phase margin may also be found using LTspice. The loop gain can be plotted from a
‘.ac’ simulation using the schematic below where the feedback loop has been opened.

Also a plot of the loop gain is shown.

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CMOS ANALOG IC DESIGN Solution to Problem 43

From the plot of the feedback voltage ܸ௙, we find a phase margin of 90.12° as shown above.

The phase margin may also be found using the ‘.meas’ directive shown in the LTspice
schematic.

The phase margin is PM = 180° � ����(��� )� = 180° + ���(��� )� = ����(��� )� where

‫ )݂݆(ܮ‬is the loop gain and ݂௧ is the frequency where |‫ |)݂݆(ܮ‬has dropped to a value of 1.
Thus, the phase of ‘-v(Vf )’ is equal to the phase margin when the magnitude of ‘v(Vf )’ is
equal to 1. The result of the ‘.meas’ directive is found in the error log file which shows a
phase margin of 90.1147°, perfectly matching the calculated phase margin.

Question 4:
Shown below is an LTspice schematic of the feedback amplifier with two poles in the ‫ܣ‬
ିଵ
-circuit. The two ܴ‫ ܥ‬networks provide a time constant ߬ଵ = ൫2ߨ݂௣ଵ ൯ and a time constant
ିଵ
߬ଶ = ൫2ߨ݂௣ଶ ൯ . The low-frequency open-loop gain is modeled by the voltage-controlled
voltage source ‘E1’ and the feedback factor ߚ is modeled by the voltage-controlled voltage
source ‘E2’.

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CMOS ANALOG IC DESIGN Solution to Problem 43

From a ‘.ac’ simulation, we obtain the following plot of the output voltage from which
we find a low-frequency gain of 26.0 dB ¾ 20.0 V/V and a −3 dB frequency of 849 kHz.

Alternatively, the low-frequency gain and the bandwidth may be found using the ‘.meas’
directives shown in the schematic. From the error log file, we find the low-frequency gain
to be 26.0032 dB ¾ 20.0 V/V and the bandwidth to be 849.400 kHz.

We may also estimate the bandwidth by recognizing that the amplifier is a second-order system
with a gain-bandwidth product of the loop gain of ݂௧௟ = ݂௣ଵ ߚ‫ܣ‬଴ = 1.2 kHz × 0.05 V/V ×
10000 V/V = 600 kHz and a second pole at the frequency ݂௣ଶ = 1.2 MHz. This gives the
ratio ݂௣ଶ /݂௧௟ = 2 and from Fig. 6.30 in ‘CMOS Analog IC Design: Fundamentals’, we
may estimate the closed-loop bandwidth to be BW ≃ 1.41���� = 1.41 × 600 kHz = 846 kHz,
closely matching the simulated value.

Question 5:
For a second-order system with ݂௣ଶ /݂௧௟ = 2 , we find a phase margin of 65.5°, see Fig.
6.35(a) in ‘CMOS Analog IC Design: Fundamentals’.

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CMOS ANALOG IC DESIGN Solution to Problem 43

The phase margin may also be found using LTspice. The loop gain can be plotted from a
‘.ac’ simulation using the schematic below where the feedback loop has been opened. Also
a plot of the loop gain is shown.

From the plot of the feedback voltage ܸ௙, we find a phase margin of 65.6° as shown above.

Using the same approach as in Question 3, the phase margin may also be found using the
‘.meas’ directive shown in the LTspice schematic.

The result of the ‘.meas’ directive is found in the error log file which shows a phase margin
of 65.6587°, closely matching the value found from Fig. 6.35(a) in ‘CMOS Analog IC
Design: Fundamentals’.

Question 6:
The following figure shows an LTspice schematic of the feedback amplifier with the dominant
pole in the ‫ܣ‬-circuit and the non-dominant pole in the ߚ-circuit.

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CMOS ANALOG IC DESIGN Solution to Problem 43

The open-loop gain is modeled by the voltage-controlled voltage source ‘E1’ and the ܴ‫ܥ‬
network ‘R1’ and ‘C1’. The voltage-controlled voltage source ‘E3’ serves as an output
buffer ensuring an output resistance of zero for the ‫ܣ‬-circuit. The feedback network is
modeled by the voltage-controlled voltage source ‘E2’, the ܴ‫ ܥ‬network ‘R2’ and ‘C2’ and
the voltage-controlled voltage source ‘E4’ (serving as an input buffer, ensuring an infinite
input impedance of the ߚ-network).

From a ‘.ac’ simulation, we obtain the following plot of the output voltage from which we
find a low-frequency gain of 26.0 dB ¾ 20.0 V/V and a −3dB frequency of 1.076 MHz.

Alternatively, the low-frequency gain and the bandwidth may be found using the ‘.meas’
directives shown in the schematic. From the error log file, we find the low-frequency gain
to be 26.0032 dB ¾ 20.0 V/V and the bandwidth to be 1.08127 MHz.

We notice that the bandwidth is larger for this configuration than for the configuration
with both poles in the ‫ܣ‬-circuit. With both poles in the ‫ܣ‬-circuit, we find
‫)ݏ(ܣ‬ ‫ܣ‬଴
‫ܣ‬஼௅ (‫= )ݏ‬ =
1 + ߚ‫ )ݏ(ܣ‬൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯ + ߚ‫ܣ‬଴

With the dominant pole in the ‫ܣ‬-circuit and the non-dominant pole in the ߚ-circuit, we find

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CMOS ANALOG IC DESIGN Solution to Problem 43

‫)ݏ(ܣ‬ ‫ܣ‬଴ ൫1 + ‫ݏ‬/߱௣ଶ ൯

‫ܣ‬஼௅ (‫= )ݏ‬ =
1 + ߚ(‫ )ݏ(ܣ)ݏ‬൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯ + ߚ‫ܣ‬଴

When comparing the two expressions for the closed-loop gain, we see that the poles are
the same for the two configurations but the configuration with the non-dominant pole
in the ߚ-network also has a zero at the frequency ߱௣ଶ, pushing the −3 dB frequency to a
higher value.

Question 7:
The phase margin is determined by the loop gain

ߚ ‫ܣ‬଴ ߚ‫ܣ‬଴
‫ = )ݏ(ܣ)ݏ(ߚ = )ݏ(ܮ‬ቆ ቇቆ ቇ=
1 + ‫ݏ‬/߱௣ଶ 1 + ‫ݏ‬/߱௣ଵ ൫1 + ‫ݏ‬/߱௣ଵ ൯൫1 + ‫ݏ‬/߱௣ଶ ൯

We notice that the expression for the loop gain is the same for the amplifier with the
non-dominant pole in the ‫ܣ‬-circuit and the amplifier with the non-dominant pole in the
ߚ-circuit. Hence, the phase margin is the same for the two amplifiers, i.e., PM ≃ 65.6°.

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CMOS ANALOG IC DESIGN Appendix A

APPENDIX A

Deriving a small-signal equivalent circuit from a large-signal schematic

Deriving a small-signal equivalent circuit requires some experience. For the beginner, it may
be useful to apply a step-by-step procedure when creating the small-signal equivalent circuit.

The steps in the procedure are the following:

1. Reset all dc voltage sources and current sources. A voltage source is reset by
replacing it with a short circuit. A current source is reset by replacing it with
an open circuit, i.e., by removing it.
2. Remove components (e.g., transistors, resistors, etc.) which are subject to only
dc voltages or dc currents. This is typically components used for generating dc
bias voltages or currents. Alternatively, this step may be performed as the first
step in deriving the small-signal equivalent circuit.
3. Replace all nonlinear components (e.g., transistors and diodes) with their
linearized small-signal models while leaving linear components (e.g., resistors,
capacitors and inductors) unchanged.
4. Reset controlled sources where the controlling signal is zero, i.e., remove
controlled current sources with a controlling signal of zero and short circuit
controlled voltage sources where the controlling signal is zero.
5. Redraw the small-signal equivalent circuit by ‘folding down’ devices which have
a ground connection pointing upwards.

We illustrate the procedure by a few examples.

Example 1. The first example is a common-source amplifier with a resistive load. The large-
signal schematic is shown below.

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CMOS ANALOG IC DESIGN Appendix A

The first step is to reset all dc voltage sources and dc current sources. Thus, ܸ஽஽ is replaced
by a short circuit and the input voltage is changed from ‫ݒ‬ூே = ܸூே + ‫ݒ‬௜௡ to
to‫ݒݒ‬௜௡௜௡ , i.e., the
dc bias voltage ܸூே is reset.

Also, the notation for the output voltage is changed from ‫ݒݒ‬ைை==ܸܸ
ைை++‫ݒݒ‬௢௢toto‫ݒݒ‬௢௢ which is only
to
the small-signal part of the output voltage. Likewise, the notation for the drain current is
changed from ݅஽ = ‫ܫ‬஽ + ݅ௗ to ݅ௗ . The following figure shows the schematic resulting from
this step.

In this circuit, there are no components which are subject to only dc voltages or dc currents
so step 2 is omitted and we proceed with the next step. The only nonlinear device in the
circuit is the transistor M1, so the next step is to replace the symbol for M1 with the small-
signal model for the transistor as shown in the following figure. The small-signal model
for M1 is shown in the box outlined with the red dashed line. Gate, drain and source are
marked by G1, D1 and S1, respectively.

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CMOS ANALOG IC DESIGN Appendix A

Finally, the small-signal equivalent circuit is redrawn with ܴ஽ ‘folded down’ towards ground
as shown in the following figure.

Example 2. The second example is a common-source amplifier with an active load. The
large-signal schematic is shown below.

The first step is to reset all dc voltage sources and current sources. Thus, ܸ஽஽ and ܸ஻ are
both replaced by short circuits and the input voltage is changed from ‫ݒ‬ூே = ܸூே + ‫ݒ‬௜௡ to
to‫ݒ‬௜௡
‫ݒ‬௜௡ , i.e., the dc bias voltage ܸூே is reset.

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CMOS ANALOG IC DESIGN Appendix A

Also, the notation for the output voltage is changed from ‫ݒ‬ை‫ݒ‬ை==ܸைܸை++‫ݒ‬௢‫ݒ‬௢to
toto‫ݒ‬௢‫ݒ‬௢ which is
only the small-signal part of the output voltage. The following figure shows the schematic
resulting from this step.

In this circuit, there are no components which are subject to only dc voltages or dc currents
so step 2 is omitted and we proceed with the next step. The only nonlinear devices in the
circuit are the transistors M1 and M2, so the next step is to replace the symbols for M1 and
M2 with the small-signal models for the transistors as shown in the following figure. The
small-signal models are shown in the boxes outlined with the red dashed lines. Gate, drain
and source are marked by G1, D1 and S1 for M1, and G2, D2 and S2 for M2.

In this circuit, we notice that the controlling signal ‫ݒ‬௚௦ଶ for the current source ݃௠ଶ ‫ݒ‬௚௦ଶ is
zero, so this current source is removed when redrawing the small-signal equivalent circuit
with ‫ݎ‬ௗ௦ଶ ‘folded down’ towards ground as shown in the following figure.

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CMOS ANALOG IC DESIGN Appendix A

Example 3. The third example is a common-source amplifier with a current mirror as an

active load. The large-signal schematic is shown below.

When examining the schematic, we notice that ܴ஻ and M3 are subject only to dc voltages.
They are used for generating the gate voltage of M2 as a dc voltage. There is no signal path
from the input signal to the gate voltage of M2 and M3 at low frequencies. Hence, ܴ஻ and
M3 may be replaced by a dc voltage ܸீଶ = ܸ஻ at the gate of M2. This turns the circuit into
a circuit which is identical to the circuit shown in Example 2 so the conversion to a small-
signal equivalent diagram results in the same small-signal diagram as shown for the amplifier
in Example 2. Neither ܴ஻, nor the small-signal parameters ݃௠ଷ and ‫ݎ‬ௗ௦ଷ are present in the
small-signal equivalent circuit.

Example 4. The fourth example is an inverting amplifier which is a parallel connection

of a PMOS common-source stage and an NMOS common-source stage. The large-signal
schematic is shown in the following figure. This circuit may also be treated as a digital
inverter.

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CMOS ANALOG IC DESIGN Appendix A

The first step in deriving the small-signal equivalent diagram is to reset all dc voltage sources
and current sources. Thus, ܸ஽஽ and ܸௌௌ are both replaced by short circuits and the input
voltage is changed from ‫ݒ‬ூே = ܸூே + ‫ݒ‬௜௡ to
to ‫ݒݒ‬௜௡௜௡ , i.e., the dc bias voltage ܸூே is reset.

Also, the notation for the output voltage is changed from ‫ݒ‬ை‫ݒ‬ை==ܸைܸை++‫ݒ‬௢‫ݒ‬௢to
toto‫ݒ‬௢‫ݒ‬௢ which is
only the small-signal part of the output voltage. The following figure shows the schematic
resulting from this step.

In this circuit, there are no components which are subject to only dc voltages or dc currents
so step 2 is omitted and we proceed with the next step. The only nonlinear devices in the
circuit are the transistors M1 and M2, so the next step is to replace the symbols for M1 and
M2 with the small-signal models for the transistors as shown in the following figure. The
small-signal models are shown in the boxes outlined with the red dashed lines. Gate, drain
and source are marked by G1, D1 and S1 for M1, and G2, D2 and S2 for M2.

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CMOS ANALOG IC DESIGN Appendix A

Finally, the small-signal equivalent circuit is redrawn with M2 ‘folded down’ towards ground
as shown in the following figure. Observe that the two transistors are connected in parallel
in the small-signal equivalent circuit.

Example 5. The fifth example is a current mirror where the output resistance is increased
by using a regulated cascode transistor. The schematic is shown in the following figure. The
current source ‫ܫ‬஻ is a dc bias current source with a finite small-signal output resistance ‫ݎ‬௢ ).
The output of the current mirror is connected to a voltage ‫ݒ‬ை = ܸை + ‫ݒ‬௢ .toThe
‫ݒ‬௢ small-signal
equivalent circuit is to be used for finding the small-signal output resistance ‫ݎ‬௢௨௧ looking
into the drain of M3.

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CMOS ANALOG IC DESIGN Appendix A

The first step in deriving the small-signal equivalent diagram is to reset all dc voltage sources
and current sources. Thus, ܸ஽஽ is replaced by a short circuit and for the current source, the
dc bias current is reset, i.e., removed while the output small-signal resistance appears as a
resistor ‫ݎ‬௢ ). The input current is changed from ݅ூே = ‫ܫ‬ூே + ݅௜௡ to ݅௜௡, i.e., the dc bias current
‫ܫ‬ூே is reset, and the voltage source connected to the output is changed from ‫ݒ‬ை = ܸை + ‫ݒ‬௢ to to ‫ݒ‬௢
which is only the small-signal part of the output voltage, i.e., the dc bias voltage ܸை is reset.

The following figure shows the schematic resulting from this step.

In this circuit, there are no components which are subject to only dc voltages or dc currents
so step 2 is omitted and we proceed with the next step. The nonlinear devices in the circuit
are the transistors M1 - M4, so the next step is to replace the symbols for M1 - M4 with the
small-signal models for the transistors as shown in the following figure. The small-signal
models are shown in the boxes outlined with the red dashed lines and gate, drain and source
are marked for each transistor.

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CMOS ANALOG IC DESIGN Appendix A

Finally, we may redraw the small-signal equivalent diagram as shown below. We may combine
‫ݎ‬ௗ௦ସ and ‫ݎ‬௢ ) into a single resistor which is (‫ݎ‬ௗ௦ସ ‫ݎ צ‬௢ ) as shown below.

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