EE3408E Project Design A Two-Stage Operational Amplifier

EE3408E: Integrated Analog Design
EE3408E Project (AY2016-17)

Design a Two-stage Operational Amplifier
Introduction
The objective of this project is to learn analog integrated circuit design using LTSpice.
The project consists of three sub-projects: the design of (1) a single-stage amplifier, (2) a
differential amplifier and (3) an operational amplifier (op-amp). The design will be based
on a 0.35m CMOS technology (Device model library file: CMOS035.lib). To spread the
loading across the whole semester, you are required to submit a short project reports for
each sub-project when it is due. You may be requested to give a short demonstration of
your design and simulation results.
The project counts 30% of the total assessment and the weightage of each sub-project
are
- Sub-project 1: 5%
- Sub-project 2: 10%
- Sub-project 3: 15%
You will be using LTSPICE for circuit simulation. LTSPICE is a very handy and yet
powerful circuit design software from Linear Technology and can be free downloaded at
www.linear.com. It can be run on PC or laptop. You can also copy LTSPICE files on a
USB drive and run it on any PC or laptop.
LTSPICE tutorials, device model and symbol files for simulation can be downloaded
from module folder on IVLE. Note that there will be no formal lab session for the project.
If you have any problem with LTSpice simulation, please see me during scheduled
consultation time or make a separate appointment.
This is an individual project. You must work on your project INDEPENDENTLY.
Sub-project 1: Design a CS amplifier with CSL (due on Friday of Week 4)
This sub-project consists of two parts: (1) MOSFET parameter extraction and (2) design
of a CS amplifier with CSL
(1) MOSFET parameter extraction
Plot I-V curves, ID~VDS and ID~VGS for both NMOS and PMOS transistor in LTSPICE,
and extract the following parameters with the aid of equations (Do not use the drain
current equation in linear region).
Threshold voltage (VTH), for VBS=0, -0.5V(NMOS) and 0.5V(PMOS)

Gain factor (k),
Channel length modulation factor ()
The circuit set up for nMOSFET is given in Fig. 1. The maximum voltage for both VDS
and VGS is 3V. Note that the channel length modulation coefficient is a function of
channel length. The minimum allowed channel length is 0.35m in this technology. For
analog design, relatively long channel length is preferred as long channel length has (1)
high output resistance and (2) less impact by process variation (L). However do
remember that long channel length results in large transistor size and hence more silicon
area and large parasitic capacitance. In this part, choose W=20m and L=1m.
Please list the extracted parameters in a table and include the necessary plots, data and
calculation in your report. The extracted parameters can be used later in sub-project 2
and 3 for hand calculation.
ID
VDS
VGS
VBS
Fig. 1. Circuit setup for parameter extraction.

Some hints:
1. Threshold voltage (VTH) extraction
From the square-law ID equation in saturation region, we notice that (ID)1/2 is a linear
function of VGS, and when ID=0, VGS=VTH. Plot (ID)1/2 vs. VGS curve in LTSPICE.
Extrapolate the linear portion of the curve to x-axis (ID=0). The interception on VGS
axis is the VTH.
Repeat the above with different body bias VBS, you can manifest the body effect and
obtain the new VTH under different body bias.
2. Channel length modulation factor () extraction
Based on the formula for on Slide 21 (Lecture 2), plot ID~VDS. Find the slope
ID/VDS and can be calculated. You may choose the ID around 0.5mA for
calculation, though theoretically, ID shouldnt matter.
3. Gain factor (k) extraction
Once is known, plot ID~VDS. Find the ID value in the simulation. With known and ID,
k can be obtained from the drain current equation.
4. Construct the circuit setup for PMOS and repeat 1, 2 and 3. Make sure that the
polarities of the voltage sources are defined correctly.
(2) Single-stage CS amplifier with CSL
Design a single-stage CS amplifier with CSL for the following specifications. You may
refer to the design steps taught in the lecture 3.
1) Supply voltage (VDD):
2) Open-loop gain:
3) Output voltage swing:
3 V (Single supply)
> 50
> 1.2 Vp-p
4) DC output voltage:
5) Supply current:
6) Maximum channel width:
~ 1.5 V
< 500 A
500 m
VDD
RB
Vin
M1
Vout
M2
M3
Sub-project 2: Design a differential pair amplifier (due on Friday of Week 9)

This sub-project is to design a differential pair amplifier, as shown in Fig.2. You may
refer to the design steps in Lecture 6.
VDD
M5
VB
Vin
M1
M2
Vout
M3
M4
Fig. 2. Differential pair amplifier

The design specifications are as follows:
7) Supply voltage (VDD):
8) Open-loop gain:
9) CMRR :
11) Offset voltage:
12) Supply current:
3 V (Single supply)
> 50 dB (within the full common-mode range)
> 50 dB
> 200 mVp-p
< 2 mV
< 300 A
1000m
Sub-project 3: Design a two-stage op-amp (due on Friday of week 13)

This project is to design a classic two-stage op-amp with pMOS as input transistors. The
differential pair designed in sub-project 2 can be used for this part, with addition of
second stage. Frequency compensation needs to be applied to meet the bandwidth and
phase margin requirements.
Specifications (100%):
1) Supply voltage:
2) Open-loop DC gain:
3) Gain peaking:
4) Unity gain bandwidth:
5) Phase Margin:
6) CMRR :
8) Offset voltage:
9) Supply current:
10) Output load capacitance:
3 V (Single supply)
> 72 dB
< 3 dB (ratio of maximum gain to gain at DC)
> 18 MHz
> 60 degree
> 70 dB
> 1.0 V (Peak-to-Peak)
< 2m V
< 600 A
0.3 pF
1000m
Notes:
Only one DC voltage source is allowed, that is, the VDD. The bias current or voltage
required for op-amp must be generated from VDD.
Project reports (For all sub-projects)

Your project reports should contain
Introduction (background and objectives)
Circuit design with necessary hand calculations
LTSpice simulation results
Discussions of results and observations
Conclusion
Appendixes (if any)
Necessary figures, graphs, schematics must be included in the report to clearly show
whether the specifications are met.

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EE3408E: Integrated Analog Design

EE3408E Project (AY2016-17)

Threshold voltage (VTH), for VBS=0, -0.5V(NMOS) and 0.5V(PMOS)

EE3408E: Integrated Analog Design

Fig. 1. Circuit setup for parameter extraction.

EE3408E: Integrated Analog Design

Sub-project 2: Design a differential pair amplifier (due on Friday of Week 9)

Fig. 2. Differential pair amplifier

Sub-project 3: Design a two-stage op-amp (due on Friday of week 13)

EE3408E: Integrated Analog Design

Project reports (For all sub-projects)

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