Engineer-to-Engineer Note EE-302

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Interfacing ADSP-BF53x Blackfin® Processors to NAND FLASH Memory

Contributed by Ke Zhan and Daniel Zhao Rev 1 – November 10, 2006

Introduction NAND Flash vs. NOR Flash

NAND flash memory technology has emerged as NOR flash devices are widely used in the
a suitable, high-density alternative to hard disk electronics industry. They offer an easy memory
drives in power-sensitive portable devices. interface and are suitable for code execution,
Today, most cellular telephones, Personal Digital making them ideal for devices that do not need
Assistants (PDAs), digital cameras, Portable data storage. NOR memory offers good read
Media Players (PMPs), and other mobile performance, but has slow write/erase times.
computing/communications/consumer products However, as modern devices become more and
use NAND flash memory to store increasingly more sophisticated, they need to store more data
large media files, data, and operating systems. and programs locally while supporting faster
erase/write times. NAND flash offers all of this,
Blackfin® processors are well-suited for portable
plus better prices, in capacities ranging from 8 to
systems due to their low power dissipation, high
512 MB. NAND is an I/O device and requires a
performance, and convergent architecture. As
relatively complicated driver for any operation.
such, there is a growing demand to interface
Blackfin processors to NAND flash memories. Memory cells that are accessed frequently
become more prone to bit errors. Thus, NAND
This EE-Note describes how to interface both
flash devices typically include extra memory so
MLC- and SLC-type NAND flash memories to
that the NAND flash file system can replace bad
ADSP-BF53x Blackfin processors. Included are
blocks with good blocks without decreasing the
the low-level driver functions, which were
size of the available memory. A NAND flash
validated on a hardware platform consisting of a
file system, such as JFFS2, will typically attempt
NAND flash daughter board connected to an
to evenly wear the whole memory to increase the
ADSP-BF533 EZ-KIT LITE® (rev. 1.6)
life of the device.
evaluation system and the VisualDSP++® 4.0
(Updated April 2006) development tools.
To provide flexibility to system designers, two
NAND Flash: SLC vs. MLC
approaches are provided. The memory devices
used to demonstrate this interface are Samsung’s There are two different types of NAND flash
K9F2G08U0M SLC NAND flash and Toshiba’s devices in the market today: Single-Level-Cell
TC58NVG3D4CTG MLC NAND flash. (SLC) devices and Multi-Level-Cell (MLC)
devices. MLC chip technology is capable of
storing two or more bits of data per memory cell,
while SLC chip technology allows just one bit of
data per memory cell.

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MLC chips provide much larger storage capacity applications. SLC NAND flash is appropriate for
than SLC; however, they also suffer from lower specific, high-performance applications.
bandwidth for read and write operations. Also, SLC NAND flash is better suited for applications
the Error Correcting Code (ECC) requirement for that require speed. It performs many write/erase
MLC is higher than for SLC, as MLC technology
cycles that require high endurance and high
is more prone to bit errors. The cost per bit of reliability, such as in solid-state hard disk drives
MLC flash is much lower than that of SLC and devices used for seismic data recording,
devices. Figure 1 shows the comparison. networking, HDTV, bar code scanners,
Item SLC MLC shockproof PCs, flight recorders, handheld code
storage devices, as well as PDAs and digital still
Storage capacity Small Large
cameras.
Throughput High Low Typical applications that are well-suited for
ECC 1bit/528B 4bit/528B MLC NAND flash memory include digital video
Write/Erase Endurance 100K times 10K times and digital still camera memory cards, USB flash
drives, MP3 players, automobile diagnostic
Cost High Low
monitors, GPS devices, animatronics devices,
Figure 1. SLC vs. MLC Performance Comparison video game cards, and many toy applications.
Applications that may be suited for either MLC
MLC NAND flash memory provides a NAND or SLC NAND technology include
competitive level of performance and makes memory cards for printers (fonts), cell phones,
high-density NAND cards more affordable, telecom applications, voice mail, and TV set-top
enabling new breakthroughs in portable boxes. Figure 2 illustrates the classifications.

Figure 2. Typical Applications for SLC and MLC Devices

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NOR flash memories and other traditional when CE# is asserted. The Address Latch Enable
SRAM-like devices and memories use discrete (ALE) signal is used to latch the address into the
address data buses and basic control signals. address register of the flash device. Figure 3
NAND flash memory is optimized for large depicts the internal register accessed as a result
block transfers, incorporating a single set of I/O of valid combinations of CLE and ALE.
pins that are used for both address and data.
For Blackfin processors, it is possible to map the ALE CLE Register Selected
NAND flash memory ports to asynchronous
0 0 Data Register
memory space and access them as a standard
memory-mapped device. The hardware interface 0 1 Command Register
for both SLC and MLC NAND flash is identical. 1 0 Address Register
1 1 Reserved

Basic NAND Flash Interface Figure 3. Valid ALE/CLE Combinations

NAND flash devices utilize I/O pins for both

address and data, as well as for command inputs. Samsung K9F2G08U0M Interface
The command signals and command words are The Samsung K9F2G08U0M is offered in a
the same for both SLC and MLC NAND flash 256M x 8-bit (2G-bit) configuration with a spare
devices. This makes the interface to both SLC 64M-bit capacity. This memory device is an
and MLC flash chips universal for all Blackfin optimal solution for large nonvolatile storage
processors. applications such as solid-state file storage and
Flash memory is accessed by column, page, and other portable applications requiring non-volatile
block. The read and program operations execute memory.
at the page level, and erase operations are The device is offered in 2.7 V, 3.3 V, and 3.6 V
performed at the block level. supply voltage ranges. Typically, a program
The basic commands supported by NAND flash operation can be performed in 200 µs on the
memories are block erase, page program, read 2112-byte page, and an erase operation can be
status, and page read. The Chip Enable (CE#) pin performed in 2 ms on a 128-Kbyte block. Each
should be asserted low to access the device. byte in the data page can be read in 30 ns. The
When asserted, the NAND flash can be I/O pins serve as the ports for address and data
controlled to accept bytes provided by the host input/output, as well as for command input. One
when the Write Enable (WE#) signal is asserted page in the K9F2G08U0M consists of 2112
low or provide data to the host when the Read bytes, and one block comprises 64 pages.
Enable (RE#) signal is asserted low. When CE# is Figure 4 shows the organization of the
high, the chip ignores RE# and WE#, and the I/O is K9F2G08U0M flash memory device in terms of
tri-stated. The Command Latch Enable (CLE) pages and blocks.
signal is used to send commands to the device

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Figure 4. K9F2G08U0M Flash Memory Organization

Toshiba TC58NVG3D4CTG10 Interface necessary delays to match the timing

The Toshiba TC58NVG3D4CTG10 device is a requirements for NAND access.
single 3.3 V 8-Gbit NAND Electrically-Erasable Figure 5 shows details regarding the connections
and Programmable Read-Only Memory (NAND between an ADSP-BF533 Blackfin processor
E2PROM), organized as 2112 (2048+64) bytes and a Samsung K95G08U0M flash memory
per page, 128 pages per block, and 4160 device.
(4096+64) blocks.
The device has two 2112-byte static registers that
allow program and read data to be transferred
between the register and the memory cell array in
2112-byte increments. The erase operation is
implemented on a single block unit.

NAND Flash Interface to the

Figure 5. Using GPIO for NAND Flash Interface
ADSP-BF53x Processor
Because ADSP-BF53x Blackfin processors do
Using EBIU Pins to Interface to NAND Flash
not have an on-chip NAND flash controller, a
software driver is used to control and access A second approach is to use the External Bus
NAND flash memory. Two approaches are used Interface Unit (EBIU) and a single GPIO pin to
to interface a Blackfin processor to a NAND communicate with the NAND flash memory
flash device: GPIO pins and EBIU pins. device. Standard NAND flash requires that its
CE# remains valid during the read busy period.
Using GPIO Pins to Interface to NAND Flash So, for compatibility with both standard NAND
flash and Chip Enable Don’t Care (CEDC)
The first approach uses General-Purpose I/O pins NAND flash, a GPIO pin is used to drive the CE#
(GPIOs) to drive all the required control signals. signal. All other signals are driven directly by the
This approach requires careful timing for the EBIU interface.

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Figure 6 shows details regarding the connections which is the frequency at which all synchronous
between an ADSP-BF533 Blackfin processor memories interfaced to the processor will
and a Samsung K9F2G08U0M flash memory operate. Since the EBIU is automatically
device. controlled by the asynchronous memory
controller of the Blackfin processor, hooking the
NAND flash in this way is simple and yields
optimal access performance.

NAND Flash Driver Development

This EE-Note provides a basic Samsung
K9F2G08U0M and Toshiba TC58NVG3D4CTG
NAND flash driver for the two interface
Figure 6. Using EBIU Pins for NAND Flash Interface
approaches described above.
The EBIU can be programmed to control up to This section focuses on the second approach
four banks of devices with very flexible timing implementation and provides timing waveforms
parameters. Each bank occupies a 1-Mbyte for each command. Listing 1 shows the code
segment, regardless of the size of the device example for the block erase code implemented.
used, so these banks will only be contiguous if
each is fully populated with 1 Mbyte of memory.
The EBIU is clocked by the system clock (SCLK),

bool _NF_Block_Erase(unsigned int Block_Address){

unsigned char NAND_Data = 0;

NAND_Address_Table.Value = Block_Address << 12;

Write_Command(0x60);
Write_Address(NAND_Address_Table.NAND_Address.NAND_Address_A12_A19,
NAND_Address_Table.NAND_Address.NAND_Address_A20_A27,
NAND_Address_Table.NAND_Address.NAND_Address_A28,
NAND_Address_Table.NAND_Address.NAND_Address_A0_A7,
NAND_Address_Table.NAND_Address.NAND_Address_A8_A11,
0x03);

Write_Command(0xd0);
while(!Wait_NAND_RADY());
Write_Command(0x70);

delay(50000);
NAND_Data = *pNAND_DATA_REG;
NAND_Finish();

if(NAND_Data != 0xe0)//0xc0)
return false;

else return true;

}

Listing 1. Block Erase Function

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Listing 2 shows the code example using the page write function.
bool _NF_Page_Write(unsigned int Block_Address,unsigned short Page_Address,unsigned
char *psrc)
{
int i;
unsigned char NAND_Data;
int NAND_Addr;

NAND_Addr = (Block_Address << 12) | Page_Address;

NAND_Address_Table.Value = NAND_Addr;
Write_Command(0x80);
Write_Address(NAND_Address_Table.NAND_Address.NAND_Address_A0_A7,
NAND_Address_Table.NAND_Address.NAND_Address_A8_A11,
NAND_Address_Table.NAND_Address.NAND_Address_A12_A19,
NAND_Address_Table.NAND_Address.NAND_Address_A20_A27,
NAND_Address_Table.NAND_Address.NAND_Address_A28,
0x05);
delay(100);

for(i = 0;i<DATA_NUM;i++)
*pNAND_DATA_REG = *(psrc+i);

Write_Command(0x10);
while(!Wait_NAND_RADY());
Write_Command(0x70);

delay(5000);
NAND_Data = *pNAND_DATA_REG;

NAND_Finish();

if(NAND_Data != 0xe0)
return false;
else
return true;
}

Listing 2. Page Write Function

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Listing 3 shows the code example for the page read code implemented.
bool _NF_Page_Read(unsigned int Block_Address,unsigned short Page_Address,unsigned
char *pdes)
{
int i;

Write_Command(0x00);
Write_Address(NAND_Address_Table.NAND_Address.NAND_Address_A0_A7,
NAND_Address_Table.NAND_Address.NAND_Address_A8_A11,
NAND_Address_Table.NAND_Address.NAND_Address_A12_A19,
NAND_Address_Table.NAND_Address.NAND_Address_A20_A27,
NAND_Address_Table.NAND_Address.NAND_Address_A28,
0x04);
Write_Command(0x30);
while(!Wait_NAND_RADY());

for(i = 0;i<DATA_NUM;i++)
{
delay(600);
*(pdes+i) = *pNAND_DATA_REG;
}
NAND_Finish();

return true;
}

Listing 3. Page Read Function

The basic NAND flash drivers are based on low-level operations, like Write_Command(),
Write_Address(), Wait_NAND_RADY(), and Set_CE(). These operations handle the GPIO and address
signals to manipulate the flash chip. Listing 4 is for the implementation of the write command.
void Write_Command(unsigned char command)
{
Set_CE(0);
Write_NAND_FLASH_Com(command);
}

Listing 4. Write_Command Function

Listing 5 is the implementation of the Set_CE signal function.

void Set_CE(bool state)
{
if(!state)
*pFIO_FLAG_D &= ~PF11;

else
*pFIO_FLAG_D |= PF11;
}

Listing 5. Set_CE Function

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Listing 6 is for the implementation of the write flash command/address register function.
void Write_NAND_FLASH_Com(unsigned char Write_Data)
{
*pNAND_COMMAND_REG = Write_Data;
}

void Write_NAND_FLASH_Addr(unsigned char Write_Data)

{
*pNAND_ADDRESS_REG = Write_Data;
}

Listing 6. Write_NAND_FLASH_Com and Write_NAND_FLASH_Addr Functions

DMA can also be used to perform read/write memory device, which will compromise the
operations from/to the flash memory device. In integrity of the interface and yield unexpected
this case, the programmer should ensure that no results.
other core or DMA accesses happen to any of the CRO screenshots representing timing diagrams
external memory banks. Any such accesses can for this interface are shown in the following
cause spurious RD# and/or WR# pulses to the flash figures.

Figure 7: Erase Command

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Figure 8: Write Block Command

Figure 9: Read Command

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Figure 10: Read Chip ID Command

ECC for NAND Flash Unlike NOR flash, NAND flash demands a
mechanism, such as TrueFFS, to be implemented
Both the SLC and MLC NAND flashes require to map bad blocks.
an Error Correction Code (ECC) to detect and
correct bit errors. The Reed-Solomon algorithm File systems in the industry, such as JFFS,
is well-suited for this and has become the JFFS2, FAT, and so on, are feasible for NAND
standard EEC method for both types of flash flash. Additionally, the YAFFS (Yet Another
memory. Flash File System) is the only file system that
has been designed specifically for use with
The RS encoder and decoder for 72-bit RS NAND flash under any operating system.
(464, 456, 4) code have been implemented and YAFFS uses journaling error correction and
integrated into the NAND flash read/write verification techniques to enhance robustness,
drivers. and is designed to work within the constraints
of⎯and exploit the features of⎯NAND flash in
order to maximize performance. A future
NAND Flash File Systems revision of this EE-note will include the
NAND flash is optimized for file structures implementation of a specific file system for
where each word does not need to be read, but NAND flash.
instead provides that sectors of data can be
moved to and from the media supporting a hard-
drive-like repository structure for data storage to
support file systems and allocation tables (FAT).

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Conclusion
Although ADSP-BF53x Blackfin processors do
not have an on-chip NAND controller, designers
can easily connect SLC and MLC NAND flash
memory devices to EBIU or GPIO. Both
interfaces are seamless, thus requiring no
additional external logic. Designers can refer to
the code supplied with this EE-Note to develop
other NAND devices drivers.

References
[1] ADSP-BF533 Blackfin Embedded Processor Data Sheet, Rev. C, May, 2006. Analog Devices, Inc.
[2] MLC NAND Performance for Consumer Applications, Toshiba America Electronic Components, Inc.
[3] K9F2G08U0M 256M x 8 Bit / 512M x 8-Bit NAND Flash Memory Data Sheet, Rev 1.2, October 31, 2005.
Samsung Electronics, Inc.
[4] TC58NVG3D4CTG 8 GBIT (1G × 8 BIT / 512M × 16 BIT) CMOS NAND E2PROM (Multi-Level-Cell) Data Sheet,
TOSHIBA Semiconductor Company.
[5] Application Note for NAND Flash Memory, Rev. 2.0, December 1999, Memory Product & Technology Division from
Samsung Electronics, Inc.
[6] ADSP-BF533 Blackfin Processor Hardware Reference, Rev. 3.2, July 2006. Analog Devices, Inc.
[7] Interfacing NAND Flash Memory with ADSP-2126x SHARC Processors (EE-279), Rev. 1, November 2005.
Analog Devices, Inc.

Document History
Revision Description

Rev 1 – November 10, 2006 Initial version

by Ke Zhan & Daniel Zhao

Interfacing ADSP-BF53x Blackfin® Processors to NAND FLASH Memory (EE-302) Page 11 of 11