9/9/2022

Chapter 2 ARM Architecture and Assembly

Language Programming
• General Purpose Registers
• Register data size: Word (32-bit), Half-word (16-bit), and
Byte (8-bit)
• Memory Map
• Program counter (pc) - - 32 bit wide
• ARM core can access 232 = bytes of memory location
• Lowest address:
• Highest address:
• No microcontroller or SoC have the entire 4 gigabytes of on-chip memory

ARM Memory Allocation

5 sections of memory allocation
1. On-chip peripherals and I/O registers (SFR):
1. Registers of
2. Memory-mapped
3. The function and the address location of
each register is fixed by
at the time of design
2. On-Chip Data SRAM
1. Accessed by instructions
2. For variables and
3. On-Chip EEPROM
1. For saving data
2. Not all ARM chips have on-chip EEPROM
4. On-Chip Flash ROM
1. Space for storing
2. Also can be used for storage of static data
such as text strings and look-up tables
5. Off-Chip DRAM Space
1. External memory connection

1
 9/9/2022

ARM Instruction
ARM Instruction
• 3-part instruction format:
• Opcode (Mnemonic) destination, source1, source2
• EX
• MOV Rn, Op2
• Load Rn register with Op2 (operand 2)
• Op2 can be a register Rm or an immediate value of 8-bit

Instruction using General Purpose Regs

2
 9/9/2022

ADD (Add)
ADD Rd, Rn, Op2 ; Rn+Op2  Rd
EX) MOV r1, #0x25
MOV r7, #0x34
ADD r5, r1, r7 ; r1 + r7  r1

EX) MOV r1, #0x25

ADD r5, r1, #0x34 ; r1 + 0x34  r5

SUB (Subtract)
SUB Rd, Rn, Op2 ; Rn - Op2  Rd
EX) MOV r1, #0x25
SUB r5, r1, #0x25 // r1 – 0x25  r5

EX) SUB r1, r1, #0x25 //r1 = r1 – 0x25

SUB r1, #0x25 //r1 = r1 – 0x25
MOV r2, #0x10
SUB r3, r1, r2 //r3=r1 – r2
SUB r1, r2 //r1 = r1 – r2

3
 9/9/2022

A simple program
1) Write a program which calculates 19 + 95

1) Write a program which calculates 19 + 95 - 5

Load-Store Instructions

• ARM’s access to memory is done with specific instruction:

Load/Store Instruction
• Load
• Store
• Load
• Format: LDR destination, source
• LDR Rd, [Rx]

• Each memory location holds only byte of data

• LDR will bring in bytes of data from consecutive
memory locations.
• Rx holds the of the memory
• R5 = Rx = 0x8000,
• Rd =

4
 9/9/2022

Load-Store Instructions
• Example: LDR R7, [R5]
• Pre: R5=0x40000200
• Post: R7=[2bytes from 0x40000203 |2 bytes from 0x40000202|2
bytes from 0x40000201|2 bytes from 0x40000200]
• “Little Endian”

Load-Store Instructions

• Store
• Format :STR source, destination
• STR Rx, [Rd]

• Each memory location holds only byte of data

• STR will write in bytes of data to consecutive
memory locations.
• Rd holds the of the memory
• R5 = Rd = 0x8000,
• Rx will write each byte to the memory location- of

• “Little Endian”

10

10

5
 9/9/2022

Load-Store Instructions
• Example: STR R3, [R6]
• Pre: R3=0x4152 6374, R6=0x4000 0200
• Post: Write 2bytes to 0x4000 0203; 2 bytes to 0x4000 0202; 2
bytes to 0x4000 0201; 2 bytes to 0x4000 0200]
• “Little Endian”

11

11

Load/Store – Byte or Half-Word

• Load smaller data size (other than 32-bit word): Suffix B or H
• Load/Store 1 Byte: LDRB, STRB
• Load/Store Half-word (or 2 bytes): LDRH, STRH
• LDRB Example
• LDRB R7, [R5] //R5=0d4000 0200 with [4000 0200]=0x74
• “Little Endian”

12

12

6
 9/9/2022

Load/Store – Byte or Half-Word

• LDRH Example
• LDRH R7, [R5]
//R5=0x4000 0200 [4000 0200 – 4000 0203] = 0x74 0x63 0x52 0x41

• “Little Endian”

13

13

Load/Store – Byte or Half-Word

• STRB Example
• STRB R1, [R5]
• //R5=0x4000 0200 R1= 0x41526374

• “Little Endian”

14

14

7
 9/9/2022

Load/Store – Byte or Half-Word

• STRH Example
• STRH R3, [R6]
//R6=0x2000 R3=0x41526374

• “Little Endian”

15

15

Manual Execution
• State the contents of RAM locations 0x92 to 0x94 after the
following program is executed

MOV r1, #0x99

MOV r6, #0x92
STRB r1, [r6]
ADD r6, r6, #1
MOV r1, #0x85
STRB r1, [r6]
ADD r6, r6, #1
MOV r1, #0x3F
STRB r1, [r6]

16

16

8
 9/9/2022

ARM CPSR (Current Program Status Register)

• ARM’s flag register to indicate arithmetic conditions

• CPSR (Current Program Status Register)
• Conditional Flags: N, Z, C, V
• N (Negative flag):

• Z (Zero flag):

• C (Carry flag)

• C=1 errors in unsigned arithmetic operation

• V (Overflow flag)

• V=1 errors in signed arithmetic operation

17

17

S suffix and Status Register

• By default, in ARM instruction, the status flags of CPSR
are not updated
• Adding S-suffix at the end of an opcode, CPSR status
bits updated
• EX) ADD  ADDS
• EX) ORR  ORRS
• EX) SUB  SUBS
• Example – C and Z flag check
• Pre
• r1=0x0000009C r2=0xFFFFFF64
• ADDS r2, r1, r2
• Post
• r1+r2 =
• C =
• Z =

18

18

9
 9/9/2022

S suffix and Status Register

• Example – C and Z flag check
• Pre
• r1=0x0000009C r2=0xFFFFFF69
• ADDS r2, r1, r2
• Post
• r1+r2 =
• C =
• Z =

19

19

ARM Assembly Emulator -- CPUlator

https://cpulator.01xz.net

Best Tutorial Video: https://www.youtube.com/watch?v=gfmRrPjnEw4

Search “Assembly Language Programming with ARM – Full Tutorial for
Beginners” “CPUlator”
20

20

10
 9/9/2022

CPUlator
• Architecture: Select ARMv7
• System: Select ARMv7 generic
• Go: Click Go

21

21

CPUlator

1. Type the code

2. “Compile and Load”

22

22

11
 9/9/2022

CPUlator

23

23

CPUlator

• To save the code: File >> Save>> file_name.s

• EX) mycode1.s
• EX) SEP16.s 24

24

12
 9/9/2022

Load/Store – Simulation
• Load: LDR, LDRH, LDRB
• Store: STR, STRH, STRB

25

25

13