Assembly

1 . Data types
Instructions Type Size
DCB Byte 8 bits | 1 Byte
DCW Halfword 16 bits| 2 Bytes
DCD Word 32 bits | 4 Bytes
DCQ 64 bits | 8 Bytes

2. Load instructions :
→ LDR is used to load something from memory into a register

Load Instruction Size & Type Size Comments

LDR Word 32 bits | 4 Bytes load to register Word
LDRB Byte 8 bits | 1 Byte Load to register unsigned byte
LDRH Halfword 16 bits| 2 Bytes Load to register unsigned Halfword

LDRSB Signed byte 32 bits | 4 Bytes load to register a signed Byte ( load 8 bits , and fill the rest 24 bits
with the same bit of sign )
LDRSH Signed Halfword 32 bits | 4 Bytes load to register a signed Halfword ( load 16 bits , and fill the rest 16
bits with the same bit of sign )

3. Store instructions
→STR is used to store something from a register to a memory address.
Store Instuction Size & Type Size Comment
STR Word 32 bits | 4 Bytes Store word
STRB Byte 8 bits | 1 Byte Store unsigned Byte
STRH Halfword 16 bits| 2 Bytes Store unsigned haflword
STRSB Signed byte 32 bits | 4 Bytes Store signed Byte
STRSH Signed Halfword 32 bits | 4 Bytes Store signed Halff Word

! There are two basic ways of viewing bytes in memory:

Little-Endian (LE) or Big-Endian (BE). The difference is the
byte-order in which each byte of an object is stored in
memory
Instruction Description Instruction Description
MOV Move data EOR Bitwise XOR
MVN Move and negate LDR Load
ADD Addition STR Store
SUB Subtraction LDM Load Multiple
MUL Multiplication STM Store Multiple
LSL Logical Shift Left PUSH Push on Stack
LSR Logical Shift Right POP Pop off Stack
ASR Arithmetic Shift Right B Branch
ROR Rotate Right BL Branch with Link
CMP Compare ( The CMP instruction do the comparison by subtracting BX Branch and eXchange
the value of the two registers → that’s why the N flag get updated
at the end of this instruction )
Keep in mind that the registers used with the CMP instruction won’t
be modified, only the CPSR will be modified based on the result of
comparing these registers against each other.
AND Bitwise AND BLX Branch with Link and eXchange
ORR Bitwise OR SWI/SVC System Call

4. Instructions
Instruction Comment
Memory Address Is written on 32 bits
RAM Address 0x20000000
in the RAM memory, user capable of reading and writing
( 0x2000000 < ) : in the flash memory user is only capable of reading which mean :
user can’t use the STR instruction !
=label The address of the that label
Align Add Zeros to the memory until it finds an address that is a multiple of 4
[R1] The content pointed by R1
[R1, #2] The content pointed by ( the value of R1 increased by 2)
PS : the value of R1 rest unchanged after this operation
[R1,#2]! The content pointed by ( the value of R1 increased by 2)
PS : the value of R1 will be changed after this operation
[R1],#2 The content pointed by R1
PS : after this operation the value of R1 will be increased by 2
 5. ARM Registers

General purpose Special Purpose Registers

R0 General purpose R6 General purpose R12 Intra Procedural Call ( IP )
R1 General purpose R7 Holds Syscall Number R13 Stack Pointer ( SP)
R2 General purpose R8 General purpose R14 Link Register ( LR )
R3 General purpose R9 General purpose R15 Program Counter ( PC )
R4 General purpose R10 General purpose CPSR Current Program Status Register
R5 General purpose R11 Frame Pointer

• R0-R12: can be used during common operations to store temporary values

• R13: SP (Stack Pointer). The Stack Pointer points to the top of the stack. The stack is an area of
memory used for function-specific storage,
• R14: LR (Link Register). When a function call is made, the Link Register gets updated with a memory
address referencing the next instruction where the function was initiated from.
• R15: PC (Program Counter). stores the address of the current instruction at execution.
• the Current Program Status Register (CPSR) contains the Flags thumb, fast, interrupt, overflow, carry,
zero, and negative. These bits define various properties of the program’s current state.

6. Current Program Status Register (CPSR)

Flag Description Flag description

N Negative Enabled if result of the E Endian bit ARM can operate either in little
instruction yields a negative endian, or big endian. This bit is set
number. to 0 for little endian, or 1 for big
endian mode.
Z Zero Enabled if result of the T Thumb bit This bit is set if you are in Thumb
instruction yields a zero value. state and is disabled when you are in
ARM state.
C Carry Enabled if result of the M Mode bits These bits specify the current
instruction yields a value that privilege mode (USR, SVC, etc.).
requires a 33rd bit to be fully
represented.
V Overflow Enabled if result of the J Jazelle Third execution state that allows
instruction yields a value that some ARM processors to execute
cannot be represented in 32 bit Java bytecode in hardware.
two’s complement.
 7. Conditional Execution
Condition Code Meaning (for cmp or subs) Status of Flags
EQ Equal Z==1
NE Not Equal Z==0
GT Signed Greater Than (Z==0) && (N==V)
LT Signed Less Than N!=V
GE Signed Greater Than or Equal N==V
LE Signed Less Than or Equal (Z==1) || (N!=V)
CS or HS Unsigned Higher or Same (or Carry Set) C==1
CC or LO Unsigned Lower (or Carry Clear) C==0
MI Negative (or Minus) N==1
PL Positive (or Plus) N==0
AL Always executed –
NV Never executed –
VS Signed Overflow V==1
VC No signed Overflow V==0
HI Unsigned Higher (C==1) && (Z==0)
LS Unsigned Lower or same (C==0) || (Z==0)

Condition Code Opposite

Code Meaning Code Meaning
EQ Equal NE Not Equal
HS Unsigned higher or same LO Unsigned lower
(or CS) (or carry set) (or CC) (or carry clear)
MI Negative PL Positive or Zero
VS Signed Overflow VC No Signed Overflow
HI Unsigned Higher LS Unsigned Lower or Same
GE Signed Greater Than or Equal LT Signed Less Than
GT Signed Greater Than LE Signed Less Than or Equal
AL Always Executed There is no opposite to AL
(or omitted)

8. B / BX / BLX
There are three types of branching instructions:
▪ Branch (B)
o Simple jump to a function
▪ Branch link (BL)
o Saves (PC+4) in LR and jumps to function
▪ Branch exchange (BX) and Branch link exchange (BLX)
o Same as B/BL + exchange instruction set (ARM <-> Thumb)
o Needs a register as first operand: BX/BLX reg