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TMS2732 UV Erasable PROM
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118 viewsTMS2732 Texas Instruments
Datasheet
TMS2732 UV Erasable PROM
Texas Instruments
Uploaded by
RchrdStrkCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
/ 12
TMS2732A
32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
AUGUST 1963 REVISED FEBRUARY 1989,
Orgonization... 4096 x 8
Single §-V Power Supply
‘All Inputa/Outputs Fully TTL Compatible
Max Acoess/Min Cycle Times
‘TMS2732A-17 170 ne
TMS2732A-20 200 ne
TMS2732A-25 260 ne
‘TMS2732A-45 450 ns
© Low Standby Power Dissipation . .
188 mW (Maximum)
(© JEDEC Approved Pinout . . . Industry
Standard
‘© 21-V Power Supply Required for
Programming PIN NOMENCLATURE
‘© N-Channel Siicon-Gate Technology ‘ reg es emer
‘© PEP4 Version Available with 168 Hour Bp Output Enaba/21 V
Burn-in, and Extended Guaranteed Operating GND Ground
‘Temperature Range from - 10°C to 85°C. 01.08 Oupus
(TMS2732A-__.JP4) Voc __5¥ Power Suppiy
description
‘The TMS2732A is an ultraviolet ight-erasable, electrically programmable reed-only memory. Ithas 32,768
bits organized as 4,096 words of 8-bit length. The TMS2732A only requires a single §-volt power supply
with a tolerance of +5%.
‘The TMS2732A provides two output control ins: Output Enable (G/Vpp) and Chip Eneble (8. This feature
allows the G/Vpp control ine to eliminate bus contention in multbus microprocessor systems, The
‘TMS2732A has a power-down mode thet reduces maximum power dissipation from 657 mW to 188 mW
when the device is placed on standby.
‘This EPROM is supplied in a 24-pin dualinsine ceramic package and is designed for operation from 0°C
t0 70°C. The TMS2732A is also offered in the PEP4 version with an extended guaranteed operating
temperature renge of ~ 10°C to 85°C and 168 hour burn-in (TMS2732A-. JPA).
EPROMs/PROMs/EEPROMs
— coeee eee rereaeee ioe
Deere cers rm
Saaemveces a
TEXAS
SRiteneyteticmenteeest —— INSTRUGENTS TMS2732A
32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
—_————_—_——————————
operation
The six modes of operation for the TMS2732A are listed in the following table
WOOE
ramon |—— 6 Seam —
Duede | tomar | PM | vertcaton | ogrmming
€
+ vi
ira vu x! vi Mu iq vin
‘Nop 1 1 v
ea vu vt x av Ve 2
Vee 7 v
Vex By ev ev § sv 5
arom
won, o wz m2 . ° we
131017)
5 ‘S\NOUd33/SWOUd/SWOUdS
th = Vin or Vi.
raad/output disable
‘The two contro! pins (E and G/Vpp) must have low-level TTL signals in order to provide data at the outputs
Chip enable (E) should be used for device selection. Output enable (G/Vpp) should be used to gate deta to th
output pins.
power down
“The power-downmode reduces the maximum power dissipation from 657 mW to 188 mW. ATTLhighleve
signal applied to selects the power-down mode. In this mode, the outputs assume a high-impedance state
independent of G/Vpp.
erasure
‘The TMS2732A is erased by exposing the chip to shortwave ultraviolet light that has a wavelength of 253.
nanometers (2537 angstroms). The recommended minimum exposure dose (UV intensity x exposure time
is fifteen watt-seconds per square centimeter. The lamp should be located about 2.5 centimeters (1 inch
‘above the chip during erasure. After erasure, el bits are at high level. It shouldbenoted that normal ambien
Tight contains the correct wavelength for erasure. Therefore, when using the TMS2732A, the window shoul
bbe covered with an opaque label.
programming
Note that the application of a voltage in excess of 22 V to G/Vpp may damage the TMS2732A.
‘Aftor erasure (all bits in logic 1 statel, logic Os are programmed into the desired locations. A logic O can ont
bbe erased by ultraviolet light. in the program mode, G/Vppis taken from a TTL lowlevel to21 V and datatob
programmed are applied in parallel to output pine Q1-O8. The location to be programmedis addressed. Onc
data and addresses are stable, ¢ 10-millsecond TTL low-level pulse is applied to E. The maximum width ¢
‘this pulseis 11 milliseconds. The programmingpulsemustbe applied at each location thatis tobe programmer
Locations may be programmed in any order
‘Several TMS2732As can be programmed simultaneously by connecting them in parallel and following th
programming sequence previously described.
program Inhibit
“The programinhibitis useful when programming multiple TMS2732Asconnectedin parallel with itforentdat:
Program inhibitcan beimplemented by applyingaahigh-tevel signal to of the device thatisnottobe programme
program verity
‘After the EPROM has been programmed, the programmed bits should be verified. To verity bit states, G/Vp
and are set to ViL.
&
TEXAS,
INSTRUMENTS TMS2732A
32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
logic symbolt
a0
at
a2
As
aa
AS
aS
aT
ag
Ao
ant
5 EPROMs/PROMs/EEPROMs
vee
‘Ti symbol isin accordance with ANSIIEEE Std 81-1984 and 1EC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
ye range, Voc - -0.3Vt07V
we, VPP... -0.3-V to 22
Input voltage range (except program) -0.3 7 V
Output voltage range . - -03V07V
Operating free-sir temperature range eee eee 09°C to 70°C
Storage temperature range ..... cevvevttteneeeete cesses + “65°C to 150°C
*stressos beyond those Kisted under "Absolute Maximum Ratings” may cause permanent damage tothe device. This i ares cating
‘only, end functional operation of the device a thee or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section ofthis speciicetion a not implied. Exposure to abeolute-meximun fated conditions for extended periods may affect
eview rtd.
TEXAS, % 615
INSTRUMENTS ‘TMS2732A
32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
————————————————————
recommended operating conditions
PARAMETER w_NOM_MAX | UNIT
Wee Suppiy vohage (eee Note 1) 4756 625 | V
Vee Supply voltage (see Nowe 2) Vee. v
Viti _High-evel input voage. 2 Weert] v
Vit__Low level input vorg0 Tor oa |v
Ta Operating free-air tempers o 70_[ 6
NOTES: 1. Vcc must be applied before or atthe same time at Vpp and removed after or a the same time 88 Vep. The dovice must
not be ineerted into or removed from the board when Vp of Vcc spied
2. Vpp-cen be connected to Vcc directly (except in the program model. Voc supply currant inthis case would be loc + IPP.
Daring progremming, Vpp mrt be maintained at 21 V (0.5 V)
electrical characteristics over full ranges of recommended operating conditions
A SINOUd33/SINOUd/SINOUdS
‘PARAMETER "TEST CONOMONS, ain wax [UNIT
Vou _Highravel output voioge Ton = ~400 6A ze Vv
Vou Lowel output votege Tou = 21 mA eas |v
T___rpat current foskoge) Vi =OV@ S250 10] A
ig Outout current eakoge Vo = 04 V0 5250 S10] A,
1ect__VoC supply curent (standby) E at Vin Svep ot Vie 20 | ma,
toca Vcc supe eurent (active) E and Givpp at Va. 726 |_ma
capscttance, over recommended supply voltage range and operating free-air temperature range,
f= 1 MHz!
PARAMETER ‘TEST CONDITIONS Pre? max [- unr
‘Al except Vee s
E y-ov
1 tot cnectenee FS A a]
To Guiput capachance Vor ov oi |
‘These parameters are tasted on sample bass ony
‘Typical vales ae at Ta = 25°C and nominal voltages.
switching characteristics over recommended supply voltage range and operating free-air temperature
range
Tear [aa aaa a aaa rasa aza
Ler coNpmons [IN MAX |" MIN. See Wax | nwa | ONT
Teas Fa Tg soo gp. ep et ae | a8 [oe
[se Asse een vetoes vo] 200 | 260 | 480 [ne
Teng) Oveut oat une ron vey | ‘ee? rm a
‘¢_ Ovtput daable time frome 7 oe| 0 60] 0 as{ 0 190] re
‘au! evwnchewrecawnten | £20.
Satan near —] S20,
way chore ot actean Earp, SePawe! |g ° ° ° ”
sticovr one
NOTE 3: For allawitching charecersin and ting measurements, nut pulse lave are 0.40 Vand 2.4 V. Input end output reference
Iavels aro 0.8 V and 2.0 V.
‘Value calculated from 0.8 V deka to massured output lavel. This parameter is only sompled, not 100% tasted.
%
‘TEXAS,
INSTRUMENTS
616 MS2732A
32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
recommended conditions for programming, TA = 25°C (see Note 4)
Ta NOM _WAX_| ONT
Vg Spy wage 4758638 | Vv
Vee —_Suppty wage ee |v 2
Teil pe Tage sa ee =
Neos iee eee at oe S$
[aig] pune reson oo | me =
Tex Adcrse sony ie z = Wi
[evioy Bate sept z =
‘euiver) Gipp setup eee 2 = z
TMA) Ass old te © = 3
yo} Bete eld ae z = &
never) G/pp hold time 2 = =e
Twetea) GWep recovery re 2 = =
Pa) GWvep roe tne dung programming <0 ne 3
EHD Delay Ue, data vals ator E tow tL &
NOTE 4: When programming he TMS2732A, connect 0.1 pF capactor between G/Vpp and GND to suppress spurious vtage endian
‘ich may damoge the devin. =z
E
Programming characteristics, Ta = 25°C
PARAMETER TEST CONDMTIONS uN
Vig Hahevel et vgs v
Tig —towievel input woes v
“Yon Ho tovt ouput voage Teal) Tog = =a v
“Nou tow level cup voege (ery Tou = 21 ma v
Trout cuenta np Vi = Vi o Vig 7”
ep Supply cuore =v 8 = ver ma
1o¢ Supp eurent mA.
ig te aa aw —— =
Texas 617
INSTRUMENTS TMS2732A,
32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
209
AL = 7200
cee
UUNOER TEST
FIGURE 1. TYPICAL OUTPUT LOAD CIRCUIT
AC testing input/output wave forms
tM ZV 7 38
oo v- osv os,
A.C. testing inputs are driven at 2.4 V for logic 1 and 0.4 V for logic 0. Timing measurement:
‘at 2.0 V for logic 1 and 0.8 V for logic 0 for both inputs and outputs.
A SWOUd93/SIWOUd/SWOUds
ae
saan
“
1 be ia—od
toni)! va
wm | 1 | _
bo—tein —ol ‘aie:
Vou
vn
wo
oe
:
vu
eee:
NOTE 3: For all witching characteristics and timing messurements, input ples levels are 0.40 V and 2.4 V. Input and output ining
reference levels re 0.8 V and 2.0 V.
e18 TEXAS %
INSTRUMENTS TMS2732A
32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
program cycle timing
aoa
1.08
EPROMs/PROMs/EEPROMs
o
NOTE 3: For all aiching characteristics and timing mensurements, input pulse levels ae 0.40 V and 2.4 V. Input end outputting =m
reference levels re 0.8 V and 2.0 V.
TEXAS, % e19
INSTRUMENTS @™@ 8961725 0077767 T
TEXAS INSTR (ASIC/MEMORY)
ese D
Designing and Manufacturing
Surface Mount Assemblies
Elizabeth Gunther, Charles Hutchins, and Paul Peterson
‘The competitive nature of the semiconductor industry has
driven vendors to minimize the sizeof electronic components,
so that more functions can be achieved in a given volume.
Tn addition, improved electrical performance, deteased mass,
and the potential for lower system cost are all by-products
‘of compacted packaging and circuitry which hold interest to
‘component manufacturers and users alike,
Surface Mount Technology (SMT) offers an excellent
method of reducing component size, A typical memory ar-
ray can be reduced to 50 percent ofits original PWB size
with single-sided mounting, and 25 to 30 percent with double-
sided mounting. Logic designs cannot achieve the same
dramatic reduction, but decreases up to 40 to 60 percent can
bbe achieved for single-sided and déuble-sided assemblies
respectively.
‘The key design and manufacturing process issues must
be understood in order to fully reap the benefits of Surface
‘Mount Technology. This article gives a general overview of
the key aspects of design, process, and manufacturing of sur-
ace mounted assemblies, and offers surfice mount as an op-
portunity to lower « system's cost without sacrificing
relibilty,
‘Components
Most surface mount components are atleast one-third
the size of the comparable through-hole mounted device (Fig-
ure 1), The 68-pln chip carer is approxmiately one quate
inc, while the 6-pin DIP is approximately three square in-
‘ches, The 20-pin chip carrer is slighty larger than OL square
inch, while the 20-pin DIP is 0,3 square inch. Similarly, other
TC packages are reduced to approximately one-ticd the size
of comparable lead count package. The passive components
‘ccupy approximately one-tenth the board are, and this is
7-90-20
why they have been used in most small consumer products
bull inthe last couple of years.
‘There were many references in the recent past to prob-
Jems with component valability, cost, and standardization,
‘This area of SMT has probably received more attention than
any other. Several recent magazine articles now state that
significantly more components (particularly actives) are now
available and that cost parity has been achleved on most of|
‘them, The effort by various industry committees on stan-
dardzation has also been effective.
“Ths, although more needs tobe socomplished in these
areas, 2 designer can begin a project with confidence that
there will be no insurmountable barriers inthis area. There
are several consultants and subcontract assembly companies
to assist inthis effort. I is strongly recommended that all
new designs utilize some form of SMT, particularly when
spaco is an important consideration,
Process
‘The process to manufacture a surfuce mount assembly
(SMA) is very simple. It consists of four basic steps, as shown
in Figure 2. Fist, the solder paste is screened on the PWB,
‘Then the component is placed on the board, with due care
to get it positioned correctly. Typical geometries require
placement accuracy of less than plus/minus 4 mils, Next the
solder is reflowed with either a vapor phase or infrared
system, Finally, the assembly is cleaned and is now ready
{or test. This process, although simple in concept, relies on
‘board and component planarity and solderabilty. These are
‘easily achievable withthe chip carriers and memory modules
we will discus later.
‘Toms Instruments has installed a Surfice Mount
‘Technology Center at its plant in Houston, Texas, At this cen-
tet, we havea complete and flexible engineering line to asi.
‘our customers in converting to Surface Mount Technology.
The engineering lie is equipped witha sereenprint-
¢r, pick and place system, vapor phase reflow, and clean-up
station that will easily handle FWBs upto 9" X 10", Larger
boards up to 14° X 16* can be processed with some addi-
tional care, TT uses this engineering line to produce its pro-
totype and demo boards It i also available to any of TT's
customers, fee of chage, for use in building test or prototype
boards,
“The effectiveness of the assembly process can be
characterized by ihe number of unacceptable solder joints
formed during the process. Unacceptable joints are defined
by their electrical and mechanical (strength and reliblity)
characteristics. The major problem is open solder joints,
followed by bridging and misregistration.
93
|
=” uopeuuoyuy suopeoyddy
WM 4961725 0077766 1
TEXAS INSTR (ASIC/MEMORY)
1. Applying solder past evenly and in the
proper amount Is extremely important.
83, Roflow tho entra aasernly with tight
‘erporatur contol to evenly solder the
WB and components together
4. Tha foal step le cleaning the assembly.
MI percent ce et nt nt
first defects detected after soldering. At Texas Instruments,
10 PPM or less is the desirable defect lovel. Several factors
that contribute to open solder joins were identified during
production start-up. Lead tip planarity of the J-leaded plastic
chip carriers isthe most important factor in obtaining ac-
ceptable process yields. Lead position, lead finish, solder
past conpston, and FW rlenby fst ps yl
as well,
Experiments in which lead tip planarity was confined
to specific limits between 1 to 7 mils indicate that a 2 mit
planarity requirement prodices acceptable results with the
process currently in use. Little gain in yeld was noted at a
1 mil planarity requirement.
‘Another interesting result showed that iver in the proc-
es, either asa lead finish or inthe solder paste, improves
Yields significantly. One explanation may have to do withthe
‘dynamics ofthe solder during the reflow process as they are
affected by the diffrent surface forees acting inthe silver
and non-silver process.
a4
T-90-20
ese D
2. Componsnta should immediatoly be plac-
fd on the PWB after the soldr printing
prosees. Accuracy Is Important.
‘The design of the PWB, in addition to providing the
component interconnections, will provide the proper amount
and correct placement of solder paste fora strong fillet for-
mation, The wave soldering process, by comparison, provides
a semi-infinite amount of solder, whereas the SMT process
will provide only a predetermined amount. Thus, the com-
ponent connection pad must be correctly placed and be of
the proper size.
Farther, consideration must be given for inspection,
testing, and rework, The deasity achievable can lead to severe
problems at these points if understanding and due care are
not exercised in the design. The project team should inelude
members from manufacturing, testing, QA, and purchasing,
‘in addition tothe design engineers, from the start. The design
and processing of test boards is strongly recommended to pro
vide experience and direction for the major projec. EE
: Mi 8961725 00777b9 3 a
‘Avery practical et of design guideline is given in Fig-
tue 3, These have been used on a number of SMT designs
and have given good results. With proper manufacturing
techniques as described later, a high yield canbe achieved.
‘Component spacings should be approximataly equal tothe
height ofthe tallest component. Ths allows an angle of 45
degrees for visual inspection of test probes.
Figure 4 shows the standard footprint forall Small
‘Outline ($0) packages, The larger and more important filet
‘ofan SO package is onthe inside of the gull-wng lead. The
solder pad, or land, should therefore be designed to exiend
+ Solder Maske
Round or Square Ende (Opt)
4
070"
) |
J-0.026"
T-90-20
slightly under the body of the package in order to optimize
this fillet. From Table 1 we can see all packages have 50 mil
center wih 25 mil spacings between lands. This allows the
designer enough space to put traces between pads, and also
reduces the occurrence of solder bridging of adjacent ands,
‘Table 1 also summarizes the and Yeagts and
fd provide a mecanially and eletialy wound ele
‘Joint,
878 MIL Min, 10/10 MIL Typ.
25 = 6M x 70+ 10MM.
TEXAS
INSTR (ASIC/MEMORY) 25E D
UU
igure 4, Standard SOIC Footprint . TEXAS
E Uopeuuojy suopeonddy
Mi 8961725 0077770 T
‘Table 1. SOIC Footprint Dimensions
ieee Atte eee
Tet 41048 PLce 4164 DP
Life Test 12642 o
SECIS AH O17 0.37 54/1000 Hours
‘utoieve 0.17 0,86 %/240 Hoss
Tie-66160 05214411000 Cyan
vic on28 00 0.02000 cytes
Terminale
a 478280 08002880
4 828280 080.028 080
10 378250080028 060
2047643007006 080
2 B78 430070028080
INSTR (ASIC/MEMORY) 2@5E D
‘Derated to 88°C Assuming 0.5EV Activation Eneray
Figure § Fallure Rate Comparison
4N64A PLCC VS DIP
‘Manufacturing
‘The SMT manufacturing area must have the following
"The criteria for choosing the sbowe is determined main-
ly by the sizes) and quantity of PWBs per month, the gross
‘number of components per PWB, and the mumber of diferent
‘components per PWB.
‘The size of te largest PWB is an important criterion
{nthe choice of al ofthe major items, The printer, pick and
place, reflow, and clean-up must all be able to hance it with
no difficulty or process nonuniformity, The number and size
‘ofthe various PWBs that may be produced will secondarily
‘be considered for ease of set up and changeover in the print-
ce and pick and place, The pick and place machine(s) will
96
T-90-20
probably be the most expensive item inthe lit above and
therefore, should get the moet attention,
‘The gross number of components and PWBs will pro-
‘vide data for choosing the pick and place. Component per
hour placement speed should be checked in actual operation,
1s the interrelationship muy affect timate speed. The mumbet
of different components per board will determine how many
feeders and what types of feeders will be required, This is
a very Key issue, e5 well asthe accuracy of placement.
Reflow
‘The solder reflow is easly achieved with any of the
‘commercially svalable equipment. Subte differences be-
‘tween vapor phase, either batch or in-line, and infrared are
overshadowed by the’ choice of solder paste and the
issue. A batch vapor phase i extremely
flexible for different sizes of boards with different compo-
‘ent counts. The in-line vapor phase isa good choice for a
more automated processing line with standard or similar sized
boards, The infrared has the advantage of being less expen
sive to operate, but requires more alteration to setup the timse-
temperature profile for a different size PWB, This would be
12 minimal problem on a manufacturing line building high
‘volumes of the same board.
Clean-up
‘The most popular lux for SMT is the mildly activated
rosin flx (RMA). This was developed inte days of vacuum
tube assembly when clean-up was next to impossible, It is
noncorrosive but provides sufficient fluxing action for good
quality components and PWBs, Thus it is te prefered choice
for SMAs with soll spacings under most passives and.
SOICS, where complete cleaning is dificult. A mild solvent,
such as Freon TMS, is generally suictent to achieve a good
visual cleanup, and there are several systems available that
provide hot vapor, spray, or ultrasonic de-luxing.
Reliability
‘With the smaller surface mount packages, there is some
concern about component reliability, Teas Instruments ad-