Microelectronics Reliability 119 (2021) 114073

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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Impact of interface trap charges on electrical performance characteristics of

a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/
Al2O3 laterally stacked gate oxide
Manas Ranjan Tripathy, A. Samad, Ashish Kumar Singh, Prince Kumar Singh, Kamalaksha Baral,
Ashwini Kumar Mishra, Satyabrata Jit *
Department of Electronics Engineering, IIT BHU, Varanasi 221005, India

A R T I C L E I N F O A B S T R A C T

Keywords: This work reports the impact of interface trap charges (ITCs) on the electrical performance characteristics of a
Vertical TFET source pocket engineered (SPE) Ge/Si heterojunction (HJ) vertical TFET (V-TFET) with an HfO2/Al2O3 laterally
Ge/Si heterojunction stacked heterogeneous gate oxide (LSHGO) structure. SILVACO ATLAS™ 3-D TCAD tool has been used to
Source pocket
compare various electrical performance parameters which includes DC parameters (i.e. ION, IOFF, ION/IOFF and
Heterogeneous gate oxide
Sub-threshold swing
subthreshold swing), RF figures of merit (i.e. transconductance, output conductance, cut-off frequency, the
Interface trap charges maximum frequency of oscillation, transit time, gain bandwidth product, transconductance generation factor
(device efficiency) and transconductance frequency product) and linearity figures of merit (i.e. gm2, gm3, Third
order voltage intercept point (VIP3), third intercept input power (IIP3), third order intermodulation distortion
power (IDM3), 1-dB compression point and zero crossover point (ZCP)) of the proposed Ge/Si SPE-HJ-LSHGO-V-
TFET with their corresponding values of SPE-HJ-V-TFET with only Al2O3 as the gate oxide for both donor (+ve)
and acceptor (− ve) interface trap charges at the gate oxide/channel interface. The reported study shows that the
proposed HfO2/Al2O3 based SPE-HJ-LSHGO-V-TFET device is more immune to ITCs than the SPE-HJ-V-TFET
device with only Al2O3 as the gate oxide.

1. Introduction TFET structure [4,12–17]. The V-TFETs are assumed to provide higher
device density in the Integrated Circuits (ICs) with better immunity to
The inherently low subthreshold current and subthreshold swing charge trapping and leakage current related issues [13] than the con­
(SS) of TFET have made it an important device for low-power VLSI ap­ ventional TFETs. The use of sandwiched thin highly doped region also
plications [1–3]. However, very low ON-current (ION) is considered to be known as source pocket in between source and channel improves the
the major drawback of the TFET [1]. Several structural modifications device-level parameters of the TFETs [18]. In place of SiO2, the use of
have been reported to improve ION of the TFET. The use of a source- vertically stacked SiO2/High-k structure is reported to boost ION of the
channel heterojunction [4–8] and inclusion of a heavily doped source TFETs [19]. High-k/low-k based laterally stacked heterogeneous gate
pocket sandwiched between the highly doped source region and oxide (LSHGO) with the high-k gate oxide at the source side is also re­
intrinsic channel region [9–10] are some of the dominant techniques to ported to improve the ON-current while low-k oxide at the drain side
enhance the ON-current of the TFETs. In addition, the use of heteroge­ reduces the ambipolar conduction in the device [11,20,21].
neous gate oxide structure in place of the only SiO2 as gate oxide [11] is Interface trap charges (ITCs) are created by different process and
another effective technique which has been adopted for further stress induced phenomena during various stages of device fabrication
improvement in ION of the TFETs. Ge based source in the Si channel is processes [21–27]. ITCs primarily exist at the channel-gate oxide
used to form heterojunction in TFET which has been widely reported to interface energy level lying in the bandgap energy of channel of the
enhance the tunnelling current (ION) by reducing the tunnelling barrier TFETs. These charges act like trap center which affect the transport of
width at the Ge/Si interface [12,13]. The vertical TFET (V-TFET) is re­ carriers in the channel having an existence of both donor and acceptor
ported to be easier for fabrication as compared to conventional lateral type charges. Donor type ITCs can be positive if the trap center is empty.

* Corresponding author.
E-mail address: sjit.ece@iitbhu.ac.in (S. Jit).

https://doi.org/10.1016/j.microrel.2021.114073
Received 23 June 2020; Received in revised form 28 January 2021; Accepted 18 February 2021
Available online 8 March 2021
0026-2714/© 2021 Elsevier Ltd. All rights reserved.
M.R. Tripathy et al. Microelectronics Reliability 119 (2021) 114073

Fig. 1. Source pocket engineering-based Ge/Si heterojunction vertical TFET structure (a) without heterogeneous gate oxide (SPE-HJ-V-TFET), and (b) with het­
erogeneous gate oxide (SPE-HJ-LSHGO-V-TFET); cross-sectional view of (c) SPE-HJ-V-TFET, and (d) SPE-HJ-LSHGO-V-TFET.

Similarly, acceptor type ITCs can be negative if the trap center is filled gate oxide interface near the tunnelling junction in the TFET. The hot
with an electron. In general, donor type traps are mostly present nearer carrier effects and positive bias temperature instability (PBTI) may also
to the valence band whereas the acceptor type traps are present nearer generate the ITCs in the conventional TFET [27]. The fabrication pro­
the conduction band of the channel material. Since a high electric field cessing step like the plasma etching may damage the gate dielectric and
at the source-channel junction is the mandatory requirement for the channel-oxide interface [10] which may also be one of the factors
lowering of the tunnelling barrier width to enhance the drain current behind the origin of the ITCs. These ITCs severely affect the drain cur­
(ION) in the TFETs, there is a possibility of generation of ITCs at channel/ rent and other performance parameters of the TFETs [21–27]. To
overcome all these hurdles faced in TFET, LSHGO TFETs are widely used
among the researchers which are more immune to ITCs [21]. Source

Table I
Various structural specification parameters of the presented Vertical TFETs.
Parameters SPE-HJ-V-TEFT SPE-HJ-LSHGO-V-TEFT

Source doping (NA) 5 × 1019 cm− 3

5 × 1019 cm− 3

Pocket doping (ND) 1 × 1019 cm− 3

1 × 1019 cm− 3

Channel doping (NA) 1 × 1016 cm− 3

1 × 1016 cm− 3

Drain doping (ND) 5 × 1018 cm− 3

5 × 1018 cm− 3

Gate oxide thickness (tox) 2 nm 2 nm

Channel thickness (tSi) 10 nm 10 nm
Gate dielectric constant of Al2O3 (ԑ) 9.3 9.3
Gate dielectric constant of HfO2 (ԑ) – 25
Gate work function (Φm) 4.2 eV 4.2 eV
Gate length (LG) 25 nm 25 nm
Source length (LS) 20 nm 20 nm
Pocket length (Lp) 5 nm 5 nm
Drain length (LD) 20 nm 20 nm
Tunnel mass of h+ in Ge (mhtGe) 0.084mo 0.084mo
Fig. 2. Comparison of experimental and simulation results-based transfer Tunnel mass of h+ in Si (mhtSi) 0.24mo 0.24mo
Tunnel mass of e- in Ge (metGe) 0.092mo 0.092mo
characteristics of a Ge/Si vertical TFET [15] for the validation of the models
Tunnel mass of e- in Si (metSi) 0.20mo 0.20mo
used in the TCAD tool.

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M.R. Tripathy et al. Microelectronics Reliability 119 (2021) 114073

pocket engineered structure is considered to be more immune against (to include non-radiative recombination processes), and the Fermi-Dirac
the ITCs compared to conventional TFET structures [18,28]. However, statistics (for carrier distribution in various regions of the device).
there is no such investigation has been done on the effects of ITCs on the Uniform doping concentrations in various regions of the device has been
performances of source-pocket engineered (SPE) heterojunction (HJ) V- assumed. A donor doping concentration (ND) of 5 × 1018cm− 3 is
TFET with an HfO2/Al2O3 based LSHGO structure. The present manu­ considered for Si-drain region to reduce the ambipolar effect in the TFET
script thus investigates for the first time the effects of ITCs on the elec­ [30]. In the case of SPE-HJ-V-TFET, a gate oxide Al2O3 [16] of 2 nm
trical performance characteristics of a SPE Ge/Si HJ V-TFET with an thickness with permittivity of 9.3 has been considered to improve ON-
HfO2/Al2O3 LSHGO structure. The device performance parameters have current whereas in case of SPE-HJ-LSHGO-V-TFET, along with Al2O3
been compared with those of SPE Ge/Si HJ V-TFET with only Al2O3 as a another high-k HfO2 of 2 nm thickness each are laterally stacked to form
gate oxide. Both positive and negative ITCs have been considered in the the heterogeneous gate oxide structure [11,20,21]. The Al2O3 (low-k)
study. The DC, RF and linearity figures of merit of both the TFETs have gate dielectric is placed near the drain side while the HfO2 (high-k) is
been compared in the presence of the ITCs using SILVACO ATLAS™ 3-D placed near to the source side in a cascade manner in the SPE-HJ-
TCAD tool [29]. LSHGO-V-TFET. The low-k (Al2O3) at the drain end is used to reduce
the ambipolar conduction (by reducing the electric field at the end)
2. Device structural description with specification and whereas the high-k (HfO2) is used to increase the field at the source end
simulation methodology for higher drive current (ON-current) in the TFETs [11,20,21]. Differ­
ence between lattice constant and thermal co-efficient of Ge and Si may
Fig. 1(a)–(b) shows presented TFETs for TCAD simulation study i.e. lead to the creation of some defects or trap (bulk trap) center at the Ge/
source pocket engineering-based Ge/Si heterojunction vertical TFET Si interface. To include the effects of such traps on the device perfor­
structure without heterogeneous gate oxide (SPE-HJ-V-TFET) and mance, we have also included the non-local trap assisted models TAT.
source pocket engineering-based Ge/Si heterojunction vertical TFET NLDEPTH and TAT.RELEI in the TCAD simulation tool. Reliability study
structure with heterogeneous gate oxide (SPE-HJ-LSHGO-V-TFET), of the proposed TFET has been investigated in the presence of interface
respectively. Their cross-sectional view is given in Fig. 1(c) and (d) trap charges where both positive (+ve) localized charges (donor) and
respectively. For TCAD simulation, we have used non-local band-to- negative (− ve) localized charges (acceptor) are introduced in the oxide-
band tunnelling (BTBT) model (to include local variation in the energy channel interface having density ± 1 × 1012 cm− 2 based on some re­
band for better accuracy); Shockley-Read-Hall model (to include the ported experimental and simulation results [31,32]. For the proposed
carrier generation-recombination phenomenon); band gap-narrowing TFET, interface trap charges effect are considered for 25 nm from source
model (to incorporate the heavy doping effects on the bandgap of end. The ITCs are assumed to be distributed uniformly at the channel/
source, drain and pocket regions); field-dependent mobility model (to oxide interface in the present study [23]. The energy level of acceptor
consider field dependent carrier velocity); Auger recombination model ITCs is kept at 0.3 eV above the Si (channel) mid gap energy and the

Fig. 3. Plot of (a) electric field pattern in ON-State of SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET, and (b) energy band distribution in OFF-State and ON-State for
SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET in presence of ITCs.

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M.R. Tripathy et al. Microelectronics Reliability 119 (2021) 114073

energy level of donor ITCs is kept at 0.3 eV below the Si (channel) mid simulation of the presented TFETs using the SILVACO ATLAS™ 3-D
gap energy as reported by Huang et al. [23]. TCAD simulation tool are shown in Table I.
For the validation of the models used in SILVACO ATLAS™ 3-D
TCAD tool, the TCAD simulation result for fabricated heterojunction 3. Results and discussion
V-TFET structure of ref. [15] have been compared with experimental
data in Fig. 2. A reasonably good matching between the two results 3.1. Impact of ITCs on DC performances
confirms the validity of various models considered in the TCAD tool.
Since a high electric field at the source/channel junction is essential to Fig. 3(a) depicts the electric field for the SPE-HJ-V-TFET and SPE-HJ-
enhance the drain current, the doping levels of the source and pocket LSHGO-V-TFET. Due to higher (lower) band bending in the presence of
regions have been optimized to achieve the optimum performance in the +ve (− ve) ITCs, the electric field is getting enhanced (reduced). We can
proposed structure. Various optimized device parameters used for observe from the same figure that the electric field in SPE-HJ-LSHGO-V-

Fig. 4. Plot of (a) transfer characteristics (linear scale and logarithm scale), and (b) drain characteristics for SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET in presence
of ITCs.

Fig. 5. Plot of (a) subthreshold slope (SS), and (b) ION/IOFF in presence ITCs for SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET.

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M.R. Tripathy et al. Microelectronics Reliability 119 (2021) 114073

TFET is less prone to ITCs compared to SPE-HJ-V-TFET. The reason for SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET [21]. The reason for the
the same has been discussed in the energy band distribution in Fig. 3 (b) same can be attributed to the higher electric field for the +ve ITCs than
which shows the influence of +ve ITCs (donor charges), − ve ITCs -ve ITCs which has been elaborated in the electric field discussion for the
(acceptor charges) on energy band diagrams of SPE-HJ-V-TFET and SPE- presented TFETs. Clear observation can be made from the inset image of
HJ-LSHGO-V-TFET in OFF-State and ON-State. In the process of simu­ Fig. 3(b) that the SPE-HJ-LSHGO-V-TFET is less prone to variation in
lation, in addition to +ve ITCs (donor charges) and − ve ITCs (acceptor energy band diagram in presence of ITCs compared to SPE-HJ-V-TFET in
charges), we have also included zero ITCs and for our conveniences and presence of ITCs. The reason for the same can be attributed to less
we have named it as no interface charges. In OFF-State, zero gate voltage variation in flat band voltage in presence of ITCs due to the use of high-k
is applied across the gate to the source terminal. In this state, the source dielectric nearer to source end. Mathematically it can be explained from
region valence band and the channel region conduction band are not Eq. (1) given below [21]:
properly aligned as shown in Fig. 3(b). Therefore, electrons cannot be
qNf
transported through the source-channel junction. However, in ON-State ΔVfb = (1)
Cox
when a positive gate to source voltage is applied at gate terminal, a
tunnelling path is created because of conduction band lowering of the where ΔVfb is the change in flat band voltage, q is the electron charge, Nf
channel. That leads to a proper alignment between the source region is the ITCs density, Cox is the gate oxide capacitance. As Cox is higher for
valence band and the channel region conduction band. This in turns heterogeneous gate oxide based SPE-HJ-LSHGO-V-TFET, the variation
makes electrons from the source to tunnel to the channel as shown in in a flat band voltage will be less. This insignificant variation in flat band
Fig. 3(b). The band bending is higher (lower) for +ve (− ve) ITCs for both voltage gives rise to negligible variation in energy band diagram for the

Table II
DC performance parameters of SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET.
Devices Parameters

ION (A) IOFF (A) ION/IOFF Avg. SS (mV/dec)

SPE-HJ-LSHGO-V-TFET +ve 1.394E-3 5.64E-15 2.471E11 18.5

No 1.384E-3 5.63E-15 2.458E11 19.8
-ve 1.382E-3 5.63E-15 2.454E11 21.2
SPE-HJ-V-TFET +ve 1.132E-3 5.57E-15 2.03E11 22.49
No 1.074E-3 5.53E-15 1.942E11 25.4
-ve 1.009E-3 5.50E-15 1.834E11 27.1

Fig. 6. Plot of (a) transconductance characteristics (gm), and (b) output conductance characteristics (gd) in presence of ITCs for SPE-HJ-V-TFET and SPE-HJ-LSHGO-
V-TFET.

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M.R. Tripathy et al. Microelectronics Reliability 119 (2021) 114073

Fig. 7. Plot of (a) fT, and (b) fmax in presence of ITCs for SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET.

SPE-HJ-LSHGO-V-TFET. bandwidth product (GBP), transconductance generation factor (TGF)

The ITCs effect on transfer characteristics and drain characteristics of and transconductance frequency product (TFP) of SPE-HJ-V-TFET and
SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET has been elucidated in SPE-HJ-LSHGO-V-TFET in the presence of ITCs. Fig. 6(a) demonstrates
Fig. 4(a) and (b) respectively. To obtain the transfer characteristics (both the transconductance characteristics (gm) of SPE-HJ-V-TFET and SPE-
linear and log scale) shown in Fig. 4(a), a constant drain voltage (VDS) of HJ-LSHGO-V-TFET whereas the output conductance characteristics
0.5 V is applied along with the gate voltage (VGS) is varied from 0 V to 1 (gd) of the two TFETs are shown in Fig. 6(b). It can be illustrated from
V. On the other hand, drain characteristics shown in Fig. 4(b) is obtained Fig. 6 (a) that gm of SPE-HJ-LSHGO-V-TFET is significantly higher than
by applying a constant VGS of 0.5 V with VDS varying from 0 V to 1 V. The SPE-HJ-V-TFET with the highest value of 3.8 mS/μm with +ve ITCs. For
band to band tunnelling of carrier increases (decreases) due to presence better conversion of gate voltage (input voltage) to drain current (output
of +ve (− ve) interface trap charges. Subsequently, ON-current increases current), it is generally required to have a higher value of gm. Tunnelling
(decreases) of the TFETs presented for study. From Fig. 4(a), it is evident current (ON-current) increases (decreases) with +ve ITCs (− ve ITCs)
that transfer characteristics show less variation for SPE-HJ-LSHGO-V- which in turn increases (decreases) gm. Clear observation can be made
TFET compared to SPE-HJ-V-TFET in presence of ITCs. Fig. 4(b) shows from the Fig. 6(a) that the gm is less influenced in presence of ITCs in the
a similar kind of behavior for drain characteristics like transfer char­ proposed SPE-HJ-LSHGO-V-TFET than SPE-HJ-V-TFET. So it can be
acteristics for both the presented TFETs. The heterogeneous gate oxide- concluded that gm is dependent on polarity and density of ITCs. Fig. 6(b)
based SPE-HJ-LSHGO-V-TFET is more immune to ITCs compared to shows the comparative plot of output conductance characteristics (gd) of
homogeneous gate oxide-based SPE-HJ-V-TFET. SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET. SPE-HJ-LSHGO-V-TFET
Fig. 5(a)–(b) shows the variation of average sub-threshold swing (SS) has much higher value of gd (1.07 mS/μm) than that of the SPE-HJ-V-
and ION/IOFF in presence of interface trap charges. The information TFET (0.42 mS/μm) in presence of +ve ITCs. The reason behind the
which can be gathered from this figure is that the performance of SPE- same can be attributed to the presence of +ve (− ve) ITCs for which
HJ-LSHGO-V-TFET is not much hampered compared to SPE-HJ-V- output current increases (decreases) so as output conductance which is
TFET counterpart in presence of ITCs. The electrical parameters of the elucidated in Fig. 6(b). The variation of gd in presence of ITCs is
presented TFETs have been listed in Table II. It can be observed from comparatively lower in case of heterogeneous gate dielectric based SPE-
Table II that the electrical parameters like ON-current, OFF-state current HJ-LSHGO-V-TFET compared to homogeneous gate dielectric based
ION/IOFF, and average SS of SPE-HJ-LSHGO-V-TFET are less affected by SPE-HJ-V- TFET.
ITCs compared to SPE-HJ-V-TFET. The fT and fmax are key RF parameters for studying the RF perfor­
mance of any TFET. fT is known as unit gain frequency and can be
formulated as [9,14]:
3.2. Impact of ITCs on RF appearances
gm
fT = ( ) (2)
This sub-section compares various RF parameters like trans­ 2π Cgd + Cgs
conductance (gm), output conductance (gd), cut-off frequency (fT),
It is already shown in Fig. 6 that gm is strongly dependent on the
maximum frequency of oscillation (fmax), transit time (τ), gain

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M.R. Tripathy et al. Microelectronics Reliability 119 (2021) 114073

Fig. 8. Plot of (a) transit time (τ), and (b) GBP for SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET in presence of ITCs.

polarity and density of the ITCs. Thus, Eq. (2) clearly shown that fT is ITCs, the transit time is also affected by the ITCs. Transit time decreases
strongly affected by both the polarity and density of the ITCs. To (increases) in presence of +ve (− ve) ITCs. The device SPE-HJ-LSHGO-V-
examine the dependence of the fT on the ITCs, the plot of fT for SPE-HJ- TFET is showing insignificant variation in τ in presence of both +ve and
LSHGO-V-TFET and SPE-HJ-V-TFET are compared in Fig. 7(a) in pres­ –ve ITCs compared to SPE-HJ-V-TFET.
ence of ITCs. It can be seen from the Fig. 7(a) that the value of fT in­ GBP, another essential RF performance parameter calculated for a
creases (decreases) in presence of +ve (− ve) ITCs. The SPE-HJ-LSHGO- DC gain of 10, conveys the region of operation where the gain is constant
V-TFET is found to have a higher value of fT with more immunity to ITCs for any MOS devices and can be expressed as [9,14]:
compared to SPE-HJ-V-TFET. g
The fmax is the frequency where unilateral power gain becomes unity GBP = ( m ) (5)
2π 10Cgd
and can be formulated as [9,14]:
√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ Fig. 8(b) shows the GBP plot for SPE-HJ-LSHGO-V-TFET and SPE-HJ-
|Y21 − Y12 |2 V-TFET. Since gm is ITCs dependent as discussed in Fig. 6, GBP is also
fmax = f0 (3)
4[Re(Y11 )Re(Y22 ) − Re(Y12 )Re(Y21 ) ] dependent on the polarity and density of the ITCs. The value of GBP
increases (decreases) for +ve (− ve) ITCs. It is clear from the afore­
Here Yij{i, j = 1, 2}are the Y-parameters which got extracted at input mentioned figure that ITCs influence on GBP is less in SPE-HJ-LSHGO-V-
frequency f0 of 1 MHz for the presented TFETs. fmax has been evaluated TFET than SPE-HJ-V-TFET.
with the values of extracted Y parameter using Eq. (3). Fig. 7(b) shows The TGF is the conversion ability of any TFET where the output
that fmax is having a higher value in SPE-HJ-LSHGO-V-TFET compared to current is converted into gm and it makes a trade-off between speed of
SPE-HJ-V-TFET. The fmax in presence of +ve (donor) ITCs increases operation and power. The TGF is formulated as [14]:
whereas fmax decreases for –ve (acceptor) ITCs for the presented TFETs.
The transit time (τ) and GBP are also considered as important ap­ gm
TGF = (6)
pearances for investigating RF performance characteristics of any TFET. Ids
Transit time is the time taken for the charge carriers to make a transition Fig. 9(a) shows TGF as a function of VGS for both the TFETs under­
from source end to drain end of a MOS device. It is formulated as [9,14]: study with the presence of ITCs. The ITCs dependence of gm discussed in
1 Fig. 6 shows that TGF is also dependent on the polarity and density of the
τ= (4) ITCs. It is noted that SPE-HJ-LSHGO-V-TFET has much higher TGF with
2πfT
less variation in presence of +ve and –ve ITCs than that of the SPE-HJ-V-
It is desired to have the transit time as low as possible for faster TFET. In presence of +ve (− ve) ITCs, the value of TGF increases
switching performance. Fig. 8(a) compares the transit time plots for SPE- (decreases).
HJ-V-TFET and SPE-HJ-LSHGO-V-TFET. Since the cut off frequency (fT) TFP is also a key RF performance parameter of the MOS transistor. It
is very much dependent on the density, energy, and distribution of the is essentially the product of TGF and fT and can be formulated as [9,14]:

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M.R. Tripathy et al. Microelectronics Reliability 119 (2021) 114073

Fig. 9. Plot of (a) TGF and (b) TFP for SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET in presence of ITCs.

Fig. 10. Plot of (a) gm2 and gm3 and (b) VIP3 for SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET in presence of ITCs.
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M.R. Tripathy et al. Microelectronics Reliability 119 (2021) 114073

Fig. 11. Plot of (a) IIP3 and (b) IDM3 for SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET in presence of ITCs.

( )
gm of SPE-HJ-LSHGO-V-TFET and SPE-HJ-V-TFET with the presence of
TFP = × fT (7)
Ids ITCs. These parameters can be defined as [21,33,34]:

Trade-off between the bandwidth and power for high frequency ∂n ID

gmn = (8)
operation of any MOS device is represented by TFP. It increases linearly ∂V n GS
with gm and higher value of TFP is necessary for high-speed circuit √̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
( )̅
design. Since ITCs is dependent on gm and cut-off frequency discussed in gm1
Figs. 6 and 7, TFP is also dependent on the polarity and density of the VIP3 = 24 × (9)
gm3
ITCs as shown in Fig. 9(b). It can be illustrated from Fig. 9(b) that SPE-
HJ-LSHGO-V-TFET has higher TFP due to its higher fT and higher TGF 2
(
gm1
)
and shows little variation in presence of +ve and –ve ITCs than that of IIP3 = × (10)
3 gm3 × Rs
SPE-HJ-V-TFET. TFP also increases (decreases) like TGF for +ve (− ve)
ITCs. From all these discussions we can find that RF parameters show [
9
]2
more immunity in terms of less variation towards ITCs in the SPE-HJ- IMD3 = × (VIP3)3 × gm 3 × Rs (11)
2
LSHGO-V-TFET than the SPE-HJ-V-TFET. This is mainly because all
these RF parameters more or less dependent on transconductance (gm) √̅̅̅̅̅̅̅
gm 1
and gm depends on drain current and electric field. As both the electric 1 − dB CP = 0.22 (12)
gm2
field and gm shows less variation towards ITCs in SPE-HJ-LSHGO-V-
TFET, correspondingly we are finding less variation in all the RF pa­ Transconductance (gm1) is the conversion ability of any MOS devices
rameters towards ITCs for the proposed SPE-HJ-LSHGO-V-TFET than where gate voltage is converted into drain current, whereas gm2 and gm3
SPE-HJ-V-TFET. are the 2nd and 3rd order derivative concerning VGS. To have greater
linearity, these parameters are desired to be as high as possible. Fig. 10
(a) shows the plot of gm2 and gm3 for SPE-HJ-LSHGO-V-TFET than SPE-
3.3. Impact of ITCs on linearity figures of merits (FOMs)
HJ-V-TFET in presence of +ve (donor) and –ve (acceptor) ITCs. It has
been shown in the aforesaid figure that the values of these parameters
Modern communication system requires high speed with minimum
increase (decrease) in presence of +ve (− ve) ITCs. The variation in gm2
distortion for analog/RF applications. Therefore, linearity should be
and gm3 are seen to be very much insignificant for the SPE-HJ-LSHGO-V-
maintained at the device level to ascertain the desired output at the
TFET compared to the SPE-HJ-V-TFET in presence of ITCs. Higher peaks
receiver end. To maintain linearity, transconductance is required to be
at a lower value of gate voltage are suitable for gm2 and gm3 for better
same over the entire input voltage. However, for both MOSFET and
linearity. It can also be elucidated from the aforementioned figure that
TFET transconductance varies with the variation in gate voltage. This
the peak of gm2 and gm3 are occurring at lower gate voltage for the de­
subsection analyses the linearity behavior in terms of different linearity
vice SPE-HJ-LSHGO-V-TFET compared to SPE-HJ-V-TFET which proves
figures of merit (FOMs) such as gmn, VIP3, IIP3, IDM3, ZCP, and 1-dB CP

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M.R. Tripathy et al. Microelectronics Reliability 119 (2021) 114073

Fig. 12. Plot of (a) ZCP and (b) 1-dB CP for SPE-HJ-V-TFET and SPE-HJ-LSHGO-V-TFET in presence of ITCs.

that the proposed device based on heterogeneous gate oxide is showing both +ve (donor) and –ve (acceptor) ITCs have been considered in this
better linearity in presence of ITCs. VIP3 is the extrapolated input study. The performance parameters in presence of ITCs of the LSHGO
voltage where1st and 3rd order harmonic voltages are the same [21,33]. based SPE HJ V-TFET have been compared with those of the device
Fig. 10(b) shows the VIP3 for the devices i.e. SPE-HJ-LSHGO-V-TFET without the LSHGO structure (i.e, with only Al2O3 as the gate oxide).
and SPE-HJ-V-TFET in presence of +ve as well as -ve ITCs. It can be The proposed LSHGO based HJ V-TFET shows improved immunity to
observable from Fig. 10(b) that the VIP3 shows less variation for SPE-HJ- the ITCs over the V-TFET device with only Al2O3 as a gate oxide. Further,
LSHGO-V-TFET than SPE-HJ-V-TFET in presence of ITCs. the proposed LSHGO based device has improved device level perfor­
The change in IIP3 along with IMD3 following gate voltage in pres­ mance parameters than the SPE HJ V-TFET with only Al2O3 as gate
ence of ITCs for the device SPE-HJ-LSHGO-V-TFET and SPE-HJ-V-TFET oxide. The superior performance parameters of the SPE HJ V-TFET with
are shown in Fig. 11. IIP3 is related to extrapolated input power where HfO2/Al2O3 LSHGO structure are attributed to lowering in the tunnel­
1st and 3rd order harmonic power becomes equal. A higher value of it is ling junction barrier height because of the shifting in the band bending
needed for better linearity and lower distortion. On the other hand, of the channel owing to the shift of the flat band voltage of the Si
IMD3 which corresponds to third order intermodulation distortion channel.
should be minimum for better linearity. It is evident from Fig. 11(a) and
(b) that the IIP3 and IDM3 are less prone to ITCs for SPE-HJ-LSHGO-V- Declaration of competing interest
TFET than SPE-HJ-V-TFET.
The best suitable biasing voltage can be considered by analyzing The authors have no affiliation with any organization with a direct or
ZCP. The minimum value of ZCP is suitable to have more linearity. indirect financial interest in the subject matter discussed in the
Fig. 12(a) shows the bar diagram of ZCP for SPE-HJ-LSHGO-V-TFET and manuscript.
SPE-HJ-V-TFET in presence of ITCs. We can observe from the figure that
SPE-HJ-LSHGO-V-TFET shows little variation for ZCP compared to SPE- References
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