Major Final Report Word

A SIMPLIFIED SINGLE-PHASE MULTISTRING MULTILEVEL INVERTER TOPOLOGY FOR
DISTRIBUTED ENERGY RESOURCES
CHAPTER 1
MICROGRID SYSTEM
1.0 INTRODUCTION:
In the micro grid system, the distributed energy resource (DER) based single-phase
inverter is usually adopted. To reduce conversion losses, the key is to save costs and size by
removing any kind of transformer as well as reducing the power devices. The objective of this
paper is to study a novel five-level multi-string inverter topology for a DERs-based DC/AC
conversion system. In this study, a high step-up converter is introduced as a front-end stage to
improve the conversion efficiency of conventional boost converters and to stabilize the output
DC voltage of various DERs such as PV and fuel cell modules for use with the simplified
multilevel inverter.
Figure 1.1 Configuration of multi-string multilevel inverter
Dept. of EEE SICET Page | 1

The simplified multilevel inverter requires only six active switches instead of the eight
required in the conventional cascaded H bridge (CCHB) multilevel inverter. In addition, two
active switches are operated under line frequency. The studied multi-string inverter topology
offers strong advantages such as improved output waveforms, smaller filter size, and lower
EMI and THD. Simulation and experimental results show the effectiveness of the proposed
solution.
In considering global warming and change in climate it is important to focus on the
emission of greenhouse gases and their reduction. The main cause of global warming is to
burning of fossil fuels to produce electricity so now everyone focusing on renewable resources.
It is difficult to replace all non-renewable electricity plants with renewable ones mainly
considering in a cost point of view. But one can reduce thermal power plant emissions by
adopting DER. By DER typically about 3kW – 10000kW range is possible either it can be used
as an alternative or synchronized with traditional power lines depending on utility usage.
In light of public concern about global warming and climate change, much effort has
been focused on the development of environmentally friendly distributed energy resources
(DERs). For delivering premium electric power in terms of high efficiency, reliability, and
power quality, integrating interface converters of DERs such as photovoltaic, wind power,
micro turbines, and fuel cells into the microgrid system has become a critical issue in recent
years.
The proposed controller with each distributed generation (DG) system in the microgrid
contains inner voltage and current loops for regulating the grid-interfacing inverter, and
external power control loops for controlling real and reactive power flow and for facilitating
power sharing between the paralleled DG systems when a utility fault occurs and the microgrid
islands.
To use DERs in electrical power systems we need an inverter. In the case of micro grid
system 1Ø multilevel inverter is usually adopted. Various research works are going on over
inverter circuit configuration mainly in reducing the switches at higher voltage levels. In such
arrangements, the utmost Distributed Energy Resources regularly supply a DC voltage that
differs in a wide range according to different load conditions. Further reducing switches &
increasing level will reduce filter cost & harmonic content. 7- Level cascaded multilevel
inverter topology requires 12 switches but this new multilevel inverter requires 6 switches in
which the same multilevel is obtained. Invariably switching losses and costs were also reduced.
In reality, a high step-up converter is used before the inverter input circuit to maintain
high constant voltage. In this paper, we are going to study only about Multi-level inverter

circuitry. The new multi-level inverter topology has a minimum number of switching devices,
improved output waveform, and lower total harmonic distortion (THD).
The advancement of multilevel inverters gives rise to converting power in multiple
voltage steps achieving lower switching losses, better electromagnetic compatibility, higher
voltage capability, and improved power quality. The multilevel converters achieve high-
voltage and high currents by means of a series of number of switching devices, each of which
lies within the ratings of the individual power devices. Among the multilevel Converters, the
cascaded H-bridge topology (CHB) is particularly attractive in high-voltage applications,
because it requires the least number of components to synthesize the same number of voltage
levels. These converter topologies can generate high-quality voltage waveforms with power
semiconductor switches operating at a frequency near the fundamental. Although, in low-
power applications, the switching frequency of the power switches is not restricted, a low
switching frequency can increase the efficiency of the converter. Additionally, multilevel
converters feature several dc links, making possible the independent voltage controls. A single-
phase grid-connected inverter is usually used for residential or low-power applications of
power ranges that are less than 10 kW. Multilevel inverters offer improved output waveforms
and lower THD. Multilevel inverters are promising; they have nearly sinusoidal output-voltage
waveforms, output current with better harmonic profile, less stressing of electronic components
owing to decreased voltages, switching losses that are lower than those of conventional two-
level inverters, a smaller filter size, and lower EMI, all of which make them cheaper, lighter,
and more compact.
1.1 LITERATURE SURVEY
Power inverters are increasingly being used in modern energy conversion systems,
including uninterruptable power supplies, motor drives, and active interfaces for localized and
distributed generation. That employs high-frequency transformers or makes no use of
transformers at all have been investigated to reduce size, weight, and expense.
For low and medium power applications international standards allow the use of grid-
connected power converters without galvanic isolation, thus allowing so-called “Transformer”
architectures.
Furthermore, as the output voltage levels increase the harmonic content of such
inverters decreases, allowing the use of smaller and less expensive output filters.
A DC voltage source supported by a relatively large capacitor feeds the main converter
circuit, a three-phase bridge. The DC voltage source can be a battery, fuel-cell stack, diode

rectifier, and/or capacitor. Six switches are used in the main circuit; each is traditionally
composed of a power transistor and an anti-parallel (or freewheeling) diode to provide
bidirectional current flow and unidirectional voltage-blocking capability. The V-source
converter is widely used.

CHAPTER-2
DER System configuration
2.0 INTRODUCTION
Fig. 1.1 shows the multi-bus microgrid configuration considered in this paper,
where two paralleled DG systems 1 and 2 are employed. Each DG system is comprised of a
DC source, a pulse-width modulation (PWM) voltage source inverter (VSI), and LC filters.
Under normal mode of operation, the microgrid is connected to the utility system at the point
of common coupling (PCC) usually through a static transfer switch (STS).
Figure 2. 1 Microgrid Configuration
This report presents a complete design and implementation results of microgrid architecture
with paralleled power conditioning systems operating in grid-tie mode, islanding mode, and
mode transfer also CAN communication has been studied. The inverter-based DGs tend to have
faster dynamic but smaller output impedance therefore it can be quickly switched between grid
tie and islanding modes.

2.1 MICROGRID ARCHITECTURE AND OPERATIONS:

Fig. 2.1 Shows a paralleled power conditioning systems (PCS) based microgrid
architecture consisting of two DGs by fuel cell PCS, an upper-level controller, a CAN bus, a
static switch, and other DGs. An upper-level controller performs monitoring and power
management through the CAN bus.
To extend the transmission distance, a load-sharing scheme was proposed to transmit
the DC quantity through a controller area network (CAN) bus among paralleled inverters with
fast transmission speed. According to the load types, critical loads and non-critical loads can
be separated by a solid-state relay (SSR).
In such systems, most DERs usually supply a DC voltage that varies in a wide range
according to various load conditions. Thus, a DC/AC power processing interface is required
and is compliable with residential, industrial, and utility grid standards. The applications of
power electronics in the integration of DG units, in particular, wind power, fuel cells, and PV
generators. Power electronics, being the technology of efficiently converting electric power,
plays an important role in the field of modern electrical engineering, it is an essential part of
the integration of dispersed generation units to achieve high efficiency and performance in
power systems.
A large number of dispersed generation (DG) units including both
 Renewable energy sources (such as Wind turbines, Photovoltaic (PV) generators, Fuel
cells)
 Nonrenewable energy sources (such as Gas/Steam power combined heat and power
stations, Nuclear, Coal, Hydro wave generators)
In this report, the characteristics of some dispersed generation units and the
general structures of the systems interfacing with the power generation units will be presented,
in particularly, fuel cells, and photovoltaic cells.
2.2 POWER ELECTRONICS IN FUEL CELL SYSTEMS:

2.2.1 Fuel Cells:
The fuel cell is a chemical device, which produces electricity directly without any
intermediate stage. Various fuel cells are available for industrial use or are currently being
investigated for use in industry, including:
1) Proton exchange membrane;
2) Solid oxide;
3) Molten carbonate;

4) Phosphoric acid;
5) Aqueous alkaline.
The efficiency of the fuel cell is quite high (40%–60%). Also, the waste heat generated
by the fuel cell can usually be used for cogeneration such as steam, air-conditioning, hot air,
and heating, then the overall efficiency of such a system could be as high as 80%. The voltage
of a fuel cell is usually small with a theoretical maximum being around 1.2 V, fuel cells may
be connected in parallel and/or in series to obtain the required power and voltage.
2.2.2 Power Electronic Conditioning System for Fuel Cells

The power conditioning circuit of a fuel cell system often consists of a DC/DC converter
and a DC/AC inverter as shown in Fig.2.2(a)another possible configuration of the system
includes a DC/AC converter which converts the voltage into a high-frequency ac voltage, then
a cyclo converter is used to change the high-frequency voltage into a power-frequency ac
voltage as shown in Fig. 2.2 (b). The commonly used configuration of the system with a DC/DC
converter plus an inverter
Figure 2.2 Schematic of fuel cell power electronic conditioning systems,

(a) DC/DC, Dc link, and DC/AC conversion and (b) DC/AC, AC link, and AC/AC conversion

In a DC/DC + DC/AC converter system, the DC/DC converter is used for isolation and
voltage step-up, and the inverter is needed for AC output. A DC/DC converter is usually put
between the fuel cell and the inverter to perform two functions.
 One is the DC isolation for the inverter because a low-frequency transformer is placed at
the output of the inverter is very bulky.
 Second is to produce sufficient voltage for the inverter input, so that the required
magnitude of the AC voltage can be produced.
For example, if only a 200-V fuel cell stack cannot produce 380-V line voltage, then a step-
up DC converter is needed.
Various converter topologies have been developed for DERs that demonstrate effective
power flow control performance whether in grid-connected or stand-alone operation. Among
them, solutions that employ high-frequency transformers or make no use of transformers at all
have been investigated to reduce size, weight, and expense. For low-medium power
applications, international standards allow the use of grid-connected power converters without
galvanic isolation, thus allowing so-called “transformer-less” architectures.
2.3 POWER ELECTRONICS IN PHOTOVOLTAIC (PV) SYSTEMS:

2.3.1 PV cell:
The PV cell is an electrical device, which produces electrical power when exposed to
sunlight and connected to a suitable load. Without any moving parts inside the PV module, the
tear-and-wear is very low. A typical PV module is made up of around 36 or 72 cells connected
in series, encapsulated in a structure made of, e.g., aluminum and teldar.
Several types of proven PV technologies exist where
 The crystalline (PV module light-to-electricity efficiency: 10%-15%)
 Multi crystalline (efficiency: 9%-12%)
 Thin-film amorphous silicon (efficiency: 10%) etc.
2.3.2 Power Electronic Interfaces
The power electronic interface for PV systems has two main tasks:
 One is to convert the generated DC voltage into a suitable AC for the utility
 The other is to control the terminal conditions of the PV module(s) to track the
Maximum Power Point (MPP) for maximizing the energy capture.
The MPP is tracked using an MPP Tracker (MPPT) device, based on one of the following
schemes: incremental conductance, parasitic capacitance, or constant voltage.

2.4 THE CONFIGURATION OF PV SYSTEMS

2.4.1 Centralized scheme:
The past centralized inverter system is illustrated in Fig. where tens of PV modules are
connected in series and/or parallel, and connected to the inverter.
This may require an individual design for each installation. The inverters for this power range
are mostly connected to a three-phase utility.
Figure 2. 3 (a) String inverter

2.4.2 String Inverters:
The present string inverter system shown in fig. is a reduced version of the centralized inverter
with a single string of modules connected to the inverter. The overall efficiency is high as
compared with the centralized inverter.
Fig2. 3(b)Multilevel inverters

Fig2. 3(b)Multilevel inverters, AC modules, and single-cell converter systems.
The future multi-string inverter is a further development of the string inverter, where
several strings are interfaced with their own dc/dc converter to a common dc/ac inverter.
Figure 2.3(c) ac-module

Fig 2.3 is a reduction of the string inverter, where each PV module has its integrated
power electronic interface to the utility. The power loss of the system is lowered due to reduced
mismatch among the modules.
The applications of power electronics in various dispersed generation units, in
particular fuel cells and PV generators have been reviewed and it is clear that power electronics
is the enabling technology for dispersed power generation.
A single-phase multi-string five-level inverter integrated with an auxiliary circuit was
recently proposed for DC/AC power conversion.
This report presents a new multilevel inverter topology using an H-bridge output stage
with a bidirectional auxiliary switch. The new topology produces a significant reduction in the
number of power devices and capacitors required to implement a multilevel output. The new
topology is used in the design of a five-level inverter; only five controlled switches, eight
diodes, and two capacitors are required to implement the five-level inverter using the proposed
topology.
The new topology achieves a 37.5% reduction in the number of main power switches.
Multilevel converters were used only in some high-power applications such as high-
power motor drivers in marine, mining, or chemical industries applications, high power
transmission, power line conditioners. Multilevel converters offer high power capability,
associated with lower output harmonics and lower commutation losses.
Figure 2.4 Configuration of multi string inverter for various DERs application.

CHAPTER 3
OVERVIEW OF MULTILEVEL INVERTER AND PWM

TECHNIQUES
3.0 INTRODUCTION
At first, this chapter introduces the basic converter theory of power electronics. Then
three mostly used multilevel inverter topologies and their basic operations as well as their
relative advantages and disadvantages are presented. Finally, some very simple modulation
techniques used to control the output voltages of multilevel inverters are briefly described.
Multilevel power conversion has been receiving increasing attention in the past few years for
high-power applications. Numerous topologies have been introduced and studied extensively
for utility and drive applications in the recent literature. These converters are suitable in high
voltage and high-power applications due to their ability to synthesize waveforms with better
harmonic spectrum and attain higher voltage with a limited maximum device rating. There are
various current control methods for two-level converters. Hysteresis control of power
converters, based on instantaneous current errors, is widely used for the compensation of the
distribution system as it has good dynamic characteristics and robustness against parameter
variations and load non-linearities.
3.1. UNIFIED CONVERTER THEORY
In the preface of his book “Switching Power Converters”, Wood introduces the concept
of a unified converter theory. There he states: “Most traditional views of the field have seemed
somewhat disjointed; converters were largely regarded as related only because they all use
semiconductor switches and have certain topological similarities. the view expounded herein
(is that) switching power converters are related by function and behavior; their basic
characteristics do not in any way depend on the types of switches used, nor on the applications
to which they are put, nor on the topologies in which they are realized”.
According to this unified theory, any power electronic converter can be viewed as a
matrix of switches that connects its input nodes to its output nodes. These nodes may be either
DC or AC, and either inductive or capacitive; and the power flow may be in either direction.

Two obvious restrictions are enforced by some basic laws of electricity. If one set of
nodes (input or output) is inductive, the other set must be capacitive, so as not to create a cut
set of voltage or current sources when the switches are closed.
The combination of open and closed switches should never open circuit an inductor, or
short circuit a capacitor.
This unified set of converters is generally broken into several subsets. The term rectifier
is used when the power flow is predominately from the AC port to the DC port and the term
inverter is used when power flow is predominately from the DC port to the AC port. The term
converter is used either when there is no predominant direction of power flow or as a general
term to encompass both rectifiers and inverters.
In a Voltage Source Converter (VSC), the DC port is the capacitive port and is voltage
stiff (i.e. a large DC bus capacitor). The voltages in such a converter are well-defined by this
port and are generally considered independent of the converter’s operation. The value of the
AC side inductance is comparatively small and modulation of the converter controls these AC
side inductor currents. Should the voltage source converter be responsible for the control of the
DC bus capacitor voltage, then this voltage is indirectly controlled by controlling the net current
flow in the capacitor. The switches in such a converter must block a unidirectional voltage, but
be able to conduct current in either direction if bidirectional power flow is desired.
According to this unified theory, any power electronic converter can be viewed as a
matrix of switches that connects its input nodes to its output nodes. These nodes may be either
DC or AC, and either inductive or capacitive; and the power flow may be in either direction.
Two obvious restrictions are enforced by some basic laws of electricity.
1) If one set of nodes (input or output) is inductive, the other set must be capacitive, so as
not to create a cut set of voltage or current sources when the switches are closed.
2) The combination of open and closed switches should never open circuit an inductor, or
short circuit a capacitor.

3.2 VOLTAGE SOURCE OR CURRENT SOURCE INVERTER
This unified set of converters is generally broken into several subsets. The term
rectifier is used when the power flow is predominately from the AC port to the DC port and
the term inverter is used when power flow is predominately from the DC port to the AC port.
The term converter is used either when there is no predominant direction of power flow or as
a general term to encompass both rectifiers and inverters.
In a Voltage Source Converter (VSC), the DC port is the capacitive port and is voltage
stiff (i.e. a large DC bus capacitor). The voltages in such a converter are well-defined by this
port and are generally considered independent of the converter’s operation. The value of the
AC side inductance is comparatively small and modulation of the converter controls these AC
side inductor currents. Should the voltage source converter be responsible for the control of
the DC bus capacitor voltage, then this voltage is indirectly controlled by controlling the net
current flow in the capacitor. The switches in such a converter must block a unidirectional
voltage, but be able to conduct current in either direction if bidirectional power flow is desired.
Figure 3.1 Half-bridge configurations.

Figure 3.2 Full-bridge configuration.
In a single-phase half-bridge inverter, only two switches are needed. To avoid shoot-
through faults, both switches are never turned on at the same time. S 1 is turned on and S2 is
turned off to give a load voltage, VAO in Fig. 3.1, of VS/ 2. To complete one cycle, S1 is turned
off and S2 is turned on to give a load voltage, VAO, of -VS/ 2.
In full-bridge configuration, turning on S1 and S4 and turning off S2 and S3 give a

voltage of VS between points A and B (VAB) in Fig. 3.2, while turning off S1 and S4 and turning
on S2 and S3 give a voltage of –VS. To generate zero levels in a full-bridge inverter, the
combination can be S1 and S2 on while S3 and S4 off or vice versa. The three possible levels
referring to the above discussion are shown in Table 3.1.
Conducting Switches Load Voltage VAB
S1 , S4 +VS
S2 , S3 -VS
S1, S2 or S3 , S4 0
Table 3.1 Load voltage with corresponding conducting switches.

Note that S1 and S3 should not be closed at the same time, nor should S 2 and S4 . Otherwise, a
short circuit would exist across the DC source. The output waveform of the half-bridge and
full-bridge of the single-phase voltage source inverter is shown in Fig. 4.3 and 4.4,
respectively.
Figure 3.3 Output waveform of half-bridge configuration.
Figure 3.4 Output waveform of full-bridge configuration.

3.3 MULTI LEVEL VOLTAGE SOURCE INVERTER
A multilevel inverter can switch either its input or output nodes (or both) between
multiple (more than two) levels of voltage or current. The multilevel voltage source inverter is
recently applied in many industrial applications such as ac power supplies, static VAR
compensators, drive systems, etc. One of the significant advantages of multilevel configuration
is the harmonic reduction in the output waveform without increasing switching frequency or
decreasing the inverter power output. The output voltage waveform of a multilevel inverter is
composed of the number of levels of voltages, typically obtained from capacitor voltage
sources. The so-called multilevel starts from three levels. As the number of levels reach
infinity, the output THD approaches zero. The number of the achievable voltage levels,
however, is limited by voltage unbalance problems, voltage clamping requirement, circuit
layout, and packaging constraints.
Here, three mostly used voltage synthesis-based multilevel inverters are introduced, i.e.
1. Diode-Clamped Multilevel Inverter.

2. Flying-Capacitor Multilevel Inverter.
3. Cascaded-Inverters with Separated DC Sources.
3.3.1. Diode-Clamped Multilevel Inverter (DCMI)
The diode-clamped multilevel inverter uses capacitors in series to divide up the dc bus
voltage into a set of voltage levels. To produce m levels of the phase voltage, an m-level diode-
clamp inverter needs m-1 capacitors on the dc bus. A single-phase five-level diode-clamped
inverter, which can produce a nine-level phase to phase voltage waveform, is shown in Fig.
3.5.

Figure 3.5 A single-phase five-level diode-clamped inverter
The dc bus consists of four capacitors, i.e., C1, C2, C3, and C4. For a dc bus voltage Vdc ,
the voltage across each capacitor is Vdc/4, and each device voltage stress will be limited to one
capacitor voltage level, Vdc /4, through clamping diodes. DCMI output voltage synthesis is
relatively straightforward.

To explain how the staircase voltage is synthesized, point O is considered as the output
phase voltage reference point. Using the five-level inverter shown in Fig. 2.5, there are five
switch combinations to generate five level voltages across A and O.
Table 3.2 shows the phase voltage level and their corresponding switch states. In the
Table, state 1 represents that the switch is on, and state 0 represents the switch is off. There
exist four complementary switch pairs in each phase, i.e., S1 -S5, S2 -S6 , S3 -S7 and S4 -S8 .
Output Switch State
VAO S1 S2 S3 S4 S5 S6 S7 S8
V5=Vdc 1 1 1 1 0 0 0 0
V4 =3Vdc /4 0 1 1 1 1 0 0 0
V3=Vdc /2 0 0 1 1 1 1 0 0
V2=Vdc /4 0 0 0 1 1 1 1 0
V 1 =0 0 0 0 0 1 1 1 1
Table 3.2 Diode-clamped five-level inverter voltage levels and their switch states.
However, it seems to have many disadvantages, particularly when extended beyond three level
topologies. Many of these issues in practice limit the diode-clamped topology to a maximum
of five levels:
1) Although the transformer can be eliminated, extra components (diodes) are required to
Ensure load current continuity. The number of extra components rises sharply as the
number of levels increase.
2) These extra components do not necessarily ensure equal voltage sharing for all
switches.

3) Switch utilization is not equal, outer switches receiving a lower average load. This
becomes particularly apparent as the number of levels increase and the modulation
depth is small.
4) Similarly, the power flows to and from the different capacitors in the capacitor string
are not balanced.
5) Not all switch states are allowed. The disallowed states must be re-mapped to their
equivalent allowed states.
6) Different equivalent states slew the capacitor voltages in different directions. This must
be used to control the capacitor voltages.
For the above reasons, a more complicated, dedicated modulation strategy must be used, which
has been specifically tailored to the topology of the converter.
3.3.2. Flying-Capacitor Multilevel Inverter (FCMI)
Probably the most important multilevel topology to appear recently is the flying
capacitor inverter, or imbricated cells multilevel inverter, proposed by Meynard and Foch. A
FCMI shown in Fig. 4.6 uses a ladder structure of dc side capacitors where the voltage on each
capacitor differs from that of the next capacitor.
To generate m-level staircase output voltage, m-1 capacitors in the dc bus are needed.
Each phase-leg has an identical structure. The size of the voltage increment between two
capacitors determines the size of the voltage levels in the output waveform.

Figure 3.6 A single-phase five-level flying-capacitor inverter.
Here the switch pair-capacitor ‘cell’ is isolated and inserted within a similar cell –
hence the term imbricated cells inverter. This inner pair of switches and their associated
capacitor now ‘flies’ as the outer pair of devices switch. The combination of conducting
switches and capacitors ensures that the voltage across any blocking switch is always well
defined. Table 4.3 shows the switch combination of the voltage levels and their corresponding
switch states. In fact, there is more than one combination to produce output voltages V 2, V3,
and V4. That makes the FCMI more flexibility than DCMI.

The flying capacitor family of converters appears very attractive:
1) The flying capacitor concept can be applied to a number of different converter types -
current or voltage source, DC-DC, DC-AC or AC-AC.
2) Any switch combination is valid and ensures voltage sharing, so long as switch pairs
receive complementary drive signals. Most modulation strategies are easily applied to
this topology simply by phase shifting the drive signals.
3) The voltages of the capacitors are automatically balanced by this conventional
modulation strategy. If desired, the capacitor voltages can be actively controlled by an
appropriate modification of the control signals.
4) The load is by default equally shared among the switches.
5) The topology is modular and not reliant on a transformer.
There are some significant disadvantages, which are not at first apparent:
1) The topology requires a lot of high voltage capacitors — many more than other
topologies. These capacitors need to conduct the full load current for at least part of the
switching cycle. Fortunately, if the switch frequency is high, these capacitors can
usually be relatively small in capacitance value.
2) Since these capacitors initially have zero voltage across them, starting the converter
safely may be a non-trivial task.
3) The topology is not inherently fault tolerant.

Output S1 S2 S3 S4 S5 S6 S7 S8
VAO
V5=Vdc 1 1 1 1 0 0 0 0
V4 =3Vdc /4 1 1 1 0 0 0 0 1
1 1 0 1 0 0 1 0
1 0 1 1 0 1 0 0
0 1 1 1 1 0 0 0
V3=Vdc /2 1 1 0 0 0 0 1 1
1 0 1 0 0 1 0 1
1 0 0 1 0 1 1 0
0 1 1 0 1 0 0 1
0 1 0 1 1 0 1 0
0 0 1 1 1 1 0 0
V2=Vdc /4 1 0 0 0 0 1 1 1
0 1 0 0 1 0 1 1
0 0 1 0 1 1 0 1
0 0 0 1 1 1 1 0
V 1 =0 0 0 0 0 1 1 1 1
Table 3.3 Switch combination of the voltage levels and their corresponding switch states.

3.3.3. Cascaded-Inverters with Separated DC Sources
The last structure introduced here is a multilevel inverter, which uses cascaded
inverters with separate dc sources (SDCSs). The general function of this multilevel inverter is
the same as that of the other two previous inverters. The multilevel inverter using cascaded-
inverter with SDCSs synthesizes a desired voltage from several independent sources of dc
voltages, which may be obtained from batteries, fuel cells, or solar cells. This configuration
recently becomes very popular in ac power supply and adjustable speed drive applications.
This new inverter can avoid extra clamping diodes or voltage balancing capacitors. A single-
phase two-cell series configuration of such an inverter is shown in Fig 3.7.
Figure 3.7 Single-phase structure of a two-cell cascaded inverter.
Each SDCS is associated with a single-phase full-bridge inverter. The ac terminal

voltages of different level inverters are connected in series. By different combinations of the

four switches, S1 -S4 , each inverter level can generate three different voltage outputs, +Vdc, -
Vdc, and zero. The ac output of each of the different level of full-bridge inverters are connected
in series such that the synthesized voltage waveform is the sum of the inverter outputs. Note
that the number of output phase voltage levels is defined in different way from those of two
previous inverters. In this topology, the number of output phase voltage levels is defined by
m=2s+1, where s is the number of dc sources. Table 3.4 shows the switch combination of the
voltage levels and their corresponding switch states.
Output S1 S2 S3 S4 S5 S6 S7 S8
VAO
V5 =2Vdc 1 0 0 1 1 0 0 1
V4=Vdc 1 0 0 1 1 0 1 0
V 3 =0 0 0 0 0 0 0 0 0
V2 =-Vdc 0 1 1 0 0 1 0 1
V1 =-2Vdc 0 1 1 0 0 1 1 0
Table 3.4 Two-cell cascaded-inverter voltage levels and their switch states.
This multilevel converter structure has some very significant advantages, if its limitations are
acceptable. Its advantages are:
1) It has perhaps the simplest architecture and the lowest component cou nt. No
transformer is needed, so capital costs are low.
2) Again, the converter is very modular and easy to understand. This applies not only to
its structure, but also to its control.

Limitations:
1) There is only limited access to DC bus capacitors, which limits its area of application
to either those with only reactive power flow, or those where the power source or load
can be both modular and isolated.
Should a module fail (or be removed), it must fail short circuit, or be bypassed. The converter
can continue to operate, at full current capacity, but at reduced voltage rating. These will in
practice mean that if fault tolerance is required, the converter will need a more conservative
voltage rating a potential cost penalty.
3.4. H – BRIDGE INVERTER

“H” topology has many redundant combinations of switches’ positions to produce the
same voltage levels. As an example, the level “zero” can be generated with switches in position
S (1) and S (2), or S (3) and S (4), or S (5) and S (6), and so on.
Another characteristic of “H” converter is that they only produce an odd number of
levels, which ensures the existence of the “0V” level at the load. For example, a 51-level
inverter using an “H” configuration with transistor-clamped topology requires 52 transistors,
but only 25 power supplies instead of the 50 required when using a single leg. Therefore, the
problem related to increasing the number of levels and reducing the size and complexity has
been partially solved, since power supplies have been reduced to 50%.
The single-phase H – Bridge of cascaded inverter. The ac terminal voltages of each

bridge are connected in series. Unlike the diode clamp or flying capacitors inverter, the
cascaded inverter does not require any voltage-clamping diodes or voltage balancing
capacitors.
This configuration is useful for constant frequency applications such as active front-
end rectifiers, active power filters, and reactive power compensation.
In this case, the power supply could also be voltage regulated dc capacitor. The circuit
diagram consists of two cascade bridges. The load is connected in such a way that the sum of
output of these bridges will appear across it. The ratio of the power supplies between the
auxiliary bridge and the main bridge is 1:3. One important characteristic of multilevel
converters using voltage escalation is that electric power distribution and switching frequency
present advantages for the implementation of these topologies

3.5 MULTILEVEL CURRENT SOURCE INVERTER

The inverters which were focused upon in the previous section were voltage source
inverters, with multilevel voltage waveforms. These inverters divide the total input voltage
among a number of switches, and allow a reduction of the voltage harmonics. As mentioned,
these are the most commonly used and best understood multilevel inverters. As we broaden
the scope of multi-level again, it is important to see the distinction between these two aspects
of a multilevel inverter the application of the inverter (voltage source or current source) and
the internal topology of the inverter (multilevel voltage or multilevel current).
If the capacitive port were an AC port and the inductive port current stiff and DC, then
this would be classified as a current source, multilevel current inverter. Two multilevel current
inverters are shown in Fig 4.8 and 4.9 below. In both of these examples they present a
multilevel current waveform to the capacitive port. The voltage rating of the inverter is limited
to that of the switches, however, the input current is divided between the multiple switches.
Figure 3.8 The flying inductor inverter – multilevel current inverter.

Figure 3.9 The isolated flying bridge inverter – formed from current Source bridges
placed in parallel.
Current source inverters have a number of advantages:
1) Current is well controlled short term over-current protection is inherently provided by

the DC bus inductor; long term by the current control loop.
2) The DC bus energy storage component is a large inductor, rather than a large capacitor.
A large power inductor is arguably simpler, cheaper and most importantly, more
reliable.
3) Current source inverters are suited to the high-power devices such as thyristors and
GTOs, which can block voltage in either direction, but conduct current only in the
forward direction.
4) Soft switching is either intrinsic to such devices, or easily ensured.
DISADVANTAGES:
1) Inductors have higher losses than capacitors.

2) Switch voltages are poorly defined. Most semiconductor switches tolerate transient
over-current better than transient over-voltages.
3) There are more potential resonance problems in input and output filters than for voltage
source.

4) When used as a back to back rectifier inverter pair, a more complex and expensive
controlled rectifier with closed loop control is required as a current source. An
uncontrolled diode rectifier is often suitable for voltage source converters.
Voltage source inverters have become the dominant configuration, even at high power
levels. The direction of semiconductor technology has reflected this, with asymmetrical or
reverse conducting thyristors (RCTs) and GTOs being developed specifically for VSC rather
than CSC applications.
3.6 MODULATION TOPOLOGIES FOR MULTILEVEL INVERTERS
Almost all power electronic inverters are operated in the “switched mode”. This means
the switches within the inverter are always in either one of two states — turned off (so no
current flows), or saturated (turned on completely, with only a small voltage drop across the
switch). Any operation in the linear region, other than for the unavoidable transition from
conducting to non-conducting, incurs an undesirable loss of efficiency and an unbearable rise
in switch power dissipation. To control the flow of power in the inverter, the switches alternate
between these two states. This happens rapidly enough that the inductors and capacitors at the
input and output nodes of the inverter average or filter the switched signal. The switched
component is attenuated and the desired DC or low frequency AC component is retained. This
process is called Pulse Width Modulation (PWM), since the desired average value is controlled
by modulating the width of the pulses.
To achieve the greatest possible attenuation of the switching component, it is generally

desirable that the switch frequency fc is high — many times the frequency of the desired
fundamental AC component f1 seen at the input or output terminals. Two requirements which
all low pulse number PWM candidates should observe are synchronism with the fundamental
frequency and quarter and half wave symmetry.
Synchronism with the fundamental frequency means ensuring the switching frequency
fc is an integer multiple of the synthesized fundamental frequency f1. That is, the pulse number
N=fc/f1 must be an exact integer. The frequency spectrum of the PWM waveform will then
consist of discrete frequencies at multiples of the fundamental frequency nf1, where n is an
integer. Quarter and half wave symmetry ensure that no even harmonics will exist in the output
spectrum. This can be achieved by choosing N odd. An important even harmonic which is
eliminated is the DC component.

No frequency components below the fundamental frequency (commonly referred to as

sub-harmonics) will exist. This is important since an undesired harmonic component near zero
frequency, even if small in amplitude, can cause large currents to flow in inductive loads.
Beyond these basic requirements, there are many different ways of generating PWM
switching edges. Any technique can probably be placed into one of the following three
categories:
1) Off-line or pre-calculated PWM technique

2) Hysteresis control PWM
3) Carrier based PWM.
3.6.1. Off-line or Pre-Calculated PWM Technique

Selective Harmonic Elimination (SHE) and Selective Harmonic Minimization (SHM)
are two off-line (pre-calculated) non-carrier based PWM techniques. SHE was proposed in a
early paper by Patel and Hoft. Accepting first the conditions of quarter and half wave symmetry
to cancel all even harmonics, the angles of the switching edges in the first quarter cycle can be
considered variables for optimization. Each angle is one degree of freedom. For each degree
of freedom, one harmonic may be set to zero or any other reasonable desired value. Using
Fourier transforms, simultaneous equations in these angles are solved given desired values for
the fundamental and the lowest significant harmonics. These calculations are slow and are
done off-line. A look up table of edge angles is created which the on-line controller uses to set
the edge times. Optimal PWM or selected harmonic elimination PWM (SHE-PWM) seems
attractive, but cannot react to transients quickly. This is because pulses do not occur at fixed
intervals, that is, the switch period is not constant. Moving one edge may completely upset the
optimized spectrum. Closed loop control using SHE/SHM is generally limited to cycle by
cycle control of the fundamental frequency and modulation depth. Some works have been done
on closing feedback loops around optimized PWM modulators to remove errors when they
occur. These techniques cannot compensate for distortions due to DC bus ripple, or switching
imperfections.
3.6.2. Hysteresis Control PWM
A hysteresis band modulator calculates the error between the desired output and the
measured output. The state of the switches is changed when this error exceeds a certain bound
(leaves the hysteresis band) so as to drive the error back within that bound. This method
requires that the controlled output quantity of the inverter is integrated either by the load, or as

part of the controller. For example, in a voltage source hysteretic inverter, the output current
(the measured and subsequently controlled quantity) will be integrated by an inductive load.
This technique has the advantage of bounded, predictable error and fast transient
response to changes at either the input or the output. It is closed loop by nature and
demonstrates low distortion. It is simple to implement in its simplest form. It has however a
number of disadvantages, which limit its usefulness to low power, high switching frequency
applications.
One disadvantage is the variable nature of the switch period. Because of this, the output
spectrum is continuous and spread to an extent, rather than discrete and grouped as with carrier-
based techniques. Further, the switching instants are not necessarily synchronous or cyclic and
so sub-harmonics may be present. For these reasons, hysteresis control is not applied for low
switching frequencies.
One method of eliminating sub-harmonics is to force quarter wave symmetry by

resetting the error at each zero crossing and forcing a switching, and hence a reflection of the
pattern, at 90 degrees. This gives discrete spectra without sub-harmonics. Another technique
which limits the variations in switching frequency is to modulate the width of the hysteresis
band. This places upper and lower limits on the switching frequency, but does not address the
problem of sub-harmonics.
3.6.3. Carrier Based PWM Techniques
There are many variations of carrier based PWM.
1) Analog vs. Digital

2) Sine-triangle vs. Space vector (in reality very similar)
3) Triangular vs. Saw tooth carrier
4) Symmetric vs. Asymmetric (sampled once/twice per triangle)
5) Uniform sampling vs. Natural sampling
6) Periodic vs. Aperiodic carrier.
For the purposes of defining this broad category, carrier based PWM methods are those
where the switching decisions of the inverter are made for each switching cycle either at the
beginning or during that switch cycle. That is, the PWM waveform is calculated on a cycle by
cycle basis, either pulse by pulse, or edge by edge. This distinguishes it from SHE and SHM

PWM, where multiple switching edges are mapped out for the entire fundamental period or
some fraction therein; and hysteresis PWM, where neither edges nor switch period are defined,
calculated or even known in advance. A comparison of waveforms and frequency spectra of
three different PWM strategies are shown in Fig. 3.10 below.
Fundamental fS
Carrier fC
Sine-sawtooth PWM
Sine-triangle PWM

Harmonic elimination PWM
Figure 3.10 Wave forms and PWM
Figure 3.10 From the top, wave forms and frequency spectra of the original sinusoidal
modulating waveform, the unmodulated PWM square wave, sine-saw tooth (single edge
carrier) PWM, sine-triangle (double edge carrier) PWM, Selective Harmonic Elimination
(SHE) PWM and Hysteresis PWM.
3.6.4 Hysteresis PWM
The two basic approaches used to generate the PWM signals for multilevel inverters are:
1. Sub harmonic or Sub-Oscillation carrier based PWM-modulating waveform

comparison with offset triangular carriers.
2. Space Vector PWM-space vector modulation based on a rotating vector in multilevel
space.
These are the extensions of traditional two-level control strategies to several levels.
The two main advantages of PWM inverters in comparison to square-wave inverters are (i)
control over output voltage magnitude. (ii) Reduction in magnitudes of unwanted harmonic
voltages.

Good quality output voltage in SPWM requires the modulation index (m) to be less
than or equal to 1.0. For m>1 (over-modulation), the fundamental voltage magnitude increases
but at the cost of decreased quality of output waveform. The maximum fundamental voltage
that the SPWM inverter can output (without resorting to over-modulation) is only 78.5% of the
fundamental voltage output by square-wave inverter.
The merits and demerits of these two PWM techniques are compared under comparable
circuit conditions on the basis of factors like (i) quality of output voltage (ii) obtainable
magnitude of output voltage (iii) ease of control etc. The peak obtainable output voltage from
the given input dc voltage is one important figure of merit for the inverter.
Carrara considered different methods of disposing the many carrier bands required in
multilevel PWM.
Four alternative carrier PWM strategies with differing phase relationships for a multilevel
inverter are as follows:
1) In-phase disposition (IPD), where all the carriers are in phase- Technique A1;
2) Phase opposition disposition (POD), where the carriers above the zero reference are in phase,
but shifted by 1800 from those carriers below the zero reference- Technique A2;
3) Alternative phase opposition disposition (APOD), where each carrier band is shifted by 1800
from the adjacent bands- Technique A3; 4) Phase Disposition (PD), all the carriers are phase
shifted by 2N/(N-1) radians- Technique B.PD strategy is used most frequently because it
produces minimum harmonic distortion for the line–to–line output voltage.
3.6.5. Sub Harmonic Pulse Width Modulation SHPWM Technique
In SHPWM technique the intersection of the triangular carrier and the modulation wave
determines the generation of the pulse. This requires a carrier of much higher frequency than
the modulation frequency. The generated rectilinear output voltage pulses are modulated such
that their duration is proportional to the instantaneous value of the sinusoidal waveform at the
center of the pulse; that is, the pulse area is proportional to the corresponding value of the
modulating sine wave. If the carrier frequency is very high, an averaging effect occurs,
resulting in a sinusoidal fundamental output with high-frequency harmonics, but minimal low-
frequency harmonics.

Conventional SHPWM technique for multilevel inverters employ extension of carrier-

based techniques for two level inverters. It has been reported that the spectral performance of
five level waveforms can be significantly improved by employing alternative dispositions and
phase shift in the carrier signals. This paper extends this concept to a seven-level case where
the available options for polarity and phase variation. The carrier polarity variation is
implemented control for DSTATCOM in this project. It is based on a comparative evaluation
of possible dispositions of triangular carrier waveforms depending on their relative polarities.
For an m-level inverter this technique requires m-1, which are compared to a reference sine
wave. Thus, for a seven-level inverter the number of carrier signals is six and there exists five
possible carrier signal configurations. The carriers are named +1V, +0.66V, +0.33V, -0.33, -
0.66Vand -1V after their dc position as shown in Fig.3.11. Their phase position is + for a carrier
in phase and – for a carrier 180 degree out of phase.
Figure 3.11. Reference and carriers signal for SHPWM technique.

Figure 3.11 shows generation of reference and carriers signal for SHPWM technique,
which is used to control the switches of TBMCSL H- bridges inverter.
The carriers are named +1V, +0.66V, +0.33V, -0.33, -0.66V and -1V after their
dc position as shown in Fig.3.11. Their phase position is + for a carrier in phase and – for a
carrier 180 degree out of phase.

CHAPTER 4
TOPOLOGY OF FIVE-LEVEL INVERTER
4.0 System Description

This report presents a multi string multilevel inverter for DERs application. The multi
string inverter shown in Fig.2.5 is a further development of the string inverter, whereby several
strings are interfaced with their own DC/DC converter to a common inverter. This centralized
system is beneficial because each string can be controlled individually. Thus, the operator may
start his own PV/fuel cell power plant with a few modules. Further enlargements are easily
achieved because a new string with a DC/DC converter can be plugged into the existing
platform, enabling a flexible design with high efficiency.
Fig 4. 1 Single-phase multi string five-level inverter topology.

Figure 4.1 shows the complete power circuit used in the five-level inverter. The H-bridge is
formed by the four main power devices, Disp1 to Disp4. A capacitor voltage divider, formed
by C1 and C2 provides a half supply voltage point, node A in Figure. The auxiliary switch,

formed by the controlled switch Disp5 and the four diodes, D5 to D8, connects the center point
of the left-hand half-bridge to node A.
4.1 SYSTEM COMPONENTS

4.1.1 Main power switches:
The new topology achieves a 37.5% reduction in the number of main power switches
required, using only five controlled power switches instead of the eight required in any of the
other three configurations. The auxiliary switch voltage and current ratings are lower than the
ones required by the main controlled switches.
4.1.2 Auxiliary devices (diodes and capacitors):
a) The new configuration reduces the number of diodes by 60% (eight instead of 20) and the
number of capacitors by 50% (two instead of four) when compared with the diode clamped
configuration.
b) The new configuration reduces the number of capacitors by 80% (two instead of 10) when
compared with the capacitor clamped configuration.
4.1.3 Power stage operation:
The required five voltage output levels (Vs, Vs/2, 0, -Vs/2, -Vs) are generated.
a) Maximum positive output Vs: Disp1 is ON, connecting the load positive terminal to Vs,
and Disp4 is ON, connecting the load negative terminal to ground. All other controlled switches
are OFF; the voltage applied to the load terminals is Vs.
b) Half-level positive output, Vs/ 2: The auxiliary switch, Disp5 is ON, connecting the load
positive terminal to point A, through diodes D5 and D8, and Disp4 is ON, connecting the load
negative terminal to ground. All other controlled switches are OFF; the voltage applied to the
load terminals is Vs/ 2.
c) Zero output: The two main switches Disp3 and Disp4 are ON, short-circuiting the load. All
other controlled switches are OFF; the voltage applied to the load terminals is zero.
d) Half-level negative output, -Vs/ 2: The auxiliary switch, Disp5 is ON, connecting the load
positive terminal to point A, through diodes D6 and D7, and Disp2 is ON, connecting the load
negative terminal to. All other controlled switches are OFF; the voltage applied to the load
terminals is –Vs/2.

e) Maximum negative output: Disp2 is ON, connecting the load negative terminal to, and
Disp3 is ON, connecting the load positive terminal to ground. All other controlled switches are
OFF; the voltage applied to the load terminals is (-Vs).
The five-level inverter can operate in a very wide modulation frequency range.
 The lower operating frequencies, below 10 kHz, will be appropriate for high power
applications where low speed power devices will be used.
 The upper operating frequency range, up to 200 kHz, will be appropriate for medium
and low power applications such as uninterruptible power supply (UPS) high speed
devices (fast IGBTs or POWERFETs) will be used, reducing the size and the cost of
the output filters.
This topology configuration consists of two high step-up DC/DC converters
connected to their individual DC bus capacitor and a simplified multilevel inverter. Input
sources, DER module 1, and DER module 2 are connected to the inverter followed a linear
resistive load through the high step-up DC/DC converters. The studied simplified five-level
inverter is used instead of a conventional phase disposition (PD) pulse width modulated (PWM)
inverter because it offers strong advantages such as improved output waveforms, smaller filter
size, and lower electromagnetic interference and THD. It should be noted that, by using the
independent voltage regulation control of the individual high step-up converter, voltage
balance control for the two bus capacitors Cbus1, Cbus2 can be achieved naturally.
4.2. HIGH STEP-UP CONVERTER STAGE:
In this study, high step-up converter topology in is introduced to boost and stabilize the
output DC voltage of various DERs such as PV and fuel cell modules for employment of the
proposed simplified multilevel inverter. The architecture of a high step-up converter initially
introduced from, depicted in Fig 4.1, and is composed of different converter topologies: boost,
fly back, and a charge pump circuit. The coupled inductor of the high step-up converter in Fig.
4.1 can be modeled as an ideal transformer, a magnetizing inductor, and a leakage inductor.
According to the voltage seconds balance condition of the magnetizing inductor, the voltage of
the primary winding can be derived as,
------------------- (1)

where Vin represents each the low-voltage DC energy input source, and voltage of the
secondary winding is
----------- (2)
Similar to that of the boost converter, the voltage of the charge-pump capacitor Cpump and
clamp capacitor Cc can be expressed as
-------------- (3)
Hence, the voltage conversion ratio of the high step-up converter, named input voltage to bus
voltage ratio, can be derived as
-------- ------- (4)
4.2.1 Simplified Multilevel Inverter Stage:
To assist in solving problems caused by cumbersome power stages and complex control
circuits for conventional multilevel inverters, this work reports a new single-phase multi string
topology, presented as a new basic circuitry in Fig. 4.2. Referring to Fig. 4.3, it should be
assumed that, in this configuration the two capacitors in the capacitive voltage divider are
connected directly across the DC bus, and all switching combinations are activated in an output
cycle. The dynamic voltage balance between the two capacitors is automatically controlled by
the preceding high step-up converter stage. Then, we can assume Vs1=Vs2=Vs. This topology
includes six power switches—two fewer than the CCHB inverter with eight power switches—
which drastically reduces the power circuit complexity and simplifies modulator circuit design
and implementation. The PD PWM control scheme is introduced to generate switching signals
and to produce five output-voltage levels: zero, VS, 2VS, -VS, and -2VS.

Figure 4.2 Basic five-level inverter circuitry.
Figure 4.3: Carrier signals and reference signal to generate PWM signals
This inverter topology uses two carrier signals and one reference to generate PWM
signals for the switches. The triangular wave form is the carrier signal and sine waves are
reference signal.

Figure 4.4 Modulation strategy: (a) carrier/reference signals; (b) modulation logic
The modulation strategy and its implemented logic scheme in Fig. 4.4 (a) and (b) are a
widely used alternative for phase disposition modulation. With the exception of an offset value
equivalent to the carrier signal amplitude, two comparators are used in this scheme with
identical carrier signals Vtri1 and Vtri2 to provide high-frequency switching signals for
switches Sa1, Sb1, Sa3 and Sb3. Another comparator is used for zero crossing detection to
provide line-frequency switching signals for switches Sa2 and Sb2. For convenient illustration,
the switching function of the switch in Fig.1. 3 is defined as follows:

----------- (5)
----------- (6)
Table 4.1 lists switching combinations that generate the required five output levels. The
corresponding operation modes of the multilevel inverter stage are described clearly as follows:
(1) Maximum positive output, 2VS: Active switches Sa2, Sb1, and Sb3 are on; the voltage
applied to the L-C output filter is 2VS.
(2) Half-level positive output, +Vs: This output condition can be induced by two different
switching combinations. One switching combination is such that active switches Sa2,
Sb1, Sa3 are on; the other is such that active switches Sa2, Sa1, Sb3 are on. During this
operating stage, the voltage applied to the L-C output filter is +Vs.
(3) Zero output, 0: This output condition can be formed by either of the two switching
structures. Once the left or right switching leg is on, the load will be short-circuited,
and the voltage applied to the load terminals is zero.
(4) Half-level negative output, -Vs: This output condition can be induced by either of the
two different switching combinations. One switching combination is such that active
switches Sa1, Sb2, Sb3 are on; the other is such that active switches Sa3, Sb1, Sb2 are
on.
(5) Maximum negative output, -2Vs: During this stage, active switches Sa1, Sa3, and Sb2
are on, and the voltage applied to the L-C output filter is -2Vs. In these operations, it
can be observed that the open voltage stress of the active power switches Sa1, Sa3, Sb1,
Sb3 are equal to input voltage VS; moreover, the main active switches Sa2 and Sb2 are
operated at the line frequency. Hence, the resulting switching losses of the new
topology are reduced naturally, and the overall conversion efficiency is improved.

Table 4.1 Switching Combinations
To verify the feasibility of the single-phase five-level inverter, a widely used software
program PSIM is applied to simulate the circuit according to the previously mentioned
operation principle.
The control signal block is shown in Fig.2.8; m(t) is the sinusoidal modulation signal.
Both Vtri1 and Vtri2 are the two triangular carrier signals.
The peak value and frequency of the sinusoidal modulation signal are given as
mpeak=0.7 and fm=60Hz, respectively. The peak-to-peak value of the triangular modulation
signal is equal to 1, and the switching frequency ftri1 and ftri2 are both given as 1.8kHz. The
two input voltage sources feeding from the high step-up converter is controlled at 100V, i.e.
Vs1=Vs2=100V. The simulated waveform of the phase voltage with five levels is shown in Fig.
4.5. The switch voltages of Sa1, Sa2, Sa3, Sb1, Sb2, and Sb3 are all shown in Fig. 4.4. It is
evident that the voltage stresses of the switches Sa1, Sa3, Sb1, and Sb3 are all equal to 100V,
and only the other two switches Sa2, Sb2 must be 200V voltage stress.

Figure 4.5 Simulated waveforms of phase voltage VAB of inverter stage [Scale:
100V/div]
It is evident that the voltage stresses of the switches Sa1, Sa3, Sb1, and Sb3 are all equal
to 100V, and only the other two switches Sa2, Sb2 must be 200V voltage stress.

Figure 4.6 Simulated waveforms of switch voltage for inverter stage within a line
period. [Scale: 100V/div]
--------- (7)
where tc (on) and tc (off) are the turn-on and turn-off crossover intervals, respectively; VDS is
the voltage across the switch; and Io is the entire current which flows through the switch.
Compared with the CCHB circuit topology as shown in Fig. 4.6, the voltage stresses of the
eight switches of the CCHB inverter are all equal to Vs. For simplification, both the proposed
circuit and CCHB inverter are operated at the same turn-on and turn-off crossover intervals
and at the same load Io. Then, the average switching power loss Ps is proportional to VDS and
fs as
----------- (8)

According to Eq. (8) and Table IV, the switching losses of the CCHB inverter from eight
switches can be obtained as
---------- (9)
Figure 4.7 Five-level inverter topology of CCHB inverter.

Table 4.2. Harmonics of VAB for CCHB Inverter
The phase shift PWM technique is adopted for the CCHB Inverter. Both of the CCHB
multilevel inverter and the studied multilevel inverter are operated in the same condition,
including the same switching frequency 18kHz, the same modulation index ma, the same input
voltage VS=100V and output L-C filter, Lo=420uH, Co=4.7uF. Table II and Table III show
the harmonic components and THD for the CCHB multilevel inverter and the studied
multilevel inverter, respectively. It follows from Table 4.2 and Table 4.3; one can find that the
studied multilevel inverter has lower THD than the CCHB multilevel inverter. It implies that
the output waveform is improved and smaller filter size can be used. Finally, for further
revealing the potential merits of the studied multi string multilevel inverter.
Table 4.3. Harmonics of VAB for New Multilevel Inverter

Table 4.4. Comparisons of Two Multilevel Inverters
Table 4.4 is provided to summarize comparisons of the switch/diode number, voltage

stress, switching losses for the CCHB multilevel inverter and the simplified single-phase five-
level inverter.
The specifications of the two preceding high step-up DC/DC converters are
(a) Input voltage 30V;
(b) Controlled output voltage 100V; and
(c) Switching frequency 85kHz.
The corresponding specifications of the simplified multilevel DC/AC inverter stage are
(1) Output power, Po=230W;
(2) Input voltage, Vs=100V;
(3) Output voltage, vo=110Vrms;
(4) Line frequency, fm=60Hz;
(5) Switching frequency, fs=40kHz; and
(6) Peak modulation index, mpeak=0.76.

For better understanding, the guidelines and considerations of the DC-link capacitance and the
use of an L-C output filter at the output are described as follows.
4.3 Sizing DC-link capacitor

For the discussed two-stage DC/AC conversion system, the DC-link capacitance is
sized to keep voltage fluctuations within specified limits to prevent over-voltage on the DC
bus. To calculate the relationship between capacitance and voltage limits, the net power
flowing into the bus capacitor, i.e. DC link capacitor, is expressed as,
------------ (10)
Where, PDER is the total output power of the DER modules, and Vo and Io are the peak AC-
side quantities.
----------- (11)
Assuming a steady-state operating condition whereby the net average power flow is zero, the
instantaneous power flow into the bus capacitance Cbus is PDER cos 2wt . Integrating this
expression provides the energy, and equating the peak change in energy stored in the capacitor
with,
------------- (12)
4.4 Choice of output L-C filter:

The output L-C filter is tuned to below the switching frequency as follows:
----------- (13)
where fs is the switching frequency, and Lo and Co are inductance and capacitance of the output
L-C filter, respectively. The experimental results of the simplified single-phase inverter stage
operated at the rated output power are shown in Figs. 4.2 -2.4.

Figure 4.8 Measured waveforms of PWM switching signals for inverter stage. [Scale:
10V/div, Time: 5ms/div]

Figure 4.9 Measured waveforms of voltage stresses of active switches for inverter
stage. [Scale: 200V/div, Time: 5ms/div]
Figures 4.8 - 4.9 show the PWM signals and voltage stresses of the six power
switches for the five-level inverter, respectively. It is evident that the voltage stresses of the
switches Sa1, Sa3, Sb1, and Sb3 are all equal to 100V, and only the other two switches Sa2,
Sb2 must be 200V voltage stress

Figure 4.10 Measured waveforms of output voltage vo, output current io, and
voltage applied to L-C filter terminal VAB. [Time: 5ms/div]
Fig. 4.10 shows steady state waveforms of output voltage vo, output current io, and the
voltage applied to L-C output filter terminal VAB, respectively, for the inverter with a resistive
load of 51Ω. As can be seen in Fig. 1.14, the waveform shows the desired five voltage levels:
200V, 100V, 0V, -100V, and -200V.
The measured RMS value of vo is approximately 110V, while the measured RMS value
of io is approximately 2.12A.
The conversion efficiency of the implemented inverter and THD of the output voltage
measured in this case are approximately 96% and 3%, respectively.
This work reports a newly-constructed single-phase multi string multilevel inverter
topology that produces a significant reduction in the number of power devices required to
implement multilevel output for DERs.
The studied inverter topology offers strong advantages such as improved output
waveforms, smaller filter size, and lower EMI and THD. Simulation and experimental results
show the effectiveness of the proposed solution.

CHAPTER 5
MATLAB SOFTWARE
5.0 INTRODUCTION
MATLAB is a high-performance language for technical computing. It integrates computation,

visualization, and programming in an easy-to-use environment where problems and solutions
are expressed in familiar mathematical notation. Typical uses include-
 Math and computation

 Algorithm development
 Data acquisition
 Modeling, simulation, and prototyping
 Data analysis, exploration, and visualization
 Scientific and engineering graphics
MATLAB is an interactive system whose basic data element is an array that does not require
dimensioning. This allows solving many technical computing problems, especially those with
matrix and vector formulations, in a fraction of the time it would take to write a program in a
scalar non-interactive language such as C or FORTRAN.
5.1 MATLAB PARTS
The MATLAB system consists of six main parts:
5.1.1 Development Environment
This is the set of tools and facilities that help to use MATLAB functions and files. Many of
these tools are graphical user interfaces. It includes the MATLAB desktop and Command
Window, a command history, an editor and debugger, and browsers for viewing help, the
workspace, files, and the search path.
5.1.2 The MATLAB Mathematical Function Library
This is a vast collection of computational algorithms ranging from elementary functions, like
sum, sine, cosine, and complex arithmetic, to more sophisticated functions like matrix inverse,
matrix Eigen values, Bessel functions, and fast Fourier transforms.

5.1.3 The MATLAB Language
This is a high-level matrix/array language with control flow statements, functions, data
structures, input/output, and object-oriented programming features. It allows both
"programming in the small" to rapidly create quick and dirty throw-away programs, and
"programming in the large" to create large and complex application programs.
5.1.4 Graphics
MATLAB has extensive facilities for displaying vectors and matrices as graphs, as well as
annotating and printing these graphs. It includes high-level functions for two-dimensional and
three-dimensional data visualization, image processing, animation, and presentation graphics.
It also includes low-level functions that allow to fully customize the appearance of graphics as
well as to build complete graphical user interfaces on MATLAB applications.
5.1.5 The MATLAB Application Program Interface (API)
This is a library that allows writing in C and FORTRAN programs that interact with MATLAB.
It includes facilities for calling routines from MATLAB (dynamic linking), calling MATLAB
as a computational engine, and for reading and writing MAT-files.
5.1.6 MATLAB Documentation
MATLAB provides extensive documentation, in both printed and online format, to help to
learn about and use all of its features. It covers all the primary MATLAB features at a high
level, including many examples. The MATLAB online help provides task -oriented and
reference information about MATLAB features. MATLAB documentation is also available in
printed form and in PDF format.
5.1.7 Mat lab tools
(i) Three phase source block

The Three-Phase Source block implements a balanced three-phase voltage source with
internal R-L impedance. The three voltage sources are connected in Y with a neutral connection
that can be internally ground.
(ii) VI measurement block
The Three-Phase V-I Measurement block is used to measure three-phase voltages and
currents in a circuit. When connected in series with three-phase elements, it returns the three
phase-to-ground or phase-to-phase voltages and the three line currents
Display signals generated during a simulation. The Scope block displays its input with
respect to simulation time. The Scope block can have multiple axes (one per port); all axes
have a common time range with independent y-axes. The Scope allows you to adjust the
amount of time and the range of input values displayed. You can move and resize the Scope
window and you can modify the Scope's parameter values during the simulation
(iii) Scope

(iv) Three-Phase Series RLC Load
The Three-Phase Series RLC Load block implements a three-phase balanced load as a
series combination of RLC elements. At the specified frequency, the load exhibits constant
impedance. The active and reactive powers absorbed by the load are proportional to the square
of the applied voltage.
(v) Three-Phase Breaker block
The Three-Phase Breaker block implements a three-phase circuit breaker where the
opening and closing times can be controlled either from an external Simulink signal or from an
internal control signal.
(vi) Gain block
lock the Gain block multiplies the input by a constant value (gain). The input and the gain can
each be a scalar, vector, or matrix.

CHAPTER 6
SIMULATION AND RESULTS
6.0 BLOCK DIAGRAM AND SIMULATION CIRCUIT

Here the simulation of Five Level Single phase multi-string multilevel inverter is
carried out in MATLAB Software. The block diagram is shown in Figure 6.1 and simulation
diagram is shown in Figure 63
Figure 6.1 MATLAB/Simulink model of single-phase multi-string multilevel inverter

The basic simulation circuit, Figure 6.3 is a multi-string inverter with combination of
six switches. Based on the selection of switches in the circuit output voltage are obtained.
Figure 6.2 Output voltage waveform of 5 level multi sting inverter using PWM
It is the reference output voltage wave form to be obtained by the 5 level multistring string
inverter using pulse width modulation.

Figure 6.3 Simulation circuit of single-phase multistring multilevel inverter

6.1 SIMULATION RESULTS
Figure 6.4 Voltage across switch S6
Maximum positive output, 2VS: Active switches S3, S2, and Sb6 are on; the voltage
applied to the L-C output filter is 2VS.
Maximum negative output, -2Vs: During this stage, active switches Sa1, Sa3, and Sb2
are on, and the voltage applied to the L-C output filter is -2Vs. In these operations, it can be
observed that the open voltage stress of the active power switches Sa1, Sa3, Sb1, Sb3 are
equal to input voltage VS

Figure 6.5 Voltage across Switch S4
Half-level positive output, +Vs: This output condition can be induced by two different
switching combinations. One switching combination is such that active switches Sa2, Sb1,
Sa3 are on; the other is such that active switches Sa2, Sa1, Sb3 are on. During this operating
stage, the voltage applied to the L-C output filter is +Vs.

Figure 6.6 Voltage across switch S6
Half-level negative output, -Vs: This output condition can be induced by either of the
two different switching combinations. One switching combination is such that active switches
Sa1, Sb2, Sb3 are on; the other is such that active switches Sa3, Sb1, Sb2 are on.

Figure 6.7 Output voltage of the multilevel inverter using PWM
Figure 6.7 shows the output voltage waveform of the inverter after pulse width
modulation. It is evident that the voltage stresses of the switches Sa1, Sa3, Sb1, and Sb3 are all
equal to 100V, and only the other two switches Sa2, Sb2 must be 200V voltage stress.

Figure 6.8 The final output voltage of Five level Single phase Multistring Multilevel
Inverter
Figure 6.7 shows the final output voltage of a single-phase multistring multilevel
inverter after using the filter.

Figure 6.9 Output Voltage and Current waveforms of single-phase multi-string

multilevel inverter
Fig. 4.10 shows steady-state waveforms of output voltage vo, output current io, and the voltage
applied to the L-C output filter terminal respectively.

CONCLUSION
This project presents a newly constructed single-phase multi-string multilevel inverter

topology that produces a significant reduction in the number of power devices required to
implement multilevel output for DERs. The studied inverter topology offers strong advantages
such as improved output waveforms, smaller filter sizes, and lower EMI and THD. Simulation
and experimental results show the effectiveness of the proposed solution. The proposed
converter produces more voltage levels with a smaller number of switches compared to the H-
bridge configuration. This will reduce the number of gate drivers and protection circuits which
in turn reduces the cost and complexity of the circuit. Finally, a single-phase multi-string
multilevel inverter of the proposed circuit is shown for evaluating the drive performance, and
simulation results are presented.

SCOPE FOR FUTURE WORK
Multilevel inverters offer higher efficiency and better harmonic performance compared
to traditional inverters. By using multilevel techniques in single-phase systems, it becomes
possible to efficiently integrate and manage DERs such as solar photovoltaic (PV) systems,
wind turbines, and energy storage systems.
With the increasing penetration of renewable energy sources in the grid, there's a
growing need for efficient and reliable inverters capable of handling these energy sources.
Single-phase multi-string multilevel inverters can efficiently integrate multiple DERs, ensuring
optimal power conversion and grid integration.
Modern grid requirements necessitate inverters to provide various grid support

functions such as voltage regulation, frequency control, and reactive power compensation.
Multilevel inverters can be designed with advanced control strategies to provide these
functionalities, enhancing the stability and reliability of the grid.
The development of advanced control techniques such as model predictive control

(MPC), artificial intelligence (AI)-based control, and adaptive control algorithms can further
enhance the performance of single-phase multi-string multilevel inverters. These techniques
enable optimal operation of the inverters under varying operating conditions and grid
disturbances.
Distributed energy resources play a crucial role in enhancing the resilience and
reliability of the power system, especially in the face of natural disasters and grid disturbances.
Single-phase multi-string multilevel inverters, with their ability to integrate multiple DERs and
provide grid support functions, contribute to improving the overall resilience and reliability of
the grid.

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A SIMPLIFIED SINGLE-PHASE MULTISTRING MULTILEVEL INVERTER TOPOLOGY FOR

DISTRIBUTED ENERGY RESOURCES

Figure 1.1 Configuration of multi-string multilevel inverter

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Figure 2. 1 Microgrid Configuration

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2.1 MICROGRID ARCHITECTURE AND OPERATIONS:

2.2 POWER ELECTRONICS IN FUEL CELL SYSTEMS:

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2.2.2 Power Electronic Conditioning System for Fuel Cells

Figure 2.2 Schematic of fuel cell power electronic conditioning systems,

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2.3 POWER ELECTRONICS IN PHOTOVOLTAIC (PV) SYSTEMS:

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2.4 THE CONFIGURATION OF PV SYSTEMS

Figure 2. 3 (a) String inverter

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2.4.2 String Inverters:

Fig2. 3(b)Multilevel inverters

Figure 2.3(c) ac-module

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OVERVIEW OF MULTILEVEL INVERTER AND PWM

3.1. UNIFIED CONVERTER THEORY

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Two obvious restrictions are enforced by some basic laws of electricity.

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3.2 VOLTAGE SOURCE OR CURRENT SOURCE INVERTER

Figure 3.1 Half-bridge configurations.

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Figure 3.2 Full-bridge configuration.

In full-bridge configuration, turning on S1 and S4 and turning off S2 and S3 give a

Conducting Switches Load Voltage VAB

Table 3.1 Load voltage with corresponding conducting switches.

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Figure 3.3 Output waveform of half-bridge configuration.

Figure 3.4 Output waveform of full-bridge configuration.

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3.3 MULTI LEVEL VOLTAGE SOURCE INVERTER

1. Diode-Clamped Multilevel Inverter.

3.3.1. Diode-Clamped Multilevel Inverter (DCMI)

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Figure 3.5 A single-phase five-level diode-clamped inverter

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Output Switch State

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3.3.2. Flying-Capacitor Multilevel Inverter (FCMI)

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Figure 3.6 A single-phase five-level flying-capacitor inverter.

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The flying capacitor family of converters appears very attractive:

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3.3.3. Cascaded-Inverters with Separated DC Sources

Figure 3.7 Single-phase structure of a two-cell cascaded inverter.

Each SDCS is associated with a single-phase full-bridge inverter. The ac terminal

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