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    Dice Game in VHDL

    Uploaded by

    hassan ullah khan

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Dice Game in VHDL

    Uploaded by

    hassan ullah khan
    91 views6 pages

    Copyright

    © © All Rights Reserved

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    DOCX, PDF, TXT or read online from Scribd

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    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    91 views6 pages

    Dice Game in VHDL

    Uploaded by

    hassan ullah khan

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    You are on page 1of 6

    Section # 01:

    Block Diagram of DICE GAME :

    Design the individual part of the each part:

    1. Control Unit Results:

    2. Counter and Adder Results:


    3. Pointer Register:

    4. Comparator and test Logic Result:


    5. TOP Module of the DICE game Code:
    VHDL Code :

    ----------------------------------------------------------------------------------
    -- Company:
    -- Engineer:
    --
    -- Create Date: 04/27/2024 01:17:35 PM
    -- Design Name:
    -- Module Name: DICE_GAME_TOP - Behavioral
    -- Project Name:
    -- Target Devices:
    -- Tool Versions:
    -- Description:
    --
    -- Dependencies:
    --
    -- Revision:
    -- Revision 0.01 - File Created
    -- Additional Comments:
    --
    ----------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    --use IEEE.NUMERIC_STD.ALL;
    -- Uncomment the following library declaration if instantiating
    -- any Xilinx leaf cells in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;
    entity DICE_GAME_TOP is
    Port (
    clk, reset: in std_logic;
    Rb : in std_logic;
    win : out std_logic;
    loss : out std_logic
    );
    end DICE_GAME_TOP;
    architecture Behavioral of DICE_GAME_TOP is
    -- two counter and adder module
    component Counter_Adder
    port ( clk: in std_logic;
    reset: in std_logic;
    Roll: in std_logic;
    sum: out integer range 2 to 12);
    end component;
    -- Pointer Register Module Components
    component PointerRegister
    port (
    Sum : in integer range 2 to 12;
    Sp : in std_logic;
    LockedSum :out integer range 2 to 12
    );
    end component;
    -- Comparator and test Module Component
    component Comparator
    port (
    Sum,LockedSum:in integer range 2 to 12;
    Eq,D7,D711,D2312:out std_logic
    );
    end component;

    -- Counter UNIT Component


    component ControllerUNIT
    port (
    clk : in std_logic;
    reset: in std_logic;
    Rb : in std_logic;
    D7, D711, D2312 : in std_logic; -- ('1' if sum of dice is 7) ('1' if sum is 7 or 11)
    Eq : in std_logic;
    Roll : out std_logic;
    SP : out std_logic; -- sum to store here
    win : out std_logic;
    loss : out std_logic
    );
    end component;
    -- signal Declaration for the modules connecition
    signal Roll_C_C: std_logic;
    signal Sum_PR_T: integer range 2 to 12;
    signal D7_T_C: std_logic;
    signal D711_T_C: std_logic;
    signal D2312_T_C: std_logic;
    signal Eq_T_C: std_logic;
    signal Sp_C_PR: std_logic;
    signal LockSum_T : integer range 2 to 12;
    begin
    -- Module instantiation
    CNT_UNIT : ControllerUNIT port map (
    clk => clk,
    reset => reset,
    Rb => Rb,
    D7 => D7_T_C,
    D711 => D711_T_C,
    D2312 => D2312_T_C,
    Eq => Eq_T_C,
    Roll => Roll_C_C,
    SP => Sp_C_PR,
    win => win,
    loss => loss
    );
    CADR_UNIT : Counter_Adder port map (
    clk => clk,
    reset => reset,
    Roll => Roll_C_C,
    sum => Sum_PR_T
    );
    PR_UNIT : PointerRegister port map (
    Sum => Sum_PR_T,
    Sp => Sp_C_PR,
    LockedSum => LockSum_T
    );
    COMT_UNIT : Comparator port map (
    Sum => Sum_PR_T,
    LockedSum => LockSum_T,
    Eq => Eq_T_C,
    D7 => D7_T_C,
    D711 => D711_T_C,
    D2312 => D2312_T_C
    );
    end Behavioral;

    synthesis Design of the DICE Game:


    Final Simulation Result of the DICE game In VHDL:

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