fpga4student.

com
-- FPGA projects, VHDL projects, Verilog projects
-- VHDL code for full adder
-- Structural code for full adder
library ieee;
use ieee.std_logic_1164.all;
entity Full_Adder_Structural_VHDL is
port(
X1, X2, Cin : in std_logic;
S, Cout : out std_logic
);
end Full_Adder_Structural_VHDL;
architecture structural of Full_Adder_Structural_VHDL is
signal a1, a2, a3: std_logic;
begin
a1 <= X1 xor X2;
a2 <= X1 and X2;
a3 <= a1 and Cin;
Cout <= a2 or a3;
S <= a1 xor Cin;
end structural;
Library IEEE;
USE IEEE.Std_logic_1164.all;
-- fpga4student.com
-- FPGA projects, VHDL projects, Verilog projects
-- VHDL code for full adder
-- Testbench code of the structural code for full adder
entity Testbench_structural_adder is
end Testbench_structural_adder;

architecture behavioral of Testbench_structural_adder is

component Full_Adder_Structural_VHDL
port(
X1, X2, Cin : in std_logic;
S, Cout : out std_logic
);
end component;
signal A,B,Cin: std_logic:='0';
 signal S,Cout: std_logic;
begin
structural_adder: Full_Adder_Structural_VHDL port map
(
X1 => A,
X2 => B,
Cin => Cin,
S => S,
Cout => Cout
);
process
begin
A <= '0';
B <= '0';
Cin <= '0';
wait for 100 ns;
A <= '0';
B <= '0';
Cin <= '1';
wait for 100 ns;
A <= '0';
B <= '1';
Cin <= '0';
wait for 100 ns;
A <= '0';
B <= '1';
Cin <= '1';
wait for 100 ns;
A <= '1';
B <= '0';
Cin <= '0';
wait for 100 ns;
A <= '1';
B <= '0';
Cin <= '1';
wait for 100 ns;
A <= '1';
B <= '1';
 Cin <= '0';
wait for 100 ns;
A <= '1';
B <= '1';
Cin <= '1';
wait for 100 ns;
end process;

end behavioral;

The VHDL code for the full adder using the behavioral
model:
-- fpga4student.com
-- FPGA projects, VHDL projects, Verilog projects
-- VHDL code for full adder
-- Behavioral code for full adder
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Full_Adder_Behavioral_VHDL is
port(
X1, X2, Cin : in std_logic;
S, Cout : out std_logic
);
end Full_Adder_Behavioral_VHDL;
architecture Behavioral of Full_Adder_Behavioral_VHDL is
signal tmp: std_logic_vector(1 downto 0);
begin
process(X1,X2,Cin)
begin
tmp <= ('0'& X1) + ('0'& X2) +('0'& Cin) ;
end process;
S <= tmp(0);
Cout <= tmp(1);
end Behavioral;
Library IEEE;
USE IEEE.Std_logic_1164.all;
-- fpga4student.com
-- FPGA projects, VHDL projects, Verilog projects
-- VHDL code for full adder
-- Testbench code of the behavioral code for full adder
entity Testbench_behavioral_adder is
end Testbench_behavioral_adder;

architecture behavioral of Testbench_behavioral_adder is

component Full_Adder_Behavioral_VHDL
port(
X1, X2, Cin : in std_logic;
S, Cout : out std_logic
);
end component;
signal A,B,Cin: std_logic:='0';
signal S,Cout: std_logic;
begin
behavior_adder: Full_Adder_Behavioral_VHDL port map
(
X1 => A,
X2 => B,
Cin => Cin,
S => S,
Cout => Cout
);
process
begin
A <= '1';
B <= '1';
Cin <= '1';
wait for 50 ns;
A <= '1';
B <= '1';
Cin <= '0';
wait for 50 ns;
A <= '1';
B <= '0';
Cin <= '1';
wait for 50 ns;
A <= '0';
B <= '0';
Cin <= '0';
wait for 50 ns;
A <= '0';
B <= '0';
Cin <= '1';
 wait for 50 ns;
A <= '0';
B <= '1';
Cin <= '0';
wait for 50 ns;
A <= '0';
B <= '1';
Cin <= '1';
wait for 50 ns;
A <= '1';
B <= '0';
Cin <= '0';
wait for 50 ns;

end process;

end behavioral;

VHDL code for the comparator:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- VHDL project: VHDL code for comparator
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects

entity comparator is
port (
clock: in std_logic;
-- clock for synchronization
A,B: in std_logic_vector(7 downto 0);
-- Two inputs
IAB: in std_logic; -- Expansion input ( Active low)
Output: out std_logic -- Output = 0 when A = B
);
end comparator;
architecture Behavioral of comparator is
signal AB: std_logic_vector(7 downto 0); -- temporary variables
signal Result: std_logic;
begin

AB(0) <= (not A(0)) xnor (not B(0));

-- combinational circuit
AB(1) <= (not A(1)) xnor (not B(1));
AB(2) <= (not A(2)) xnor (not B(2));
AB(3) <= (not A(3)) xnor (not B(3));
 AB(4) <= (not A(4)) xnor (not B(4));
AB(5) <= (not A(5)) xnor (not B(5));
AB(6) <= (not A(6)) xnor (not B(6));
AB(7) <= (not A(7)) xnor (not B(7));
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
process(clock)
begin
if(rising_edge(clock))then
if(AB = x"FF" and IAB = '0') then
-- check whether A = B and IAB =0 or not
Result <= '0';
else
Result <= '1';
end if;
end if;
end process;
Output <= Result;
end Behavioral;

Testbench VHDL code for the comparator:

--------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for comparator
ENTITY tb_comparator IS
END tb_comparator;
ARCHITECTURE behavior OF tb_comparator IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT comparator
PORT(
clock : IN std_logic;
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
IAB : IN std_logic;
Output : OUT std_logic
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal IAB : std_logic := '0';
--Outputs
 signal Output : std_logic;
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: comparator PORT MAP (
clock => clock,
A => A,
B => B,
IAB => IAB,
Output => Output
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= x"AA";
B <= x"BB";
wait for clock_period*10;
B <= x"AA";
-- insert stimulus here
wait;
end process;
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
END;

The instruction set of the 16-bit ALU is as follows:

1. ADD: ABUS + BBUS -> ALUOUT
2. SUB: ABUS - BBUS -> ALUOUT
3. AND: ABUS & BBUS -> ALUOUT
4. OR: ABUS | BBUS -> ALUOUT
5. XOR: ABUS ^ BBUS -> ALUOUT
6. NOT: ~ABUS -> ALUOUT
7. MOV: ABUS -> ALUOUT
The addition/ subtraction of the 16-bit ALU is designed and
implemented using the Verilog N-bit Adder.
VHDL code for 16-bit ALU:
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for 16-bit ALU
-- Top level VHDL code for 16-bit ALU
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- 16-bit ALU
entity ALU is
port (
ABUS: in std_logic_vector(15 downto 0); -- ABUS data input of the 16-bit
ALU
BBUS: in std_logic_vector(15 downto 0); -- BBUS data input of the 16-bit
ALU
ALUctrl: in std_logic_vector(3 downto 0); -- ALUctrl control input of the
16-bit ALU
ALUOUT: out std_logic_vector(15 downto 0) -- 16-bit data output of the 16-
bit ALU
);
end ALU;

architecture Behavioral of ALU is

-- N-bit Adder in Verilog
component N_bit_adder is
generic (
N: integer:=32
);
port( input1: in std_logic_vector(N-1 downto 0);
input2: in std_logic_vector(N-1 downto 0);
answer: out std_logic_vector(N-1 downto 0)
);
end component N_bit_adder;
signal BBUS_not: std_logic_vector(16-1 downto 0);
signal tmp_out1: std_logic_vector(16-1 downto 0);
signal tmp_out2: std_logic_vector(16-1 downto 0);
signal tmp: std_logic_vector(16-1 downto 0);
begin
-- instantiate Verilog N-bit Adder in VHDL code
u1_N_bit_adder: N_bit_adder generic map ( N => 16) -- ABUS + BBUS
port map( input1 => ABUS, input2 => BBUS,answer => tmp_out1 );
u2_N_bit_adder: N_bit_adder generic map ( N => 16) -- ABUS + (~BBUS)
port map( input1 => ABUS, input2 => BBUS_not,answer => tmp_out2 );
u3_N_bit_adder: N_bit_adder generic map ( N => 16) -- ABUS + (~BBUS) + 1 =
ABUS - BBUS
port map( input1 => tmp_out2, input2 => x"0001",answer => tmp );
BBUS_not <= not BBUS;
-- Other instructions of the 16-bit ALU in VHDL
process(ALUctrl,ABUS,BBUS,tmp_out1,tmp)
begin
case(ALUctrl) is
when "0000" => ALUOUT <= tmp_out1; -- ADD
when "0001" => ALUOUT <= tmp ;-- SUB
when "0010" => ALUOUT <= ABUS and BBUS; -- AND
when "0011" => ALUOUT <= ABUS or BBUS; -- OR
when "0100" => ALUOUT <= ABUS xor BBUS; -- XOR
when "0101" => ALUOUT <= not ABUS; -- NOT
when "0110" => ALUOUT <= ABUS; -- MOVE
when others => ALUOUT <= tmp_out1;
end case;
end process;

end Behavioral;

Testbench VHDL code for 16-bit ALU:

-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for 16-bit ALU
-- Testbench VHDL code for 16-bit ALU
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Testbench
ENTITY tb_ALU IS
END tb_ALU;

ARCHITECTURE behavior OF tb_ALU IS

-- Component Declaration for the 16-bit ALU

COMPONENT ALU
PORT(
ABUS : IN std_logic_vector(15 downto 0);
 BBUS : IN std_logic_vector(15 downto 0);
ALUctrl : IN std_logic_vector(3 downto 0);
ALUOUT : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;

--Inputs
signal ABUS : std_logic_vector(15 downto 0) := (others => '0');
signal BBUS : std_logic_vector(15 downto 0) := (others => '0');
signal ALUctrl : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal ALUOUT : std_logic_vector(15 downto 0);

BEGIN

-- Instantiate the 16-bit ALU

uut: ALU PORT MAP (
ABUS => ABUS,
BBUS => BBUS,
ALUctrl => ALUctrl,
ALUOUT => ALUOUT
);
stim_proc: process
begin
ABUS <= x"000A";
BBUS <= x"0002";
ALUctrl <= x"0";
-- change ALU Control input
for i in 0 to 15 loop
ALUctrl <= ALUctrl + x"1";
wait for 100 ns;
end loop;
ABUS <= x"00F6";
BBUS <= x"000A";
wait;
end process;

END;

code for traffic light controller:

-- fpga4student.com FPGA projects, VHDL projects, Verilog projects
-- VHDL project: VHDL code for traffic light controller
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Traffic ligh system for a intersection between highway and farm way
-- There is a sensor on the farm way side, when there are vehicles,
-- Traffic light turns to YELLOW, then GREEN to let the vehicles cross the
highway
-- Otherwise, always green light on Highway and Red light on farm way
entity traffic_light_controller is
port ( sensor : in STD_LOGIC; -- Sensor
clk : in STD_LOGIC; -- clock
rst_n: in STD_LOGIC; -- reset active low
light_highway : out STD_LOGIC_VECTOR(2 downto 0); -- light outputs of
high way
light_farm: out STD_LOGIC_VECTOR(2 downto 0)-- light outputs of farm
way
--RED_YELLOW_GREEN
);
end traffic_light_controller;
architecture traffic_light of traffic_light_controller is
signal counter_1s: std_logic_vector(27 downto 0):= x"0000000";
signal delay_count:std_logic_vector(3 downto 0):= x"0";
signal delay_10s, delay_3s_F,delay_3s_H, RED_LIGHT_ENABLE,
YELLOW_LIGHT1_ENABLE,YELLOW_LIGHT2_ENABLE: std_logic:='0';
signal clk_1s_enable: std_logic; -- 1s clock enable
type FSM_States is (HGRE_FRED, HYEL_FRED, HRED_FGRE, HRED_FYEL);
-- HGRE_FRED : Highway green and farm red
-- HYEL_FRED : Highway yellow and farm red
-- HRED_FGRE : Highway red and farm green
-- HRED_FYEL : Highway red and farm yellow
signal current_state, next_state: FSM_States;
begin
-- next state FSM sequential logic
process(clk,rst_n)
begin
if(rst_n='0') then
current_state <= HGRE_FRED;
elsif(rising_edge(clk)) then
current_state <= next_state;
end if;
end process;
-- FSM combinational logic
process(current_state,sensor,delay_3s_F,delay_3s_H,delay_10s)
begin
case current_state is
when HGRE_FRED => -- When Green light on Highway and Red light on Farm way
 RED_LIGHT_ENABLE <= '0';-- disable RED light delay counting
YELLOW_LIGHT1_ENABLE <= '0';-- disable YELLOW light Highway delay counting
YELLOW_LIGHT2_ENABLE <= '0';-- disable YELLOW light Farmway delay counting
light_highway <= "001"; -- Green light on Highway
light_farm <= "100"; -- Red light on Farm way
if(sensor = '1') then -- if vehicle is detected on farm way by sensors
next_state <= HYEL_FRED;
-- High way turns to Yellow light
else
next_state <= HGRE_FRED;
-- Otherwise, remains GREEN ON highway and RED on Farm way
end if;
when HYEL_FRED => -- When Yellow light on Highway and Red light on Farm way
light_highway <= "010";-- Yellow light on Highway
light_farm <= "100";-- Red light on Farm way
RED_LIGHT_ENABLE <= '0';-- disable RED light delay counting
YELLOW_LIGHT1_ENABLE <= '1';-- enable YELLOW light Highway delay counting
YELLOW_LIGHT2_ENABLE <= '0';-- disable YELLOW light Farmway delay counting
if(delay_3s_H='1') then
-- if Yellow light delay counts to 3s,
-- turn Highway to RED,
-- Farm way to green light
next_state <= HRED_FGRE;
else
next_state <= HYEL_FRED;
-- Remains Yellow on highway and Red on Farm way
-- if Yellow light not yet in 3s
end if;
when HRED_FGRE =>
light_highway <= "100";-- RED light on Highway
light_farm <= "001";-- GREEN light on Farm way
RED_LIGHT_ENABLE <= '1';-- enable RED light delay counting
YELLOW_LIGHT1_ENABLE <= '0';-- disable YELLOW light Highway delay counting
YELLOW_LIGHT2_ENABLE <= '0';-- disable YELLOW light Farmway delay counting
if(delay_10s='1') then
-- if RED light on highway is 10s, Farm way turns to Yellow
next_state <= HRED_FYEL;
else
next_state <= HRED_FGRE;
-- Remains if delay counts for RED light on highway not enough 10s
end if;
when HRED_FYEL =>
light_highway <= "100";-- RED light on Highway
light_farm <= "010";-- Yellow light on Farm way
RED_LIGHT_ENABLE <= '0'; -- disable RED light delay counting
 YELLOW_LIGHT1_ENABLE <= '0';-- disable YELLOW light Highway delay counting
YELLOW_LIGHT2_ENABLE <= '1';-- enable YELLOW light Farmway delay counting
if(delay_3s_F='1') then
-- if delay for Yellow light is 3s,
-- turn highway to GREEN light
-- Farm way to RED Light
next_state <= HGRE_FRED;
else
next_state <= HRED_FYEL;
-- if not enough 3s, remain the same state
end if;
when others => next_state <= HGRE_FRED; -- Green on highway, red on farm way
end case;
end process;
-- Delay counts for Yellow and RED light
process(clk)
begin
if(rising_edge(clk)) then
if(clk_1s_enable='1') then
if(RED_LIGHT_ENABLE='1' or YELLOW_LIGHT1_ENABLE='1' or
YELLOW_LIGHT2_ENABLE='1') then
delay_count <= delay_count + x"1";
if((delay_count = x"9") and RED_LIGHT_ENABLE ='1') then
delay_10s <= '1';
delay_3s_H <= '0';
delay_3s_F <= '0';
delay_count <= x"0";
elsif((delay_count = x"2") and YELLOW_LIGHT1_ENABLE= '1') then
delay_10s <= '0';
delay_3s_H <= '1';
delay_3s_F <= '0';
delay_count <= x"0";
elsif((delay_count = x"2") and YELLOW_LIGHT2_ENABLE= '1') then
delay_10s <= '0';
delay_3s_H <= '0';
delay_3s_F <= '1';
delay_count <= x"0";
else
delay_10s <= '0';
delay_3s_H <= '0';
delay_3s_F <= '0';
end if;
end if;
end if;
end if;
end process;
-- create delay 1s
process(clk)
begin
if(rising_edge(clk)) then
counter_1s <= counter_1s + x"0000001";
if(counter_1s >= x"0000003") then -- x"0004" is for simulation
-- change to x"2FAF080" for 50 MHz clock running real FPGA
counter_1s <= x"0000000";
end if;
end if;
end process;
clk_1s_enable <= '1' when counter_1s = x"0003" else '0'; -- x"0002" is for
simulation
-- x"2FAF080" for 50Mhz clock on FPGA
end traffic_light;

VHDL Testbench code for traffic light controller:

-- fpga4student.com FPGA projects, VHDL projects, Verilog projects
-- VHDL project: VHDL code for traffic light controller
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Testbench VHDL code for traffic light controller
ENTITY tb_traffic_light_controller IS
END tb_traffic_light_controller;

ARCHITECTURE behavior OF tb_traffic_light_controller IS

-- Component Declaration for the traffic light controller
COMPONENT traffic_light_controller
PORT(
sensor : IN std_logic;
clk : IN std_logic;
rst_n : IN std_logic;
light_highway : OUT std_logic_vector(2 downto 0);
light_farm : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
signal sensor : std_logic := '0';
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
--Outputs
signal light_highway : std_logic_vector(2 downto 0);
signal light_farm : std_logic_vector(2 downto 0);
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the traffic light controller
trafficlightcontroller : traffic_light_controller PORT MAP (
sensor => sensor,
clk => clk,
rst_n => rst_n,
light_highway => light_highway,
light_farm => light_farm
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
rst_n <= '0';
sensor <= '0';
wait for clk_period*10;
rst_n <= '1';
wait for clk_period*20;
sensor <= '1';
wait for clk_period*100;
sensor <= '0';
wait;
end process;

END;

VHDL code for Rising Edge D Flip Flop:

-- FPGA projects using VHDL/ VHDL
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for rising edge D flip flop
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity RisingEdge_DFlipFlop is
port(
 Q : out std_logic;
Clk :in std_logic;
D :in std_logic
);
end RisingEdge_DFlipFlop;
architecture Behavioral of RisingEdge_DFlipFlop is
begin
process(Clk)
begin
if(rising_edge(Clk)) then
Q <= D;
end if;
end process;
end Behavioral;

VHDL code for Rising Edge D Flip-Flop with Synchronous

Reset:
-- FPGA projects using VHDL/ VHDL
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for Rising edge D flip flop with Synchronous Reset input
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity RisingEdge_DFlipFlop_SyncReset is
port(
Q : out std_logic;
Clk :in std_logic;
sync_reset: in std_logic;
D :in std_logic
);
end RisingEdge_DFlipFlop_SyncReset;
architecture Behavioral of RisingEdge_DFlipFlop_SyncReset is
begin
process(Clk)
begin
if(rising_edge(Clk)) then
if(sync_reset='1') then
Q <= '0';
else
Q <= D;
 end if;
end if;
end process;
end Behavioral;

VHDL code for Rising Edge D Flip-Flop with Asynchronous

Reset High Level:
-- FPGA projects using VHDL/ VHDL
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for Rising edge D flip flop with Asynchronous Reset high
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity RisingEdge_DFlipFlop_AsyncResetHigh is
port(
Q : out std_logic;
Clk :in std_logic;
sync_reset: in std_logic;
D :in std_logic
);
end RisingEdge_DFlipFlop_AsyncResetHigh;
architecture Behavioral of RisingEdge_DFlipFlop_AsyncResetHigh is
begin
process(Clk,sync_reset)
begin
if(sync_reset='1') then
Q <= '0';
elsif(rising_edge(Clk)) then
Q <= D;
end if;
end process;
end Behavioral;

VHDL code for Rising Edge D Flip-Flop with Asynchronous

Reset Low Level:
-- FPGA projects using VHDL/ VHDL
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for Rising edge D flip flop with Asynchronous Reset low
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity RisingEdge_DFlipFlop_AsyncResetLow is
port(
Q : out std_logic;
Clk :in std_logic;
sync_reset: in std_logic;
D :in std_logic
);
end RisingEdge_DFlipFlop_AsyncResetLow;
architecture Behavioral of RisingEdge_DFlipFlop_AsyncResetLow is
begin
process(Clk,sync_reset)
begin
if(sync_reset='0') then
Q <= '0';
elsif(rising_edge(Clk)) then
Q <= D;
end if;
end process;
end Behavioral;

VHDL code for Falling Edge D Flip Flop:

-- FPGA projects using VHDL/ VHDL
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for falling edge D flip flop
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity FallingEdge_DFlipFlop is
port(
Q : out std_logic;
Clk :in std_logic;
D :in std_logic
);
end FallingEdge_DFlipFlop;
architecture Behavioral of FallingEdge_DFlipFlop is
begin
process(Clk)
 begin
if(falling_edge(Clk)) then
Q <= D;
end if;
end process;
end Behavioral;

VHDL code for Falling Edge D Flip-Flop with Synchronous

Reset:
-- FPGA projects using VHDL/ VHDL
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for Falling edge D flip flop with Synchronous Reset input
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity FallingEdge_DFlipFlop_SyncReset is
port(
Q : out std_logic;
Clk :in std_logic;
sync_reset: in std_logic;
D :in std_logic
);
end FallingEdge_DFlipFlop_SyncReset;
architecture Behavioral of FallingEdge_DFlipFlop_SyncReset is
begin
process(Clk)
begin
if(falling_edge(Clk)) then
if(sync_reset='1') then
Q <= '0';
else
Q <= D;
end if;
end if;
end process;

end Behavioral;
VHDL code for Falling Edge D Flip-Flop with
Asynchronous Reset High Level:

-- FPGA projects using VHDL/ VHDL

-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for Falling edge D flip flop with Asynchronous Reset high
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity FallingEdge_DFlipFlop_AsyncResetHigh is
port(
Q : out std_logic;
Clk :in std_logic;
sync_reset: in std_logic;
D :in std_logic
);
end FallingEdge_DFlipFlop_AsyncResetHigh;
architecture Behavioral of FallingEdge_DFlipFlop_AsyncResetHigh is
begin
process(Clk,sync_reset)
begin
if(sync_reset='1') then
Q <= '0';
elsif(falling_edge(Clk)) then
Q <= D;
end if;
end process;
end Behavioral;

VHDL code for Falling Edge D Flip-Flop with

Asynchronous Reset Low Level:
-- FPGA projects using VHDL/ VHDL
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for Falling edge D flip flop with Asynchronous Reset low
Library IEEE;
USE IEEE.Std_logic_1164.all;
entity FallingEdge_DFlipFlop_AsyncResetLow is
port(
Q : out std_logic;
Clk :in std_logic;
sync_reset: in std_logic;
D :in std_logic
);
end FallingEdge_DFlipFlop_AsyncResetLow;
architecture Behavioral of FallingEdge_DFlipFlop_AsyncResetLow is
begin
process(Clk,sync_reset)
begin
if(sync_reset='0') then
Q <= '0';
elsif(falling_edge(Clk)) then
Q <= D;
end if;
end process;
end Behavioral;

VHDL code for PWM Generator with Variable Duty Cycle:

-- fpga4student.com: FPGA Projects, Verilog projects, VHDL projects
-- VHDL code for PWM Generator
-- Two de-bounced push-buttons
-- One: increase duty cycle by 10%
-- Another: Decrease duty cycle by 10%
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PWM_Generator is
port (
clk: in std_logic; -- 100MHz clock input
DUTY_INCREASE: in std_logic; -- button to increase duty cycle by 10%
DUTY_DECREASE: in std_logic; -- button to decrease duty cycle by 10%
PWM_OUT: out std_logic -- PWM signal out with frequency of 10MHz
);
end PWM_Generator;

architecture Behavioral of PWM_Generator is

-- D-Flip-Flop for debouncing module
component DFF_Debounce
Port (
CLK : in std_logic;
 en : in std_logic;
D : in std_logic;
Q : out std_logic
);
end component;
signal slow_clk_en: std_logic:='0'; -- slow clock enable for debouncing
signal counter_slow: std_logic_vector(27 downto 0):=(others => '0');--
counter for creating slow clock
signal tmp1,tmp2,duty_inc: std_logic;-- temporary signals for deboucing
signal tmp3,tmp4,duty_dec: std_logic;-- temporary signals for deboucing
signal counter_PWM: std_logic_vector(3 downto 0):=(others => '0');-- counter
for PWM signal
signal DUTY_CYCLE: std_logic_vector(3 downto 0):=x"5";
begin
-- Debouncing process
-- First generate slow clock enable for deboucing (4Hz)
process(clk)
begin
if(rising_edge(clk)) then
counter_slow <= counter_slow + x"0000001";
--if(counter_slow>=x"17D7840") then -- for running on FPGA -- comment when
running simulation
if(counter_slow>=x"0000001") then -- for running simulation -- comment when
running on FPGA
counter_slow <= x"0000000";
end if;
end if;
end process;
--slow_clk_en <= '1' when counter_slow = x"17D7840" else '0';-- for running
on FPGA -- comment when running simulation
slow_clk_en <= '1' when counter_slow = x"000001" else '0';-- for running
simulation -- comment when running on FPGA
-- debounce part for duty increasing button
stage0: DFF_Debounce port map(clk,slow_clk_en , DUTY_INCREASE, tmp1);
stage1: DFF_Debounce port map(clk,slow_clk_en , tmp1, tmp2);
duty_inc <= tmp1 and (not tmp2) and slow_clk_en;
-- debounce part for duty decreasing button
stage2: DFF_Debounce port map(clk,slow_clk_en , DUTY_DECREASE, tmp3);
stage3: DFF_Debounce port map(clk,slow_clk_en , tmp3, tmp4);
duty_dec <= tmp3 and (not tmp4) and slow_clk_en;
-- for controlling duty cycle by these buttons
process(clk)
begin
if(rising_edge(clk)) then
if(duty_inc='1' and DUTY_CYCLE <= x"9") then
 DUTY_CYCLE <= DUTY_CYCLE + x"1";--increase duty cycle by 10%
elsif(duty_dec='1' and DUTY_CYCLE>=x"1") then
DUTY_CYCLE <= DUTY_CYCLE - x"1";--decrease duty cycle by 10%
end if;
end if;
end process;
-- Create 10MHz PWM signal
process(clk)
begin
if(rising_edge(clk)) then
counter_PWM <= counter_PWM + x"1";
if(counter_PWM>=x"9") then
counter_PWM <= x"0";
end if;
end if;
end process;
PWM_OUT <= '1' when counter_PWM < DUTY_CYCLE else '0';
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- fpga4student.com: FPGA Projects, Verilog projects, VHDL projects

-- VHDL code for D Flip Flop
-- D-Flip-Flop for debouncing module
entity DFF_Debounce is
Port (
CLK : in std_logic;
en: in std_logic;
D : in std_logic;
Q : out std_logic
);
end DFF_Debounce;
architecture Behavioral of DFF_Debounce is
begin
process(CLK)
begin
if (rising_edge(CLK)) then
if (en='1') then
Q <= D;
end if;
end if;
end process;
end Behavioral;
VHDL Testbench code for the PWM Generator with
Variable Duty Cycle:
-- fpga4student.com: FPGA Projects, Verilog projects, VHDL projects
-- VHDL testbench code for PWM Generator
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_PWM_Genenrator IS
END tb_PWM_Genenrator;

ARCHITECTURE behavior OF tb_PWM_Genenrator IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT PWM_Generator
PORT(
clk : IN std_logic;
DUTY_INCREASE : IN std_logic;
DUTY_DECREASE : IN std_logic;
PWM_OUT : OUT std_logic
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal DUTY_INCREASE : std_logic := '0';
signal DUTY_DECREASE : std_logic := '0';

--Outputs
signal PWM_OUT : std_logic;

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: PWM_Generator PORT MAP (
clk => clk,
 DUTY_INCREASE => DUTY_INCREASE,
DUTY_DECREASE => DUTY_DECREASE,
PWM_OUT => PWM_OUT
);

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
DUTY_INCREASE <= '0';
DUTY_DECREASE <= '0';
wait for clk_period*10;
DUTY_INCREASE <= '1';
wait for clk_period*10;
DUTY_INCREASE <= '0';
wait for clk_period*10;
DUTY_INCREASE <= '1';
wait for clk_period*10;
DUTY_INCREASE <= '0';
wait for clk_period*10;
DUTY_INCREASE <= '1';
wait for clk_period*10;
DUTY_INCREASE <= '0';
wait for clk_period*10;
DUTY_DECREASE <= '1';
wait for clk_period*10;
DUTY_DECREASE <= '0';
wait for clk_period*10;
DUTY_DECREASE <= '1';
wait for clk_period*10;
DUTY_DECREASE <= '0';
wait for clk_period*10;
DUTY_DECREASE <= '1';
wait for clk_period*10;
DUTY_DECREASE <= '0';
wait for clk_period*10;
 -- insert stimulus here

wait;
end process;

END;

VHDL code for the comparator:

-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for a comparator
-- A comparator with 2 2-bit input A and B, and three outputs
-- A less than B, A equal B, and A greater than B
-- The comparator is designed by using truth table, K-Map.
-- The final output expressions are used for VHDL coding
library IEEE;
use IEEE.std_logic_1164.all;
entity comparator_VHDL is
port (
A,B: in std_logic_vector(1 downto 0); -- two inputs for comparison
A_less_B: out std_logic; -- '1' if A < B else '0'
A_equal_B: out std_logic;-- '1' if A = B else '0'
A_greater_B: out std_logic-- '1' if A > B else '0'
);
end comparator_VHDL;
architecture comparator_structural of comparator_VHDL is
signal tmp1,tmp2,tmp3,tmp4,tmp5, tmp6, tmp7, tmp8: std_logic;
-- temporary signals
begin
-- A_equal_B combinational logic circuit
tmp1 <= A(1) xnor B(1);
tmp2 <= A(0) xnor B(0);
A_equal_B <= tmp1 and tmp2;
-- A_less_B combinational logic circuit
tmp3 <= (not A(0)) and (not A(1)) and B(0);
tmp4 <= (not A(1)) and B(1);
tmp5 <= (not A(0)) and B(1) and B(0);
A_less_B <= tmp3 or tmp4 or tmp5;
-- A_greater_B combinational logic circuit
tmp6 <= (not B(0)) and (not B(1)) and A(0);
tmp7 <= (not B(1)) and A(1);
tmp8 <= (not B(0)) and A(1) and A(0);
A_greater_B <= tmp6 or tmp7 or tmp8;
end comparator_structural;
VHDL testbench code for the comparator:
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for a comparator
-- Testbench VHDL code for comparator
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY tb_comparator_VHDL IS
END tb_comparator_VHDL;

ARCHITECTURE behavior OF tb_comparator_VHDL IS

-- Component Declaration for the comparator in VHDL

COMPONENT comparator_VHDL
PORT(
A : IN std_logic_vector(1 downto 0);
B : IN std_logic_vector(1 downto 0);
A_less_B : OUT std_logic;
A_equal_B : OUT std_logic;
A_greater_B : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(1 downto 0) := (others => '0');
signal B : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal A_less_B : std_logic;
signal A_equal_B : std_logic;
signal A_greater_B : std_logic;
BEGIN

-- Instantiate the comparator in VHDL

uut: comparator_VHDL PORT MAP (
A => A,
B => B,
A_less_B => A_less_B,
A_equal_B => A_equal_B,
A_greater_B => A_greater_B
);

-- Stimulus process
stim_proc: process
begin
 -- create test cases for A_less_B
for i in 0 to 3 loop
A <= std_logic_vector(to_unsigned(i,2));
B <= std_logic_vector(to_unsigned(i+1,2));
wait for 20 ns;
end loop;
-- create test cases for A_greater_B
for i in 0 to 3 loop
A <= std_logic_vector(to_unsigned(i+1,2));
B <= std_logic_vector(to_unsigned(i,2));
wait for 20 ns;
end loop;
-- create test cases for A_equal_B
for i in 0 to 3 loop
A <= std_logic_vector(to_unsigned(i,2));
B <= std_logic_vector(to_unsigned(i,2));
wait for 20 ns;
end loop;
wait;
end process;

END;

VHDL Code For 4 to 1 Multiplexer

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_4to1 is
port(

A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_4to1;

architecture bhv of mux_4to1 is

begin
process (A,B,C,D,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
Z <= A;
elsif (S0 ='1' and S1 = '0') then
Z <= B;
elsif (S0 ='0' and S1 = '1') then
Z <= C;

else
Z <= D;
end if;

end process;
end bhv;

VHDL TestBench Code for 4 to 1 Multiplexer

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_mux IS
END tb_mux;

ARCHITECTURE behavior OF tb_mux IS

– Component Declaration for the Unit Under Test (UUT)

COMPONENT mux_4to1
PORT(

A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;
 Z : OUT std_logic
);
END COMPONENT;

– Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';

--Outputs
signal Z : std_logic;

BEGIN

– Instantiate the Unit Under Test (UUT)

uut: mux_4to1 PORT MAP (
A => A,
B => B,
C => C,
D => D,
S0 => S0,
S1 => S1,
Z => Z
);

– Stimulus process
stim_proc: process
begin
– hold reset state for 100 ns.
wait for 100 ns;

A <= '1';
 B <= '0';
C <= '1';
D <= '0';

S0 <= '0'; S1 <= '0';

wait for 100 ns;

S0 <= '1'; S1 <= '0';

wait for 100 ns;

S0 <= '0'; S1 <= '1';

wait for 100 ns;

S0 <= '0'; S1 <= '1';

wait for 100 ns;

end process;

END;

VHDL Code for 2 to 1 Mux

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2_1 is
port(A,B : in STD_LOGIC;
S: in STD_LOGIC;
Z: out STD_LOGIC);
end mux2_1;

architecture Behavioral of mux2_1 is

begin

process (A,B,S) is
begin
if (S ='0') then
Z <= A;
else
Z <= B;
end if;
end process;

end Behavioral;

VHDL 4 to 1 Mux using 2 to 1 Mux

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4_1 is
port(

A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux4_1;

architecture Behavioral of mux4_1 is

component mux2_1
port( A,B : in STD_LOGIC;
S: in STD_LOGIC;
Z: out STD_LOGIC);
end component;
signal temp1, temp2: std_logic;

begin
m1: mux2_1 port map(A,B,S0,temp1);
m2: mux2_1 port map(C,D,S0,temp2);
m3: mux2_1 port map(temp1,temp2,S1,Z);

end Behavioral;

The FIR filter is basically implemented by using D-Flip-

Flops, signed multipliers and adders. A basic block includes
one N-bit register, one multiplier, and one adder. The VHDL
generate statement is used to generate the full design using
the basic block.
VHDL code for the low pass FIR filter:
Library IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.Std_logic_signed.all;
-- fpga4student.com: FPGA projects, VHDL projects, Verilog projects
-- LOW pass FIR filter for ECG Denoising
-- VHDL project: VHDL code for FIR filter
entity FIR_RI is -- VHDL projects
generic (
input_width : integer :=8 ;-- set input
width by user
output_width : integer :=16 ;-- set output
width by user
coef_width : integer :=8 ;-- set
coefficient width by user
tap : integer :=11 ;-- set
filter order
 guard : integer :=0) ;-- log2(tap)
+1
port(
Din : in std_logic_vector(input_width-1 downto 0) ;--
input data
Clk : in std_logic
;-- input clk
reset : in std_logic
;-- input reset
Dout : out std_logic_vector(output_width-1 downto 0)) ;--
output data
end FIR_RI;
architecture behaivioral of FIR_RI is
-- N bit Register
component N_bit_Reg
generic (
input_width : integer :=8
);
port(
Q : out std_logic_vector(input_width-1 downto 0);
Clk :in std_logic;
reset :in std_logic;
D :in std_logic_vector(input_width-1 downto 0)
);
end component;
-- fpga4student.com: FPGA projects, VHDL projects, Verilog projects
type Coeficient_type is array (1 to tap) of std_logic_vector(coef_width-1
downto 0);
-----------------------------------FIR filter
coefficients----------------------------------------------------------------
constant coeficient: coeficient_type :=
( X"F1",
X"F3",
X"07",
X"26",
X"42",
X"4E",
X"42",
X"26",
X"07",
X"F3",
X"F1"
);
------------------------------------------------------------------------------
----------------
type shift_reg_type is array (0 to tap-1) of std_logic_vector(input_width-1
downto 0);
signal shift_reg : shift_reg_type;
type mult_type is array (0 to tap-1) of
std_logic_vector(input_width+coef_width-1 downto 0);
signal mult : mult_type;
type ADD_type is array (0 to tap-1) of
std_logic_vector(input_width+coef_width-1 downto 0);
signal ADD: ADD_type;
begin
-- fpga4student.com: FPGA projects, VHDL projects, Verilog projects
shift_reg(0) <= Din;
mult(0)<= Din*coeficient(1);
ADD(0)<= Din*coeficient(1);
GEN_FIR:
for i in 0 to tap-2 generate
begin
-- N-bit reg unit
N_bit_Reg_unit : N_bit_Reg generic map (input_width => 8)
port map ( Clk => Clk,
reset => reset,
D => shift_reg(i),
Q => shift_reg(i+1)
);
-- filter multiplication
mult(i+1)<= shift_reg(i+1)*coeficient(i+2);
-- filter conbinational addition
ADD(i+1)<=ADD(i)+mult(i+1);
end generate GEN_FIR;
Dout <= ADD(tap-1);
end Architecture;

Library IEEE;
USE IEEE.Std_logic_1164.all;

-- fpga4student.com: FPGA projects, VHDL projects, Verilog projects

-- LOW pass FIR filter for ECG Denoising
-- VHDL project: VHDL code for FIR filter
-- N-bit Register in VHDL
entity N_bit_Reg is
generic (
input_width : integer :=8
 );
port(
Q : out std_logic_vector(input_width-1 downto 0);
Clk :in std_logic;
reset :in std_logic;
D :in std_logic_vector(input_width-1 downto 0)
);
end N_bit_Reg;
-- fpga4student.com: FPGA projects, VHDL projects, Verilog projects
architecture Behavioral of N_bit_Reg is
begin
process(Clk,reset)
begin
if (reset = '1') then
Q <= (others => '0');
elsif ( rising_edge(Clk) ) then
Q <= D;
end if;
end process;
end Behavioral;

Testbench VHDL code for the FIR filter:

Library IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.numeric_std.all;
Use STD.TEXTIO.all;
-- fpga4student.com: FPGA projects, VHDL projects, Verilog
projects
-- VHDL project: VHDL code for FIR filter
-- Testbench VHDL code for FIR Filter
entity TB_FIR is
end TB_FIR;
architecture behaivioral of TB_FIR is
Component FIR_RI is
generic (
input_width : integer :=8 ;
-- set input width by user
output_width : integer :=16 ; --
set output width by user
 coef_width : integer :=8 ;
-- set coefficient width by user
tap : integer :=11
; -- set filter order
guard : integer :=4)
; -- log2(tap)+1
port(
Din : in std_logic_vector(input_width-1
downto 0) ; -- input data
Clk : in std_logic
; -- input clk
reset : in std_logic
; -- input reset
Dout : out std_logic_vector(output_width-1 downto
0)) ;-- output data
end Component;
signal Din : std_logic_vector(7 downto 0) ;
signal Clk : std_logic:='0'
;
signal reset : std_logic:='1'
;
signal output_ready : std_logic:='0';
signal Dout : std_logic_vector(15 downto 0) ;
signal input: std_logic_vector(7 downto 0);
file my_input : TEXT open READ_MODE is "input101.txt";
file my_output : TEXT open WRITE_MODE is
"output101_functional_sim.txt";
begin
-- fpga4student.com: FPGA projects, VHDL projects, Verilog
projects
FIR_int : FIR_RI
generic map(
input_width => 8,
output_width => 16,
coef_width => 8,
tap => 11,
guard => 0)
port map (
 Din => Din,
Clk => Clk,
reset => reset,
Dout => Dout
);
process(clk)
begin
Clk <= not Clk after 10 ns;
end process;
reset <= '1', '1' after 100 ns, '0' after 503 ns;
-- fpga4student.com: FPGA projects, VHDL projects, Verilog
projects
-- Writing output result to output file
process(clk)
variable my_input_line : LINE;
variable input1: integer;
begin
if reset ='1' then
Din <= (others=> '0');
input <= (others=> '0');
output_ready <= '0';
elsif rising_edge(clk) then
readline(my_input, my_input_line);
read(my_input_line,input1);
Din <= std_logic_vector(to_signed(input1,
8));
--Din<=input(7 downto 0);
output_ready <= '1';
end if;
end process;
process(clk)
variable my_output_line : LINE;
variable input1: integer;
begin
if falling_edge(clk) then
if output_ready ='1' then
write(my_output_line,
to_integer(signed(Dout)));
 writeline(my_output,my_output_line);
end if;
end if;
end process;

end Architecture;

Multiplexer

Multiplexer (MUX) select one input from the multiple inputs and forwarded to output line
through selection line. It consist of 2 power n input and 1 output. The input data lines are
controlled by n selection lines.

For Example, if n = 2 then the mux will be of 4 to 1 mux with 4 input, 2 selection line and 1
output as shown below.

Truth Table for Multiplexer 4 to 1

Mux 4 to 1 design using Logic Gates
VHDL Code For 4 to 1 Multiplexer

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_4to1 is
port(

A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_4to1;

architecture bhv of mux_4to1 is

begin
process (A,B,C,D,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
Z <= A;
elsif (S0 ='1' and S1 = '0') then
Z <= B;
elsif (S0 ='0' and S1 = '1') then
Z <= C;

else
Z <= D;
end if;

end process;
end bhv;

VHDL TestBench Code for 4 to 1 Multiplexer

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_mux IS
END tb_mux;

ARCHITECTURE behavior OF tb_mux IS

– Component Declaration for the Unit Under Test (UUT)

COMPONENT mux_4to1
PORT(

A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;

– Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';

--Outputs
signal Z : std_logic;

BEGIN
 – Instantiate the Unit Under Test (UUT)
uut: mux_4to1 PORT MAP (
A => A,
B => B,
C => C,
D => D,
S0 => S0,
S1 => S1,
Z => Z
);

– Stimulus process
stim_proc: process
begin
– hold reset state for 100 ns.
wait for 100 ns;

A <= '1';
B <= '0';
C <= '1';
D <= '0';

S0 <= '0'; S1 <= '0';

wait for 100 ns;

S0 <= '1'; S1 <= '0';

wait for 100 ns;

S0 <= '0'; S1 <= '1';

wait for 100 ns;

 S0 <= '0'; S1 <= '1';

wait for 100 ns;

end process;

END;

Output Waveform for 4 to 1 Multiplexer

Another Method of Constructing VHDL 4 to 1 mux is by using 2 to 1 Mux. For that

implementation first we have write VHDL Code for 2 to 1 Mux and Port map 3 times 2 to 1 mux
to construct VHDL 4 to 1 Mux.

4 to 1 Mux Implementation using 2 to 1 Mux

VHDL Code for 2 to 1 Mux

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2_1 is
port(A,B : in STD_LOGIC;
S: in STD_LOGIC;
Z: out STD_LOGIC);
end mux2_1;

architecture Behavioral of mux2_1 is

begin

process (A,B,S) is
begin
if (S ='0') then
Z <= A;
else
Z <= B;
end if;
end process;

end Behavioral;

VHDL 4 to 1 Mux using 2 to 1 Mux

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4_1 is
port(

A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux4_1;

architecture Behavioral of mux4_1 is

component mux2_1
port( A,B : in STD_LOGIC;
S: in STD_LOGIC;
Z: out STD_LOGIC);
end component;
signal temp1, temp2: std_logic;

begin
m1: mux2_1 port map(A,B,S0,temp1);
m2: mux2_1 port map(C,D,S0,temp2);
m3: mux2_1 port map(temp1,temp2,S1,Z);

end Behavioral;

VHDL code for 1 to 4 Demux

February 2, 2016 by shahul akthar

Table of Contents

 DeMultiplexer
 1 to 4 Demux
 Truth table for Demux 1 to 4
 1 to 4 Demux design using Logic Gates
 VHDL Code for 1 to 4 Demux
 VHDL Testbench Code for 1 to 4 Demux
 Testbench waveform for 1 to 4 Demux

DeMultiplexer
Demultiplexer (DEMUX) select one output from the multiple output line and fetch the single
input through selection line. It consist of 1 input and 2 power n output. The output data lines are
controlled by n selection lines. For Example, if n = 2 then the demux will be of 1 to 4 mux with
1 input, 2 selection line and 4 output as shown below. Also VHDL Code for 1 to 4
Demux described below.

1 to 4 Demux

Truth table for Demux 1 to 4

1 to 4 Demux design using Logic Gates

VHDL Code for 1 to 4 Demux

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity demux_1to4 is
port(
 F : in STD_LOGIC;
S0,S1: in STD_LOGIC;
A,B,C,D: out STD_LOGIC
);
end demux_1to4;

architecture bhv of demux_1to4 is

begin
process (F,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
A <= F;
elsif (S0 ='1' and S1 = '0') then
B <= F;
elsif (S0 ='0' and S1 = '1') then
C <= F;

else
D <= F;
end if;

end process;
end bhv;

VHDL Testbench Code for 1 to 4 Demux

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_demux IS
END tb_demux;

ARCHITECTURE behavior OF tb_demux IS

 – Component Declaration for the Unit Under Test (UUT)

COMPONENT demux_1to4
PORT(

F : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;
A : OUT std_logic;
B : OUT std_logic;
C : OUT std_logic;
D : OUT std_logic
);
END COMPONENT;

--Inputs
signal F : std_logic := '0';
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';

--Outputs
signal A : std_logic;
signal B : std_logic;
signal C : std_logic;
signal D : std_logic;
– No clocks detected in port list. Replace <clock> below with
– appropriate port name

BEGIN

– Instantiate the Unit Under Test (UUT)

uut: demux_1to4 PORT MAP (
F => F,
S0 => S0,
S1 => S1,
A => A,
B => B,
C => C,
D => D
);

– Stimulus process
stim_proc: process

begin
– hold reset state for 100 ns.
wait for 100 ns;

F <= '1';

S0 <= '0'; S1 <= '0';

wait for 100 ns;

S0 <= '1'; S1 <= '0';

wait for 100 ns;

S0 <= '0'; S1 <= '1';

wait for 100 ns;

S0 <= '1'; S1 <= '1';

wait for 100 ns;

– insert stimulus here

wait;
end process;

END;