GENERAL PURPOSE FOLDED-CASCODE CMOS OPAMP DESIGN

Edgar Mauricio Camacho, Luiz Alberto Pasini Melek, Márcio Cherem Schneider

Universidade Federal de Santa Catarina, Florianópolis, SC, Brazil

ABSTRACT The off-chip reference current source, IREF, is used to

bias the input differential pair formed by M1-M2. VBIAS3
This paper presents a single-ended folded-cascode provides a voltage to M11-M12 in a way that they work
CMOS operational amplifier, designed for general as two current sources for the folded-cascode topology.
purpose applications. Primary specifications are a gain M1A and M2A are connected in a common-gate
better than 80dB, GBW of 10MHz, systematic offset configuration with VBIAS2 and are part of the folded-
lower than 200µV, THD less that 0.1% at 3.5Vpp output cascode output stage. M3, M3A, M4 and M4A form a
and a load of 20pF, operating with a single supply voltage low-voltage cascode current mirror biased by VBIAS1. CL
of 5V. The circuit was fabricated using AMIS 1.5um is the load capacitance.
technology, available from MOSIS through the With equal voltages at the input nodes V+ and V-, the
Educational Program. current in each transistor of the differential pair is half the
reference current. When V+ is higher than V-, the current
in M1 becomes higher than in M2. Since M11 and M12
1. INTRODUCTION form two current sources, the difference in the current in
M1A and M2A is compensated with an increase in the
Operational amplifiers are one of the many basic drain-source voltage of M2A and, consequently, in the
building blocks in analog design. This paper presents a output voltage. Similar analysis can be made when V+ is
methodology for an opamp design with load capacitance lower than V-, when the output voltage falls.
using the ACM (Advanced Compact Mosfet Model)
equations. The folded-cascode configuration was chosen 3. DESIGN METHODOLOGY
because it improves common-mode input range and
increases the output swing [1] if compared to the Expression (1) gives the relation between the
conventional cascode amplifier. This paper is divided as bandwidth, GBW, and the gate transconductance, gmg,
follows. In Section 2, we describe the circuit and its according to the load capacitance [1]. With GBW of
operation. In Section 3, we present the methodology 10MHz, the gmg is 1.26mA/V.
employed to determine the size of the transistors using the
ACM equations [2,3]. In Section 4, we present a g mg = 2π ⋅ GBW ⋅ C L (1)
comparison between theoretical, simulation and
experimental results. We finish the paper with the For a proper operation, all the transistors must be in
conclusions, in Section 5. saturation [1]. In this situation, the drain current, ID, and
the forward inversion level, if, in the differential pair are
2. CIRCUIT DESCRIPTION AND OPERATION related with the gate transconductance by [2,3]

The topology used for the folded-cascode opamp is

shown in figure 1. Bias voltages, indicated in figure 1, g mg =
(
2 ⋅ ID 1+ i f −1 ) (2)
were designed according to [4], in a way such that the n ⋅ φT ⋅ i f
transistors are biased in the edge of saturation. where n is the slope factor and ÖT is the thermal voltage.
We choose ID=120µA to limit power consumption and
if=33 not to make M1 and M2 so large, because if and the
aspect ratio are inversely proportional, as will be shown
later. Since that all the current in these transistors is
provided from the reference current, we have
IREF=240µA. M11 and M12 work as current sources, and
we make them equal to IREF. So, the currents that flow in
the transistors M1A-M3A-M3 and M2A-M4A-M4 is the
same as in the differential pair.
M3 and M4, M3A and M4A, M1A and M2A and
M11 and M12 must be saturated, within a 3.5Vpp output
signal. So their saturation voltage, VDSSAT, given by (3)
[2,3], must be lower than 375mV. In order to avoid the
Figure 1: Opamp circuit effects of process parameters variation, we choose if=100.
 (
VDSSAT = φT ⋅ 1 + i f + 3 ) (3) g
RO ≈  ds 2 A
⋅ (g ds12 + g ds 2 ) g ds 4 A ⋅ g ds 4 
+ 
−1
(6)
 g ms 2 A g ms 4 
The aspect ratio, W/L, of each transistor can be
determined by expression (4) that relates the drain current gds is the output transconductance and gms is the source
in saturation, technological parameters and the forward transconductance.
inversion level [2,3]. Theoretical Simulation* Measurements*
' φT2W Output voltage 3.75Vpp 3.7 Vpp 3.84 Vpp
I D = i f ⋅ µ ⋅ n ⋅ Cox ⋅ (4) for THD<0.1%
2 L Offset 105 µV 122 µV 150-650 µV
Power 2.64 mW 2.6 mW 2.6 mW
ì is the carrier mobility, n is the slope factor, C’ox is the Slew-rate 12 V/µs 7.2 V/µs 5.3-5.7 V/µs
oxide capacitance/area. AVO 81 dB 82 dB 72-73 dB
Table 1 summarizes drain currents, inversion levels, Dominant pole 881 Hz 644 Hz -
aspect ratios, widths and lengths for all transistors. The fT 10.3 MHz 7.8 MHz 7.2 MHz
final length was chosen with help of simulations, in order Phase Margin 68° 70° 66-68°
to avoid short channel effects, to achieve the specified Settling time 170 ns 250 ns 244-250 ns
gain and to reduce the output offset voltage. large @ 0.1%
Settling time 180 ns 150 ns 162-168 ns
if ID (µA) W/L W (µm) L (µm) small @ 1%
M1, M2 33 120 360 1440 4 Table 2: Results (* CL=26pF)
M1A, M2A 135 120 62.5 400 6.4
M3, M4, 100 120 120 480 4
Figure 2 shows the layout of the operational amplifier
M3A, M4A integrated circuit.
M11, M12 68 240 62.5 400 6.4
Table 1: Transistors’ sizes

4. RESULTS
The circuit was fabricated with the AMIS 1.5µm,
available from MOSIS through the Educational Program.
Theoretical, simulation and experimental results in three
different chips were compared to assess the opamp
design. Due to limitations of the measurement equipment,
the load capacitance was set to 26pF. In order to provide Figure 2: Layout of the opamp
compatible results, simulations were also done with this
load. Table 2 summarize them. 5. CONCLUSIONS
Operating point and DC transfer simulations were
made in order to determine the linearity, the offset and The design of a general purpose folded-cascode
power consumption. First, the opamp was connected in operational amplifier using ACM equations was shown
the follower configuration in order to determine the here. Experimental results were compared with theoretical
output voltage range for which THD<0.1%. Offset was and simulated ones and showed that they agreed very
measured with both inputs shorted and set to 2.5V. It well.
was, then, referenced to the input. 6. REFERENCES
Slew-rate, SR, is determined by the maximum
variation of the output voltage in a period of time, and is [1] Gray, P., Hurst, P., Lewis, S., Meyer, R., Analysis and
given by the ratio of the available current, IREF, and the Design of Analog integrated Circuits, John Wiley & Sons, Inc.,
Fourth Edition.
load capacitance. Transient analysis was made to
[2] A. I. Cunha, M. C. Schneider, C. Galup-Montoro, “An
determine it with a 2Vpp input square signal around the MOS transistor Model for analog circuit design”, IEEE J. Solid-
operating point. State Circuits, vol. 33, pp. 1510-1519, Oct. 1998.
Frequency response was carried out to verify the [3] C. Galup-Montoro, M. C. Schneider, A. I. Cunha, “A
performance achieved by the opamp by means of small- current-based MOSFET model for integrated circuit design”, in
signal simulations and theoretical formulations from the Low-Voltage/Low-power Integrated Circuits and Systems, E.
equivalent circuit. Each transistor was substituted by its Sánchez-Sinencio and A. G. Andreou, Eds. New York: IEEE
model, to determine the gain at low frequencies, the Press, 1999.
dominant pole, transition frequency, fT, and phase margin. [4] Johns, D., Martin K., Analog Integrated Circuit Design,
John Wiley & Sons, Inc., 1997.
The DC gain, AVO, is given by

AVO = g mg ⋅ RO (5)
where RO is the output resistance, approximated by