10.08.

2023

DIGITAL LOGIC CIRCUITS Semester III

Course Code BEE 306A CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:0:0 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory Total Marks 100
Credits 04 Exam Hours 03
Examination nature (SEE) Theory
Course objectives:
 To illustrate simplification of algebraic equations using Karnaugh Maps and Quine-McClusky methods
 To design decoders, encoders, digital multiplexer, adders, subtractors and binary comparators
 To explain latches and flip-flops , registers and counters
 To analyze Melay ad Moore Models
 To develop state diagrams synchronous sequential circuits
 To understand the applications of sequential circuits

Teaching-Learning Process (General Instructions)

These are sample Strategies; that teachers can use to accelerate the attainment of the various course outcomes.
1. Lecturer method (L) needs not to be only traditional lecture method, but alternative effective teaching
methods could be adopted to attain the outcomes.
2. Use of Video/Animation to explain functioning of various concepts.
3. Encourage collaborative (Group Learning) Learning in the class.
4. Ask at least three HOT (Higher order Thinking) questions in the class, which promotes critical thinking.
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop design thinking
skills such as the ability to design, evaluate, generalize, and analyze information rather than simply recall
it.
6. Introduce Topics in manifold representations.
7. Show the different ways to solve the same problem with different circuits/logic and encourage the
students to come up with their own creative ways to solve them.
8. Discuss how every concept can be applied to the real world-and when that's possible, it helps improve
the students' understanding.
MODULE-1
Principles of Combinational Logic: Definition of combinational logic, canonical forms, Generation of
switching equations from truth tables, Karnaugh maps-3,4,5 variables, Incompletely specified functions
(Don‘t care terms) Simplifying Max term equations, Quine-McCluskey minimization technique, Quine-
McCluskey using don‘t care terms, Reduced prime implicants Tables.
MODULE-2
Analysis and Design of Combinational logic: General approach to combinational logic design,
Decoders, BCD decoders, Encoders, digital multiplexers, Using multiplexers as Boolean function
generators, Adders and subtractors, Cascading full adders, Look ahead carry, Binary comparators.
MODULE-3
Flip-Flops: Basic Bistable elements, Latches, Timing considerations, The master-slave flip-flops (pulse
triggered flip-flops): SR flip-flops, JK flip-flops, Edge triggered flip- flops, Characteristic equations.
MODULE-4
Flip-Flops Applications: Registers, binary ripple counters, synchronous binary counters, Counters
based on shift registers, Design of a synchronous counter, Design of a synchronous mod-n counter using
clocked T, JK, D and SR flip-flops.
MODULE-5
Sequential Circuit Design: Mealy and Moore models, State machine notation, Synchronous Sequential
circuit analysis, Construction of state diagrams, counter design. Memories: Read only and Read/Write
Memories, Programmable ROM, EPROM, Flash memory.
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Course outcomes (Course Skill Set):

At the end of the course, the student will be able to:
 Explain the concept of combinational and sequential logic circuits
 Analyse and design combinational circuits
 Describe and characterize flip flops and its applications
 Design the sequential circuits using SR, JK, D and T flip-flops and Melay and Moore applications
 Design applications of combinational and sequential circuits
 Employ the digital circuits for different applications
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the
SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be
deemed to have satisfied the academic requirements and earned the credits allotted to each subject/
course if the student secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 For the Assignment component of the CIE, there are 25 marks and for the Internal Assessment Test
component, there are 25 marks.
 The first test will be administered after 40-50% of the syllabus has been covered, and the second test
will be administered after 85-90% of the syllabus has been covered
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The teacher should not conduct two assignments at
the end of the semester if two assignments are planned.
 For the course, CIE marks will be based on a scaled-down sum of two tests and other methods of
assessment.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy as
per the outcome defined for the course.
Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers for the
course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a maximum of 3
sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
Marks scored sha ll be proportionally reduced to 50 marks.
Suggested Learning Resources:
Books
1) John M Yarbrough , Digital logic applications and design, Thomson Learning, 2001.
2)Donald D Givone, Digital Principles and design, MC Graw Hill 2002
3)Charles H Roth Jr, Larry L Kinney, Fundamentals of logic design , Cengage Learning, 7th Edition
Reference books:
1)D.P.Kothari and J S Dhillon, -Digital circuits and design, Pearson, 2016
2)Morris Mano, Digital Design, PHI, 3rd edition
3)K.A. Navas, Electronics Lab Manual, Vol.1, PHI 5th edition, 2015.