Chapter 1.

Basic
Structure of Computers
Functional Units
Functional Units
Arithmeti
Inpu c an
t d
logi
c
Memor
y

Outpu Contro
t l

I/ Processo
O r

Figure 1.1. Basic functional units of a

computer.
Information Handled by a
Computer
● Instructions/machine instructions
Govern the transfer of information within a computer as
well as between the computer and its I/O devices
Specify the arithmetic and logic operations to be
performed
Program
● Data
Used as operands by the instructions
Source program
● Encoded in binary code – 0 and 1
Memory Unit
● Store programs and data
● Two classes of storage
Primary storage
❖ Fast
❖ Programs must be stored in memory while they are being executed
❖ Large number of semiconductor storage cells
❖ Processed in words
❖ Address
❖ RAM and memory access time
❖ Memory hierarchy – cache, main memory
Secondary storage – larger and cheaper
Arithmetic and Logic Unit
(ALU)
● Most computer operations are executed in
ALU of the processor.
● Load the operands into memory – bring
them to the processor – perform operation in
ALU – store the result back to memory or
retain in the processor.
● Registers
● Fast control of ALU
Control Unit
● All computer operations are controlled by the
control unit.
● The timing signals that govern the I/O transfers are
also generated by the control unit.
● Control unit is usually distributed throughout the
machine instead of standing alone.
● Operations of a computer:
Accept information in the form of programs and data through an
input unit and store it in the memory
Fetch the information stored in the memory, under program control,
into an ALU, where the information is processed
Output the processed information through an output unit
Control all activities inside the machine through a control unit
The processor : Data Path and
Control

Two types of functional units:

elements that operate on data values (combinational)
elements that contain state (state elements)
 Five Execution Steps
Step name Action for R-type Action for Memory- Action for Action for
instructions reference Instructions branches jumps

Instruction fetch IR = MEM[PC]

PC = PC + 4

Instruction decode/ register A = Reg[IR[25-21]]

fetch B = Reg[IR[20-16]]
ALUOut = PC + (sign extend (IR[15-0])<<2)

Execution, address ALUOut = A op B ALUOut = A+sign IF(A==B) Then PC=PC[31-28

computation, branch/jump extend(IR[15-0]) PC=ALUOut ]||(IR[25-0]<<
completion 2)

Memory access or R-type Reg[IR[15-11]] = Load:MDR =Mem[ALUOut]

completion ALUOut or
Store:Mem[ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] =

MDR
Basic Operational
Concepts
Review
● Activity in a computer is governed by instructions.
● To perform a task, an appropriate program
consisting of a list of instructions is stored in the
memory.
● Individual instructions are brought from the memory
into the processor, which executes the specified
operations.
● Data to be used as operands are also stored in the
memory.
A Typical Instruction
● Add LOCA, R0
● Add the operand at memory location LOCA to the
operand in a register R0 in the processor.
● Place the sum into register R0.
● The original contents of LOCA are preserved.
● The original contents of R0 is overwritten.
● Instruction is fetched from the memory into the
processor – the operand at LOCA is fetched and
added to the contents of R0 – the resulting sum is
stored in register R0.
Separate Memory Access and
ALU Operation
● Load LOCA, R1
● Add R1, R0
● Whose contents will be overwritten?
Connection Between the
Processor and the Memory
Registers
● Instruction register (IR)
● Program counter (PC)
● General-purpose register (R0 – Rn-1)
● Memory address register (MAR)
● Memory data register (MDR)
Typical Operating Steps
● Programs reside in the memory through
input devices
● PC is set to point to the first instruction
● The contents of PC are transferred to MAR
● A Read signal is sent to the memory
● The first instruction is read out and loaded
into MDR
● The contents of MDR are transferred to IR
● Decode and execute the instruction
Typical Operating Steps
(Cont’)
● Get operands for ALU
General-purpose register
Memory (address to MAR – Read – MDR to ALU)
● Perform operation in ALU
● Store the result back
To general-purpose register
To memory (address to MAR, result to MDR – Write)
● During the execution, PC is
incremented to the next instruction
Interrupt
● Normal execution of programs may be preempted if
some device requires urgent servicing.
● The normal execution of the current program must
be interrupted – the device raises an interrupt signal.
● Interrupt-service routine
● Current system information backup and restore (PC,
general-purpose registers, control information,
specific information)
Bus Structures
● There are many ways to connect different
parts inside a computer together.
● A group of lines that serves as a connecting
path for several devices is called a bus.
● Address/data/control
Bus Structure
● Single-bus
Speed Issue
● Different devices have different transfer/
operate speed.
● If the speed of bus is bounded by the
slowest device connected to it, the efficiency
will be very low.
● How to solve this?
● A common approach – use buffers.
Performance
Performance
● The most important measure of a computer
is how quickly it can execute programs.
● Three factors affect performance:
Hardware design
Instruction set
Compiler
Performance
● Processor time to execute a program depends on the hardware
involved in the execution of individual machine instructions.

Main Cach
memor memor Processo
e
y y r

Bu
s

Figure The processor

1.5. cache.
Performance
● The processor and a relatively small cache
memory can be fabricated on a single
integrated circuit chip.
● Speed
● Cost
● Memory management
Processor Clock
● Clock, clock cycle, and clock rate
● The execution of each instruction is divided
into several steps, each of which completes
in one clock cycle.
● Hertz – cycles per second
Basic Performance Equation
● T – processor time required to execute a program that has been
prepared in high-level language
● N – number of actual machine language instructions needed to
complete the execution (note: loop)
● S – average number of basic steps needed to execute one
machine instruction. Each step completes in one clock cycle
● R – clock rate
● Note: these are not independent to each other

How to improve
T?
Pipeline and Superscalar
Operation
● Instructions are not necessarily executed one after
another.
● The value of S doesn’t have to be the number of
clock cycles to execute one instruction.
● Pipelining – overlapping the execution of
successive instructions.
● Add R1, R2, R3
● Superscalar operation – multiple instruction
pipelines are implemented in the processor.
● Goal – reduce S (could become <1!)
Clock Rate
● Increase clock rate
Improve the integrated-circuit (IC) technology to make
the circuits faster
Reduce the amount of processing done in one basic
step (however, this may increase the number of basic
steps needed)
● Increases in R that are entirely caused by
improvements in IC technology affect all
aspects of the processor’s operation equally
except the time to access the main memory.
CISC and RISC
● Tradeoff between N and S
● A key consideration is the use of pipelining
S is close to 1 even though the number of basic steps
per instruction may be considerably larger
It is much easier to implement efficient pipelining in
processor with simple instruction sets
● Reduced Instruction Set Computers (RISC)
● Complex Instruction Set Computers (CISC)
Compiler
● A compiler translates a high-level language
program into a sequence of machine instructions.
● To reduce N, we need a suitable machine
instruction set and a compiler that makes good use
of it.
● Goal – reduce N×S
● A compiler may not be designed for a specific
processor; however, a high-quality compiler is
usually designed for, and with, a specific processor.
Performance Measurement
● T is difficult to compute.
● Measure computer performance using benchmark programs.
● System Performance Evaluation Corporation (SPEC) selects and
publishes representative application programs for different application
domains, together with test results for many commercially available
computers.
● Compile and run (no simulation)
● Reference computer
Multiprocessors and
Multicomputers
● Multiprocessor computer
Execute a number of different application tasks in parallel
Execute subtasks of a single large task in parallel
All processors have access to all of the memory – shared-memory
multiprocessor
Cost – processors, memory units, complex interconnection networks
● Multicomputers
Each computer only have access to its own memory
Exchange message via a communication network – message-
passing multicomputers
 Machine
Instructions and
Programs
Objectives
● Machine instructions and program execution,
including branching and subroutine call and return
operations.
● Number representation and addition/subtraction in
the 2’s-complement system.
● Addressing methods for accessing register and
memory operands.
● Assembly language for representing machine
instructions, data, and programs.
● Program-controlled Input/Output operations.
 Arithmetic
Operations, and
Characters
Signed Integer
● 3 major representations:
Sign and magnitude
One’s complement
Two’s complement
● Assumptions:
4-bit machine word
16 different values can be represented
Roughly half are positive, half are negative
Sign and Magnitude
Representation

High order bit is sign: 0 = positive (or zero), 1 = negative

Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = +/-2n-1 -1
Two representations for 0
One’s Complement
Representation

● Subtraction implemented by addition & 1's complement

● Still two representations of 0! This causes some problems
● Some complexities in addition
Two’s Complement
Representation

like 1's comp

except
shifted
one position
clockwise

● Only one representation for 0

● One more negative number than positive
number
 Binary, Signed-Integer
Representations
Page 28 B Values
represented
Sign
b 3 b 2 b1 b 0 magnitud
and 1s 2s
e ' complement ' complement
0 1 1 1 +7 +7 + 7
0 1 1 0 +6 +6 + 6
0 1 0 1 +5 +5 + 5
0 1 0 0 +4 +4 + 4
0 0 1 1 +3 +3 + 3
0 0 1 0 +2 +2 + 2
0 0 0 1 +1 +1 + 1
0 0 0 0 +0 +0 + 0
1 0 0 0 - 0 -7 - 8
1 0 0 1 - 1 -6 - 7
1 0 1 0 - 2 -5 - 6
1 0 1 1 - 3 -4 - 5
1 1 0 0 - 4 -3 - 4
1 1 0 1 - 5 -2 - 3
1 1 1 0 - 6 - 1 - 2
1 1 1 1 - 7 -0 - 1

Figure 2.1. Binary, signed-integer representations.

Addition and Subtraction – 2’s
Complement
4 010 -4 1100
0
+ + 1101
If carry-in to the high 3 0011 (-3)
order bit = 11001
carry-out then ignore 7 0111 -7
carry

if carry-in differs from 4 0100 -4 1100

carry-out then
overflow - 1101 + 0011
3 3
1000 1111
1 1 -1

Simpler addition scheme makes twos complement the most

common
choice for integer number systems within digital systems
 2’s-Complement Add and
Subtract Operations
(a 001 ( + 2) (b 010 ( + 4)
) + 0
001 ( + 3) ) + 1
001 (- 6)
Page 31 1 0 (- 2)
010 ( + 5) 111
(c 1
101 (- 5) (d 0
011 ( + 7)
) + 111 (- 2) ) + 110 ( - 3)
0
100 (- 7) 1
010 ( + 4)
(e 1
110 (- 3) 0
110
) - 100 (- 7) + 1
011
1 1
010 ( + 4)
(f 001 ( + 2) 0
001
) - 010 ( + 4) + 1
010
0 0
111 ( - 2)
(g 011 ( + 6) 0
011
) - 001 ( + 3) + 1
010
1 1
001 ( + 3)
(h 100 ( - 7) 1
100
) - 101 (- 5) + 0
110
1 1
111 ( - 2)
(i 100 (- 7) 0
100
) - 0
100 ( + 1) + 111
1 1
100 ( - 8)
(j 001 ( + 2) 0
001
) 110
- 0 ( - 3) + 001
1 1
010 ( + 5)
1
Figure 2.4. 2's-complement Add and Subtract operations.
Overflow - Add two positive numbers to get a
negative number or two negative numbers to
get a positive number

- + - +
1 0 1 0
- 1111 000 + - 1111 000 +
2 0 1 2 0
-
1110 000 1110 000 1
1 + - 1 +
3 1101 1101
001 2 3 001 2
- 0 - 0
4 1100 0011 + 4 1100 0011 +
- 1011
3 - 3
010 1011
5 + 5 010 +
0 0
101 4 101 4
- 0 010 - 0 010
6 100 1 + 6 100 1 +
0110 5 0110 5
- 1 1
100 0111 + - 100 0111 +
7 0 6 7 0 6
- + - +
8 7 8 7
5+3= -7 - 2 =
-8 +7
Overflow Conditions
0111 1000
5 010 - 100
1 7 1
3
001 - 110
- 1 2 0
8
Overflo 100 Overflo
7 1011
w 0 w 1
0000 1111
5 010 - 1101
1 3
2 1011
001 -
7 0 5 1100
0
No 011 No-
overflow 1 8
overflow
Overflow when carry-in to the high-order bit does not equal carry
out
 Sign Extension
● Task:
● Given w-bit signed integer x
● Convert it to w+k-bit integer with same value

● Rule:
● Make k copies of sign bit:
● X ′ = x w–1 ,…, x w–1 , x w–1 , x w–2 ,…, x 0
w
X • • •
k copies of
MSB

• •
•
X′ • •
• • •
•
k w
Sign Extension Example

short int x = 15213;

int ix = (int) x;
short int y = -15213;
int iy = (int) y;
Memory Locations,
Addresses, and
Operations
Memory Location, Addresses,
and Operation
n
bits
first
● Memory consists word
second
of many millions word
of storage cells,
•
each of which can •
•
store 1 bit.
● Data is usually i th
accessed in n-bit word

groups. n is •
called word •
•
length.
last
word

Figure 2.5. Memory

Memory Location, Addresses,
and Operation
● 32-bit word length example
32 bits

b3 b3 b1 b0

•
•
•
1 0

Sign bit: b3 = 0 for positive

b13 = 1 numbers
for negative numbers
1
(a) A signed integer

8 8 8 8
bits bits bits bits

ASCI ASCI ASCI ASCI

characte
I characte
I characte
I characte
I
r r r r
(b) Four characters
Memory Location, Addresses,
and Operation
● To retrieve information from memory, either for one
word or one byte (8-bit), addresses for each
location are needed.
● A k-bit address memory has 2k memory locations,
namely 0 – 2k-1, called memory space.
● 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
● 32-bit memory: 232 = 4G (1G=230)
● 1K(kilo)=210
● 1T(tera)=240
Memory Location, Addresses,
and Operation
● It is impractical to assign distinct addresses
to individual bit locations in the memory.
● The most practical assignment is to have
successive addresses refer to successive
byte locations in the memory – byte-
addressable memory.
● Byte locations have addresses 0, 1, 2, … If
word length is 32 bits, they successive
words are located at addresses 0, 4, 8,…
Big-Endian and Little-Endian
Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant
bytes of the word
Wor
d
addres Byte Byte
s address address
0 1 2 3 0 3 2 1 0
0
4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian

assignment
Figure 2.7. Byte and word
Memory Location, Addresses,
and Operation
● Address ordering of bytes
● Word alignment
● Words are said to be aligned in memory if they
begin at a byte addr. that is a multiple of the num
of bytes in a word.
● 16-bit word: word addresses: 0, 2, 4,….
● 32-bit word: word addresses: 0, 4, 8,….
● 64-bit word: word addresses: 0, 8,16,….
● Access numbers, characters, and character
strings
Memory Operation
● Load (or Read or Fetch)
Copy the content. The memory content doesn’t change.
Address – Load
Registers can be used
● Store (or Write)
Overwrite the content in memory
Address and Data – Store
Registers can be used
Instruction and
Instruction
Sequencing
“Must-Perform” Operations
● Data transfers between the memory and the
processor registers
● Arithmetic and logic operations on data
● Program sequencing and control
● I/O transfers
Register Transfer Notation
● Identify a location by a symbolic name
standing for its hardware binary address
(LOC, R0,…)
● Contents of a location are denoted by
placing square brackets around the name of
the location (R1←[LOC], R3 ←[R1]+[R2])
● Register Transfer Notation (RTN)
Assembly Language Notation
● Represent machine instructions and
programs.
● Move LOC, R1 = R1←[LOC]
● Add R1, R2, R3 = R3 ←[R1]+[R2]
CPU Organization
● Single Accumulator
● Result usually goes to the Accumulator
● Accumulator has to be saved to memory quite
often
● General Register
● Registers hold operands thus reduce memory
traffic
● Register bookkeeping
● Stack
● Operands and result are always in the stack
Instruction Formats
● Three-Address Instructions
● ADD R1, R2, R3 R1 ← R2 + R3
● Two-Address Instructions
● ADD R1, R2 R1 ← R1 + R2
● One-Address Instructions
● ADD M AC ← AC + M[AR]
● Zero-Address Instructions
● ADD TOS ← TOS + (TOS – 1)
● RISC Instructions
● Lots of registers. Memory is restricted to Load & Store

Opcode Operand(s) or Address(es)

Instruction Formats
Example: Evaluate (A+B) * (C+D)
● Three-Address
1. ADD R1, A, B ; R1 ← M[A] + M[B]
2. ADD R2, C, D ; R2 ← M[C] + M[D]
3. MUL X, R1, R2 ; M[X] ← R1 * R2
Instruction Formats
Example: Evaluate (A+B) * (C+D)
● Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 + M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 + M[D]
5. MUL R1, R2 ; R1 ← R1 * R2
6. MOV X, R1 ; M[X] ← R1
Instruction Formats
Example: Evaluate (A+B) * (C+D)
● One-Address
1. LOADA ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOADC ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC * M[T]
7. STORE X ; M[X] ← AC
 Instruction Formats
Example: Evaluate (A+B) * (C+D)
● Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)*(A+B)
8. POP X ; M[X] ← TOS
Instruction Formats
Example: Evaluate (A+B) * (C+D)
● RISC
1. LOADR1, A ; R1 ← M[A]
2. LOADR2, B ; R2 ← M[B]
3. LOADR3, C ; R3 ← M[C]
4. LOADR4, D ; R4 ← M[D]
5. ADD R1, R1, R2 ; R1 ← R1 + R2
6. ADD R3, R3, R4 ; R3 ← R3 + R4
7. MUL R1, R1, R3 ; R1 ← R1 * R3
8. STORE X, R1 ; M[X] ← R1
Using Registers
● Registers are faster
● Shorter instructions
● The number of registers is smaller (e.g. 32
registers need 5 bits)
● Potential speedup
● Minimize the frequency with which data is
moved back and forth between the memory
and processor registers.
 Instruction Execution and
Straight-Line Sequencing
Addres Content
s s
i
Assumptions:
Begin execution Mov A,
here e R0 3- - One memory operand
i+ Ad B, progra
instruction
segmen per instruction
i 4+ m
d R0
Mov R0, t
8 e C - 32-bit word length
- Memory is byte
addressable
A - Full memory address
can be directly specified
in a single-word
B Data instruction
the
for
program Two-phase procedure
- Instruction fetch
- Instruction execute
C
Page 43

Figure 2.8. A program for C ← [Α] + [Β].

 i Mov NUM1,R
e 0
i+4 Ad NUM2,R

Branching i+8
d
Ad
d
0
NUM3,R
0
•
•
•

i + 4n - 4 Ad NU n,
d M R0
i + 4n Mov R0,SU
e M

•
•
•

SU
M
NUM
1
NUM
2
•
•
•

NU n
M

Figure 2.9. A straight-line program for adding n

 Mov N,
e R1
Clea R
r 0
Branching LOO
P Determine address
"Next"
of number and
Progra "Next"
add number to
m loo R0
p Decremen R
t 1
Branch> LOO
Branch 0 P
target Mov R0,SU
e M
Conditional
branch •
•
•

SU
M
N n
NUM
1
Figure 2.10. Using a loop to add n NUM
numbers. 2
•
•
•

NU n
M
Condition Codes
● Condition code flags
● Condition code register / status register
● N (negative)
● Z (zero)
● V (overflow)
● C (carry)
● Different instructions affect different flags
Conditional Branch
Instructions
● Example: A: 11110000
● A: 1 1 1 1 0 0 0 0 +(−B): 1 1 1 0 1 1 0 0
● B: 0 0 0 1 0 1 0 0 11011100

C=1 Z=0
S=1
V=0
Status Bits

Cn-1
A B

Cn ALU
F
V Z S C
Fn-1

Zero Check
Addressing
Modes
Generating Memory Addresses
● How to specify the address of branch target?
● Can we give the memory operand address
directly in a single Add instruction in the
loop?
● Use a register to hold the address of NUM1;
then increment by 4 on each pass through
the loop.
Addressing Modes

Opcode Mode ...

● Implied
● AC is implied in “ADD M[AR]” in “One-Address”
instr.
● TOS is implied in “ADD” in “Zero-Address” instr.
● Immediate
● The use of a constant in “MOV R1, 5”, i.e. R1 ←
5
● Register
● Indicate which register holds the operand
Addressing Modes
● Register Indirect
● Indicate the register that holds the number of the
register that holds the operand R1
MOV R1, (R2)
R2 = 3
● Autoincrement / Autodecrement
● Access & update in 1 instr. R3 = 5
● Direct Address
● Use the given address to access a memory
location
Addressing Modes
● Indirect Address
● Indicate the memory location that holds the
address of the memory location that holds the
data
AR = 101

100
101 0 1 0 4
102
103
104 1 1 0 A
Addressing Modes

● Relative Address
0
● EA = PC + Relative Addr
1
PC = 2 2

100
AR = 100
101
102 1 1 0 A
Could be Positive 103
or Negative 104
(2’s Complement)
 Addressing Modes
● Indexed
● EA = Index Register + Relative Addr

Useful with XR = 2
“Autoincrement” or
“Autodecrement”
+

100
AR = 100
101
Could be Positive
or Negative 102 1 1 0 A
(2’s Complement) 103
104
 Addressing Modes
● Base Register
● EA = Base Register + Relative Addr

Could be Positive AR = 2
or Negative
(2’s Complement)
+

100 0 0 0 5
BR = 100
101 0 0 1 2
102 0 0 0 A
Usually points 103 0 1 0 7
to the beginning 104 0 0 5 9
of an array
 Addressing Modes
Nam Asse ble sy tax Addressingfunctio
● The different e m r n n
ways in Immediat # alue O eran = Value
which the e V p d
location of an Registe Ri E = Ri
operand is r A
Absolute (Direct LO E = LO
specified in ) C A C
an instruction Indirec ( i) E = [Ri ]
are referred t R
(LOC A = [LOC
E
to as ) A ]
addressing Index X( i) E = [Ri ] + X
modes. R A
Bas wit index ( i ,Rj ) E = [Ri ] + [Rj ]
e h R A
Bas wit index X( i,Rj ) E = [Ri ] + [Rj ] + X
e an hoffse R A
d t
Relativ X(PC E = [PC + X
e ) A ]
Autoincreme t ( i) E = [Ri ] ;
n R + AIncreme t Ri
n
Autodecremen −( i ) Decreme t R i ;
t R n E = [Ri]
A
Indexing and Arrays
● Index mode – the effective address of the operand
is generated by adding a constant value to the
contents of a register.
● Index register
● X(Ri): EA = X + [Ri]
● The constant X may be given either as an explicit
number or as a symbolic name representing a
numerical value.
● If X is shorter than a word, sign-extension is needed.
Indexing and Arrays
● In general, the Index mode facilitates access
to an operand whose location is defined
relative to a reference point within the data
structure in which the operand appears.
● Several variations:
(Ri, Rj): EA = [Ri] + [Rj]
X(Ri, Rj): EA = X + [Ri] + [Rj]
Relative Addressing
● Relative mode – the effective address is determined
by the Index mode using the program counter in
place of the general-purpose register.
● X(PC) – note that X is a signed number
● Branch>0 LOOP
● This location is computed by specifying it as an
offset from the current value of PC.
● Branch target may be either before or after the
branch instruction, the offset is given as a singed
num.
Additional Modes
● Autoincrement mode – the effective address of the operand is
the contents of a register specified in the instruction. After
accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
● (Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit
operands, and 4 for 32-bit operands.
● Autodecrement mode: -(R i) – decrement first
Mov N,
Mov
e #NUM1,R
R1 Initializatio
e
Clea 2
R n
LOO r
Ad 0
(R2)+,
P Decremen
d R
R0
t
Branch> 1
LOO
Mov
0 R0,SU
P
e M

Figure 2.16. The Autoincrement addressing mode used in the program of Figure 2.12.
Assembly
Language
Types of Instructions
● Data Transfer Instructions
Name Mnemonic
Data value is
Load LD not modified
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
 Data Transfer Instructions
Mode Assembly Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC+ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR+XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1+1
 Data Manipulation Instructions
● Arithmetic Name Mnemonic
Increment INC
● Logical & Bit Manipulation Decrement DEC
Add ADD
● Shift Subtract SUB
Multiply MUL
Divide DIV
Name Mnemonic Add with carry ADDC
Clear CLR Subtract with borrow SUBB
Complement COM Negate NEG
Name Mnemonic
AND AND Logical shift right SHR
OR OR Logical shift left SHL
Exclusive-OR XOR Arithmetic shift right SHRA
Clear carry CLRC Arithmetic shift left SHLA
Set carry SETC Rotate right ROR
Complement Rotate left ROL
COMC
carry Rotate right through
Enable interrupt EI RORC
carry
Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Subtract A – B but
Call CALL don’t store the result

Return RET
Compare
CMP
(Subtract) 10110001
Test (AND) TST
00001000

Mask
00000000
Conditional Branch
Instructions

Mnemonic Branch Condition Tested Condition

BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0
Basic Input/
Output
Operations
I/O
● The data on which the instructions operate
are not necessarily already stored in memory.
● Data need to be transferred between
processor and outside world (disk, keyboard,
etc.)
● I/O operations are essential, the way they
are performed can have a significant effect
on the performance of the computer.
Program-Controlled I/O
Example
● Read in character input from a keyboard and
produce character output on a display
screen.
Rate of data transfer (keyboard, display, processor)
Difference in speed between processor and I/O device
creates the need for mechanisms to synchronize the
transfer of data.
A solution: on output, the processor sends the first
character and then waits for a signal from the display
that the character has been received. It then sends the
second character. Input is sent from the keyboard in a
similar way.
 Program-Controlled I/O
Example

- Registers
- Flags
- Device
interface
Program-Controlled I/O
Example
● Machine instructions that can check the
state of the status flags and transfer data:
READWAIT Branch to READWAIT if SIN = 0
Input from DATAIN to R1

WRITEWAIT Branch to WRITEWAIT if SOUT = 0

Output from R1 to DATAOUT
Program-Controlled I/O
Example
● Memory-Mapped I/O – some memory
address values are used to refer to
peripheral device buffer registers. No special
instructions are needed. Also use device
status registers.

READWAIT Testbit #3, INSTATUS

Branch=0 READWAIT
MoveByte DATAIN, R1
 Program-Controlled I/O
Example
● Assumption – the initial state of SIN is 0 and
the initial state of SOUT is 1.
● Any drawback of this mechanism in terms of
efficiency?
● Two wait loops processor execution time is wasted
● Alternate solution?
● Interrupt
Stacks
Home Work
● For each Addressing modes mentioned
before, state one example for each
addressing mode stating the specific benefit
for using such addressing mode for such an
application.
Stack Organization
Current
Top of
● LIFO Stack
0
TOS
Last In First Out 1
2
3
4
5
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack 10 0 0 1 5
Bottom Stack
Stack Organization
Current 1 6 9 0
Top of
● PUSH Stack
0
TOS
SP ← SP – 1 1
M[SP] ← DR 2
3
If (SP = 0) then (FULL ← 1)
4
EMPTY ← 0 5 1 6 9 0
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack 10 0 0 1 5
Bottom Stack
Stack Organization
Current
Top of
● POP Stack
0
TOS
DR ← M[SP] 1
SP ← SP + 1 2
3
If (SP = 11) then (EMPTY ← 1)
4
FULL ← 0 5 1 6 9 0
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack 10 0 0 1 5
Bottom Stack
Stack Organization
● Memory Stack
● PUSH PC 0
1
SP ← SP – 1 2
M[SP] ← DR
● POP AR 100
DR ← M[SP] 101
102
SP ← SP + 1

200
SP 201
202
Reverse Polish Notation
● Infix Notation
A+B
● Prefix or Polish Notation
+AB
● Postfix or Reverse Polish Notation (RPN)
AB+
(2) (4) * (3) (3) * +
RPN (8) (3) (3) * +
A*B+C*D AB*CD*+
(8) (9) +
17
Reverse Polish Notation
● Example
(A + B) * [C * (D + E) + F]

(A B (D E C*F+*
+) +)
Reverse Polish Notation

● Stack Operation
(3) (4) * (5) (6) * +
PUSH 3
PUSH 4
6
MULT
PUSH 5 30
4
5
PUSH 6
3
42
12
MULT
ADD
 Additional
Instructions
Logical Shifts
● Logical shift – shifting left (LShiftL) and shifting right
(LShiftR)
C R 0
0

before 0 0 1 1 1 0 . . . 0 1 1
:

after 1 1 1 0 . . . 0 1 1 0 0
:
(a) Logical shift LShiftL
left #2,R0

0 R C
0

before 0 1 1 1 0 . . . 0 1 1 0
:

after 0 0 0 1 1 1 0 . . . 0 1
:
(b) Logical shift igh LShiftR #2,R0
r t
Arithmetic Shifts

R C
0

before 1 0 0 1 1 . . . 0 1 0 0
:

after 1 1 1 0 0 1 1 . . . 0 1
:
(c) Ar ithmetic shift igh AShiftR #2,R0
r t
 C R
0
. . .

Rotate
before 0 0 1 1 1 0 0 1 1
:
after 1 1 1 0 . . . 0 1 1 0 1
:
(a) Rotate left without y RotateL
carr #2,R0

C R
0
before 0 0 1 1 1 0 . . . 0 1 1
:
after 1 1 1 0 . . . 0 1 1 0 0
:
(b) Rotate left with y RotateLC
carr #2,R0

R C
0
before 0 1 1 1 0 . . . 0 1 1 0
:
after 1 1 0 1 1 1 0 . . . 0 1
:
(c) Rotate irght without y RotateR
carr #2,R0

R C
0

before 0 1 1 1 0 . . . 0 1 1 0
:
after 1 0 0 1 1 1 0 . . . 0 1
:
(d) Rotate irght with y RotateRC
carr #2,R0
Figure 2.32. Rotate
instructions.
Multiplication and Division
● Not very popular (especially division)
● Multiply Ri, Rj
Rj ← [Ri] х [Rj]
● 2n-bit product case: high-order half in R(j+1)
● Divide Ri, Rj
Rj ← [Ri] / [Rj]
Quotient is in Rj, remainder may be placed in R(j+1)
Encoding of
Machine
Instructions
Encoding of Machine
Instructions
● Assembly language program needs to be converted into machine
instructions. (ADD = 0100 in ARM instruction set)
● In the previous section, an assumption was made that all
instructions are one word in length.
● OP code: the type of operation to be performed and the type of
operands used may be specified using an encoded binary pattern
● Suppose 32-bit word length, 8-bit OP code (how many instructions
can we have?), 16 registers in total (how many bits?), 3-bit
addressing mode indicator.
● Add R1, R2 8 7 7 1
0
● Move 24(R0), R5
OP Sourc Des Other
● LshiftR #2, R0 code e t info
● Move #$3A, R1
● Branch>0 LOOP (a) One-word
instruction
Encoding of Machine
Instructions
● What happens if we want to specify a memory
operand using the Absolute addressing mode?
● Move R2, LOC
● 14-bit for LOC – insufficient
● Solution – use two words

OP Sourc Des Other

code e t info
Memory address/Immediate operand

(b) Two-word
instruction
Encoding of Machine
Instructions
● Then what if an instruction in which two operands
can be specified using the Absolute addressing
mode?
● Move LOC1, LOC2
● Solution – use two additional words
● This approach results in instructions of variable
length. Complex instructions can be implemented,
closely resembling operations in high-level
programming languages – Complex Instruction Set
Computer (CISC)
Encoding of Machine
Instructions
● If we insist that all instructions must fit into a single
32-bit word, it is not possible to provide a 32-bit
address or a 32-bit immediate operand within the
instruction.
● It is still possible to define a highly functional
instruction set, which makes extensive use of the
processor registers.
● Add R1, R2 ----- yes
● Add LOC, R2 ----- no
● Add (R3), R2 ----- yes