The State of The Book

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RW W FE ATURE

Vadim Issakov

IMAGE LICENSED BY INGRAM PUBLISHING


The State of the
Art in CMOS VCOs
T
here is a growing interest in the realization with transit frequencies ^ fT h and maximum oscillation
of highly integrated radar transceivers op- frequencies ( fmax ) exceeding several hundreds of giga-
erating at millimeter-wave (mm-wave) fre- hertz. This enables the realization of highly integrated,
quencies. In this case, CMOS is the natural digitally intensive transceiver systems on chip for mm-
technology choice. Modern nanoscale CMOS wave applications, such as 77-GHz automotive radar
technologies offer excellent transistor performance [1] or wireless data communication systems [2]. Several

Vadim Issakov (Vadim.Issakov@ovgu.de) is with the Otto von Guericke University Magdeburg, Germany.
This work was written when he was working at Infineon Technologies, Neubiberg, Germany.
Digital Object Identifier 10.1109/MMM.2019.2941633
Date of current version: 12 November 2019

December 2019
1527-3342/19©2019IEEE 59
advanced nanoscale CMOS nodes even surpass the fT of a number of delay cells (CMOS inverters or simple
and fmax values achieved by silicon germanium (SiGe) differential pairs loaded by resistive loads), designed
heterojunction bipolar transistor technologies [3]. such that they fulfill the Barkhausen criteria to sustain
The voltage-controlled oscillator (VCO) is the heart a stable oscillation [5]. The main advantage of these
of every mm-wave radar or communication system. It circuits is the lack of integrated inductors and, thus,
needs to fulfill very challenging requirements, such as a very compact chip area and wide tunable frequency
low phase noise (PN), and, simultaneously, a wide fre- range. However, ring oscillators have a significantly
quency tuning range (FTR). This is particularly challeng- higher PN than their LC oscillator counterpart.
ing at mm-wave frequencies. The lowest possible PN Therefore, despite many advantages, this VCO type is
is required to achieve the best target discrimination in not usable at mm-wave frequencies. To my knowledge,
radar systems or to enable efficient modulation schemes the fastest operation frequency of an inductorless ring
with large symbol constellations in communication sys- oscillator reported so far is 32 GHz in [6].
tems. Additionally, a wide FTR is required in frequency- The LC oscillator is based on a resonant tank circuit
modulated, continuous-wave radar sensors to achieve consisting of an integrated inductor L and capacitor
the high range resolution needed for many applications, C. The losses of the physical components can be rep-
such as car radar or gesture recognition. Multigigahertz resented by a parallel resistor Rp (Figure 1). To have a
FTR requires the use of large varactors, which degrade sustainable oscillation, the losses of the tank must be
the VCO PN due to the low quality factor they exhibit compensated for by a negative resistance R act, gener-
at mm-waves. This poses a tradeoff between low PN ated by the active circuitry. For example, as shown in
and achievable FTR [4]. In this article, these tradeoffs Figure 1(b), a cross-coupled pair is used as an active
are addressed systematically, with a discussion of the circuit, with the negative resistance seen looking into
technology limitations, and an overview is given of the the drains given by [7]
recently published mm-wave state-of-the-art VCOs.
R act = - 2 , (1)
gm
RF CMOS VCO Basics
There are two main types of commonly used where g m is the transconductance. This implies that, to
integrated CMOS VCOs: RC ring oscillators [Fig- generate more negative resistance, one needs to burn
ure 1(a)] and inductance–capacitance (LC) oscilla- more current. The center oscillation frequency is sim-
tors [Figure 1(b)]. The ring oscillators are composed ply given by
f0 = 1 . (2)
2r LC
By varying the capacitance, one can tune the center
frequency. However, the varactor has a limited qual-
τ τ τ τ
ity factor at mm-wave frequencies. This deteriorates
the quality factor of the resonator and degrades the PN.
(a) Hence, there is an inherent tradeoff between the wide
Vdd FTR and low PN. Nevertheless, the LC VCO is the
most popular type of oscillator in CMOS at mm-wave
L
frequencies due to the low power dissipation and low
Rp Passive achievable PN. The main disadvantage of the LC VCO is
LC Tank that it requires at least one tank inductor, which results
C
in a larger area consumption compared to the ring oscil-
lator. Finally, there are several options for distributed
–Ract oscillators that can be implemented in CMOS at mm-
Vo+ Vo– wave frequencies, such as the rotary traveling wave
[8]. However, these circuits are complex to design and
consume a larger chip area than a single LC VCO. Even
Active though distributed VCOs can achieve excellent per-
Circuit
formance, the following sections focus only on the LC
VCO, since it is the most common approach used in the
lower mm-wave frequency range, such as for commer-
(b) cial applications operating at 60 or 77 GHz. For VCOs
operating at fundamental oscillation frequencies in the
Figure 1. The common types of CMOS oscillators: (a) the upper mm-wave region, toward 300 GHz (approach-
RC ring oscillator and (b) the LC oscillator. ing fmax of the available technologies), both distributed

60 December 2019
standing-wave VCOs [9] and even inductively loaded mm-wave frequencies. An LC VCO usually has more
ring VCOs [10] again become a very interesting and than a single inductive device; therefore, coupling
viable option. between these devices must be carefully modeled in an
electromagnetic field solver. Several inductor-shielding
mm-Wave VCO Design Challenges techniques and “8”-shaped coils can be used to reduce
As opposed to a VCO operating at the classical RFs of a the crosstalk. Their efficiency is analyzed empirically up
few gigahertz, the design of VCOs at mm-wave frequen- to mm-wave frequencies in [21].
cies (per definition, 30–300 GHz) poses several additional Finally, as the operation frequency increases to-
challenges. First, running an LC VCO at the fundamental ward higher mm-wave frequencies, the inductor size
mm-wave frequency has disadvantages, since the qual- decreases almost quadratically [11]. This means that
ity factor of varactors or switched-capacitor banks drops the parasitic inductance of the traces becomes compa-
rapidly with increasing frequency. This leads to PN deg- rable to the values of wanted inductors in the range of a
radation in the thermal region and smaller output power few picohenrys; eventually, it makes more sense to use
[11]. A common solution to this is to operate a VCO at a short transmission lines instead.
lower RF and then increase it to the wanted mm-wave
frequency without introducing additional noise. This is PN of LC VCOs
achieved typically by a frequency multiplier (e.g., qua- The PN of resonator-based VCOs can be described
drupler [12]), subharmonic injection-locking techniques using an empirical expression by Leeson [22]. The PN
[13], extraction of harmonics (e.g., second [4] or third at a frequency offset Δf from a carrier at f0 is given by
harmonic [14], [15]), or any combination of these tech-
2

L ^Δf h = 10 $ log ) 2FkT =1 + e o Ge 1 + o3 ,(3)


niques. The choice of lower frequency at which to oper- f0 Δfc
ate the VCO has been thoroughly analyzed in [16]. Psig 2Q tank Δf Δf
Unfortunately, it appears that the flicker noise cor-
ner frequency gets worse for VCOs operating at mm- where F is the noise excess factor of the active device; k
wave frequencies [15]. Furthermore, the cause itself is the Boltzmann’s constant; T is the absolute tempera-
(1/f noise) gets worse for smaller-scale CMOS technol- ture; Q tank is the loaded quality factor of the tank; Psig
ogy nodes. Considerable research is ongoing on PN is the oscillation power, which is roughly related to the
2
reduction in the flicker noise region by shaping of the oscillation amplitude as Psig ~V osc; f0 is the oscillation fre-
oscillation waveforms, as discussed in the “PN Opti- Δf
quency; and c is the flicker noise corner frequency. This
mization in the Flicker Noise Region 1/Δf 3” section. expression is shown graphically in Figure 2. At small off-
Another major challenge of mm-wave VCOs, as set frequencies from a carrier, the PN exhibits a slope of
opposed to RF VCOs, is the higher impact of device par- 1/Δf 3, that is, 30 dB per decade. This region of offset fre-
asitics and passive interconnects (e.g., chip layout and quencies is dominated by the flicker noise upconversion.
package transitions). Several unwanted effects might In CMOS, this is particularly challenging, since the 1/f
take place. First, parasitic capacitors add up to the noise corner frequency is very high. Above that, the slope
wanted (tunable or switched) capacitance and degrade is 20 dB per decade. This is the offset frequencies region
the tuning range [11]. The values of parasitic capaci- dominated by thermal noise upconversion. Finally, at
tance might be in the range of the wanted capacitors. higher offset frequencies from the carrier, the spectrum
This is particularly challenging for realizing digitally is flat, limited by the noise floor of the active circuit (see
controlled oscillators (DCOs) at mm-wave frequen- Figure 1), which is given by kTF/Psig [3].
cies. Solutions can be magnetic tuning [17] or capaci-
tive tuning with reconfigurable passive resonators [18]
or capacitive divider ladder networks C-2C [19], which
PN (dBc/Hz)

are discussed in the “Advanced mm-Wave VCO Cir- Flicker Noise


1/∆f 3 (30 dB/decade)
cuit Techniques” section. Second, current return paths
are extremely important and might shift the common-
mode (CM) resonance frequency. This might degrade Thermal Noise
the PN and even cause unwanted oscillations if the CM 1/∆f 2 (20 dB/decade)
return path is not well defined.
It is challenging to accurately model the transitions Noise Floor
to external decoupling capacitors and the supply path at
mm-wave frequencies. Several techniques for codesign
∆f c Offset ∆f (Hz)
and cosimulation of circuits and package transitions are
proposed in [20]. Furthermore, the coupling between
neighboring integrated coils increases significantly at Figure 2. The PN spectrum of a resonator-based oscillator.

December 2019 61
Choice of VCO Circuit Topology seen as a series combination of C 1 and C 2. Hence, the
At mm-wave frequencies, a differential circuit topology oscillation frequency is given by
is highly recommended. When deciding to use any of
the three-point VCOs (Clapp, Colpitts, or Hartley) [7], f0 = 1 .(4)
.
one should choose a differential variant of such. The 2r L tank C 1 C 2
C1 + C2
reason for this is a higher immunity to CM interference
of differential signaling compared to the single-ended The negative resistance for these two types, seen in the
counterpart, when applied to distribution of the local terminals of the transistor, is given by
oscillator signal generated by the VCO. Additionally, gm
Rs = - . (5)
the cross-coupled topology is the most popular inte- ^ 2rf0 h2 C 1 C 2
grated CMOS VCO realization. The simplest circuit
realizations are shown in Figure 3. The passive reso- Using the well-known series-to-parallel transformation
nant tank is marked in blue for all three topologies. The and assuming a high value of tank quality factor, one
active parts, which generate the negative equivalent can approximate the equivalent parallel tank resis-
resistance that should compensate for the losses of the tance as R p . R s Q 2tank = R s ^L tank ~ 0 /R s h2 = ^L tank ~ 0 h2 /R s .
resonant tank, are marked in red. Ne x t, by c om bi n i ng t h i s e x pr e s sio n w it h (4)
Unfortunately, Clapp and Colpitts topologies are a nd (5) (note that ~ 0 = 2rf0 ), the start-up condi-
often confused in the literature. The operating fre- tion g m $ R p $ ^C 1 + C 2 h2 /C 1 C 2 = ^C 1 /C 2 h + ^C 2 /C 1 h + 2
quency and start-up condition are equal for these two is obtained [7]. The g m is minimized for C 1 = C 2, and
topologies. The equivalent input capacitance for both is the oscillation condition simplifies to g m $ R p $ 4. For

Vdd Vdd

LD LD Ltank Ltank

Vo+ Vbias Vo– Vo+


Ct Ct Vbias Vo–
Ltank
C1 C1 C1 C1

C2 C2
Vtune C3

LS LS C2 C2

(a) (b)

Vdd Vdd

Ltank Ltank

Cvar Cvar
Vb
Vo+ Vo– Vo+ Vo–

lD1 lD2 lD1 lD 2

IB IB CT

(c) (d)

Figure 3. The common types of resonant-tank-based LC VCOs: (a) Clapp, (b) Colpitts, (c) class-B, and (d) ac-coupled cross-
coupled oscillators.

62 December 2019
the cross-coupled oscillator, the start-up condition is negligible by design and might mask the aforemen-
g m $ R p $ 1. This means that one needs one quarter of tioned idealized considerations.
the transconductance g m and, therefore, much less cur- In large signal operation, the Colpitts oscillator exhib-
rent to achieve the oscillation. Alternatively, one can its waveforms similar to class-C operation, whereas the
allow for a lower quality factor of the tank and lower classical cross-coupled VCO [see Figure 3(c)] exhibits a
R p while spending the same current. The more robust class-B-type operation. Idealized current and voltage
oscillation start-up is one of the reasons that cross-cou- waveforms are compared in Figure 4.
pled oscillators are preferred over three-point ones. The drain voltages in both topologies swing about the
Next, for a comparison of VCO topologies, con- CM level of Vdd . In class-B operation [Figure 4(a)], the cur-
sider t he f ig u re of mer it (FoM) a nd FOM T (FoM rent is fully steered into the left or right branch, resulting
including FTR) in a duty cycle (conduction angle) of about 50%. When the
almost-square-wave current with a period of T = 1/f0 is
2

FoM = - 10 log =L ^Δf h $ PDC ^mW h $ e o G,


Δf transformed to the frequency domain, the spectral com-
f0 ponent at f0 has an amplitude I f 0 . 2/r $ I B . First, this
2 
means that current efficiency h I is not high. Next, when
FoM T = - 10 log =L ^Δf h $ PDC ^mW h $ e oG
Δf FTR . (6)
$ the current flows through the differential tank resistance,
f0 10
as shown in Figure 1(b), one obtains a differential volt-
We will consider the definition of the power effi- age swing of Vosc = V +O - V -O . 2/r $ I B $ R p . By increas-
ciency of a VCO h P, that is, the ratio between the RF ing the current, one can increase the voltage swing A diff ;
power in the tank PRF and the dc power dissipated in this operation region is known as current limited. This
VCO PDC, which is composed of voltage and current works until the peak voltage limit of 2Vdd is reached,
efficiencies [23]: known as the voltage-limited operation region. Accord-
ing to the Leeson’s expression in (3), increasing signal
hP =
PRF = I RF $ VRF = h h , (7) power Psig reduces the PN. For a given resonant-tank
I V
PDC I DC VDC
equivalent parallel resistance R p in Figure 1(b), increas-
where I RF and VRF are the root mean square values of ing voltage swing increases the power and reduces
the fundamental oscillation component of the current the PN Psig ? V osc2
/ ^2R p h. Thus, the PN improvement
and voltage in the tank and IDC and VDC are the supply in a single-core, cross-coupled VCO is limited by sup-
current and voltage, respectively [23]. ply voltage. A simplified qualitative description of the
Finally, consider the excess noise factor (ENF), which
describes by how far the VCO FOM is below the maxi-
mum theoretically achievable FOM. The lower the VOut
ENF, the better and more efficient the VCO. Vo+
Under several idealized assumptions, it was shown Vdd
in [23] that the upper bound on FoM and the lower
Vo–
bound on ENF are given as
t
ID
FoM = 173.8 + 10 log = G,
2h P Q 2 IB
ID1
1 + c MOS

ENF = 10 log ; E,
1 + c MOS ID2
(8)
hP t
(a)
where c MOS is the metal–oxide-semiconductor (MOS)
transistor noise ENF (typically in the range from 0.66 VOut
to 1.5). This means that the only way to reduce the low- Vo+
est bound on ENF, related to the thermal noise of the Vdd
transistor and neglecting other noise mechanisms, is to
Vo–
increase the power efficiency. Similarly, the only way
to improve the maximal achievable FoM is to increase t
ID ~3IB
the power efficiency h P and the quality factor Q of the ID2 ID1
resonator tank. The only way to improve h P is to use
higher classes of operation, which are defined similarly
t
as for power amplifiers by conduction angle (a higher (b)
class leads to smaller the conduction angle). However,
in practice, there are additional noise contributions, Figure 4. The current and voltage waveforms in (a) class-B
discussed later in this article, that cannot be made cross-coupled and (b) class-C and Colpitts VCOs.

December 2019 63
steady-state oscillation amplitude versus bias current I B the cross-coupled pair, the bias voltage can be set to a
is shown in Figure 5. At lower current levels, the ampli- desired value. In case of class C, the bias voltage VB in
tude is proportional to the bias current, and the oscilla- Figure 3(d) is set quite low, typically to . VDD /3 [25].
tor operates in the current-limited region. When further Additionally, a large capacitor CT is attached in parallel
increasing the current to the point at which the oscilla- to the current source. This causes the drain current to be
tion amplitude increases to almost 2Vdd, the transistors shaped as tall and narrow pulses, as shown in Figure 4(b).
enter the triode region, and the VCO enters the voltage- When Fourier decomposition of this waveform is con-
limited region. As a rule of thumb, using the qualitative sidered, the spectral component of the current at the
description in Figure 5, it is recommended that an ini- fundamental oscillation frequency f0 has the amplitude
tial bias point be placed at the transition between these of I B [26]. Therefore, the current efficiency h I reaches
two regions. Increasing the bias current beyond this 100%. However, class C has a disadvantage in that, at
point would not increase the oscillation amplitude, but large voltage-oscillation amplitudes, the transistors may
it would cause an additional power dissipation without enter the triode region and thus deteriorate the PN.
any advantage [24]. According to [23], the best ENF is achieved by the
Class-C operation can also be achieved using the class-B VCO by using an ac coupling and LC filter at
cross-coupled topology of the configuration shown in the tail node. Since the current efficiency in class B is
Figure 3(d). Thanks to the ac coupling at the gates of lower than 100%, one would need a peak-to-peak oscil-
lation amplitude above 2Vdd to achieve 100% power
efficiency, but this would pose device-reliability con-
cerns. Therefore, 100% power efficiency for class B is
Vosc
only a theoretical value.
2Vdd Another option is to use N-type MOS (NMOS)/
p-type MOS (PMOS) complementary VCO topology
to achieve 100% power efficiency [23]. However, this
approach is limited so far at mm-wave frequencies since
Current Voltage PMOS is slower than NMOS. However, PMOS is catch-
Limited Limited ing up in the newest nanoscale CMOS technologies.
Alternatively, excellent FoM values can be achieved
IB in class-F topology by means of waveform shaping
(Figure 6). In this way, the voltage waveform becomes
Figure 5. The differential amplitude in a class-B cross- more square-like, and the voltage efficiency increases
coupled VCO versus bias current. [24]. However, this is not easily applicable at mm-
wave frequencies because, in addition to the LC tank
resonator at the fundamental frequency f0, we need
Vdd to realize a resonator at 3f0 . Even more challeng-
ing is the condition that, to reduce the PN, the reso-
nance tank at 3f0 should have a higher quality factor
than the tank at fundamental frequency f0 [24]. So
Ltank
f0 far, there are several class-F topologies reported in
Ctank CMOS, mainly in the low-gigahertz RF frequencies
[27]. Fewer VCOs have been reported in the mm-wave
frequency range [28].
3f0 3f0 A systematic comparison between differential
Colpitts and differential cross-coupled LC VCOs in
class-B operation is presented in [29]. First, it shows
Vo+ Vo– that, under conditions of fair comparison (same oscil-
lation frequency, power consumption, tank inductors,
and losses), both topologies achieve the same voltage
ID 1 ID 2 amplitude. Also, the thermal noise contribution from
the lossy tank to the overall PN N L,Rt is equal for both
topologies. Finally, the ratio of PN contributions from
IB
transistors N L,Ids is given by [29]

N L, Ids, Colpitts c Colpitts 1 - n , (9)


=
Figure 6. A class-F cross-coupled VCO. N L, Ids, Cross - coupled c Cross - coupled n

64 December 2019
where n / C 1 /C 1 + C 2 for Colpitts topology and n opt frequency, at which we can minimize the expression
is equal to 1/3 for c Colpitts = 1. Thus, under the assump- R p /Q 2tank. Consider realizing a VCO at a lower fre-
tion that MOS transistors have the same excess noise quency fosc = f0 /N, where N is the ratio of the output
c Colpitts . c Cross - coupled = 1, the Colpitts VCO has twice frequency (in this example, f0 = 60 GHz) and the fun-
the higher PN contribution in the 1/Δf 2 region, resulting damental oscillation frequency of the VCO (e.g., fosc
in approximately 2-dB-degraded PN. = 15 GHz, if we use a frequency multiplier of N = 4).
The Colpitts VCO needs a higher current (or higher According to (3), reducing the oscillation frequency by
quality factor of the tank) to achieve a robust oscil- N results in a 20 log ^N h PN reduction (improvement).
lation start-up, and it generates a higher PN than its Assuming a noiseless frequency multiplication by
cross-coupled equivalent. The following sections focus N to get to an output frequency of f0 = 60 GHz, the
on the cross-coupled topology, which is the most popu- PN is increased by 20 log ^N h, ideally resulting in the
lar in CMOS. There are numerous options for optimi- same value. This means that there is no theoretical PN
zation of the FoM and absolute PN for this topology, penalty for doing so. On the contrary, considering the
e.g., by a higher class operation, biasing circuitry, and physical implementation, we can physically achieve
coupling of several cores. higher quality factor values of components at lower
frequency and translate this advantage to the desired
Design Considerations for mm-wave output frequency by an almost noiseless
Cross-Coupled LC VCOs frequency multiplication.
This section systematically addresses the design For low PN, one needs to minimize R p and maxi-
aspects of mm-wave cross-coupled LC VCOs in CMOS. mize Q tank. Maximizing Q tank is also necessary for
increasing the maximum possible FoM , as seen in (8).
PN Optimization in the Thermal Both R p and Q tank are technology related and depend
Region 1/Δf 2 on the choice of metal stack and quality factor of varac-
By revisiting Leeson’s equation (3), considering only tors and capacitors.
the thermal noise frequency region for a class-B oscil- One can make another observation about the choice
lator with an ideal current source, and substituting of the tank inductance L value. The parallel resistance
2
Psig = V osc / ^2R p h, (3) may be rewritten in simplified of the tank can be rewritten as
form as
R p = L~ 0 Q tank = Q tank L . (11)
2

L ^Δf h = 10 $ log ) kTF e o 3 .(10)


R p f0 C
V 2osc Q 2tank Δf
If one needs a lower R p and high Q tank, the inductance
The minimal value of F is set by the technology. For a must be minimized without degrading the quality fac-
standard current-biased LC VCO NMOS topology, the tor of the inductor, since it affects the total tank quality
minimum possible noise factor is given by F = 1 + c MOS factor given by
[30], where c MOS is the channel noise coefficient of
Q tank = c 1 + 1 m , (12)
-1
an NMOS transistor, as explained previously for (8). QL QC
Therefore, there is not much one can do to push F
below a certain value set by the technology (typically where Q L and Q C are the qualify factors of the induc-
approximately 2–3). tor and the overall capacitance (including the fixed
To optimize for the lowest achievable PN (as and variable parts). Therefore, one must find a sweet
needed for radar applications), designers try to spot of inductor geometry that gives a maximum
achieve the maximum possible voltage swing of about quality factor and minimal inductance. One can start
2Vdd . However, the supply voltage Vdd of advanced with a high-quality-factor inductor and start reducing
nanoscale CMOS technologies continuously reduces its dimensions until the optimal point is reached, as
with lower gate sizes, due to the constant field scal- shown in Figure 7 [31].
ing. Supply-voltage scaling, therefore, leads directly If one reduces R p by reducing L, there would
to PN degradation. A typical value of Vdd for a 28-nm need to be an increase in tank capacitance C. Higher
CMOS technology is 0.9 V, and it continues decreasing capacitance results in large devices, and, due to para-
for lower nodes. sitic capacitance, this will limit the FTR. Finally, if we
Additionally, there is a need to minimize the reduce R p but need to maintain the oscillation ampli-
expression ^R p $ f 02 h /Q 2tank. If one realizes an oscillator tude, we would need to increase the bias current to
at a mm-wave frequency (e.g., f0 = 60 GHz), the qual- compensate for the lower R p, since, as we mentioned
ity factor of the tank will be low. Therefore, it might be previously, Vosc . 2/r $ I B $ R p.
not optimal to realize a VCO at the fundamental fre- An interesting question is determining the optimal
quency of f0 = 60 GHz. It makes sense to use a lower frequency for PN minimization. A thorough comparison

December 2019 65
of two scenarios for frequency generation and analysis of Another effect that contributes to PN degradation in
the optimal oscillation frequency was carried out in [16] the 1/∆f 2 region is related to the thermal noise of the
(Figure 8). The authors show that the optimal frequency tail-current source at 2f0, which is directly downcon-
for minimizing the expression R p /Q 2tank for an ultra- verted to PN around f0 . A solution to this is to filter
scaled CMOS technology lies at approximately 5 GHz. the noise at the second harmonic by a large tail capac-
They use the ratio of the inductors’ self-resonance fre- itance C tail . Additionally, a series inductance L tail is
quency (SRF) to the operation frequency for the analysis used to resonate with tail capacitance and parasitic
d = fSRF /fosc . A high value of d indicates a small induc- capacitance to form a high impedance at the second
tor value (and vice versa). As one can see in Figure 9(a), harmonic [32].
the sweet spot for lowest PN is achieved at 5 GHz and
for small inductor values (large d ). On the other hand, PN Optimization in the Flicker
the maximum achievable FoM in (8) depends on Q tank Noise Region 1/Δf 3
(power efficiency h P is fixed by the choice of topology). Flicker noise is modulated onto the oscillation as side-
According to the study in [16], the Q tank tends to increase bands and contributes to the PN close to the carrier. In
for large inductor values, as shown in Figure 9(b). This radar systems operating with very low intermediate fre-
means that optimizing for the lowest PN and highest quencies, the absolute value of PN in the flicker noise
FoM results in different inductance values, and these region is critical. Unfortunately, the MOS transistor has a
conditions cannot be satisfied simultaneously. Addi- very high flicker noise due to interface states and, thus,
tionally, there is a physical limit to increasing quality exhibits very high corner frequencies of several mega-
factor by increasing the inductor size due to the sub- hertz, as opposed to the few kilohertz exhibited by a
strate losses, resulting in optimum inductance value. bipolar transistor [33], making it very difficult to achieve
PN values in CMOS comparable to SiGe realizations.
Rael and Abidi [34] provide an initial description
of two mechanisms describing how the flicker noise
of the tail current source (M T in Figure 10) at low fre-
quency fm upconverts to the oscillation frequency

40 µ m 100 µ m 180 µ m 12
Our Design 10 δ=3
35 Choice 500 δ=5
8
Rp /Qtank (dBΩ)
Parallel Resistance (Ω)

30 6
Q 400 δ = 10
Quality Factor

25 4
2

20 Rp 300 2
15 0
200
–2 δ = 15
10
100 –4
5 0 10 20 30 40
100 200 300 400 500 fOSC (GHz)
Inductance (pH) (a)
20
δ=5
Figure 7. Tank inductor optimization [31].
16
δ = 10
Qtank

12

δ = 15
fLO fOSC fLO 8
Multi-N δ=3
4
0 10 20 30 40
(a) (b) fOSC (GHz)
(b)
Figure 8. The scenarios for generating a mm-wave
frequency analyzed in [16]: (a) a fundamental oscillator at Figure 9. An analysis of the optimal frequency for PN
f LO and (b) an oscillator at lower frequency with frequency minimization [16]: (a) Rp/Q 2tank for different values of d
multiplier. and (b) the quality factor for different values of d.

66 December 2019
f0 and results in PN sidebands f0 ! fm . In the first noise upconversion. This can be achieved either by
mechanism, the switching action of the differential increasing the bias current or using larger devices.
pair commutates the noise of the tail current source Next, we consider the flicker noise contribution of
similarly to a single-balanced mixer. Noise enters the the differential pair transistors M 1, M 2 . Another Gro-
resonator as amplitude modulation (AM). Then, it szkoswski effect takes place due to parasitic device
is converted to frequency modulation (FM) through capacitances, summed as C par in Figure 11(a). This
nonlinear parasitic capacitances of the transistors, capacitance is seen as negative capacitance at the dif-
varactors, and capacitors. One solution to eliminate ferential outputs. Thus, (1) needs to be corrected as
this effect would be to use a small varactor and a large R act = - ^2/g m h - j~aC par [34]. Flicker noise of the core
bank of switched capacitors as the tank capacitance. transistors is modulated onto the current through
Another is to omit a tail-current source completely C par at the second harmonic at zero crossings. After
and use a resistor instead, making the VCO operate in the commutation through M 1, M 2, the flicker noise
the voltage-biased regime [24]. This is why, in most of is downconverted to the oscillation frequency and
our VCO realizations, the tail-current source is omit- presents an effective fluctuating capacitance. Modu-
ted [4], [35]–[38]. lation of the capacitance due to the flicker noise
The second mechanism can be the dominant effect
if the countermeasures are already taken on the first
one, and this is related to the incremental Groszkowski
Vdd
effect [39]. The steady-state oscillation frequency of
a VCO is shifted by Δf from the expected resonance
frequency set by the tank f0 = 1/ ^2r LC h. The reason Ltank
is that the differential pair generates a current with a
rich harmonic content. Higher harmonics flow into
Cvar
the lower-impedance capacitor and upset the reactive
Ract
power balance, as shown in Figure 11(b). However, the
Vo+ Vo–
harmonic content of the current in the tank is a func-
tion of the bias current I B . The shift in frequency as a
Vn2
function of current fluctuations 2f0 /2I B results in an M1 M2
indirect VCO FM by the flicker noise of the tail-current 2f0
source [34]. A very thorough and systematic analysis Cpar
of the 1/f noise upconversion effect by the incremen- Ltail
tal Groszkowski effect is provided by Bevilacqua and
Andreani in [40]. As a solution, the authors suggest that
MT Ctail
more saturated active devices are less prone to flicker

(a)

Vdd Lp Lp
Cd Cd

Ltank Cc Cc

Rp Rp
0

π/2
π/2

Cvar
IH 1

IH 3
IH 2
IH 2

Vo+ Vo– ID 2 ID 1

M1 M2
π

π
IH 3

IH 1

MT (b)

Figure 11. The 1/∆f 3 region contribution by the 1/f noise


of the differential pair. (a) The 1/f voltage noise source and
Figure 10. The tail-current source flicker noise 2f0 filtering. (b) The current harmonics path leading to the
upconversion due to AM/FM nonideality of the varactor. Groszkowski effect [41].

December 2019 67
results i n frequency sh ifts a nd PN i n t he 1/Δf 3 resonance in the tank at 2f0 in addition to the funda-
r e g io n [41]. A solution to this is to suppress the mental resonance at f0 . This causes the current at 2f0 to
current at 2f0 by a tail filter at the second harmonic, flow into the equivalent resistance and the waveform
as shown in Figure 11(a). Additionally, the flicker to become more symmetric.
noise of the transistors M 1, M 2 can be reduced by This technique is taken further by pseudosquaring the
increasing the transistor area, as seen when looking drain-voltage waveform via second-, third-, and fourth-
at the expression for the 1/f noise voltage of the MOS harmonic peaking, that is, realizing a class-F234 VCO
transistor given by V 2n ^ f h = ^K/W $ L h $ ^1/f ch6 V 2 /Hz@ [28]. Additionally, a multiresonant tank proposed in [44]
[7]. However, this creates additional parasitic capac- enables waveform shaping at the second and third har-
itance, reduces the tuning range, and degrades monics and CM-only capacitor tuning.
the maximum oscillation frequency fmax . Another Furthermore, Hu et al. [15] provide the latest find-
solution is to add a differential source capacitor and ings of flicker noise upconversion mechanisms. If one
thereby keep the amplitude of the second harmonic revises the ISF theory, the NMF is modeled as a time-
constant [42]. varying conductance, describing only the effect of
More recent insights into the upconversion mecha- carrier number fluctuation when the carriers are ran-
nism of the flicker noise of transistors M 1, M 2 can domly trapped and released at the interface. Addition-
be gained by using the impulse sensitivity function ally, [15] describes 1/f noise mechanism-correlated
(ISF) theory proposed by Hajimiri and Lee [43]. With mobility fluctuation, which becomes more important
this approach, the flicker noise upconversion can be in the latest CMOS technologies with short chan-
described as follows [15]. First, low-frequency voltage nels. The trapped electrons change the mobility of the
noise at the gate [as shown in Figure 11(a)] is modulated free electrons due to scattering. Finally, Hu et al. [45]
by means of a noise-modulation function (NMF), which prove a very interesting observation: that flicker noise
is typically modeled by a time-varying transconduc- upconversion can be reduced by narrowing the con-
tance. This results in a cyclostationary current noise duction angle, that is, by operating the voltage-based
around the harmonics k~ 0 ! Δ~, which is converted VCO in class C.
into PN through the effective ISF. It can be shown that
upconversion of flicker noise is related to the dc value Advanced mm-Wave VCO Circuit Techniques
of the effective ISF; this can be reduced by making the In this section, we briefly discuss some recent circuit
oscillation waveform more symmetric [41]. The oscilla- techniques to overcome technology limitations at mm-
tion waveform of a voltage-biased VCO tends to have wave VCOs.
asymmetrical rise and fall times due to even-order cur-
rent harmonics flowing into the capacitive part of the PN Reduction by Multiple-Core Coupling
resonant tank, as shown in Figure 11(b). This results in As discussed in previous sections, there is an ultimate
a nonzero dc value of ISF and causes the 1/f noise cur- limit on the PN level that can be achieved by a single
rent of the switching MOS devices to be upconverted VCO core due to low supply and limited quality factor
to the 1/Δf 3 PN region. Therefore, Shahmohammadi of the tank. Thus, the only viable way to further lower
et al. [41] proposed a solution by introducing an auxiliary the PN is by bilateral coupling of several identical cores
(Figure 12). Ideally, this results in improvement of PN
by 10 $ log ^N h [12], [31], [46], where N is the number
of coupled cores. The coupling between the VCO cores
can be done resistively [12], [31], [46] or inductively [38].
However, to realize the PN advantage, the coupling
network must be designed carefully. This technique is
also bounded practically by power consumption and
chip area.

Techniques to Extend FTR


There is an inherent tradeoff between PN and FTR.
To achieve a lower PN, varactors are minimized; thus,
continuously tunable FTR (required for radar appli-
cations) is reduced. To overcome this limitation, one
can consider using a silicon-on-insulator (SOI) CMOS
technology. It seems that SOI offers the advantage of
Figure 12. A quad-core, resistively coupled VCO topology varactors with lower parasitics; for example, in [38], we
for PN reduction. achieved an FTR of 36%.

68 December 2019
At the circuit level, one can apply several tech- harmonic while suppressing the fundamental and sec-
niques. The varactor can be “removed” from the ond harmonic.
resonant tank by adding a transformer and tuning
the transformer on the secondary side, as demon- Techniques for Switched-Capacitor Banks
strated in [46] and analyzed in [47]. Additionally, The frequency resolution Δf of a DCO is determined as
Nakamura [48] has proposed using a loop-ground Δf = ^1/2 h^ f0 /C tank h ΔC [19], where f0 = 1/2r LC tank is
transmission line to achieve a wide tuning range. the center frequency, C tank is the total tank capacitance,
Another promising technique is inductive tuning, L is the tank inductance, and ΔC is the switched-capac-
as shown in [49]. itor minimum capacitance. To achieve a resolution of
several kilohertz at mm-wave frequencies, one would
Techniques to Extract the Second need ΔC below attofarads, which is below the physi-
and Third Harmonics cally achievable value of the technology. The work in
As discussed previously, it makes more sense to real- [18] proposes a distributed LC fine-tuning by loading
ize a VCO at a lower frequency instead of the fun- the inductor capacitively along the length. This enables
damental at mm-waves. However, instead of using a a resolution of 160 kHz at 60 GHz. The work in [19]
frequency doubler, one can get the second harmonic proposes a C-2C with exponential steps, achieving a
“for free” by realizing a push–push VCO, since the sec- resolution of 4 Hz for a DCO operating around 60 GHz.
ond harmonic is present in the CM in several nodes in
the circuit [see Figure 11(a)]. Conclusions
In reality, it is not really free because, if a buffer is In this article, we discussed the main challenges
attached at this node, a parasitic capacitance is added and related to the design of mm-wave VCOs in advanced,
might degrade the PN of the VCO. Therefore, a trans- ultrascaled CMOS technologies. Cross-coupled VCOs
former can be used to couple out the second harmonic are most suitable for CMOS realization. It is worth-
at the source node [4], as shown in Figure 13. Alterna- while to realize a VCO at lower frequency to achieve
tively, one can distinguish the fundamental from the a sweet spot in terms of quality factor of tank com-
second harmonic by the mode of signaling. The funda- ponents and then use a push–push configuration and
mental harmonic at f0 is present in the differential mode, frequency multipliers to achieve the needed mm-wave
whereas the second harmonic 2f0 is present in the CM frequency. A summary of the state-of-the-art mm-
and can be coupled out capacitively [50]. Another tech- wave VCOs around 60-GHz published in the last years
nique for extracting a higher frequency (the third har- is given in Table 1. Due to the tradeoff between FTR
monic in this case) is presented in [14] and [15]. By means and PN, a comment regarding how frequency tuning
of a two-stage power amplifier, one can boost the third is achieved has been added.

Vdd Pin (dBm)


Pout, ZDM (dBm)
Vtune

Coupling Device
C1
f1 f2
f1
Frequency (Hz) eld ZDM
Fi L2 Frequency (Hz)
M1 M2 Inp H
Pout at f1 Is Nonzero
L1 Pout at f2 Is Negligible
EF Pout, ZCM (dBm)
T1 iel L3
Inn d
Vbias Rs Rs
ZCM
at 2f0
Vin1∠0° at f1 Vin1∠180° at f1
Vin2∠0° at f2 Vin2∠0° at f2
f2
Frequency (Hz)
Pout at f1 Is Negligible
Pout at f2 Is Nonzero
(a) (b)

Figure 13. The circuit techniques used to couple out the second harmonic for push–push VCO realization: (a) coupling
inductively at the tail node [6] and (b) coupling from the tank by mode separation [43].

December 2019 69
TABLE 1. The state of the art for CMOS VCOs around 60 GHz.

PN at
CMOS 1 MHz at fosc FOMT Frequency Tuning
Reference Year Node (nm) fosc (GHz) (dBc/Hz) FTR (%) (dBc/Hz) Technique
[4] 2017 40 59.5 −91.8 25 182.28 Continuous
[35] 2018 28 60 –87 16 176 Continuous
[36] 2018 45 SOI 60 –101.7 19 187 Continuous
[37] 2019 45 SOI 63.1 –94.4 16 180 Continuous
[38] 2017 45 SOI 66.4 –87.1 36 186 Continuous
[51] 2013 90 55.6 −91.6 12.5 188 Split in switched modes
[52] 2016 130 57.7 −100.6* 16.8 190.85 Continuous
[14] 2016 40 58 −100 25.4 187.9 Switched capacitors
[53] 2014 65 66.1 −88.4 27.9 177.2 Split in two switched modes
[54] 2016 65 54 −95.5 9.1 179 Split in 16 switched modes
[55] 2013 65 73.8 −86* 41.1 192.2 Split in six switched modes
[56] 2013 65 67.9 −88.9* 22.3 187.4 Split in two switched modes
[57] 2015 65 59.3 −90.3* 39 190.6 Split in two switched modes
[58] 2015 40 58.1 −99.5 14.8 188.9 Split with switched modes
*These values are estimated from figures or extrapolated from data.

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