IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 24, NO.

4, AUGUST 1989 951

A 50-dB Variable Gain Amplifier Using

Parasitic Bipolar Transistors in CMOS
TZU-WANG PAN AND ASAD A. ABIDI, MEMBER, IEEE

Abstract -A variable gain amplifier (VGA) with a gain range of 50 dB conform very accurately to the exponential characteristic
has been implemented in a standard 3-pm CMOS process using parasitic over many decades of bias currents, so the core of a
lateral and vertical bipolar transistors to form the core of the circuit. The
translinear circuit will normally provide its designed func-
bipolars had been characterized extensively. The VGA has a bandwidth
larger than 7 MHz over the whole gain range and operates on a single 5-V tion over a very wide dynamic range. As the circuit func-
power supply. Active area is about 0.8 X 0.9 mm? tion is determined by the interplay of transistors in a loop,
no overall feedback and no compensation are required;
translinear circuits are thus wide band. Subnanosecond
I. INTRODUCTION
multiplication using such a circuit was reported in the late
VARIABLE gain amplifier (VGA) is an essential 1960’s [4].
A part of automatic gain control loops at the front end
of communication receivers. In telecommunication VLSI’s,
MOS equivalents of the four-quadrant multiplier have
been reported [5]-[7], which use the square law ID-V,,
a VGA is typically implemented using binary weighted property of long-channel MOSFET’s. The dynamic range
arrays of capacitors or resistors that are digitally selected of these circuits is, however, normally limited to about two
as feedback elements around an operational amplifier [l], decades of gain, which is the range of current in any one
[2]. T h s is a conceptually straightforward and attractive MOSFET over whch it obeys the square law; at very low
scheme for CMOS implementation because of the ready currents, the device enters subthreshold, whereas at very
availability of analog switches and accurately ratioed ca- high currents, mobility degradation due to high electric
pacitors. However, it has some limitations. When a large fields and extrinsic resistances make the FET deviate from
decibel range of controllable gain is sought, the ratio of the square law.
maximum to minimum, or spread, of feedback element
values grows exponentially and may consume a substantial
chip area. Further, the frequency of operation is usually 11. USINGBIPOLARSIN CMOS
limited because the operational amplifier must be compen-
Analog CMOS circuits are popular because of the low
sated for stable operation in feedback. These limitations
cost and ready integration with digital circuits they afford.
may be partly overcome by making a VGA from the
However, some circuit designers have come to realize that
cascade of several VGA‘s, each one spanning a fraction of
bipolar transistors coexisting on the same substrate as
the desired gain range.
CMOS could enhance circuit speed because their h g h
A classic technique suited to wide dynamic range and
transconductance translates into an ability to drive capaci-
wide-band VGA’s has evolved in bipolar IC‘s. It is based
tive loads at high speeds. As the discussion in the previous
on the Gilbert gain cell, whose gain is accurately con-
section suggests, they may also allow compact realizations
trolled by the ratio of bias currents. The Gilbert gain cell is of certain analog functions, such as VGA’s with a wide
a two-quadrant analog multiplier, which is a simpler ver- dynamic range. Considerations such as these have led to
sion of the highly evolved four-quadrant analog multiplier the development of BiCMOS technologes [8], although it
topology [3]. These circuits take advantage of the exponen- has not been fully decided to date whether the increased
tial I - V characteristic, or the linear dependence of cost of such a technology justifies the results.
transconductance on bias current, of the bipolar transistor
If only a limited use of bipolar transistors is sought in
and are thus referred to as translinear circuits. Bipolars
an otherwise conventional CMOS circuit, the parasitic
bipolar that is inherent in the CMOS well may be consid-
Manuscript received December 12, 1988; revised April 28, 1989. This ered (Fig. 1) without any need for modification of the IC
work was supported by Rockwell International, Western Digital Corpora-
tion, and the State of California MICRO program. process. Two collectors are available on such a bipolar: the
A. A. Abidi is with the Electrical Engineering Department, University vertical to the substrate, which always exists in the well,
of California, Los Angeles, CA 90024.
T.-W. Pan was with the Electrical Engineering Department, University and the lateral, whch may optionally be added by a
of California, Los Angeles, CA 90024. He is now with Silicon Systems, diffusion surrounding the emitter. The well acts as the
Inc., Tustin, CA.
IEEE Log Number 8929066. base. The vertical bipolar transistor has been suggested for

0018-9200/89/0800-0951$01.00 01989 IEEE

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 CI E B

li' I
J YCL b
P-Well

N-SUB E

P
1016
n-sub
N-SUB 10 I S

Fig 1. (a) Structure of the lateral and vertical bipolars in a CMOS well ( b ) Circuit synibol. ( c ) Design rules in a 3-pm
CMOS process. ( d ) Doping profiles. (e) Geometry of niiniInum-size lateral bipolar.

circuit use before [9], and has been used to build bandgap To assess the feasibility of using the parasitic lateral and
voltage references [lo] and emitter followers to drive ca- vertical bipolars (intermingled with CMOS) in high-
pacitive lines on SRAM chips 1111. The use of this transis- frequency circuits, we report here the results of extensive
tor is severely limited by the fact that its collector is always measurements on bipolar test structures fabricated in a
tied to the substrate of the chip as well as to one of the production 3-pm p-well CMOS process provided by
power supplies. The lateral transistor offers a free collector MOSIS. We then describe the design and performance
but at the expense of an unavoidable vertical collector that of a VGA implemented with these devices. using the
is inherited from the bottom area of the well. A standard Gilbert gain cell as the core circuit. The VGA IC had a
CMOS technology does not offer the buried layer that is gain that could be varied continuously from 0 dB to
the standard way of suppressing vertical collection in greater than 50 dB with a -3-dB bandwidth greater than
bipolar IC technologies. Recently, the lateral transistor has 5 MHz over this range. Requiring only a single 5-V power
been put to circuit use in CMOS operational amplifier supply, the circuit took up an active area of 0.7 mm2. It
input stages with a low offset voltage [12] and in improved thus met our goal of a compact amplifier with a video
bandgap voltage references [ 131. bandwidth and a wide dynamic range: as an added bonus.

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 PAN AND ABIDI: 5 0 - d a VARIABLE GAIN AMPLIFIER 953

a very low distortion was observed in its large signal BETAL

0
characteristics. This macrocell may be readily used in the
front end of a highly integrated telecommunications LSI,
where it would suffer little interaction with digital circuits
due to its large common-mode and power-supply rejection.
We note that although it is implemented in conventional
CMOS, the amplifier effectively demonstrated some of the
advantages offered by BiCMOS technologies to circuit
design.

OF PARASITIC
111. CHARACTERISTICS BIPOLARS
Vittoz, who has extensively used lateral bipolars in
CMOS, reported the dc characteristics of bipolar transis-
tors in a 6-pm p-well CMOS technology [14] and discussed
the possibility of applying these devices to dc circuits like
voltage references and to operational amplifiers. We
wanted to investigate how the characteristics he had re-
ported would be different in a production 3-pm technol-
ogy because the characteristics of the parasitic bipolars, BETAL
BETAV
C
C
>> -- AICLIAIB
AICVIAIB
VC

determined by dimensions and doping levels in the well

.‘CL
and substrate, might not scale in the same way as MOS-
FET’s in a short-channel CMOS process. We also wanted
to measure the fT and extrinsic resistances of these bipo-
IB VE 1 v
lars to allow accurate modeling and circuit simulation of
wide-band circuits. To this end, experimental structures
were fabricated, and the results of measurements on these
are now summarized [15].

A . Experimental Structures

The test chip included several structures of different

geometries. Minimum-size lateral bipolars consisted of an
emitter with a single contact surrounded by a square
“ring” collector at the minimum allowable separation of
3 pm. In modern CMOS processes, recessed local oxida-
tion isolates neighboring diffusions that do not have a
polysilicon gate between them [16]; to prevent this field
oxide from recessing into the base region and increasing
the base width of our lateral bipolar, all but one of the
transistors were laid out with a polysilicon gate between
the emitter and collector. The one without the gate was
used to verify that lateral bipolar transistor action was
indeed suppressed by the recessed oxide. Large interdigi-
tated transistors, capable of sustaining emitter currents
between 1 and 10 mA before the onset of hgh level
injection, were also fabricated to enable operation in a
50-!J environment for fr measurement. Arrays of devices
with identical geometries were included to determine the BETAL
BETAV
C
C
>
> -
-’AICL/IIB
AICV/AIB
5v
4v
quality of matching in their bipolar characteristics. 9

B. Current Gain and Log Conformity

The current gain of lateral structures fir. was about 100
over five decades of current (Fig. 2), and the current gain
of the vertical f i v was up to a factor of 2 greater than the
lateral. This was a respectable value, comparable to fi
‘B

(b)
d VE

Fig. 2. (a) /3 versus I, for lateral. (b) /3 versus I, for vertical.

1v

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 Er
-v
1E-03 IV

decode
/div

1E-12
1. no3 2. non -14.70 0 4 . 2 ~ ~
L'B . 10C3/div ( V) vc 2 . 100/div ( V)

"c Fig. 4. Earl? effect in lateral.

14-20 V for structures of different geometries (Fig. 4)).

This was a consequence of the light base doping (p-well)
relative to the collector (n+ ) that made the depletion
region at the collector-base (C-B) junction fall almost
4 I L1" entirely within the base, which enhanced base-width modu-
lation. In circuit applications, the low VA of the laterals
Fig. 3 Log conforrnit! of lateral bipolar: log ( I,, ) versus ,;L could cause substantial error currents to flow in the output
resistance of the transistor; this makes it almost essential
values in a typical bipolar IC process. Although the base to use MOSFET cascode devices connected to the lateral
widths of both our lateral and vertical bipolars were about collectors [12] to reduce the signal voltage swing at these
3 pm, bulk recombination was negligible; surface recombi- nodes.
nation was suppressed in the lateral bipolar by biasing the In the I - V characteristics of the lateral, I,. became 0
gate electrode (fabricated between the emitter and lateral for V,, = 0.2 V and reversed polarity for lower V , (not
collector) slightly negative relative to the emitter, thereby shown in Fig. 4). This was due to the presence of the
creating a depletion region under the Si-Si02 interface, vertical collector. which was always biased in the forward
and shielding the electrons diffusing in the p-well from active region by the substrate voltage. Lowering V(.,- < V,,
recombination sites at the interface. The ,B was thus deter- (ON) of the lateral made its collector appear as an addi-
mined by enutter injection efficiency. tional emitter for the vertical device, so current now flowed
To perform multiplication with low distortion when into the lateral collector terminal rather than out of it.
connected as an analog multiplier, it is important that the
bipolars conform to the ideal exponential I - V characteris- D. Luterul Collector Efficiency
tics (log conformity) over several decades of current. Mea-
surements indicated that the laterals did obey this charac- Although the lateral bipolar offers a free collector. mak-
teristic over at least four decades of current. limited at the ing it desirable for use in a circuit, it collects only a
upper end hy high-level injection (Fig. 3). The forward fraction a , of the emitter current; the remaining fraction
I - V characteristics of our devices could be f i t to the 1 - aL. is collected by the vertical bipolar that is always
equation biased in the forward active region. u L is determined by
the sidewall-to-area ratio of the emitter diffusion. We
measured c y I - on minimum-sized 9-pm-square emitter, ring
collector structures, and on transistors with large rectangu-
with 7 = 1.0'7, which corresponds t o a near ideal bipolar lar emitters with a smaller side of 9 pm and found a [ , to be
behavior. 1/3 and 1/5, respectively: these values are roughly in the
2 : 1 perimeter-to-area ratio of a square relative to a long
C. Eurly Voltage und Offset in I V Charwteristics
-
rectangle. For higher collection efficiency. the minimum-
size transistor is thus preferable when a floating collector
The Early voltage ()
'V of a bipolar transistor determines is desired.
the maximum voltage gain available from a single device. The dependence of a I on operating current density.
realized when the transistor is biased by an ideal current lateral collector voltage I+,:,,. and gate voltage V& was
source and drives its own output resistance. V4L.for the also determined for the minimum-size structures. At a
vertical transistors was measured to be about 100 V. .
given V,,, a,. did not change with current (Fig. 5(a)) as
The value of V,, of the laterals was low (in the range of expected because i t was determined by geometry. How-

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 PAN AND ABIDI: 5 0 - d ~VARIABLE GAIN AMPLIFIER 955

RAT IO ever, the strong Early effect in the lateral did cause the
< )
effective a , to increase with V,, (Fig. 5(b)). For
ano. o
E-03

50.00
/div

(1)
where the terms with subscript 0 refer to their values at
low V,,.

E. Effect of Gate Voltage

300. 0
1E-11 1E 4 2 An inversion layer would be induced in the base of the
IEE decodddiv C )
lateral bipolar if the voltage at the gate electrode exceeded
the threshold V, of the MOSFET that coexists with the
bipolar. This would short circuit the emitter to collector of
the bipolar. Measurement of V, versus the substrate bias
IEE
RATID C
C >
>
-- -1E
ICL/IN 5 v P
vc 4v
Vs,( = - V B E )showed that at a typical junction forward
bias (when V,, = - 0.7 V), V, = 0 in our devices. This
means that to prevent the MOSFET inversion layer from
Ratio
a=- shorting out the bipolar action, the gate potential must be
1 + Ratio
below the emitter to bias the MOSFET in subthreshold.
When used as a common emitter stage connected to the
negative rail, this would necessitate creating a bias voltage
below rail to connect to the gate, which is undesirable [14];
in many current-driven circuits such as a differential pair,
however, MOSFET only could be connected to the nega-
tive rail, and the emitters of lateral bipolars may be biased
RATIO above the rail by MOSFET current sources, in which case
0
the gate of the lateral bipolar may be connected to the rail
[121.
It is desirable to bias the MOSFET into deep subthresh-
old in order to create a depletion region under the gate and
shield base minority carriers from surface recombination.
We found that parameters like a and j3 attained the
maximum value and became independent of the gate volt-
age for V,, < -0.5 V .

F. Gain-Bandwidth Product
The fT was measured [17] on the bipolars with interdigi-
tated emitters with a total dimension of 1000x9 pm.2 An
extrapolated unity current gain frequency f T of 100 MHz
was obtained for both lateral and vertical bipolars (Fig.
6(a)), wluch compared well with 116 MHz predicted from
a first-order estimate of the electron transit time through a
3-pm long base, assuming a uniform base doping of
10'6/cm3. Strictly, the ratio of the f T s of the lateral and
vertical collectors should be as (1 - a L ) / a L but
, this could
a= Ratio = l a / IE not be resolved in our experiments. The f r showed a broad
VCE = V C - VE peak as a function of I , (Fig 6(b)), with the maximum
value available over more than a decade of current.

G. Extrinsic Resistances
(b)
Fig. 5. (a) Current splitting (expressed as I c L / I c y ) versus I,. The collector (r:), emitter (r:), and base ( r l ) resistances
(b) Current splitting ( I c L / K c v ) versus VCE. were measured [18] for the minimum sized transistors. r:

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 +--
7. 100pA
40-
IOpA

. . . . . . . .h l h . IPA

. . . . . . . t X I X . 100nA

O L L
0.0 I
~ L

0. I
1

I
- ~

10 IO0
.- . ...“A. .)I. IOnA

f, MHz
(a) I
. ... . ,- , . I , i . p;,
1 ,
,
In A
- ,

7- - -- ~ ~~ -40% -20% 1.0 20% 40%

I * /11
Sialisilcs 01 matching in current mirrors vs curreni level MOS and bipolar

1 0 0 A~
!
- I
~ . !.~
~ ~
gj
-
IOpA

IO-- . ~~ , ~~

0. I I IO IO0
ICLm A. lOOn A

(b)
Fig. 6 . (a) Extrapolated unit); current gain frequent! f7 of lateral
( b ) fr of lateral verbus I,,
~ - ~~1

-10% 1.0 10%

was in the range of 500-600 D for the lateral device, I,/ 11
whereas for the vertical device on the same structure. r,’ Fig. 7. Histogranis of matching of current mirrors \ersus current l e v e l .
was 150 12. The latter corresponded to a parallel combina-
tion of the spreading resistance to the back-side substrate
contact as U ell as to substrate contacts surrounding the
CMOS well on the surface of the chip. When the transistor pA, the ratio of collector currents of several identical pairs
was biased at I,. = 50 p A to obtain optimum 0,the dc of lateral transistors with the same terminal voltages was
voltage drop across r(‘ of the lateral would only be 25 mV. measured and plotted as a histogram (Fig. 7). A standard
rc,’ was measured to be about 25 D for the vertical and deviation of better than 1 percent resulted. With the same
lateral devices. r; was determined using a noise measure- structures operated as MOSFET’s, the standard deviation
ment-based instrument [19] to be 990 D at V,,y= -1 V. was much worse at the low range of operating currents.
This instrument also showed that there was negligible MOSFET’s, being surface conduction devices. are subject
flicker noise in the device for frequencies above 5 kHz. to a strong influence by inhomogeneities in the surface
The current lost to the substrate in the lateral bipolar potential produced by random fixed charge in the gate
worsened the equivalent input noise because only a frac- oxide [20]. and these effects are pronounced at low cur-
tion of the emitter signal current was collected by the rents when the MOSFET operates in subthreshold [21].
lateral, although noise due- to the full emitter current was The gate area of the MOSFET’s in the array was 144 pm’,
perceived at the base. If i,, is the spectral density of the whereas the emitter area of the bipolars was 81 pm’.
equivalent input shot noise current contribution, then

( 2 ) 1. Junction Cupucitunces
The lateral bipolar introduces a sizable parasitic capaci-
Compared to a conventional bipolar, the power spectral tance when its geometry conforms to usual CMOS design
density u a s increased by a factor l / a l ~ .The equivalent rules. For example, in a minimum-size lateral transistor in
input noise voltage of the lateral was unaffected by the typical 3-pm design rules (Fig. l), the junction capacitance
presence of the vertical collector. from the base to the lateral collector was 0.3 pF, whereas
the capacitance from the base to the substrate (vertical
H . Transistor Matching collector) was 1.7 pF. The latter was the largest extrinsic
capacitance in the structure; as the substrate is held at a
To obtain low offset voltages in differential pairs, as constant potential, however, it is not subject to Miller multi-
well as to effect current cancellation in multiplier circuits. plication. Even at large operating currents, minimum-size
it is desirable for transistors of identical geometry on the laterals connected in parallel are preferred because of their
same chip to match well. Over the range of 1 nA to 100 higher a!. over a transistor with a single large emitter.

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 PAN AND ABIDI: SO-dB VARIABLE GAIN AMPLIFIER

IV. A VARIABLEGAINAMPLIFIER 4101

C l IO2

We designed a VGA cell using parasitic bipolars that

could be freely mixed with other analog and digital circuits
on the same chip. Clocks and logic-level transitions gener-
ated elsewhere on such a chip would act as sources of
a3 Q4
interference for the cell, which it was designed to reject. A
fully differential configuration was chosen for t h s purpose
so that undesirable coupling onto the power supplies or
the input terminals appeared as a common-mode signal.
The core of the VGA was a Gilbert gain cell. A differential
voltage was accepted at the input and provided at the
1,-ix
0
--
L

Fig. 8. Gilbert gain cell

output terminals. The gain was varied by a single control
voltage, which determined the bias currents in the gain
cell. obtained when the emitter currents of Q1 and Q2 became
very small, even though linearity in the transconductance
could only be retained with the collector current in Q5 and
A . Core Circuit
Q6 sufficiently large to maintain g,R, >> 1. Introducing
The Gilbert gain cell [22] (Fig. 8) consists of four I , resolved this conflict. Q5 and Q6 could be biased by I,,
transistors making up a cascade of differential pairs with whereas Ql and Q2 were driven by ( I ,- 13).
their collectors cross connected. The bases of Ql and Q 2 CMOS common source stages Ml1-Ml4 with shunt-
are tied to a fixed-bias voltage. With the differential input feedback resistors R , were used to construct the output
signals i , entering the emitters of Q1 and Q2, the ampli- transresistance stage. This offered a low resistance at the
fied output current, appearing as the difference of collector collectors of the lateral bipolars in the gain cell, keeping
currents, is given by the voltage swing there small. The low Early voltage of the
lateral bipolars no longer limited the attainable voltage

IO2- Io, = 2ix( $+ 1). (3)

gain because these transistors were only required to deliver
a current to the transresistance stage, while the MOSFET's
developed a large voltage swing without being limited by a
strong Early effect. The feedback also helped to increase
The current gain of the amplifier thus depends on the ratio
the bandwidth. The overall voltage gain of the VGA was
of the two bias currents I , and I,. The maximum attain-
given by
able current gain is limited by the /3 of Q3 and Q4 because
if I , were set to zero, the base currents of Q3 and Q4
would still flow through Ql and Q2. As long as the
(4)
transistors satisfy the exponential characteristic, the trans-
fer function remains linear for large signals.
In our implementation of the Gilbert gain cell in CMOS The gain of the VGA could be varied by the three bias
(Fig. 9), lateral bipolars Ql-Q4 constituted the core of the currents 11,12, and I,. It was undesirable to burden a
circuit. Buffers were inserted to screen Ql and Q2 from single transistor with a very wide range of bias currents
the base currents of Q3 and Q4 and thus increase the because at low currents this could introduce a dominant
maximum gain attainable in the cell. Buffers were also pole and reduce the circuit bandwidth. Further, current
inserted to drive the large parasitic and intrinsic capaci- sources implemented by MOSFET's could only sustain
tance of Q3 and Q4 and thus increase the bandwidth. The good matching over a current range of about one decade,
buffers consisted of vertical bipolars Q7-QlO in a Dar- and poor matching would worsen the circuit offset. To
lington configuration that provided a high-input resistance obtain the best combination of bandwidth, noise, power
without the large offset voltage of a buffer based on an dissipation, distortion, and offset, the current range for I ,
MOS voltage follower. was chosen from 20 to 200 pA, 140 p A to 1 mA for I,,
A transconductance stage (voltage-to-current converter) and 0 to 8 p A for 13. This corresponded to a sweep in
and a transresistance stage (current-to-voltage converter) current densities comparable in all three current sources.
were added to the input and output, respectively, of the At a gain setting of G , the intrinsic bandwidth of an
core circuit. The transconductance stage consisted of a ideal Gilbert gain cell is about f,/G because the domi-
degenerated differential pair with lateral bipolars Q5, Q6, nant poles of the circuit, at the emitters of Ql and Q2, are
MOSFET current sources M,, M 2 , and p-well resistor R E . determined by g,,/C,,, and gm2/Cn4if junction capaci-
The bipolar-based transconductance afforded several ad- tances are neglected. By including buffers between Ql, Q2
vantages: a high linearity, a low-input offset voltage, and and Q3, Q4, the bandwidth could be extended to almost
low flicker noise. This transconductance stage could not be fT. The effect of junction capacitances of parasitic bipolar
mated directly to the gain cell because high gain would be structures in CMOS depends on the range of the current

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 ~

958 i L L r JOI K ~ A or
L W L I D - S T A T ~C I K C UITS. \ O L 24.1'0 4. A I GIJSI 1989

+5V

VOUt+ - VOUt

L
M

' *
<
'I3 'I3

Vin+ Q5
1 OK

(b)
Fig, 9. ( a ) Simplified circuit of our gain cell implementation. ( b ) Complete circuit diagram of glun cell in CMOS process.

that key transistors are designed to carry because the these resistors compactly. The measured resistance of this
emitter area must be sufficiently large to prevent the onset diffusion has a linear dependence on voltage, that is, the
of high-level injection at the upper end of this range; at I - V characteristic is parabolic. Distortion components
low currents, the diffusion capacitance will scale propor- generated by this even nonlinearity would appear as a
tionally with I,, and the junction capacitance will remain common-mode signal in the fully differential amplifier and
constant. Therefore, due to junction capacitances alone, would be effectively suppressed. Although the sheet resis-
the bandwidth of the gain cell degrades roughly by a factor tance of this diffusion would vary widely in value across
of the ratio of the bias current change. In our VGA at high processing, the amplifier gain depended only on the ratio
gains, the dominant poles were at the emitters of Ql and of the resistor geometries.
Q2 determined by the well (collector) capacitance of fol-
lowers Q7 and QS: at low gains, the pole frequencies at
almost all the nodes lay at about 10 MHz. B. Common-Mode Feedback and Bius Circuits
Active devices with small area lead to a compact ampli-
fier; however, to maintain reasonable current densities, A common-mode feedback circuit set the voltage at
they also must be operated at low current levels, which. in which the output nodes of the fully differential amplifier
turn, requires the resistors R , and R E to have large values biased themselves. The feedback signal was derived from
(40 and 10 kQ, respectively, in our case). P-well regions the sum of currents flowing in two source degenerated
that offer a high sheet resistance were chosen to implement MOSFET's connected to the differential transresistance

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 PAN AND ABIDI:5 0 - d ~VARIABLE GAIN AMPLIFIER 959

vB4 5- - currents were derived from (Fig. 1O(c)) a single voltage

increasing, which caused Z, and Z3 to increase
(VcVcontro,)
and Il to decrease so that the gain increased montonically.
vout+

40K $ -
$OK
p vout- The circuit also set upper and lower bounds on the values
of these currents to prevent the transistors in the amplifier
from being driven into either saturation or cutoff.

C. Sources of Distortion

Useful functions are implemented in translinear circuits

by the interplay of p-n junction voltages in a loop. Unde-
sirable voltage drops U, entering such a loop produce an
effect dependent on u c / ( k T / q ) that distorts the intended
function. The translinear loop in our circuit was composed
of the base-emitter (B-E) junctions of Ql-Q3-Q4-Q2.
Sources of distortion in our amplifier were the voltage
drops in the emitter and base resistances of Ql-Q4, the
emitter signal current in the buffers (because these transis-
tors did not constitute the core of the translinear loop),
and random mismatches between all the transistors. Simu-
lations indicated that the extrinsic resistances of the tran-
sistors were the dominant source of distortion, producing a
nonlinearity of about 1 percent.
Mismatch in the transistors constituting the gain cell or
the buffers would distort the transfer curve and produce
even-order products at the (differential) output, although
the extrinsic resistors would have an antisymmetrical effect
on the circuit, producing odd-order distortion at the out-
puts. Mismatch in other current sources would appear as a
dc offset and have no effect on distortion. High-level
VB4
injection would introduce distortion by causing the bipo-
lars to deviate from their ideal exponential I-V character-
istics; to avoid this in transistors carrying large currents,
the current density was maintained less than 10 pA per
minimum size emitter either by using single large emitters
or multiple small emitters in parallel.

RESULTS
V. CHIPDESIGNAND MEASURED
d V Control
A . Layout Considerations
(c)
Fig. 10. (a) Common-mode feedback circuit. (b) Fixed-bias generation To minimize systematic offsets in the translinear core, a
circuit. (c) Variable-bias generation circuit. common-centroid layout was employed that would cancel
a linear gradient of processing variation across the chip.
Large lateral bipolar transistors were laid out as several
minimum-sized devices in parallel to accommodate large
outputs. It then set the currents at the output collectors of currents with a high collection efficiency. Contacts on only
the gain cell (Fig. 10(a)). two sides of their bases and collectors were used so that
The VGA required some bias currents that are fixed interconnection of unit transistors was compact, although
(used for the emitter-follower buffers, transresistance am- rl and r,' would increase slightly. Large guard rings sur-
plifiers, and the common-mode feedback) and others that rounded all parasitic bipolar transistors where significant
are variable (used to change the gain). A fixed bias current substrate currents flowed to reduce the possibility of
that was relatively independent of the power supply was latch-up.
derived from the NMOS threshold voltage and a p-well Fabricated in a standard CMOS 3-pm, double-metal,
resistor ( R B ) that tracks the resistors in the common-mode single-poly process by MOSIS (Fig. l l ) , the circuit occu-
feedback circuit (Fig. 10(b)). T h s made the quiescent pied an active area of 0.8 X 0.9 mm2. This was anywhere
voltage at the amplifier output insensitive to variations in between 25 and 50 percent of the area of VGA's imple-
sheet resistance of the well diffusions. Three variable bias mented by arrays of switched capacitors [l]or resistors [2].

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 960

Fig 11 Microphotograph of active area of VGA IC

I rrqurncy.t I(

Fig. 13. Measured frequency response of VGA at different gains.

'I I

(1 I 4 i
c~~llllslll\ ( l l l : l y . \

Fig. 12. Measured variation of pain aith ,,,,(,,>, 0 I 3 4 >

O~~I~~~I,\.OII\
r~ltit~~~l[l.li

Fig. 14. Measured THI> versus output signal at different gains

B. Gain Curcle

The gain could be increased monotonically by

from 0 dB to more than 50 dB (Fig. 12): the function sponse of the VGA, they were made using discrete high-
describing this relationship was determined jointly by the frequency bipolars and characterized independently.
Gilbert gain cell and the variable bias circuit. A greater At a gain of 50 dB, the -3-dB bandwidth was about
insensitivity of this transfer function to process variations 5 MHz and increased to 10 MHz at gains lower than
could have been obtained if a parasitic bipolar and a 40 dB (Fig. 13). This bandwidth was considerably higher
p-well resistor were included in the latter circuit to model than that attained by VGA's implemented in a similar
the bias conditions of the gain cell. technology but based on other architectures. A peaking
As the gain of the VGA depended on current and near 5 MHz was observed and was caused by the capaci-
resistor ratios only, an alternative means of programming tance from the base to the lateral collector C,,.,,, which
the gain digitally would be to use three D/A converters to created a feedforward zero in the bipolars of the input
supply I , to I,. The DAC inputs words could be provided transconductance stage. This peaking could be reduced
by an encoder that contains the gain relation (4).Such a either by using transistors of smaller geometry in the
system may be attractive when an analog front end is transconductance stage (noting that deleterious effects of
followed by H digital signal processor, as is often the case the consequent high-level injection would be suppressed by
in telecommunications LSI. the degeneration) or by using MOSFET followers between
base and collector that would bootstrap Cicr,.
The bandwidth could be increased by cascading two or
C. Frequenq Respotise more gain cells in the core circuit so that each stage
experiences a smaller range of current change: this implies
Measurements were made on a network analyzer with a a smaller parasitic capacitance (see above). However, each
single-ended-to-differential converter preceding the VGA stage would suffer from current splitting in the lateral
IC and a differential-to-single-ended converter following bipolars, and the gain of a cascade of N stages would be
it. To prevent the frequency response and nonlinearity of lowered by a:. For a cascade of two stages implementing
these peripheral circuits from obscuring the sought re- the same gain range. the simulated bandwidth was 15 MHz

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 PAN AND ABIDI: 5 0 - d ~VARIABLE GAIN AMPLIFIER 961

(although the active area would be 50 percent larger be- B. Gilbert, “A precise four-quadrant multiplier with subnanosec-
ond response,” IEEE J . Solid-State Circuits, vol. SC-3, pp. 365-373,
cause many subcircuits would not be duplicated). 1968.
D. C. So0 and R. G. Meyer, “A four quadrant NMOS analog
multiplier,” IEEE J . Solid-state Circuits, vol. SC-17, pp. 1174-1178,
D. Distortion Dec. 1982.
J. N. Babanezhad and G. C. Temes, “A 20-V four-quadrand CMOS
analog multiplier,” IEEE J . Solid-state Circuits, vol. SC-21, pp.
The total harmonic distortion (THD) was measured at 430-435, Dec. 1985.
different gain settings as a function of the output voltage J. S. Peiia-Fino1 and J. A. Connelly, “A MOS four quadrant
multiplier using the quarter-square technique,” IEEE J . Solid-state
swing (Fig. 14). For a 1.5-V differential output at a gain Circuits, vol. SC-22, pp. 1064-1073, Dec. 1987.
setting of 30 dB, the THD was less than -70 dB and was M. Kubo, I. Masuda, K. Miyata, and K. Ogiue, “Perspective on
BiCMOS VLSI’s,” IEEE J . Solid-State Circuits, vol. 23, pp. 5-11,
dominated by the thrd harmonic. This indicates that the Feb. 1988.
matchng of the bipolars, which would contribute second- H. C. Lin, J. C. Ho, R. R. Iyer, and K. Kwong, “Complementary
MOS-bipolar transistor structure,” IEEE Trans. Electron Devices,
order components, is very good; it also shows that the vol. ED-16, pp. 945-951, NOV.1969.
differential scheme effectively cancels out the voltage de- Y. P. Tsividis and R. W. Ulmer, “A CMOS voltage reference,”
IEEE J . Solid-state Circuits, vol. SC-13, pp. 774-778, Dec. 1978.
pendence of the p-well resistors. 0. Minato et al., “A high speed low power Hi-CMOS 4K static
RAM,” IEEE Trans. Electron Devices, vol. ED-26, pp. 882-885,
June 1979.
E, Noise C. Laber et al., ‘‘Design considerations for a high performance
3 p m CMOS analog standard cell library,” IEEE J . Solid-State
Circuits, vol. SC-22, pp. 181-189, Apr. 1987.
Measured equivalent input density of white noise was 29 M. G. R. DeGrauwe, 0. N. Leuthold, E. A. Vittoz, H. J. Oguey,
nV/& at 50-dB gain, 36 nV/& at 30 dB, and 290 and A. Descombes, “CMOS voltage references using lateral bipolar
nV/& at 0 dB. In application, the gain of the VGA is transistors,” IEEE J. Solid-state Circuits, vol. SC-20, pp.
1151-1157, Dec. 1985.
normally adjusted to keep the output signal at a desired E. A. Vittoz, “MOS transistors operated in the lateral bipolar mode
and their application in CMOS technology,”’ IEEE J . Solid-State
level; therefore, even though the input noise voltage in- Circuits, vol. SC-18, pp. 273-219, 1983.
creases with decreasing gain, the signal-to-noise ratio actu- A. A. Abidi, V. Comino, and T.-W. Pan, “The potential of using
parasitic bipolars in CMOS for analog circuits,” in Proc. Bipolar
ally improves at lower gains. Circuits Tech. *ring (Minneapolis, MN), Sept. 1987, pp. 90-93.
At a high gain setting, the shot noise in the input L. C. Parrillo, VLSI process integration,” in VLSI Technology,
S. M. Sze, Ed. New York: McGraw-f;Iill, 1983.
transconductance stage was the largest component of the K. W. Kwan and A. Brunnschweiler, Measurement and interpre-
equivalent input noise. The presence of negative feedback tation of the j r of planar transistors operating in the inverse
mode,” Proc. Inst. Elec. Eng., vol. 128, pp. 33-36, Feb. 1981.
in the form of emitter degeneration does not normally B. Kulke and S. Miller, “Accurate measurement of emitter and
modify the equivalent input noise of a bipolar [23]. How- collector series resistances in transistors,” Proc. IRE, vol. 45, p. 90,
Jan. 1957.
ever, because of the current splitting in the lateral bipolars, Model BRlA Base Resistance Test Set, Colby Instruments, Santa
noise due to the full emitter current appeared across R E , Monica, CA.
E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Serniconduc-
whereas only a fraction aL of the desired signal in the tor) Physics and Technology. New York: Wiley, 1982.
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and the MOSFET mobility step near threshold,” IEEE Trans.
the referred input noise by a factor of (ai’- l ) g m L R E . At Electron Devices, vol. 35, pp. 2378-2383, Dec. 1988.
a lower gain setting, shot noise in Q1 and Q2 dominated B. Gilbert, “A new wide-band amplifier technique,” IEEE J .
Solid-State Circuits, vol. SC-3, pp. 353-365, Dec. 1968.
the equivalent input noise. P. R. Gray and R. G. Meyer, Analysis and Design of Analog
Integrated Circuits. New York: Wiley, 1984.

VI. CONCLUSION Tzu-Wang Pan was born in Taipei, Taiwan, 1962.

He received the B.S. degree from National Tai-
wan University in 1984, and the M.S. degree
A 50-dB variable gain amplifier fabricated in standard from the University of California, Los Angeles,
CMOS technology has been described. The circuit uses the in 1988, both in electrical engineering.
lateral and vertical parasitic bipolars to implement a In 1988 he joined Silicon Systems Incorpo-
rated, Tustin, CA, where he is now a Design
Gilbert gain cell as the core circuit. Measured results of the Engineer involved in analog hard-disk interface
VGA are summarized in Table I. Notable features are a circuit design.
bandwidth of almost 10 MHz, high linearity, and compact
size. Although parasitic bipolars may suffer from large Asad A. Abidi (S’80-M81) was born in 1956 He
junction capacitances and the current splitting effect in received the B.Sc.(Hon.) degree from Impenal
College, London, England, in 1976 and the M.S.
laterals, this amplifier demonstrates that by judiciously and Ph.D. degrees in electrical engineenng from
mixing them with CMOS, it is possible to design accurate the University of California, Berkeley, in 1978
and high-speed circuits. and 1981, respectively.
He was at Bell Laboratories, Murray Hd1, NJ,
from 1981 to 1984 as a Member of Technical
Staff in the Advanced LSI Development Labora-
REFERENCES tory. Since 1985 he has been at the Electrical
Engineering Department of the University of
C.-C. Shih, K.-K. Lam, K.-L. Lee, and R. W. Schalk, “A CMOS California, Los Angeles, where he is an Associate Professor. His research
analog front end for 9600BPS facsimile modem,” in ISSCC Dig. interests are in high-speed analog integrated circmt design, parallel ana-
Tech. Papers, 1987, vol. 30, pp. 300-301. log signal processing techmques, device modeling, and nonlinear circuit
J. N. Babanezhad and R. Gregorian, “A programmable gain loss
circuit,” IEEE J . Solid-State Circuits, vol. SC-22, pp. 1082-1090, phenomena
Dec. 1987. Dr Abidi has served as the Program Secretary for the International
B. Gilbert, “A four quadrant analog divider/multiplier with 0.01% Solid State Circuits Conference since 1984. He received the 1988 TRW
distortion,” in ISSCC Dig. Tech. Papers, 1983, pp. 248-249. Award for Innovative Teaching

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