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12 - Advanced Electronics - EC - Postal Theory-2025

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0% found this document useful (0 votes)
14 views

12 - Advanced Electronics - EC - Postal Theory-2025

Uploaded by

prawalgoyal005
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ELECTRONICS

ENGINEERING

Advanced
Electronics

Comprehensive Theory
with Solved Examples and Practice Questions

www.madeeasypublications.org
MADE EASY Publications Pvt. Ltd.
Corporate Office: 44-A/4, Kalu Sarai (Near Hauz Khas Metro
Station), New Delhi-110016 | Ph. : 9021300500
Email : infomep@madeeasy.in | Web : www.madeeasypublications.org

First Edition : 2017


Advanced Electronics Second Edition : 2018

EDITIONS
Copyright © by MADE EASY Publications Pvt. Ltd. Third Edition : 2019
All rights are reserved. No part of this publication may be Fourth Edition : 2020
reproduced, stored in or introduced into a retrieval system,
Fifth Edition : 2021
or transmitted in any form or by any means (electronic,
Sixth Edition : 2022
mechanical, photo-copying, recording or otherwise),
Seventh Edition : 2023
without the prior written permission of the above mentioned
publisher of this book. Eighth Edition : 2024

MADE EASY Publications Pvt. Ltd. has taken due care


in collecting the data and providing the solutions, before
publishing this book. Inspite of this, if any inaccuracy or
printing error occurs then MADE EASY Publications Pvt.
Ltd. owes no responsibility. We will be grateful if you could
point out any such error. Your suggestions will be appreciated.
Advanced Electronics
CHAPTER 1
CHAPTER 4
Integrated Circuits Fabrication Technology....1-16
1.1 Crystal Growth............................................................................. 1 VLSI Testing....................................................57-71
1.2 Doping and Impurities............................................................. 2 4.1 Stages of Testing.......................................................................57

1.3 Growth and Deposition of Dielectric Films....................... 8 4.2 Importance of Testing.............................................................57

1.4 Masking and Photolithography..........................................10 4.3 Testing During the VLSI Life Cycle......................................58

1.5 Metallization...............................................................................11 4.4 Challenges in VLSI Testing.....................................................59

1.6 Technological Advantages of Silicon.................................12 4.5 Test Principles............................................................................60

Objective Brain Teasers............................................................12 4.6 Design for Testability (DFT)...................................................62

Conventional Brain Teasers.....................................................13 4.7 Design Economics....................................................................67


4.8 Yield and Reject Rate..............................................................67
4.9 Types of Faults...........................................................................69
CHAPTER 2 Objective Brain Teasers............................................................70
Conventional Brain Teasers.....................................................71
VLSI Design.................................................... 17-32
2.1 Chip Developing Process.......................................................17
CHAPTER 5
2.2 VLSI Circuit Design Process...................................................18
2.3 Design Flow................................................................................20 Synthesis of Synchronous
2.4 Design Styles..............................................................................25 Sequential Circuits.....................................72-100
Objective Brain Teasers............................................................30 5.1 Finite State Machine (FSM)....................................................72
Conventional Brain Teasers.....................................................31 5.2 Design of a Sequential Circuit or
Finite State Machine................................................................81
Objective Brain Teasers............................................................97
CHAPTER 3
Conventional Brain Teasers.................................................. 100
Pipelining....................................................... 33-56
3.1 Pipelining....................................................................................33 CHAPTER 6
3.2 Types of Pipelines.....................................................................34
3.3 Instruction Pipeline..................................................................35 Programmable Logic Devices
3.4 Pipeline Hazards.......................................................................37 and Memories........................................... 101-120
3.5 Pipeline Performance Analysis............................................44 6.1 Programmable Logic Devices........................................... 102
3.6 Arithmetic Pipeline..................................................................46 6.2 Semiconductor Memories.................................................. 113
Objective Brain Teasers............................................................52 Objective Brain Teasers......................................................... 118
Conventional Brain Teasers.....................................................54 Conventional Brain Teasers.................................................. 119

iii

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