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EC : ELECTRONICS AND COMMUNICATIONS

Module 3 : Digital Circuits

INDEX

Sr. Pg.
Contents Topics
No. No.
1. Boolean Algebra
Introduction 1
Number System 2
Binary Number System 3
Binary Arithmetic 8
Octal Number System (BASE 8) 12
Hexadecimal Number System (BASE 16) 13
Codes 16
Notes
Logic Gates 21
Boolean Algebra 26
Standard Representation of Logic Functions 33
Circuit Minimization 35
Karnaugh Map (KMAP) 36
Don't-Care Input Combinations 46
LMR (Last Minute Revision) 47
Assignment1 Questions 50
Test Paper1 Questions 53
Sr. Pg.
Contents Topics
No. No.
2. Combinational Logic Circuits, MUX and Decoders
Introduction 56
Implementing Combinational Logic 56
Code Converters 58
Multiplexer 65
Demultiplexer/Decoders 70
Notes
Special Decoders 75
Encoders 76
Functions of Combinational Logic 79
Comparators 86
LMR (Last Minute Revision) 90

Assignment2 Questions 92
97
Test Paper2 Questions

3. Sequential Logic Circuits

Introduction 101
Classification of Sequential Circuits 102
Flip Flops 102
SR Flip-Flop 103
J–K Flip-Flop 105
Master  Slave JK Flip-Flop 107
DFlip-Flop 108
Notes TFlip-Flop 109
Excitation Table of Flip Flop 111
Conversion From One Type of Flip  Flop to
112
Another
I mportant Parameters of Flip Flop 113
Applications of FlipFlop 114
Clocked Sequential Circuit Analysis 125
LMR (Last Minute Revision) 128
Assignment3 Questions 129
Test Paper3 Questions 133
Sr. Pg.
Contents Topics
No. No.

4. A/D Converters, D/A Converters and Semiconductors Memories

Introduction 137
Digital to Analog Converters 137
Types of Commonly Used D/A Converters 137
Performance Characteristics for D/A Converter 141
AnalogtoDigital Converters (A/D) 143
Flash A/D Converter 145
Successive Approximation A/D Converter 146
Counter Type A/D Converter 148
DualSlope A/D Converter 149
A/D Converter Using Voltage-Frequency
151
Notes Conversion
Summary of A/D Converter Types 154
Semiconductor Memories 154
Memory Organization and Operation 155
Expanding Memory Size 158
Memory Classification 161
Random Access Memories (RAM) 162
Read Only Memories (ROM) 165
PAL  Programmable Array Logic 167
PLA  Programmable Logic Array 167
LMR (Last Minute Revision) 168
Assignment4 Questions 169
Test Paper4 Questions 172

5. Computer Organization
Introduction 175
Numbers and Arithmetic Operations 177
Basic ALU Organization 180
Notes
Instruction Cycle 190
Addressing Modes 192
Instruction Formats 195
Sr. Pg.
Contents Topics
No. No.
Instruction Interpretation 197
Implementation Methods 197
LMR (Last Minute Revision) 203
Assignment5 Questions 205
Test Paper5 Questions 209
Practice Problems Questions 212
ID Problems Questions 225
SOLUTIONS
Answer Key 231
Assignment
Model Solutions 233
Answer Key 249
Test Paper
Model Solutions 251
Answer Key 265
Practice Problems
Model Solutions 266
Answer Key 278
ID Problems
Model Solutions 279
 Topic 1 : Boolean Algebra

INTRODUCTION

Since the introduction of microprocessors, the digital systems have gained tremendous
power and importance. There is no field of knowledge which has affected our lives as
much as the digital theory and applications, in such a short span of time.

Some of the principal reasons for the widespread use of digital techniques and
systems are:
x The devices used in digital circuits generally operate in one of the two states, known
as ON and OFF resulting in a very simple operation.

x There are only a few basic operations in digital circuits which are very easy to
understand.

x Digital techniques require Boolean algebra which is very simple and can easily be
learnt even in schools.

x Digital circuits require basic concepts of electric network analysis which can easily be
learnt at the junior level in colleges. The principal electrical characteristics required
are switching speed and loading considerations. On the other hand, analog circuits
and systems involve frequency and time domain concepts, complicated circuit
analysis techniques, etc. which make the understanding of these circuits much more
difficult than the digital circuits.

x A large number of ICs are available for performing various operations. These are
highly reliable, accurate, small in size and the speed of operation is very high. A
number of programmable ICs are also available.

x Various ICs are available in a logic family with similar electrical characteristics which
make the design and development of digital systems very simple and also reduce
interfacing problems.

x The effect of fluctuations in the characteristics of the components, ageing of

components, temperature, and noise, etc. is very small in digital circuits.

x Digital circuits have capability of memory which makes these circuits highly suitable
for computers, calculators, watches, telephones, etc.

x The display of data and other information is very convenient, accurate and elegant
using digital techniques.

x Many students have an opportunity to learn programming of digital computers; hence

they have a strong motivation to study the way the digital hardware works.

x It is a very fascinating and challenging field of study because most of the latest
electronic systems are digital in nature.

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Vidyalankar : GATE – EC

NUMBER SYSTEM

Introduction
We all are familiar with the number system in which an ordered set of ten symbols
 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9, know as digits  are used to specify any number. This
number system is popularly known as the decimal number system. The radix or base of
this number system is 10 (number of distinct digits). Any number is a collection of these
digits.

For example, 1982.365 signifies a number with an integer part equal to 1982 and a
fractional part to 0.365, separated from the integer part with a radix point (˜) also known
as decimal point. There are some other systems also used to represent numbers. Some
of the other commonly used number systems are: binary, octal and hexadecimal number
systems.

There number systems are widely used in digital systems like microprocessors, logic
circuits, computers, etc. and therefore, the knowledge of these number systems is very
essential for understanding, analyzing and designing digital systems.

Number Systems
In general, in any number system there is an ordered set of symbols known as digits with
rules defined for performing arithmetic operations like addition, multiplication, etc. A
collection of these digits makes a number which in general has two parts  integer and
fractional, set apart by a radix point (.), that is

(N)b dn1dn2 di d1 d0 n d1d2 df dm

Integer portion Radix Integer portion
point

where N = a number
b = radix or base of the number system
n = number of digits in integer portion
m = number of digits in fractional portion
dn1 = most significant digit (MSB)
dm = least significant digit (LSB)

and 0 d (di or df) d b  1

Each position in the number is assigned a weight or index of importance by some

redesigned rule. Shown in the table below gives the details of commonly used number
systems.

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 Notes on Boolean Algebra

Characteristics of commonly used number systems

Weight assigned to
Base or Symbols used position
Number system Example
radix (b) (di or df) i f
Binary 2 0, 1 2i 2f 1011.11
Octal 8 0, 1, 2, 3, 4, 5, 6, 7 8
i
8f 3567.25
Decimal 0, 1, 2, 3, 4, 5, 6, 7,
10
8, 9
10i 10f 3974.57
Hexadecimal 16 0, 1, 2, 3, 4, 5, 6, 7,
16f
i
8, 9, 16 3FA9.56
A, B, C, D, E, F

BINARY NUMBER SYSTEM

x The number system with base (or radix) 2 is known as the binary number system.
x Only two symbols are used to represent numbers in this system and these are 0 and
1. These are known as bits.
x It is a positional system, which is every position is assigned a specific weight.
(i.e. power of two).
The left-most bit is known as the most significant bit (MSB) and the right-most bit is
known as the least significant bit (LSB).
Note: x In the binary number system, a group of four bits is known as a nibble, and a
group of eight bits is known as a byte.
n
x Using n bits we can count up to a decimal number (2  1).
x Binary to Decimal Conversion
Method 1 :
The value of a binary number in terms of its decimal equivalent can be determined by
adding the products of each bit and its weight. The right most bit is the Least
Significant Bit (LSB) in the binary number and has a weight of 20 = 1. The weight
increases by a power of 2 for each bit from right to left.
4 3 2 1 0
Binary weight 2 2 2 2 2
Weighted value 16 8 4 2 1
Binary No. (1 0 1 1 1)2
1 u 16 + 0 u 8 + 1 u 4 + 1 u 2 + 1 u 1 = (23)10
? (10111)2 = (23)10
Fractional number can also be represented in binary by placing bits to the right of the
binary point.
The column weights of a binary number are:
2 … 2 2 2 2 . 21 22 23 … 2n
n 3 2 1 0

p
binary point

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Vidyalankar : GATE – EC

Example: (a) (1011)2 = 1 u 23 + 0 u 22 + 1 u 21 + 1 u 20 = 8 + 0 + 2 + 1 = (11)10

1
(b) (11.01)2 = 1 u 2 + 1 u 2 + 0 u 21 + 1 u 22 = 2 + 1 +
1 0
= (3.25)10
4
Method 2 :
(Dibble Dabble Method)
(i) Start with the MSB and multiply by 2.
(ii) Add the next bit to the product.
(iii) Multiply the sum by 2.
(iv) Add the next bit to the sum.
(v) Multiply by 2 and repeat the steps until all the bits are exhausted.
Example :
(a) (1011)2
Answer: 1 u 2 = 2
2+0=2
2u2=4
4+1=5
5 u 2 = 10
10 + 1 = 11
Answer: (11)10
Or
(b) (1111)2
Answer: 1 u 2 = 2
2+1=3
3u2=6
6+1=7
7 u 2 = 14
14 + 1 = 15
Answer: (15)10
x Decimal to Binary Conversion:
(i) Sum of weight method  by placing 1 in the appropriate weight position and 0 in
other position.
5 4 3 2 1 0
Remember: … 2, 2, 2, 2, 2, 2
… 32 16 8 4 2 1 Binary weights.

(ii) (Double Dabble Method) (by repeated division method)

We begin by dividing the given decimal number by 2 and then dividing each resulting
quotient by 2 until there is 0 quotient. The remainder generated by each division forms
st
the binary number. The 1 remainder is the LSB of the binary number.
Example 1 : Convert (28)10 into it’s binary equivalent
remainder
2 28 0 LSB
2 14 0
2 7 1
2 3 1
2 1 1 MSB
0
? (28)10 = (11100)2

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 Notes on Boolean Algebra

To convert the decimal fractions to binary we use repeated multiplications by 2. We

begin multiplying the given fractional number by 2 and then multiplying each resulting
fractional part by 2 until the fractional part is zero. The integer part of each
multiplication forms the binary number. The 1st integer part produced is the MSB.

Example 2 : Convert (0.3125)10 into it’s binary equivalent

0.3125 u 2 = 0.6250
0 (MSB)
0.6250 u 2 = 1.2500
1
0.2500 u 2 = 0.5000
0
0.5000 u 2 = 1.0000
1 (LSB)
? (0.3125)10 = (0.0101)2

x Signed Binary Numbers

(a) Sign-Magnitude Representation
In the decimal number system a plus (+) sign is used to denote a positive number
and a minus () sign for denoting a negative number. This representation of
numbers is known as signed number. As is well known, digital circuits can
understand only two symbols, 0 and 1; therefore, we must use the same symbols
to indicate the sign of the number also. Normally, an additional bit is used as the
sign bit and it is placed as the most significant bit. A 0 is used to represent a
positive number and a 1 to represent a negative number. In this the MSB
represents the sign o the number and remaining bits represents the magnitude.
n1
The maximum range that a n-bit signed number can represent is from (2 1)
n1
to (2 1).

Example:
Find the decimal equivalent of the following binary numbers assuming sign-
magnitude representation of the binary numbers.
(i) 101100 (ii) 001000 (iii) 1111

Solution:
(i) Sign bit is 1, wh ich means the number is negative.
Magnitude = 01100 = (12)10
(101100)2 = (12)10
(ii) Sign bit is 0, which means the number is positive.
Magnitude = 01000 = 8
? (001000)2 = (+ 8)10

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Vidyalankar : GATE – EC

(iii) (1111)2 = (7)2

Digital circuits are used for performing binary arithmetic operations. It is
possible to use the circuits designed for binary addition to perform the binary
subtraction also if we can change the problem of subtraction to that of an
addition. This concept eliminates the need of additional circuits for
subtraction, rather the same adder circuits are used for both the operations.
This makes design of arithmetic circuits very convenient and cheaper. Thus it
is useful to learn 1’s and 2’s complement representation of signed number.

(b) One’s Complement Representation

In a binary number, if each 1 is replaced by 0 and each 0 by 1, the resulting number
is known as the one’s complement of the first number. For example, (0101)2
represents (+5)10, whereas (1010)2 represents (5)10 in this representation. In this
representation also, MSB is 0 for positive numbers and 1 for negative numbers.

Example:
(i) Find the one’s complement of the following binary numbers.
0100111001

Solution:
The 1's complement of following binary number is
1011000110

(ii) Represent the following numbers in one’s complement form.

+ 7 and 7
Solution:
(+ 7)10 = (0111)2
and (7)10 = (1000)2

From the above examples, it can be observed that for an n-bit number, the maxi-
mum positive number which can be represented in l’s complement
representation is (2  1) and the maximum negative number is  (2   1).
n1 n 1

(c) Two’s Complement Representation

If 1 is added to l’s complement of a binary number, the resulting number is
known as the two’s complement of the binary number. In, this representation
also, if the MSB is 0 the number is positive, whereas if the MSB is 1 the number
is negative. For an n-bit number, the maximum positive number which can be
represented in 2’s complement form is (2n1  1) and the maximum negative
number is 2n1.

It is also observed that the 2’s complement of the 2’s complement of a number is
the number itself.

Example:

Find the 2’s complement of the numbers:

(i) 01001110 (ii) 00110101

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 Notes on Boolean Algebra

Solution:
(i) Number 0 1 0 0 1 1 1 0
1’s complement 1 0 1 1 0 0 0 1
Add 1 1
1 0 1 1 0 0 1 0
(ii) Number 0 0 1 1 0 1 0 1
1’s complement 1 1 0 0 1 0 1 0
Add 2 1
1 1 0 0 1 0 1 1

Short cut Method :

1. If the LSB of the number is 1, its 2’s complement is obtained by changing each 0
to 1 and 1 to 0 except the least-significant bit.

2. If the LSB of the number is 0, its 2’s complement is obtained by scanning the
number from the LSB to MSB bit by bit and retaining the bits as they are up to
and including the occurrence of the first 1 and complements all other bits.

Example 1 :

Find two’s complement of the numbers:

(i) 11011000 (ii) 01100111
Solution:
p p p p
(i) Number 1 1 0 1 1 0 0 0
2’s Complement 0 0 1 0 1 0 0 0

p
(ii) Number 0 1 1 0 0 1 1 1
2’s Complement 1 0 0 1 1 0 0 1
Example 2 :

Represent (17)10 in
(i) Sign-magnitude,
(ii) One’s complement,
(iii) Two’s complement representation.

Solution:
The minimum number of bits required to represent (+ 17)10 in signed number format
is six.
? (+17)10 = (010001)2
Therefore, (17)10 is represented by
(i) 110001 in sign-magnitude representation.
(ii) 101110 in 1’s complement representation.
(iii) 101111 in 2’s complement representation.

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Vidyalankar : GATE – EC

BINARY ARITHMETIC
x Binary Addition
The rules of binary addition are given in following table.
Rules of binary addition

Augend Addend Sum Carry Result

0 0 0 0 0
0 1 1 0 1
1 0 1 0 1
1 1 0 1 10

Example 1:

Add the binary numbers:

0101 and 1111
Solution:
(1) (1) (1) m carry
0 1 0 1
(+) 1 1 1 1
1 0 1 0 0
n
carry

Example 2 :

Add the binary numbers:

0 1 1 0 1 0 1 0
0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 1
1 1 1 1 1 1 1 1

Solution:
1 Two pair of 1’s in the
previous column
(1) (1) (1) 1 (1) (1) (1) m One pair of 1’s in the
0 1 1 0 1 0 1 0 previous column
0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 1
1 1 1 1 1 1 1 1
1 1 1 1 0 0 1 0
1
Carry Even number of 1’s in column
odd number of 1’s in column
? The sum = 1 1 1 1 1 0 0 1 0

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 Notes on Boolean Algebra

From the above example, we observe the following:

(1) If the number of 1’s to be added in a column is even then the sum bit is 0, and if
the number of 1’s to be added in a column is odd then the sum bit is 1.
(2) Every pair 1’s in a column produces a carry (1) to be added to the next higher bit
column.
x Binary Subtraction
The rules of binary subtraction are given in following table.
Rules of binary subtraction
Minuend Subtrahend Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Example:
minuend: 101101
subtrahend: 100111
difference: 000110
x Binary Multiplication
Binary multiplication is similar to decimal multiplication. In binary, each partial
product is either zero (multiplication by 0) or exactly same as the multiplicand
(multiplication by 1). An example of binary multiplication is given below:
Example :
Multiply 1001 by 1101.
Solution:
10 01 Multiplicand
u1 101 Multiplier
1 0 01
I
0000 II Partial Products
10 01 III
IV
10 01
111 0 1 0 1 Final Products

In a digital circuit, the multiplication operation is performed by repeated additions of

all partial products to obtain the full product.

x Binary Division
Binary division is obtained using the same procedure as decimal division. An
example of binary division is given below:

Example:
Divide
1110101 by 1001

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Vidyalankar : GATE – EC

Solution:
1101 m Quotient
Divisor o 1001 1110101
m Dividend
1001
1011
1001
001001
1001
Ans: 1101 0000

x 1’s Complement Arithmatic

Binary subtraction can be performed by adding 1cs complement of the subtrahend to
the minuend. If a carry is generated, add the carry, (called end around carry) to the
result and answer obtained is positive (the minuend is greater than the subtrahend).
If the final carry is 0, the answer is negative (the minuend is smaller than the
subtrahend) and is in 1cs complement form.

Example:
Perform binary subtraction using 1cs complement method.
(i) Subtract 5 from 7
(ii) Subtract 7 from 5.

Solution :

(i) Subtract 5 from 7

7 0101
5 Ÿ (  ) 1000 minuend
2 10001 (1cs complement of subtrahend i.e. 5)
1
add end around
carry 0010

? The answer is (0 0 1 0)2 = (+2)10

(ii) Subtract 7 from

5 0 10 1 minuend
 
7 Ÿ 10 0 0
(1cs complement of subtrahend i.e. 7)
2 11 0 1

Here final carry is zero. Therefore the answer is negative and is in 1cs complement form.
? 1cs complement of 1 1 0 1 = 0 0 1 0 i.e. (2)10
? Therefore answer is (2)10

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 Notes on Boolean Algebra

x 2ccs Complement Arithmatic

Binary subtraction can be performed by adding the 2’s complement of the subtrahend
to the minuend. If a final carry is generated, discard the carry and the answer is given
by the remaining bits which is positive (the minuend is greater than the subtrahend).
If the final carry is 0, the answer is negative (the minuend is smaller than the
subtrahend) and is in 2’s complement form.

Example:
Perform binary subtraction using 2’s complement representation of negative numbers.
Solution:
(i)
7 0 1 1 1 Minuend
5 () 1 0 1 1 2’s complement of subtrahend
2 1 0 0 1 0
n

Discard final carry

The answer is 0 0 1 0 equivalent to (+ 2)10.

(ii) 5 0 1 0 1 Minuend
7 () 1 0 0 1 2’s complement of subtrahend
2 1 1 1 0

The final carry = 0. Therefore, the answer is negative and is in 2cs complement form.
2cs complement of 1110 = 0010. Therefore, the answer is (2)10.

Note:
Both the 1’s and 2’s complement are complex, compared to direct subtractions. But
they have distinct advantage when implemented using logic circuits because they
allow subtraction to be done by using only addition.

Both 1’s and 2’s complement can be realized using logic circuits, and 2’s complement
has an advantage over the 1’s complement in that an end around carry operation
does not have to be performed.

Overflow
For Addition
If an addition operation produces a result that exceeds the range of the number
system, overflow is said to occur. A simple rule for detecting overflow in addition: An
addition overflow occurs if the signs of the addends are the same and the sign of the
sum is different from the addends’ sign.

For Subtraction
Overflow in subtraction can be detected by examining the signs of the minuend and
the complemented subtrahend, using the same rule as in addition.

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Vidyalankar : GATE – EC

OCTAL NUMBER SYSTEM (BASE 8)

Older computer systems use octal numbers to represent binary information. There are
3
eight (2 ) combinations of 3 bit binary number. Therefore, sets of 3 bit binary numbers
can be represented by a singe octal number and this can be conveniently used for
entering data in the computer. Octal number system uses eight symbols 0 to 7. Octal
numbers are also referred to as base 8 numbers. The advantage of the octal system is its
usefulness in converting directly from a 3 bit binary number.

x Octal to Decimal Conversion

3 2 1 0
Weight 8 8 8 8
Decimal value 512 64 8 1
Octal No. 2 3 7 4

2 u 512 + 3 u 64 + 7 u 8 + 4 u 1 = (1276)10
? (2374)8 = (1276)10

Since octal number system has base of 8 each successive digit position is an
0
increasing power of 8, beginning with 8 . The decimal number can be obtained by
multiplying each digit by its weight and summing the products.

x Decimal to Octal Conversion

To get octal equivalent of a decimal number we use repeated division by 8. The
decimal number is divided by 8, the quotient is divided by 8 and the remainders
obtained will give the octal number. The first remainder is the LSB.

Example:
Convert (1276)10 to it’s octal equivalent

Solution:
8 1276 Remainder LSB
8 159 4
8 19 7
8 2 3
0 2 MSB

?(1276)10 = (2374)8

Note: Fractional numbers are converted in the same way as for binary by repeated
multiplication by 8.

x Octal to Binary Conversion

The primary application of octal number is in the representation of binary number
since it takes only one octal digit to represent three binary bits. Thus octal numbers
are much easier to read, than binary number.

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 Notes on Boolean Algebra

Octal digit Binary number

0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

To convert octal to binary, simply replace the octal digit by its binary number using 3
bits.

e.g.: (47)8 o Octal No.

(100)2 (111)2
? (47)8 = (100111)2

x Binary to Octal Conversion

Break the binary number into groups of 3 bits and convert each group into an
appropriate octal digit.

Before and after decimal point grouping should done be as shown

101101 ˜ 101110
0 (55.56)8 …( 0 Ÿ appended zero)
n n n n 2
Group 3 bits in the arrow direction

§ 100 111 ·
e.g.: ¨ ¸ o Binary
© 4 7 ¹2

? (100111)2 = (47)8.

Note : While grouping we can append zero to the left of MSB and to the right of LSB
to make pair of there as shown above.

HEXADECIMAL NUMBER SYSTEM (BASE 16)

Computers require binary data, but people working with computers have trouble
remembering long binary words. One solution to the problem is to use hexadecimal or
base – 16 number system. Hex is more compact than decimal. Two hexadecimal digits
can represent a decimal number up to 255. Each hex digit is equal to 4 binary digits.
The hexadecimal system has a base of 16 i.e. it is composed of 16 symbols. Ten digits
and six alphabetic characters make up this system 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,
E, F. Therefore it is also called alphanumeric code.

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Vidyalankar : GATE – EC

Decimal Binary Hexadecimal

0 0000 0
1 0001 1
2 0010 2
3 0011 3
4 0100 4
5 0101 5
6 0110 6
7 0111 7
8 1000 8
9 1001 9
10 1010 A
11 1011 B
12 1100 C
13 1101 D
14 1110 E
15 1111 F

x Binary to Hexadecimal Conversion

Break the binary number in four bit groups starting at the binary point and replace
each group with the equivalent hexadecimal symbol.

Example :
(11011001)2
D 9
? (1101 1001)2 = (D9)16.

x Hexadecimal to Binary Conversion

Replace each hexadecimal digit by the four bit binary number.

Example:
(4CA)16 (0100 1100 1010)2
4 C A
With 2 hexadecimal digits, we can count upto (FF)16 = (255)10, with four hexadecimal
digits, we get (FFFF)16 = (65535)10.

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 Notes on Boolean Algebra

x Hexadecimal to Decimal Conversion

To get the decimal equivalent, multiply each hexadecimal digit by its weight and sum
all the products.
Hexadecimal weight 163 162 161 160
Weight value 4096 256 16 1
Hexadecimal No. B 2 F 8
(B2F8)16 = B u 4096 + 2 u 256 + F u 16 + 8 + 1 = (45816)10
OR
We can convert the hexadecimal number to the binary number and then convert to
decimal number.
x Decimal to Hexadecimal Conversion
Repeated division of decimal number by 16 gives the hexadecimal number, formed by the
st
remainders of each division. The 1 remainder is the LSB of the hexadecimal number.

Example : Convert (45816)10 into it’s hexadecimal equivalent

Solution:
Remainder
16 45816 8 LSB
16 2863 15 (F)
16 178 2
16 11 11(B)
0 MSB

? (45816)10 = (B2F8)16

x Hexadecimal Addition
The following rules are applied:
1. In any given column of an addition problem, think of the two hexadecimal digits in
terms of their decimal value.
e.g. (5)16 = (5)10
(C)16 = (12)10

2. If the sum of these two digits is (15)10 or less, bring down the corresponding
hexadecimal digit.
3. If the sum of these two digits is greater than (15)10, bring down the amount of the
sum that exceeds (16)10 and carry a 1 to the next column.
e.g. (DF)16 + (AC)16
D F
A C
18 B

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Procedure : F + C = 15 + 12 = 27
? 27 – 16 = B with carry 1
D + A + 1 = 13 + 10 + 1 = 24
24 – 16 = 8 with a carry 1.
? (DF)16 + (AC)16 = (18B)16

CODES
Almost all digital circuits (Computers, calculators) understand only binary numbers. But
most people understand only decimal numbers. Thus, we must have electronic devices
that can translate from decimal to binary and from binary to decimal numbers.

Input Key board

1 2 3 Output Display

4 5 6 Processing
Unit Decoder
7 8 9 0

Binary Decimal
Decimal
1001
9

A typical system that can be used to translate from decimal

to binary numbers and back to decimals

The device that translates from keyboard decimal numbers to binary is called an encoder.
The device converting from binary numbers to decimal numbers is called decoder.
(i) Binary Codes
In this, the decimal numbers are converted, to their straight binary equivalent.
e.g. 13 is represented as 1101.
(ii) BCD Code (8–4–2–1)
x In this code, decimal digits 0 through 9 are represented (coded) by their natural
binary equivalents using four bits. For example, (23)10 is represented by 0010
0011 using BCD code, rather than (10111)2.
x This code is also known as 8421 code or simply BCD code. 8, 4, 2 and 1 are
the weights of the four bits of the binary code of each decimal digit similar to
straight binary number system. Therefore, this is a weighted code.
In applications such as frequency counters, digital voltmeters or calculators where
the output is decimal display, BCD code is usually used.
Example:
Decimal (5 2 9)10
BCD 0101 0010 1001

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 Notes on Boolean Algebra

(iii) Excess-3 Code

x This is another form of BCD code, in which each decimal digit is coded into a 4-
bit binary code.
x The code for each decimal digit is obtained by adding decimal 3 to the natural
BCD code of the digit. For example, decimal 2 is coded as 0010 + 0011 = 0101
in excess-3 code.
x It is not a weighted code.
x This code is a self-complementing code, which means 1 s complement of the
coded number yields 9’s complement of the number itself.
x The self complementing property of this code helps considerably in performing
subtraction operation in digital systems.

(iv) Gray Code

x It is a very useful code in which a decimal number is represented in binary form
in such a way, so that each Gray-code number differs from the preceding and the
succeeding number by a single bit.
x For example, the Gray code for decimal number 5 is 0111 and for 6 is 0101.
These two codes differ by only one bit position (third from the left).
x This code is used extensively for shaft encoders because of this property.
x It is not a weighted code.

The Gray code is a reflected code and can be constructed using this property as
given below:
(i) A 1-bit Gray code has two code words 0 and 1 representing decimal numbers 0
and 1 respectively
n1
(ii) An n-bit (n t 2) Gray code will have first 2 Gray codes of (n  1) bits written in
order with a leading 0 appended.
n1
(iii) The last 2 Gray codes will be equal to the Gray code words of an (n  1) bit
n1
Gray code, written in reverse order (assuming a mirror placed between first 2
n1
and last 2 Gray codes) with a leading 1 appended
Example:
Determine (a) 1-bit (b) 2-bit (c) 3-bit Gray codes and tabulate along with their
equivalent decimal numbers.

Solution:
(a) 1-bit Gray code is constructed using (i) above.
Decimal number Gray code
0 0
1 1
(b) 2-bit Gray code is constructed using (ii) and (iii) above and Gray code of 1-bit
Decimal number Gray code
0 00
1 01
2 11
3 10

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(c) 3-bit Gray code is constructed using 2-bit Gray code,

Decimal Number Gray-code
0 000
1 001
2 011
3 010
4 110
5 111
6 101
7 100
Different binary codes are shown in the table given below
Various Binary Codes
Decimal Binary BCD Excess-3 Gray
Number B3 B2 B1 B0 D C B A E3 E2 E1 E0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1
2 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 1
3 0 0 1 1 0 0 1 1 0 1 1 0 0 0 1 0
4 0 1 0 0 0 1 0 0 0 1 1 1 0 1 1 0
5 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 1
6 0 1 1 0 0 1 1 0 1 0 0 1 0 1 0 1
7 0 1 1 1 0 1 1 1 1 0 1 0 0 1 0 0
8 1 0 0 0 1 0 0 0 1 0 1 1 1 1 0 0
9 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0

(v) Alphanumeric Codes

When communicating with or between computers, data may consist of numerals,
letters and special symbols. We require a binary–base code which can represent
letters of the alphabet as well as numbers. If we use n bit binary code, we can
n
represent 2 elements using this code. Therefore to represent 10 digits 0 through 9
6
and 26 alphabets A to Z, we need minimum 6 bit alphanumeric code. (2 = 64). 6 bit
alphanumeric code is used in many computers to represent alphanumeric characters
and symbols internally and therefore can be called internal code. Frequently there is
a need to represent more than 64 characters including the lower case letters and
special control characters for the transmission of digital information. For this reason
the following two codes are normally used.
(a) Extended BCD Interchange Code (EBCDIC)
(b) ASCII (American standard code for information interchange)

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 Notes on Boolean Algebra

(a) EBCDIC
This is an 8 bit code without parity. A ninth bit can be added for parity. Used in
IBM equipments.
(b) ASCII
This code is widely used to send information to and from microcomputers. It is a
7 bit code used in transferring coded information from keyboards and to
computer displays and printers. The abbreviation ASCII stands for the American
Standard Code for Information Interchange. The ASCII Code is used to represent
numbers, letters, punctuation marks as well as control characters. e.g. The 7 bit
ASCII Code 111 1111 stands for DEL. i.e., Delete.
With 7 bits we can code upto 128 characters which is enough for the full upper and
lower case alphabet, numbers, punctuation marks, and control characters. The
code is arranged so that if only uppercase letters, numbers, and a few control
characters are needed, only the lower 6 bits are all that are required. If a parity
check is wanted, a parity bit is added to the basic 7 bit code in the MSB position.
The binary word 1100 0100 is the ASCII Code for uppercase D with odd parity.

(vi) Hollerith Code

Many large computers use punched cards and card readers, which read data from
the cards. When a hole is punched into a card a beam of light can pass through the
hole, and is read as 1. A card consists of 80 columns and 12 rows. Each column
represents an alphanumeric character with holes in the appropriate rows. A hole is
sensed as 1 and absence of a hole is sensed as 0 by the circuits in the Card Reader.
(vii) Error Detecting and Error Correcting Codes
When the digital information in the binary form is transmitted from one circuit or
system to another an error may occur. This means a signal corresponding to 0 may
change to 1 and vice–versa.
x Parity
Parity is error detecting technique. To detect errors a constant check of
transmitted data is done. To check accuracy an extra parity bit is generated and
transmitted. By parity we mean number of 1’s in a digital data which may be even
(even parity) or odd parity. The data along with parity bit is transmitted. The parity
of the received data is checked. If the odd number of data bit changes, the parity
check gives an error. The even numbers of change in data bit won’t affect the
parity, hence error cannot be detected.
x Hamming Codes
Hamming codes are special type of codes used for error detection and
correction. There codes have a minimum distance 3. Therefore it can detect all
one and two bit errors, while it can also correct up to one bit errors.
(a) Generation of Hamming codes Data
If ‘n’ is the number of bits to be transmitted and if ‘i’ parity bits are used then
i
length of code word : 2  1
i
number of data bits (n) : 2  1  i
number of parity bits : i

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i
(i) The bit position in Hamming code word is then numbered from 1 through 2 
1. In this case, any position whose bit position number is a power of 2 is a
parity bits and remaining are data bits, e.g. thus for 4 bit data (D3 D2 D1 D0),
number of parity bits required are 3 (P2 P1 P0). Thus code word becomes.
2 1 0
2 2 2
Bit Position 7 6 5 4 3 2 1
Code Word D3 D2 D1 P2 D0 P1 P0

(ii) After this, each parity bit is grouped with a subset of information bits, whose
position number have a 1 in the same bit when expressed in binary.
e.g. Parity bit P1 (Position 2 i.e. 0 1 0) is grouped with data bits whose
positions is 3 (0 1 1), 6 (1 1 0) and 7 (1 1 1). This process is done for all
parity bits.

(iii) Once grouping is done parity bit is chosen to produce even parity. i.e. even
number of ones.

Example:
Generate Hamming code for data bits 0 1 1 0
Step 1 :
Arranging of bits
2 1 0
2 2 2
Bit position : 7 6 5 4 3 2 1
Code Word : D3 D2 D1 P2 D0 P1 P0
0 1 1  0  
Step 2 and 3 :
Grouping and assignments
Parity
P0 : P0 D0 D1 D3 :  010 1010

P1 : P1 D0 D2 D3 :  010 1010

P2 : P2 D1 D2 D3 :  110 0110

…[value of parity bit is elected to have even parity]

Thus, P0 Ÿ 1, P1 Ÿ 1, P2 Ÿ 0
0 1 1 0 0 1 1
? Transmitted code word :
P2 P1 P0

Error detecting and correcting ability of Hamming code. From above example, we
see that transmitted code as word 0 1 1 0 0 1 1. Now let there be a 1 bit error
during transmission, such that bit position 6 becomes zero. Therefore received
code word is 0 0 1 0 0 1 1. Our aim is to detect this error and correct it.

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 Notes on Boolean Algebra

Bit position : 7 6 5 4 3 2 1
D3 D2 D1 P2 D0 P1 P0
Transmitted word : 0 1 1 0 0 1 1
Received word : 0 0 1 0 0 1 1
error

(b) Procedure to detect and correct error

Grouping parity bits in same way as it was done during transmission and
checking it if they have even parity. If they don’t have even parity, then these is
an error.

P0 D0 D1 D3 : 1 0 1 0 Ÿ error : 0
P1 D0 D2 D3 : 1 0 0 0 Ÿ error : 1
P2 D1 D2 D3 : 0 1 0 0 Ÿ error : 1

The bit position in error is (P2 P1 P0)2 Ÿ (1 1 0)2 = 610

Thus position 6 was in error, ? complement it, ?correct code word : 0 1 1 0 0 1 1
which is same as transmitted code word.

LOGIC GATES

In a digital system there are only a few basic operations performed, irrespective of the
complexities of the system. The basic operations are AND, OR, NOT, and FLIP-FLOP.
The AND, OR, and NOT operations are discussed here and the FLIP-FLOP, which is a
basic memory element used to store binary information will be introduced in chapter 4.

(i) The NOT Gate

The NOT gate (inverter) performs the operation called inversion or complementation.
The inverter changes one logic level into other logic level i.e. it changes 0 to 1 or 1 to
0. The presence of a small circle known as bubble always denotes inversion in digital
circuits.
X X X X

Standard Logic symbols of Inverter

Truth Table of inverter

I/P O/P
0 1
1 0

Complementation laws
0 1
1 0
A A

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(ii) The AND Gate

A circuit which performs an AND operation is shown in figure below. The AND
operation is defined as: the output is 1 if and only if all the inputs are 1.
Mathematically, it is written as

X = A AND B AND C … AND N

= A˜B˜C˜…˜N …[˜ Ÿ Boolean multiplication]
= ABC … N

A
B X=A˜B N
N
Standard Logic symbols for an AND gate

where A, B, C, … N are the input variables and X the output variable.

Truth Table of 2-input AND gate

INPUTS OUTPUT
A B X
0 0 0
0 1 0
1 0 0
1 1 1

The AND gate acts as an Enable/Inhibit Device: The AND gate is used to enable the
passage of signal from one point to another at certain times and to inhibit the
passage at other times.

Laws of AND function

A˜0 0 Null
A ˜1 A Identity
A˜A A Idempotent
A˜A 0 Complement
A ˜B B˜ A Commutative
ABC A(BC) (AB)C Associative
A ˜ (B  C) A ˜B  A ˜ C Distributive

(iii) The OR Gate

The following figure shows an OR gate with N inputs (N t 2) and one output. The OR
operation is defined as: the output of an OR gate is 1 if and only if one or more inputs
are 1.

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 Notes on Boolean Algebra

The OR function is mathematically represented as

X = A OR B OR C ……OR N
= A + B + C + ………...+ N …[ + Ÿ Boolean addition]

A
B
X
N
Standard Logic symbol for N input OR Gate

input OR gate
Truth table of 2

INPUTS OUTPUT
A B X
0 0 0
0 1 1
1 0 1
1 1 1

Laws of OR function
A0 A Null
A 1 1 Identity
AA A Idempotent

AA 1 Complement
A B B A Commutative law
A  (B  C)  A  B)  C Associative law

(A  B)(A  C) A B˜C Distributive law

The OR gate is also called ‘any or all’ gate.

The representation of OR, AND gate using switches

A
X
B

A B
X

OR AND
X=A+B X = A˜ B

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NAND AND NOR Operations

These operations have become very popular and are widely used, because only one
type of gates, either NAND or NOR are sufficient for the realization of any logical
expression. Because of this reason, NAND and NOR gates are known as universal
gates.

(iv) The NAND Gate

The AND  NOT operation is known as NAND operation.

NAND operation is mathematically represented as

X AB
A X
B A ˜B˜ N
N
AND NOT

A
X
B A ˜B˜ N
N

Standard Logic symbol for the NAND Gate

Truth table of 2-input NAND gate

INPUTS OUTPUT
A B X
0 0 1
0 1 1
1 0 1
1 1 0

The output of NAND gate is HIGH, when at least one input to the NAND gate is
LOW.

Basic Gates using NAND Gates only

All the three basic logic operation AND, OR and NOT can be performed by using only
NAND gate.

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 Notes on Boolean Algebra

NOT A X X =A˜A A

AND A AB X AB AB
B

OR A
A

X A˜B
 $  %
B
B

(v) The NOR Gate

The OR-NOT operation is known as NOR operation.

NOR gate is mathematically represented by

X A B N

A X AB N
B
N

A X AB N
B
N

Standard Logical symbol of NOR gate

input NOR gate

Truth Table of 2
INPUTS OUTPUT
A B X
0 0 1
0 1 0
1 0 0
1 1 0

The output of NOR gate is HIGH only when all the inputs are LOW.

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Basic Gates using NOR Gates only

Similarly as NAND gates NOR gates can be used to perform all three basic logical
operation

NOT A
Y=AA A

OR A AB
Y AB AB
B

A A
AND
Y A  B $ ˜ %

B
B

The NAND and NOR functions are commutative but not associative.

BOOLEAN ALGEBRA
The digital signals are discrete in nature and can only assume one of the two values
0 or 1. A number system based on these two digits is known as binary number system.
The rules for manipulations of binary variables, is known as Boolean algebra. This is the
basis of all digital systems like computers, calculators, etc. The Boolean algebraic
theorems are given below.

Boolean Algebraic Theorems

Theorem No. Theorem

1.1 A+0=A
1.2 A˜1=A
1.3 A+1=1
1.4 A˜0=0
1.5 A+A=A
1.6 A˜A=A
1.7 AA 1
1.8 A˜A 0
1.9 A ˜ (B + C) = AB + AC
1.10 A + BC = (A + B) (A+ C)
1.11 A + AB = A

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 Notes on Boolean Algebra

Theorem No. Theorem

1.12 A (A + B) = A
1.13 A  AB (A  B)
1.14 A (A  B) AB
1.15 AB + AB A
1.16 (A  B) ˜ (A  B) A
1.17 AB + AC (A  C) (A  B)
1.18 (A  B) (A  C) AC  AB
1.19 AB + AC  BC AB  AC
1.20 (A  B)(A  C)(B  C) (A  B)(A  C)
1.21 A ˜B ˜ C˜ A BC
1.22 A BC A ˜B ˜ C

Observe that the even numbered theorems can be obtained from their preceding odd
numbered theorems by (i) interchanging + and ˜ signs, and (ii) interchanging 0 and 1.
Theorems which are related in this way are called duals. The last two theorems are
called Demorgan’s theorems.

Theorem 1.10 can be proved by making the truth table given in table below.

Truth table to prove Theorem 1.10

A B C BC A + BC A+B A+C (A + B) (A + C)
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1
3
From the table we observe that there are 8 (=2 ) possible combinations of the three
variables A, B, and C. For each combination, the value of A + BC is the same as that of
(A + B) (A + C), which proves the theorem.

Similarly all theorems can be proved using truth table.

Operator Precedence
When solving Boolean expressions, the precedence in descending order is
1. Parenthesis 2. NOT
3. AND 4. OR

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x De Morgan’s Theorem
Statement:
It states that the complement of a function is obtained by interchanging AND and OR
operators and complementing each literal (variable).

DeMorgan’s Laws
1. A  B A ˜ B
i.e. NOR gate is equivalent to bubbled AND gate, which is as shown below.

A X AB A X A ˜ B A  B
B B

2. AB A  B
i.e. NAND gate is equivalent to bubbled OR gate, which is as shown below.

A X = AB A X AB
B B

DeMorganization ( It is use to get complement of any function)

Procedure
Step 1 : Complement the entire function
Step 2 : Change all the ANDs to ORs and all the ORs to ANDs.
Step 3 : Complement each of the individual variable.
Demorganizations can be stated in one line as
“just break the line, change the sign”.

For example, find complement of the function Y = AB  C using demorganization is

1. Complement function Y AB  C
2. Change operators Y (A  B)C
3. Complement variables Y (A  B)C

x Converting Circuits to Universal Logic

Procedure
Step 1: Draw the circuit in AND/OR/invert logic
Step 2: If NAND realization is chosen, add a circle to the outputs of each AND gate
on the logic diagram, and add circles to the inputs of all OR gates
Step 3: In NOR realization, add circle to the output of OR gates and add circle to the
inputs of AND gates.
Step 4: Add or subtract an inverter on each line that received a circle in step 2 or 3.

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 Notes on Boolean Algebra

Example:
Realize equation F = AB + C using
(i) Using AndOR gates only
(ii) Using only NAND gates only
(iii) Using only NOR gates only

Solution:
(i) Using AND  OR gates

A
B
F = AB + C
C

(ii) Using only NAND gates

Applying the procedure mentioned above, we get

A A
B B
F = AB + C Ÿ F = AB + C
C C

… [ Bubbled OR is equivalent to NAND gate (De. Morgan’s theorem)]

(iii) Using only NOR gates

F = AB + C
= (A + C) (B + C) … (Theorem refer table)

A
C
F = AB + C

Applying the procedure mentioned, we get

A A
C C
F = AB + C Ÿ F = AB + C
B B

… [Bubbled AND is equivalent to NOR]

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x The ExclusiveOR Gate (EXOR)

The EXOR is a modified form of OR gate. It is also called ‘any but not all’ gate.
EXOR function is represented by the symbol †.
EXOR is mathematically represented as
X AB  AB
A
X= A† B
B

Standard Logical Symbol for 2input EXOR Gate

Truth Table of two input EX-OR gate

INPUTS OUTPUT
A B X
0 0 0
0 1 1
1 0 1
1 1 0
EX-OR gate using AND-OR-Invert

A
B
Y AB  AB

Note: It is also noted that EXOR is inequality comparator.

The EXOR operation is mathematically represented by following ways:

1. X A † B
2. X AB  AB ….SOP form
3. X (A  B)(A  B) ….POS form

If more than 2 inputs be EXORed, then

A †B † C (AB  AB)C  (AB  AB)C

ABC  ABC  (AB ˜ AB)C

ABC  ABC  ((A  B)(A  B))C
ABC  ABC  (AA  AB  AB  BB)C
ABC  ABC  ABC  ABC
Note: There are only 2input EXOR gates available in the market.

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 Notes on Boolean Algebra

To implement EXOR function of more than 2inputs following methods are used.

1. X A †B†C

A
B X
C

2. X A †B †C†D

A
B
X
C
D

Useful formulae for EXOR function

x A†A AA  AA 0
x A†0 A0  A0 A
x A †1 A ˜ 1  A ˜1 0  A A
x A†A A˜A  A˜A A  A 1
x A † A † A......... † A = 0 if no. of terms is even
= A if no. of terms is odd
x A † 0 † 0.......... † 0 = A

x A † 1† 1........... † 1 = A if no. of terms is even

= A if no. of terms is odd
x A † A † A......... † A = 0 if no. of terms is even

= A if no. of terms is odd

x A † B  AB  AB
$%  $%
$ %
i.e. one of the inputs of EXOR is inverted then the EXOR gate works as EXNOR.
x A † B † AB A  B
x A †B †1 A †B A B

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x The Exclusive–NOR Gate (EXNOR)

The EXNOR is modified form of NOR gate.
EXNOR function is represented by the symbol
EXNOR is mathematically represented as
X A B
  AB  AB

A X A B
B
Standard Logical Symbol for 2input EXNOR Gate

Truth Table of two input EX-NOR gate

INPUTS OUTPUT
A B X
0 0 1
0 1 0
1 0 0
1 1 1
EX-NOR using standard gates
A AB
B
X A B
 ABAB

AB
EXNOR is called as equality comparator as output of EXNOR is logic 1 only when
the even no. of inputs are equal.
Useful formulae for EXNOR Gate
x A 0 A
x A 1 A
x A A 1
x A A 0
x A B A †B
x A B A †B
x A B A †B
x A B AB A  B
x A AB AB
x A (A  B) AB
x A AB A B
x A (A  B) AB AB

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 Notes on Boolean Algebra

STANDARD REPRESENTATION OF LOGIC FUNCTIONS

The most basic representation of a logic function is the truth table in which the input
combinations are arranged in rows in ascending binary counting order, and the
corresponding output values are written in a column next to the rows. The general
structure of a 3variable truth table is shown in the table below. The truth table for an n-
n
variable logic function has 2 rows, as following table has 3 variables; therefore it has
3
2 = 8 rows.
General truth table structure for a 3-variable logic function, F(X, Y, Z)
Row X Y Z F (X,Y,Z)
0 0 0 0 F(0,0,0)
1 0 0 1 F(0,0,1)
2 0 1 0 F(0,1,0)
3 0 1 1 F(0,1,1)
4 1 0 0 F(1,0,0)
5 1 0 1 F(1,0,1)
6 1 1 0 F(1,1,0)
7 1 1 1 F(1,1,1)
The information contained in a truth table can also be conveyed algebraically, before
doing this we will define some terms.
Some Definitions:
x A literal is a variable or the complement of a variable.
Examples: X, Y, Xc, Yc.
x A product term is a single literal or a logical product of two or more literals.
Examples: Zc, W˜X˜Y, X˜Yc˜Z, Wc˜Yc˜Z.
x A sum-of-products expression (SOP) is a logical sum of product terms.
Example: Zc + W˜X˜Y + X˜Yc˜Z + Wc˜Yc˜Z.
x A sum term is a single literal or a logical sum of two or more literals.
Example: Zc, W + X + Y, X + Yc + Z, Wc + Yc + Z.
x A product-of-sums expression (POS) is a logical product of sum terms.
Example: Zc ˜ (W + X + Y) ˜ (X + Yc + Z) ˜ (Wc + Yc + Z).
x A normal term is a product or sum term in which no variable appears more than once.
Examples: W ˜ X ˜ Yc, W + Xc + Y.
n
x An n-variable minterm is a normal product term with n literals. There are 2 such
product terms. Examples of 4-variable minterms: Wc ˜ Xc ˜ Yc ˜ Zc, W ˜ X ˜ Yc ˜ Z,
Wc ˜ Xc ˜ Y ˜ Zc.
x An n-variable maxterm is a normal sum term with n literals. There are 2n such sum
terms. Examples of 4-variable maxterms:
Wc+Xc +Yc +Zc, W +X +Yc +Zc, Wc +Xc +Y + Zc.
Note: There is a close correspondence between the truth table and minterms and
maxterms.
x A minterm can be defined as a product term that is 1 in exactly one row of the truth
table.
x Similarly, a maxterm can be defined as a sum term that is 0 in exactly one row of the
truth table. Following table shows the correspondence for a 3-variable truth table.

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Minterms Maxterms for a 3-variable logic function, F(X, Y, Z)

Row X Y Z F Minterm Maxterm
0 0 0 0 F(0,0,0) Xc˜ Yc˜ Zc X+Y+Z
1 0 0 1 F(0,0,1) Xc˜ Yc˜ Z X + Y + Zc
2 0 1 0 F(0,1,0) Xc˜ Y˜ Zc X + Yc + Z
3 0 1 1 F(0,1,1) Xc˜ Y˜ Z X + Yc + Zc
4 1 0 0 F(1,0,0) X˜ Yc˜ Zc Xc + Y + Z
5 1 0 1 F(1,0,1) X˜ Yc˜ Z Xc + Y + Zc
6 1 1 0 F(1,1,0) X˜ Y˜ Zc Xc + Yc + Z
7 1 1 1 F(1,1,1) X˜ Y˜ Z Xc + Yc + Zc
x An nvariable minterm can be represented by an nbit integer, the minterm number
or minterm i.
In minterm i, a particular variable appears complemented if the corresponding bit in
the binary representation of i is 0; otherwise, it is uncomplemented. For example, row
5 has binary representation 101 and the corresponding minterm is X ˜ Yc ˜ Z.
x In maxterm i, a variable is complemented if the corresponding bit in the binary
representation of i is 1. Thus, maxterm 5 (101) is Xc + Y + Zc.
Note : That all of this makes sense only if we know the number of variables in the truth
table, three in the above examples.
x The canonical sum of a logic function (standard SOP) is a sum of the minterms
corresponding to truth-table rows (input combinations) for which the function
produces a 1 output. For example, the canonical sum for the logic function shown in
table below is
Truth table for a particular 3-variable logic function, F(X,Y,Z)
Row X Y Z F
0 0 0 0 1
1 0 0 1 0
2 0 1 0 0
3 0 1 1 1
4 1 0 0 1
5 1 0 1 0
6 1 1 0 1
7 1 1 1 1

F = 6 X,Y,Z (0,3,4,6,7)
= Xc ˜ Yc ˜ Zc  Xc ˜ Y ˜ Z  X ˜ Yc ˜ Zc  X ˜ Y ˜ Zc  X ˜ Y ˜ Z
Here, the notation 6 X,Y,Z (0,3,4,6,7) is a minterm list and means “the sum of minterms 0,
3, 4, 6, and 7 with variables X, Y, and Z.”
x The canonical product of a logic function (standard POS) is a product of the
maxterms corresponding to input combinations for which the function produces a 0
output. For example, the canonical product of the same logic function shown in
above table is

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 Notes on Boolean Algebra

F = 3 X,Y,Z (1,2,5)
= (X  Y  Z„) ˜ (X  Y„ Z) ˜ (X„ Y  Z„)
Here, the notation 3 X,Y,Z (1,2,5) is a maxterm list and means “the product of
maxterms 1, 2, and 5 with variables X, Y, and Z.”

Conversion from standard (canonical) SOP to standard POS or vice versa.

From above examples we see that it’s easy to convert between a minterm list and a
maxterm list.
i.e. 6 X,Y,Z (0,3,4,6,7) = 3 X,Y,Z (1,2,5)

Example:
Consider the truth table of 3 variables as shown below.
(i) Write expression of given function F in standard SOP form
(ii) Write expression of given function F in standard POS form
A B C Output (F)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

Solution :
(i) Standard SOP
? F = ¦ m(1, 4, 6, 7) ABC  ABC  ABC  ABC …(1)
(A,B,C) (0 0 1) (1 0 0) (1 1 0) (1 1 1)

(ii) Standard POS

In order to convert it to POS
The remaining terms are (0, 2, 3, 5). Express these terms in maxterm form
F = – M(0, 2, 3, 5) (A  B  C) ˜ (A  B  C) ˜ (A  B  C) ˜ (A  B  C) …(2)
(A,B,C) (0 0 0) (0 1 0) (0 1 1) (1 0 1)

Thus, we see that both equation (1) and (2) represents the same truth table
? F = ¦ (A, B, C) (1, 4, 6, 7) –(A, B, C) (0, 2, 3, 5)

CIRCUIT MINIMIZATION
Minimization of any Boolean equation, leads to circuit with less hardware components.
This reduces the size, cost of circuit and circuit becomes more reliable. Thus circuit
minimization is one of the important steps before designing any digital circuits.

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x Circuit minimization using Boolean algebra

Consider the Boolean equation F ¦(X, Y,Z) (0,1,4,5,6) given below. The equation can
be simplified using Boolean theorem as follows
F= Xc ˜ Yc ˜ =c  Xc ˜ Yc ˜ =  X ˜ Yc ˜ =c  X ˜ Yc ˜ =  X ˜ Y ˜ =c
= [(Xc ˜ Yc) ˜ =c  (Xc ˜ Yc) ˜ =]  [(X ˜ Yc) ˜ =c  (X ˜ Yc) ˜ =]  X ˜ Y ˜ =c
= Xc ˜ Yc  X ˜ Yc  X ˜ Y ˜ =c
= [Xc ˜ (Yc)  X ˜ (Yc)]  X ˜ Y ˜ =c
= Yc  X ˜ Y ˜ =c
The corresponding logic circuit becomes.
X
Y
Z
F = Yc + X ˜ Y ˜ Zc

Thus it requires one 3-input AND gates and one 2-input OR gate (assuming inverters
are freely available).
Disadvantage
x Method is complex and not systematic.
x In a complex equation, it becomes difficult visualize relationship between various
terms.
x Also, one is not sure about the final equation obtained is truly a minimal one.

KARNAUGH MAP (KMAP)

The above difficulty is removed using k-maps. Karnaugh Map is a graphical

representation of a logic function's truth table. It provides a systematic method for
simplifying the Boolean expression to produce simplest SOP or POS expression, known
as minimal expression. Following figure shows Karnaugh maps for logic functions of 2, 3,
and 4 variables

X X X W
XY WX
01 11 10 00 01 11 10
Y 0 1 Z 00 YZ
0 2
0 0 0 2 6 4 00 0 4 12 8

1
1 3 Y 1
1 3 7 5 Z 01 1 5 13 9
Z
11 3 7 15 11
(a) 2-Variable Y Y
10 2 6 14 10
(b) 3-Variable
X
Karnaugh maps (c) 4-Variable

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 Notes on Boolean Algebra

Discription of K-maps
n
x For a n-variable function, K-map contains 2 cells, one for each possible input
combination (minterm / maxterm).
x The rows and columns of K-map are labeled so that input combination for any cell is
easily determined from row and column heading as shown above.
x In each row and column heading first bit corresponds to first variable and second bit
corresponds to second variable, which help to identify cells.
x The smaller number inside each cell is the corresponding minterm/maxterm number
in the truth table.
x Gray code has been used for identification of each cell e.g. cell 13 in 4-variable map
corresponds to the truth table row in which WXYZ = 1 1 0 1.

Representation of Truth table on K-map

To represent a logic function (truth table) on a Karnaugh map, we simply copy 1s and 0s
from the truth table or equivalent to the corresponding cells of the map following figures
(a) and (b) show the truth table and Karnaugh map for a logic function F = 6X Y Z (1, 2, 5, 7).

X Y Z F
0 0 0 0 XY X
0 0 1 1 Z 00 01 11 10
0 1 0 1
0 1 1 0 0 00 2
1
6
0
4
0
1 0 0 0
1 0 1 1 1 1 3 7 5 Z
1 0 1 1
1 1 0 0
1 1 1 1 (a) Y (b)

F = 6X,Y,Z(1,2,5,7): (a) truth table (b) Karnaugh map

On the other hand, if a K-map is given we can make the truth table corresponding to this
by following the reverse process. That is, the output F is logical 1 corresponding to the
decimal numbers/minterms represented by cells with entries 1. In all other rows, the
output F is logical 0.
Note: From now on, we’ll reduce the clutter in maps by copying only the 1s or the 0s, not
both.

Representation of Standard SOP Form on K-map

A logical equation in standard SOP form can be represented on a K-map by simply
entering 1’s in the cells of the K-map corresponding to each minterm present in the
equation.
Example 1 :
Represent following equation on K-map.
F = ABC  ABC  ABC  ABC …(3)

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Solution:
The given function is F = 6A,B,C(1,2,4,7). Thus, AB
corresponding to each minterm in the equation, 00 01 11 10
C
there is a cell in the K-map and a 1 is entered in 0 0 2 6 4
each one of these cells. The K-map will be as 0 1 0 1
shown in following figure (1). Similarly, from the 1 1 3 7 5
K-map, we can write the corresponding logical 1 0 1 0
equation in standard SOP form by ORing the
minterms corresponding to each 1 entry in the Fig.: 1 K-map for example 1
K-map.

Example 2 :
Write the logical equation in the standard SOP form for the K-map of following figure (2).

AB
00 01 11 10
CD
0 4 12 8
00
1 1
1 5 13 9
01
1 1
3 7 15 11
11
1 1
2 6 14 10
10 1
Fig.2: K-map of example 2

Solution :
F = ¦m(0,5,7,9,12,14,15)
= ABCD  ABCD  ABCD  ABCD ABCD ABCD ABCD

Representation of Standard POS form on K-Map

Logical equation in standard POS form can be represented on K-map by entering 0’s in
the cells of K-map corresponding to each maxterm present in the equation.

Example 1 :

Represent equation (4) on K-map.

F = (A  B  C) (A  B  C) (A  B  C) (A  B  C) …(4)

Solution :
The above function F = –(A,B,C)(0,3,5,6). Thus, corresponding to each maxterm in the
equation, there is a cell in the K-map and a 0 is entered in each one of these cells. The
K-map will be same as shown in above figure (1). From a given K-map, we can write the
logical equation in the standard POS form by ANDing the maxterms corresponding to
each 0 entry in the K-map.

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 Notes on Boolean Algebra

Example 2 :
Write the logical equation in the standard POS form for the K-map of shown in above
figure (2).

Solution:
Y = 3 M (1, 2, 3, 4, 6, 8, 10, 11, 13)
= (A  B  C  D) (A  B  C  D) (A  B  C  D)
(A  B  C  D) (A  B  C  D) (A  B  C  D)
(A  B  C  D) (A  B  C  D) (A  B  C  D)

Simplification of Logical Functions Using K-Map

Simplification of logical functions with K-map is based on the principle of combining terms
in adjacent cells. Two cells are said to be adjacent if they differ in only one variable. In
adjacent cells one of the literals is same, whereas the other literal appears in
uncomplemented form in one and in the complemented form in the other cell.

From this it becomes clear that if the Gray code is used for the identification of cells in K-
map, physically adjacent (horizontal and vertical but not diagonal) cells differ in only one
variable. Also, the left-most cells are adjacent to their corresponding right-most cells and
similarly the top cells are adjacent to their corresponding bottom cells. The simplification
of logical function is achieved by grouping adjacent 1cs or 0cs in groups of 2i, where i = 1,
2, …n and n is the number of variables.

x If a circle covers only areas of the map where the variable is 0, then the variable is
complemented in the product term.
x If a circle covers only areas of the map where the variable is 1, then the variable is
uncomplemented in the product term.
x If a circle covers both areas of the map where the variable is 0 and areas where it is
1, then the variable does not appear in the product term.

Different Grouping of Kmap

a) Grouping of two adjacent ones

x On 3  variables Kmap AB AB AB AB
00 01 11 10
C0 1 1 1 1

C 1 1 1 1 1

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x On 4 variables Kmap AB AB AB AB

CD 1 1 1

CD 1 1

CD

CD 1 1

b) Grouping of four adjacent ones

x On 3 variables Kmap x On 4 variables Kmap

AB
AB 00 01 11 10
CD
C 00 01 11 10
00 1 1 1 1
0 1 1 1 1
01 1
1 1 1 1
11 1 1 1
10 1 1 1 1

c) Group of 8 adjacent ones

x On 3 variable Kmap x On 4 variable Kmap

AB
00 01 11 10
AB CD
C 00 01 11 10
00 1 1 1 1
0 1 1 1 1
01 1 1 1 1
1 1 1 1 1
11 1 1 1

10 1 1 1

Note: For POS form, same grouping mechanism is followed, in which 0’s are grouped
instead of 1cs.

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 Notes on Boolean Algebra

Minimization of SOP Form

For minimizing a given expression in SOP form or for a given truth table, we have to
prepare the K-map first and then look for combinations of ones on the K-map. The
following algorithm can be used which will definitely lead to minimized expression:

1. Identify the ones which can not be combined with any other ones and encircle them.
These are essential prime implicants.
2. Identify group of eight adjacent ones, encircle such groups of ones.
3. Identify group of four adjacent ones, encircle such groups of ones.
4. Identify groups of two adjacent ones, encircle such groups of ones.
5. After identifying the essential groups of 2, 4, and 8 ones, if there still remain some 1s
which have not been encircled then these are to be combined with each other or with
other already encircled 1s. Of course, however, we should combine the left-over ones
in largest possible groups and in as few groupings as possible.
Example 1 :
Minimize the four-variable logic function using K-map.
f (A, B, C, D) = 6m (0, 1, 2, 3, 5, 7, 8, 9, 11, 14)
Solution :
The K-map of above function is shown in figure below.

AB
00 01 11 10
CD
1
00 0 4 8
1 BC
1
1 5 1 1 9 BD
01 1
1
3 7 1 1
11 1 1 1
2 6 1 1
10 1 1 ABCD

AB AD
K-map for given function
Therefore, the minimized equation is
f (A, B, C, D) = ABCD  BC  BD  AD  AB

Minimization of POS Form

For minimizing a given expression in POS form or for a given truth table we write zeros in
the cells corresponding to maxterms for 0 outputs. The K-map is simplified by following
the same procedure as used for SOP form, except ones are replaced by zeros. In this,
groups of zeros are formed rather than groups of ones.

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Example:
Minimize following function in POS form
(i) F ¦(X, Y, Z) m(0, 1, 4, 5, 6) in POS form
(ii) F ¦(A, B, C, D) m(0, 1, 2, 3, 5, 7, 8, 9, 11, 14) in POS form
Solution :
(i) As we know that for POS form function must be in maxterm form.
? F = ¦ (X, Y, Z) m(0, 1, 4, 5, 6) –(X, Y, Z) M(2, 3, 7)
? Corresponding K-map is

(X  Y)
XY 0 0 0 1 1 1 1 0
Z
0 0

1 0 0

(Y  Z)

? F = (X  Y) (Y  Z)
which is minimal POS equation

(ii) Similarly
? F = ¦(A, B, C, D) m(0, 1, 2, 3, 5, 7, 8, 9, 11, 14) –(A, B, C, D) M(4,6, 10, 12, 13, 15)
? Corresponding K-map is

AB 0 0 0 1 1 1 1 0
CD
00 0 0 (A  B  C)
01 0

(A  B  D) 11 0 (A  B  D)

10 0 0 (A  B  C  D)

?F= (A  B  C) ˜ (A  B  D) (A  B  D) ˜ (A  B  C  D)

which is minimal POS equation.

Note: Thus K-Map definitely simplifies the process of function minimization

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 Notes on Boolean Algebra

Minimization of logic function not specified in minterm/maxterm

If logic function is not specified in minterm / maxterm we cannot directly use K-map to
simply it. There a two methods to handle such situation. (We will explain the method
using examples)
Example 1:
Method 1:
Consider logic function
F(A,B,C,D) ABCD  ABCD  ABC  ABD  AC  ABC  B
express this in standard SOP form and minimize it.

Solution:
this is a 4-variable function, each term must have 4 literals (either complemented or
uncomplemeted form) so as to consider as a standard SOP form.
Here we use following theorem.
X˜1=X
X ˜ (Y + y ) = X … [as Y + Y = 1]
Thus, the missing term are added in the form Y  Y
? F(A,B,C,D) = ABCD  ABCD  ABC(D  D)  AB(C  C)D  A(B  B)C(D  D)
ABC(D  D)  (A  A)B(C  C)(D  D)

= ABCD  ABCD  ABCD  ABCD  ABCD  ABCD

ABCD  ABCD  ABCD  ABCD  ABCD

= ¦(A,B,C,D) m(0, 1, 2, 3, 7, 8, 9, 10, 11, 12, 13)

… [in required standard SOP form]
Now we can minimize this using K-map

AB 0 0 0 1 1 1 1 0
CD
00 1 1 1

01 1 1 1 AC

11 1 1 1

10 1 1

A CD B
? minimal SOP form is
F = B  AC  ACD

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Method 2 :
Follow the following procedure
1. Enter ones for minterms and zeros for maxterms
2. Enter a pair of ones/zeros for each of the terms with one variable less than the total
number of variables.
3. Enter four adjacent ones/zeros for terms with two variables less than the total number
of variables.
4. Repeat for other terms in the similar way.

Once the K-map is prepared the minimization procedure is same as discussed earlier.
? Term A C can be represented as AB 0 0 0 1 1 1 1 0
CD
A Ÿ 1 (we see column 3 and 4)
C Ÿ 0 (we see row 1 and 2) 00 1 1
AC
So intersection of this is the required region 0 1 1 1
11

10

Similarly we can represent other terms, in order to prepare entire K-map. Once this is
done simplification process is same as discussed before

Example 2 :
Express following logic function in standard POS form and then minimize it
F(A,B,C,D) (A  B  C  D) ˜ (A  C  D) ˜ (A  B  C  D) ˜ (B  C) ˜ (B  C) ˜ (A  B) ˜ (B  D)
Solution :
Method 1 :
Here we use
X+0=X
X + Y˜Y X … [as Y ˜ Y 0]
and (X + Y) ˜ (X + Y ) = X

… [Distributive property of addition i.e. logical addition distributes one logical multiplication]
where Y Ÿ missing term
? Given function becomes
? F(A,B,C,D) = (A  B  C  D) ˜ (A  C  D  BB) ˜ (A  B  C  D) ˜
(AA  B  C  DD) ˜ (AA  B  C  DD) ˜ (A  B  CC  DD) ˜ (A A  B  CC  D)
= (A  B  C  D) ˜ (A  B  C  D) ˜ (A  B  C  D) ˜ (A  B  C  D) ˜
(A  B  C  D) ˜ (A  B  C  D) ˜ (A  B  C  D) ˜ (A  B  C  D) ˜
(A  B  C  D) ˜ (A  B  C  D) ˜ (A  B  C  D)
= –(A,B,C,D)M(3,4,5,6,7,9,11,12,13,14,15) … [required standard POS form]

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 Notes on Boolean Algebra

? K-map for maxterm is

AB 0 0 0 1 1 1 1 0
CD
00 0 0

01 0 0 0
(A  D)
11 0 0 0 0
(C  D)
10 0 0

? minimal POS form

B
F (A,B,C,D) B ˜ (A  D) ˜ (C  D)

Method 2 :
It is similar to method 2, used for SOP form. Here only difference is that we use zeros in
place of ones, for instance the term (A  B) in above function can be represented as
AB 0 0 0 1 1 1 1 0
(for maxterm form) CD
here 00 0
A Ÿ 0 (we see column 1 and 2
B Ÿ 1 (we see column 2 and 3) 01 0
? intersection of this, it the desired region.
11 0

10 0

(A  B)

Similarly we represent other terms, in order to get final K-map. Once K-map is obtained
minimization process is straight forward obtained by grouping zeros.
Diagonal and Offset Grouping

If we have to construct the equation using EXOR or EXNOR gates then use the
Diagonal and Offset grouping.
Diagonal Grouping

AC
AB
00 01 11 10
C
0 1 1

1 1
1

diagonal AC

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From above figure F = AC + AC = A C

Offset Grouping

(i) (ii) AB
AB
C 00 01 11 10
C 00 01 11 10
0
0 1 1 AB
AB 1 1 1
1 1 1
offset
offset ABC
ABC

? F = AB + AB ? F = ABC  ABC
= A B = C (AB  AB)
= C(A B)
Note: Avoid the mixing of grouping (i.e. horizontal, vertical with diagonal and offset).

DON'T-CARE INPUT COMBINATIONS

Sometimes the specification of a combinational circuit is such that its output doesn’t
matter for certain input combinations, called don’t cares. This may be true because the
outputs really don’t matter when these input combinations occur, or because these input
combinations never occur in normal operation.

Consider for example, suppose we wanted to build a prime-number detector whose 4-bit
input
B = B3B2B1B0 is always a BCD digit; then minterms 1015 should never occur.

A prime BCD-digit detector function may therefore be written as follows:

F = 6B3 ,B2 ,B1,B0 (1,2,3,5,7)  d(10,11,12,13,14,15)
The d(…) list specifies the don’t-care input combinations for the function, also known as
the d-set.

The procedure for circling sets of 1s is as follows:

x Allow d’s to be included when circling sets of 1s, to make the sets as large as
possible.
x Do not circle any sets that contain only d’s.
x Just a reminder: As usual, do not circle any 0s.
Example:
Minimize given logic function, a prime number indicator, with 4-bit BCD input.

? F= ¦(B ,B ,B ,B ) m(1,2,3,5,7)  d(10, 11, 12, 13, 14, 15)

3 2 1 0

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 Notes on Boolean Algebra

? K-map becomes
B3B2
B1B0 0 0 0 1 1 1 1 0
00 d don't group cells
don't consider since containing all dcs
01 1 1 d
two 1cs are already B3B0
considered 11 1 1 d d

10 1 d d

…[d Ÿ don’t care]

B2B1
? F = B2B1  B2B0

LMR (LAST MINUTE REVISION)

x Conversion methods for common radices
Conversion Method Example
Binary to
Octal Substitution 101110110012 = 10 111 011 0012 = 27318
Hexadecimal Substitution 101110110012 = 101 1101 10012 = 5D916
Decimal Summation 101110110012 = 1 ˜ 1024 + 0 ˜ 512 + 1 ˜ 256 + 1 ˜ 128 + 1 ˜ 64
+ 0 ˜ 32 + 1 ˜ 16 + 1 ˜ 8 + 0 ˜ 4 + 0 ˜ 2 + 1 ˜ 1 = 149710

Octal to
Binary Substitution 12348 = 001 010 011 1002
Hexadecimal Substitution 12348 = 001 010 011 1002 = 0010 1001 11002 = 29C16
Decimal Summation 12348 = 1 ˜ 512 + 2 ˜ 64 + 3˜ 8 + 4 ˜ 1 = 66810

Hexadecimal
to
Binary Substitution C0DE16 = 1100 0000 1101 11102
Octal Substitution C0DE16 = 1100 0000 1101 11102 = 1 100 000 011 011 1102 = 1403368
Decimal Summation C0DE16 = 12 ˜ 4096 + 0 ˜ 256 + 13 ˜ 16 + 14 ˜ 1 = 4937410

Decimal to
Binary Division 10810 y 2 = 54 remainder 0 (LSB)
y 2 = 27 remainder 0
y 2 = 13 remainder 1
y 2 = 6 remainder 1
y 2 = 3 remainder 0
y 2 = 1 remainder 1
y 2 = 0 remainder 1 (MSB)
10810 = 11011002
Octal Division 10810 y 8 = 13 remainder 4 (LSB)
y 8 = 1 remainder 5
y 8 = 0 remainder 1 (MSB)
10810 = 1548
Hexadecimal Division 10810 y 16 = 6 remainder 12 (LSB)
y 16 = 0 remainder 6 (MSB)
10810 = 6C16

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x Summary of Addition and Subtraction Rules for binary Numbers

Number System Addition Rules Negation Rules Subtraction Rules

Unsigned Add the numbers. Not applicable Subtract the
Result is out of range subtrahend
if a carry out of the from the minuend.
MSB occurs. Result is out of range
if a borrow out of the
MSB occurs.
Signed (same sign) Add the Change the Change the sign bit
magnitude magnitudes; overflow number’s sign bit. of the subtrahend
occurs if a carry out of and proceed as in
MSB occurs; result has addition.
the same sign.
(opposite sign) Subtract
the smaller magnitude
from the larger; overflow
is impossible; result has
the sign of the larger.
Two’s Add, ignoring any Complement all Complement all bits
complement carry out of the MSB. bits of the number; of the subtrahend
Overflow occurs if the add 1 to the result. and add to the
carries into and out of minuend with an
MSB are different. initial carry of 1.
Ones’ Add; if there is a carry Complement all Complement all bits
complement out of the MSB, and 1 bits of the number. of the subtrahend
to the result. Overflow and proceed as in
occurs if carries into addition.
and out of MSB are
different.

x 8–4–2–1 (BCD) Code

Decimal digits 0 through 9 are represented by their binary equivalents using four bits.
x Excess-3 Code
The code can be derived from the BCD by adding 3 to each coded number.
x Boolean algebra uses two binary operations ‘+’ (plus) and ‘.’(dot) and one uniary
operation ‘/’(complement) variable.
x Variable: A variable is a symbol used to represent a logical quantity, can have a
value 1 or 0.
Complement:It is the inverse of a variable.
Literal :It is a variable or the complement of a variable
x There are three types of basic logic Gates : AND, OR, NOT.
x The NOT gate (inverter) performs the operation called inversion or complementation.
x In inverter, when the input is LOW, the output is HIGH; when the input is HIGH, the
output is LOW. The bubble always indicate inversion in digital circuit.
x In AND gate, the output is HIGH only if both the inputs are HIGH.

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 Notes on Boolean Algebra

x An OR gate produces a HIGH on the output when any of the inputs is HIGH.
x Boolean addition is the same as the OR function.
x Boolean addition differs from binary addition in the case where two 1’s are added.
There is no carry in Boolean addition.
x When solving Boolean expressions, the precedence in descending order is
a. Parenthesis b. NOT c. AND d. OR
x DeMorgan’s Theorem : It states that the complement of a function is obtained by
interchanging AND and OR operators and complementing each literal.
x DeMorganization : “just break the line, change the sign”.
x The NAND and NOR gates are called universal gates as any basic gate (AND, OR
and NOT) can be implemented using these gates.
x NAND gate is equivalent to bubbled OR gate.
x The output of NAND gate is HIGH, when at least one input to the NAND gate is LOW.
x NOR gate is equivalent to bubbled AND gate.
x The output of NOR gate is HIGH only when all the inputs are LOW.
x The NAND and NOR functions are commutative but not associative.
x Converting circuits to Universal Logic :
a) Draw the circuit in AND/OR/invert logic
b) If NAND realization is chosen, add a circle to the outputs of each AND gate on
the logic diagram, and add circles to the inputs of all OR gates.
c) In NOR realization, add circle to the output of gates and add circle to the inputs
of AND gates.
d) Add or subtract an inverter on each line that received a circle in step 2 or 3.
x EXOR is mathematically represented as
X AB  AB
x In EXOR, for even inputs output is LOW and for odd inputs output is HIGH.
x It is also noted that EXOR is inequality comparator.
x EXNOR is mathematically represented as
X AB  AB
x EXNOR is called as equality comparator as output of EXNOR is logic 1 only when
the even no. of inputs are equal.
n
x Kmap is used to determine minimal expression. Each n variable map consists of 2
cells or squares.
x Minterm : ‘Minterm’ is a product term which has each of all the variables as factors in
either complemented or uncomplemented form.
x Maxterm : ‘Maxterm’ is a sum term which has each of all the variables as factors in
either complemented or uncomplemented form.
x Canonical form : The switching function expressed as the sum of all the minterms is
called the canonical Sum Of Products (SOP) or disjunctive normal expression.
x The switching function expressed as a produce of all the Maxterms is called the
canonical Product Of Sum (POS) form.
x POS form is found out by complementing minterm equation.
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Vidyalankar : GATE – EC

ASSIGNMENT  1
Duration : 45 Min. Maximum Marks : 30

Q1 to Q 6 carry one mark each

1. (1101101 . 1011)2 = ( )10

(A) 109.6875 (B) 109.7865
(C) 109.6880 (D) 119.08

2. The equivalent in decimal for the excess3 code 843 is

(A) 510 (B) 840
(C) 846 (D) None of these

3. Find odd man out

i) AA = A ii) 1+A=1+ A
iii) A + BC = (A + B) (A + C) iv) A  AC A  C
(A) (ii) and (iv) (B) (ii), (iii) and (iv)
(C) (i) and (iv) (D) None of the above

4. Inhibitor is also known as

(A) ANDNOT (B) ORNOT
(C) Strobe (D) None of these

5. Subtraction of the given signed number is

00001100  11110111 (assume number are in 2cs complement form)
(A) 00010101 (B) 11101010
(C) 00001011 (D) 00110101

6. Determine the decimal values of the binary numbers in 2’s complement

Number is : 10101010
(A) + 86 (B)  86
(C) + 98 (D) 98

Q 7 to Q 18 carry two marks each

7. Given Boolean equation as

 C,D)
y (A,B, 
y 30(0,1  ,2,3,6,7,8,9,11
 ,15)


The minimized POS form of above equation is

(A) yPOS (A  C)(C  D)(B  C)
(B) yPOS (A  D)(D  C)(B  D)
(C) yPOS (A  D)(C  D)(B  D)
(D) yPOS (A  C)(C  D)(B  C)

GATE/EC/DC/SLP/Module_3/Ch.1_Assign/Pg.50
 Assignment on Boolean Algebra

8. The number of NOR gates required to implement NAND gate is

(A) 3 (B) 4
(C) 5 (D) 2

9. To represent reduced expression of the following POS form, the no. of NOR
gates required are
y = 3 M(0, 1, 2, 3, 6, 7, 8, 9, 11, 15)
(A) 6 (B) 7
(C) 8 (D) 9

10. The no. of required gates to represent XOR using NAND only are
(A) 3 (B) 4
(C) 5 (D) 6
11. The decimal number 39 is expressed in 2’s complement form as
(A) 00100111 (B) 11011000
(C) 11011001 (D) 11010001

12. The switching diagram depicts

Lamp

(A) OR gate (B) NOR gate

(C) AND gate (D) NAND gate

13. (A  B) ˜ (A  B)
(A) A B (B) A B
(C) A (D) B

14. For the switching circuit given below, taking open as 0 and close as 1, the
expression for the circuit is

A C E G
y y
B D F H

(A) y (A  B)(CE  DF)(G  H)

(B) y (A  B)(C  E  D  F)(G  H)
(C) y AB  CD  EF  GH
(D) None of these

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Vidyalankar : GATE – EC

15. The given expression can be reduced to

y AB  ABC  A(B  AB)
(A) 1 (B) 0
(C) A (D) AB

16. To realize minimized function of K  map shown below, no. of gates required are
AB
CD
1 1

1 1

1 1
1 1

(A) 1 (B) 3
(C) 4 (D) None of these

17. The following diagram represents which type of gate?

Vcc  5V

Rc2 Rc3

RB1
Q1 Q3

RB2
Q2

(A) AND (B) NAND

(C) OR (D) NOR

18. The minimum number of NOR gates to implement the function f = AB + AB are
(A) 0 (B) 2
(C) 4 (D) 6

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GATE/EC/DC/SLP/Module_3/Ch.1_Assign/Pg.52
 Test Paper on Boolean Algebra

TEST PAPER  1
Duration : 30 Min. Maximum Marks : 25

Q1 to Q5 carry one mark each

1. If one of the input to an ______ gate is inverted then it becomes an INHIBITOR.

(A) AND (B) NAND
(C) NOR (D) XOR

2. [(A  AB)(A  AB)][(CD  CD)  (C † D)]

(A) B (B) A
(C) 0 (D) 1

3. Which one of the following is equivalent to ORAND realization?

(A) NANDNOR realization (B) NANDNAND realization
(C) NORNOR realization (D) None of these

4. Which of the following gates is a series circuit gate ?

(A) AND gate (B) OR gate
(C) XOR gate (D) XNOR gate

5. The maxterm designator of the term, with D as MSB

A  B  C  D is
(A) 10 (B) 05
(C) 13 (D) None of these

Q6 to Q13 carry two mark each

6. The Boolean expression for shaded area in the Venn diagram is

x
y

(A) (x  y)  x y z (B) x  z  (x  y  z)
(C) (x  z)  (x  y  z) (D) (x  y)  (x  y  z)

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Vidyalankar : GATE – EC

7. The floating point binary number is given as

S E M
1 10010001 10001110001000000000000
Find the binary value of given number.
(A) 1100011000110000000 (B) 1100011000110000000
(C) 110001110001000000 (D) 1100011100010000000

8. For the following Kmap, POS form equation is

AB
00 01 11 10
CD
00 1 0 0 1

01 0 1 1 0

11 0 1 1 0

10 1 0 0 1

(A) –M(1, 3, 4, 6, 9, 11, 12, 14) (B) –M(0, 2, 5, 7, 8, 10, 11, 15)
(C) –M(1, 3, 4, 7, 8, 10, 11, 15) (D) –M(0, 2, 4, 7, 9, 11, 12, 14)

9. How many minimum NAND gates are required to implement following Boolean
function ?
y (A  B) ˜ (A  C)

(A) 5 (B) 6
(C) 7 (D) 8

10. (NOR) ˜ (XOR) ˜ (NAND)

(A) NOR (B) NAND
(C) XOR (D) XNOR
11. Simplify this expression AB + (B + C)A + B(B + C)
(A) B + AC (B) A + BC
(C) A+B (D) B+C

12. The singleprecision floating point binary number of the binary no.
111111011100000 is
(A) 0 10001101 11111011100000000000000
(B) 1 10001001 11111101110000000000000
(C) 0 10110101 11111011100100000000000
(D) 1 11001010 11011001110010000000000

13. A xyz  xyz  xyz+xyz To implement the above Boolean expression,

minimum no. of gates required are
(A) 1 (B) 2
(C) 3 (D) 4

GATE/EC/DC/SLP/Module_3/Ch.1_Test/Pg.54
 Test Paper on Boolean Algebra

Q14(a) & (b) Carry two marks each

Linked Answer Questions

14(a). The 10cs complement of a no. is (47480)10 Find the no. in decimal equivalent.
(A) 52520 (B) 37480
(C) 47480 (D) 63620

14(b). The octal equivalent of the answer of part a is

(A) (146450)8 (B) (131450)8
(C) (134570)8 (D) None of these

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GATE/EC/DC/SLP/Module_3/Ch.1_Test/Pg.55