Electronics & Communication Engineering

DIGITAL ELECTRONICS

DIGITAL
ELECTRONICS
P.N.Sankar M.E.

GEOMETRIC’S
SMART CLASS
N.POONGODI M.E. P.N.Sankar M.E.
Scan me
V.SUNDARA RAJA PANDIAN M.E.

REGULATION - 2023
III SEMESTER R2023

DIGITAL
ELECTRONICS
Electronics and Communication Engineering

Authors

N.POONGODI M.E.
K.KARTHIKEYAN M.E.
V.SUNDARA RAJA PANDIAN M.E.
DIGITAL ELECTRONICS

Author: P.N.SANKAR M.E.

First edition : 2019

Second edition : 2021
Third edition : 2024

2024EC

ISBN: 978-93-92395-44-4
ISBN: 978-93-87810-50-1

Rs. 220/-

Printed by
Geometric Publications
Virudhunagar
 Syllabus

DIGITAL ELECTRONICS

UNIT I - NUMBER SYSTEM AND BOOLEAN ALGEBRA:

Introduction to number system: Decimal, Binary, Octal and
Hexa Decimal – conversion between the above number
systems – 1’s and 2’s Complement representation – Binary
addition and Binary Subtraction – BCD, Gray code, ASCII:
Definition.
Introduction to Boolean Algebra: Basic Boolean laws –
Demorgan’s Theorems – Definition and proof using truth table
method – Simplification of Boolean equations using Boolean
laws – Simple problems only using two and three variables –
Implementation of logic circuits for Boolean equations –
SOP and POS definition – Karnaugh
Map: Simplification of Boolean equations using K-Map –
Simple problems (Maximum 4 variables in SOP form)

UNIT II - LOGIC GATES & ARITHMETIC CIRCUITS:

Introduction to Logic Gates: Symbol, Definition, Logic
Equation, and truth table for AND, OR, NOT, NAND, NOR,
XOR and XNOR gates – Universal Gates – NAND and NOR –
Realization of logic gates using Universal gates – Tristate
Buffer and Bi-directional Buffer – Truth table and operation.
Logic families: Types of logic families–Fan-in, Fan-out,
Propagation delay, Noise Margin and Power dissipation
(Definition only).
Arithmetic Circuits: Truth table, Logic equations, Logic
Digital Electronics S-1
 Syllabus
diagram and working principle of Half Adder, Full Adder, Half
Subtractor, Full Subtractor and four-bit parallel adder –
Working Principle of single bit Digital Comparator.

UNIT III - Combinational Logic Circuits:

Multiplexor: Symbol, Logic equation, logic diagram and
operation of 4to 1 MUX – Realization of 8 to 1 MUX using two
4 to 1 MUX.
Demultiplexor: Symbol, Logic equation, logic diagram and
operationof 1 to 4DEMUX.
Decoder: Symbol, Logic equation, logic diagram and
operation of 2 to 4 Decoder and BCD to Seven Segment
Decoder.
Encoder: Symbol, Logic equation, logic diagram and
operation of Octalto Binary Encoder.
Parity Generator & Checker: Parity bit: Types of Parity -
BasicConcepts of Parity Generator and Checker.

UNIT IV - SEQUENTIAL LOGIC CIRCUITS:

Introduction to Sequential logic circuits – Basic Latch
circuits using NAND and NOR gates – Triggering: Types of
Triggering (level and edge) Definitions only – Clocked SR
Flipflop using NAND gates: Logic diagram, Truth table and
operation – Preset and Clear (Need and Concept only) –
Logic diagram, Truth table and Operation of JK, D,T flip-flop
and JKMS Flip-flop – Applications of flip-flops.
Counters: Definition – Logic diagram, truth table and

Digital Electronics S-2

 Syllabus
operation of 4 - bit Asynchronous counter, 4-bit
Synchronous counter, 3bit asynchronous up-down counter
and decade counter: Applications of counters – Difference
between Synchronous and Asynchronous counters.

UNIT V - STORAGE DEVICES AND LOGIC FAMILIES:

Shift Registers: Definition – Logic diagram and Operation of
Serial in Serial out, Parallel in Serial out, Serial in Parallel out
and Parallel in Parallel out – Applications of registers.
Introduction to memory: ROM – Organization of ROM and
types of ROM (PROM, EPROM, UVEPROM and Flash)
Simple description only – RAM: Organization of RAM, Simple
structure of SRAM and DRAMs – Comparison between RAM
and ROM – Expansion of Memory (4K to 8K) – Principles of
Cache memory and associative memory (Basic Concepts
only)

Digital Electronics S-3

 Syllabus
Assessment Methodology:

End
Continuous Assessment (40 marks)
Semester
Examination
CA1 CA2 CA3 CA4 (60 marks)
Written Written
Quiz / Model Written
Test Test (Unit
Mode (Unit I & II) III & IV) MCQ Examination Examination

Duration 2 hours 2 hours 1 hour 3 hours 3 hours

Exam
60 60 40 100 100
Marks

Converted
20 20 10 10 60
to

Marks 40 60

Note:
• CA1 and CA2 Assessment test should be conducted.
Best of one will be considered for the internal
assessment of 20 Marks.
• CA3 Online quiz examination (MCQ) should be
conducted covering the complete syllabus. The marks
should be converted to 10 marks for the internal
assessment
• CA4 Model examination should be conducted as per
the end semester question pattern. The marks should
be converted to 10 marks for the internal assessment.

Digital Electronics S-4

Unit I Number system and Boolean algebra

UNIT I- NUMBER SYSTEM AND BOOLEAN ALGEBRA

1.1 NUMBER SYSTEMS AND BOOLEAN ALGEBRA

1.1.1 Number systems
Any number system is an ordered set of symbols known as
digits with two parts – an integer part and a fractional part, separated
by a radix point (.).
There are different number systems available. To name a few:
1. Decimal number system
2. Binary number system
3. Octal number system
4. Hexadecimal number system

Decimal Number Systems

• Has base 10 : ( ) 10
• Each number [called as digits] takes 10 possible values :
0,1,2,3,4,5,6,7,8 or 9
• Each digit represents a multiple of a power of 10 which are
implied by the position of the digits.

Digital Electronics I-1

Unit I Number system and Boolean algebra

• The place value of each position is given below:

103 102 101 100 . 10-1 10-2 10-3

1000 100 10 1 . 0.1 0.01 0.001
Example:
3436 .67 =
3 x 1000 4 x 100 3 x 10 6x1 . 0.1 x 6 0.01 x 7

Binary number system

• Has base 2 : ( )2
• Each number [called as bits] takes only 2 values : 0 or 1
• Each bit represents a multiple of a power of 2 which are
implied by the position of the digits.
• The place value of each position is given below:

23 22 21 20 . 2-1 2-3
2-2
8 4 2 1 . ½ = 0.5 ¼ = 0.25 1/8 = 0.125

Example:
1010 .01 =
1x8 0x4 1x2 0x1 . 0 x 0.5 1 x 0.25
8 0 2 0 . 0 .25
Binary 1010 .01 = Decimal 10.25

The left most bit is called the most

significant bit[MSB] as it carries the
maximum value and the right most bit is
called the least significant bit [LSB] as it carries the minimum
value.
In the binary number system, a group of four bits is known
as a nibble and a group of eight bits is known as byte.

Digital Electronics I-2

Unit I Number system and Boolean algebra

Octal number system

• Has base 8 : ( )10
• Each number [called as bits] takes only 8 values :
0,1,2,3,4,5,6 or 7
• Each bit represents a multiple of a power of 8 which are
implied by the position of the digits.
• The place value of each position is given below:
83 82 81 80 . 8-1 8-2
512 64 8 1 . 1/8 1/16

Example:
567 .41 =
5 x 64 6x8 7x1 . 4 x 1/8 1 x 1/16
320 48 7 . 0.5 0.0625
Octal 567 .41 = Decimal 375.5625
Hexadecimal number system
• Has base 16 : ( )16
• Uses both alphabets and numerals
• Each number [called as bits] takes only 15 values:
0,1,2,3,4,5,6,7,8,9,A,B,C,D,E or F
• Each bit represents a multiple of a power of 16 which are
implied by the position of the digits.
• The place value of each position is given below:

163 162 161 160 . 16-1 16-2

4096 256 16 1 . 1/16 1/32

Example:
A2E .12 =
A x 256 2 x 16 Ex1 . 1 x 1/16 2 x 1/32
2560 32 14 . 0.0625 0.0625
Hexa A2E .12 = Decimal 2606.125

Digital Electronics I-3

Unit I Number system and Boolean algebra

2. Write the Quotient and remainder separately as shown

below
3. Continue the division till the quotient becomes 0
4. The binary equivalent is obtained from the remainders taken
is reverse order i.e bottom to top

25 24 23 22 21 20
1 0 1 0 0 1
( 41 )10 = ( 101001 )2

Checking: Converting binary to decimal

(101001)2 = 1 x 25 + 0 x 24 + 1 x 23 + 0 x 22 + 0x 21 +1 x 20
= 32 + 8 + 1
= (41)10
1B) Converting a decimal fraction to binary
1. Multiply the fraction with 2 to give a new integer and a new
fraction
2. The new fraction is again multiplied by 2 to give another
new integer and a new fraction
3. Continue the process until fraction becomes 0 or until the
number have sufficient memory
4. Note the coefficients from top to bottom
Example convert (0.6875)10 to binary

integer fraction coefficient

0.6875 x2= 1 + 0.3750 a -1 = 1
0.3750 x2= 0 + 0.7500 a -2 = 0
0.7500 x2= 1 + 0.5000 a -3 = 1
0.5000 x2= 1 + 0.0000 a -4 = 1
(0.6875)10 = (0. a -1a -2a -3 a -4)2 = (0. 1011)2

Digital Electronics I-5

Unit I Number system and Boolean algebra

Checking:
(0.1011)2 = 1 x 2-1 + 0 x 2-2 + 1 x 2-3 + 1 x 2-4
= 0.5 + 0.125 + 0.0625
= (0.6875)10
2A) Converting a decimal number (integer part) to Octal:
1. Divide the integer part of the given decimal number by 8
2. Write the Quotient and remainder separately as shown
3. Continue the division till the quotient becomes 0
4. The octal equivalent is obtained from the remainders taken
is reverse order i.e. bottom to top

83 82 81 80
- 2 3 1
(153)10 = (231)8

Checking: Converting octal to decimal

(231)8 = 2 x 82 + 3x 81 +1 x 80 = 128 + 24 + 1 = (153)10
2B) Converting a decimal fraction to octal
1. Multiply the fraction with 8 to give a new integer and a new
fraction
2. The new fraction is again multiplied by 8 to give another
new integer and a new fraction
3. Continue the process until fraction becomes 0 or until the
number have sufficient memory
4. Note the coefficients from top to bottom
Example convert (0.513)10 to octal
integer fraction coefficient
0.513 x8= 4 + 0.104 a -1 = 4
0.104 x8= 0 + 0.832 a -2 = 0
0. 832 x8= 6 + 0.656 a -3 = 6
0.656 x8= 5 + 0.248 a -4 = 5

Digital Electronics I-6

Unit I Number system and Boolean algebra

(0.513)10 = (0. a -1a -2a -3 a -4)2 = ( 0. 4065)8  continue multiplication

to get more approximation

2C) Converting a binary to octal

• Each octal digit corresponds to three binary digits
• The conversion from binary to octal is easily accomplished
by partitioning the binary number into groups of three digits
each, starting from the binary point and proceeding to the
left and to the right
• The corresponding octal digit is then assigned to each
group.
• For example consider converting 110101.01011 to octal
binary 110 101 . 010 11
groups of 3 bits
octal equivalent 6 5 . 2 7

(110101.01011)2 = (65.27)8

2D) Converting an octal to binary

• It is just the reverse procedure
• Each octal digit is converted to its three-digit binary equivalent
• For example ( 456.23)8 =

Octal digit 4 5 6 . 2 3
binary 100 101 110 . 010 011
groups of 3 bits
(456.23)8 = (100 101 110 .010 011)2

3A) Converting a decimal number (integer part) to Hexadecimal:

1. Divide the integer part of the given decimal number by 16

Digital Electronics I-7

Unit I Number system and Boolean algebra

3. Neglect carry, therefore result is 0001

4. Add 1 to the result [0001 + 1 ] = 0010
5. Put a + sign
Therefore answer = + 0010 = 210
Problem 2
Subtract 1111[subtrahend] from 1101[minuend].
Note: It is decimal 13 – 15. Therefore answer should be decimal - 2
or binary – 0010. lets check
1. Find 1′s compliment of subtrahend 1111
it is 0000
2. Add this to minuend i.e. 0000 + 1101 =
0000
1101
1101
Therefore carry = 0 means answer is a negative number
3. Find 1′s compliment of the result, which is 0010
4. Put a - sign
Therefore answer = - 0010 = -210

SUBTRACTION USING 2′S COMPLIMENT

Consider subtraction of two numbers A – B. The following
steps are to be followed during subtraction using 2′s compliment
1. Find 2′’s compliment of subtrahend [B + 1]
2. Add this to the minuend { A + [B + 1 ]}
3. Check carry
c) if carry = 1
• Means answer is a positive number
• Neglect carry
• Note the result as a positive number [put a + sign]
d) if carry = 0

Digital Electronics I-12

Unit I Number system and Boolean algebra

• Means answer is a negative number

• Find 2′s compliment the result
• Note the result as a negative number [put a - sign]
Problem 3
Subtract 1101 from 1111 using 2′s complement
Note: It is decimal 15 – 13. Therefore answer should be decimal +2
or binary + 0010
1. Find 2′s compliment of subtrahend 1101
it is 0010 + 1 = 0011
2. Add this to minuend 0011 + 1111 =
0011
1111
10010
Therefore carry = 1 means answer is a positive number
3. Neglect carry, therefore result is 0010
4. Put a + sign
Therefore answer = + 0010 = 210
Problem 4
Subtract 1111[subtrahend] from 1101[minuend] using 2′s
complement
Note: It is decimal 13 – 15. Therefore answer should be decimal - 2
or binary – 0010. lets check
1. Find 2′s compliment of subtrahend 1111
it is 0000 + 1 = 0001
2. Add this to minuend 0001 + 1101 =
0001
11 0 1
1110
Therefore carry = 0 means answer is a negative number
3. Find 2′s compliment of the result :

Digital Electronics I-13

Unit I Number system and Boolean algebra

Therefore result is = 0001 +1 = 0010

4. Put a - sign
Therefore answer = - 0010 = -210

1.1.3 Binary Addition

Digital computers perform various arithmetic operations. The
most basic operation is the addition of two binary digits. The input
and output can have only 2values: 0 or 1. Accordingly:
0+0=0
0+1=1
1+0=1
1 + 1 = 10 2 sum = 0[LSB] and carry = 1 [MSB]
1 + 1 + 1 = 112 sum = 1 [LSB] and carry = 1 [MSB]

The logic circuit which performs this operation is called a

half-adder. The circuit which performs addition of three bits is a full-
adder.
When two numbers are added, the first number is called
Augend and the second number is called Addend

Problem
1. ADD 1010 + 1011 2. ADD 0111 + 1001

Carry 1 1 Carry 1 1 1 1
Augend 1 0 1 0 Augend 0 1 1 1
Addend 1 0 1 1 Addend 1 0 0 1
Sum 1 0 1 0 1 Sum 1 0 0 0 0
1.1.4 Binary subtraction
When two numbers are subtracted, the first number is called
minuend and the second number is called Subtrahend
The basic rules for subtraction are:
Digital Electronics I-14
Unit I Number system and Boolean algebra

0 -0 =0
1 -0 =1
1 -1 =0
0 -1 =1 difference = 1 and borrow =1
10 - 1 = 1 difference = 1 [as it is binary 2 - 1]
The logic circuit that performs subtraction of 1 bit is called a
half- subtractor.
Problem
1. Subtract 1011 - 0101 2. Subtract 1111 + 1001

Borrow 1 Borrow 1 1
minuend 1 0 1 1 minuend 1 1 0 1
Subtrahend 0 1 0 1 Subtrahend 0 1 1 1
Difference 0 1 1 0 Difference 0 1 1 0
1.1.5 BINARY CODES
Digital electronic circuits in computers and calculators use
mostly the binary code to represent numbers. Many other special
codes are used in digital electronics to represent numbers, letters,
and punctuation marks and control characters. These special codes
are generally called binary codes. Some of the special binary codes
are BCD code, Gray code, and Excess 3 code.
BCD code
BCD is an abbreviation for Binary-Coded Decimal. Here
decimal digits 0 through 9 are individually represented using their 4
bit binary equivalents.
For example, the decimal number 567 is expressed in BCD as:
Decimal number: 5 6 7
BCD number: 0101 0110 0111
Decimal 10 = Binary 1010 = BCD 0001 0000
As BCD numbers are decimal numbers, it is more preferred
than the binary representation although it occupies more space

Digital Electronics I-15

Unit I Number system and Boolean algebra

Gray Code
It is a special binary code used in optical encoders. In this
code, only one bit will change each time the decimal number is
incremented. It is also called mirror code.

Decimal Binary BCD digit Excess-3 Gray code

0 0000 0000 0011 0000
1 0001 0001 0100 0001
2 0010 0010 0101 0011
3 0011 0011 0110 0010
4 0100 0100 0111 0110
5 0101 0101 1000 0111
6 0110 0110 1001 0101
7 0111 0111 1010 0100
8 1000 1000 1011 1100
9 1001 1001 1100 1101
10 1010 0001 0000 1101 1111
11 1011 0001 0001 1110 1110
12 1100 0001 0010 1111 1010
13 1101 0001 0011 10000 1011
14 1110 0001 0100 10001 1001
15 1111 0001 0101 10010 1000

ASCII
• ASCII stands for American Standard Code for Information
Interchange.
• It is a seven bit code.
• The first three MSB bits represent whether a number letter or
character is coded.
• The last four bits represent the actual code of number letter or
character.
• Totally it contains 128 combinations of characters. 26
combinations represent letters in uppercase and another 26 for
representing lowercase letters. 10 combinations are used for
numerals.

Digital Electronics I-16

Unit I Number system and Boolean algebra

• The remaining combinations are used to represent functions

punctuation marks and various special characters.

Fig 2.6
• To represent the letter ‘A’, the code ‘100 0001’ is used. Similarly
to represent the letter ‘B’, the code ‘100 0010’ is used.
• In both cases the first 3 bits are same. But the remaining four
bits change according to a standard progressive value, i.e. it
varies from 0000 to 1111 respectively.
• Similarly the first three bits also follow a standard progression
from 000 to 111. Number ‘2’ is coded as 011 0010 and the letter
B is coded as 100 0010. The representation of ASCII code is
shown in the table.

Digital Electronics I-17

Unit I Number system and Boolean algebra

1.2 INTRODUCTION TO BOOLEAN ALGEBRA

Digital circuits perform the binary arithmetic operations with
binary digits 1 and 0. These operations are called logic functions or
logical operators. The algebra used to symbolically describe logic
functions is called Boolean algebra.
Boolean algebra is a form of mathematics developed by
English mathematician George Boole (1815–1864). Boole created a
system by which certain logical statements can be expressed in
mathematical terms. The variables are termed alphabetically as A,
B,C,….. and can have only 2 values – vice: 0 and 1.
Boolean algebra uses four symbols:
i) Equals sign =: refers to maths equal to
ii) Plus sign +: refers to binary (bit vice) addition [OR operation]
iii)Multiply sign .: refers to binary multiplication [AND operation]
iv) Bar -: refers to inversion / complement operation

Basic Rules in Boolean Algebra:

• True is represented by the value 1.
• False is represented by the value 0.
AND is represented by A.B
OR is represented by A + B
NOT is represented by A' or Ā
AND Operations (·) OR Operations (+) NOT Operations (')
0· 0 = 0 A· 0 = 0 0+0=0 A+0 =A 0' = 1 A'' = A
1· 0 = 0 A· 1 = A 1+0=1 A+1 =1 1' = 0
0· 1 = 0 A· A = A 0+1=1 A+A =A
1· 1 = 1 A · A' = 0 1+1=1 A + A' = 1

Boolean theorems
Theorem 1 A+0=A
Theorem 2 A. 1 = A
Theorem 3 A + A = 1
Theorem 4 A.A = 0

Digital Electronics I-18

Unit I Number system and Boolean algebra

Positive and Negative Logic

A digital signal can take only two possible values – a high
level or a low level. Hence it is binary in nature. There are 2 logics in
representing these values
• Positive logic and
• Negative logic
Positive logic – logic 1 level is at a higher voltage level compared
to logic 0 level.
When a logic 1 / high level is represented by +5 volts and
a logic 0 / low level is represented by 0 volts, it is called
positive logic.
Negative logic -logic 0 level is at a higher voltage level compared to
logic 1 level.
When a logic 0 / low level is represented by +5 volts and
a logic 1 / high level is represented by 0 volts, it is called
negative logic.
All variables are expressed in positive logic .i.e. when variable
A = logic 1, it is expressed as Aand when A = logic 0, it is expressed
as A or A′.

1.2.2 DE-MORGAN′S THEOREMS

De-Morgan′s theorems is used to simplify the Boolean function.
It is used to minimize number of gates used in circuits.
There are two laws:
1. The complement of the sum of the two variables is
equal to the product of the complements of the
individual variables.
A + B = A .B

Fig 1.9

Digital Electronics I-20

Unit I Number system and Boolean algebra

The above theorem can be proved using truth table as given below

A B A B
0 0 1 1 1 1
0 1 1 0 0 0
1 0 0 1 0 0
1 1 0 0 0 0

Thus the LHS is equal to a NOR gate logic and RHS is

equivalent to an AND gate with its input inverted.
2. The complement of the product of two variables is equal
to the sum of the complements of the individual
variables
A .B = A + B

Fig 1.10

The above theorem can be proved using truth table as given below

A B A B
0 0 1 1 1 1
0 1 1 0 1 1
1 0 0 1 1 1
1 1 0 0 0 0

Thus the LHS is equal to a NAND gate logic and RHS is

equivalent to an OR gate with its input inverted.

Digital Electronics I-21

Unit I Number system and Boolean algebra

1.2.3 Simplification of Boolean equations using Boolean laws

Problem 1:
Simplify the Boolean Expression: A.(A + B)

A.(A+B) Start

multiply: A.A + A.B Distributive Law

but: A.A = A Idempotent Law

then: A + A.B Reduction

thus: A.(1 + B) Annulment Law

equals to: A Absorption Law

A.(A + B) = A

Problem 2:
Simplify the following Boolean expression
Y = (A + B) (A + B)
Solution
Y = (A + B) (A + B) on multiplying we get
= AA +AB + BA + BB
= 0 +AB + AB + B
= B (A + A + 1)
= B (1 + 1) = B

Hence Y=B

Problem 3: Boolean Expression: (A + B)(A + C)

Digital Electronics I-22

Unit I Number system and Boolean algebra

(A + B)(A + C) Start

multiply: A.A + A.C + A.B + B.C Distributive law

but: A.A = A Idempotent Law

then: A + A.C + A.B + B.C Reduction

however: A + A.C = A Absorption Law

thus: A + A.B + B.C Distributive Law

again: A + A.B = A Absorption Law

thus: A + B.C Result

(A + B)(A + C) = A + B.C

Problem 4: Boolean Expression: AB(BC + AC)

AB(BC+AC) Start

multiply A.B.B.C + A.B.A.C Distributive Law

again: A.A = A Idempotent Law

then: A.B.B.C + A.B.C Reduction

but: B.B = 0 Complement Law

so: A.0.C + A.B.C Reduction

becomes: 0 + A.B.C Reduction

as: 0 + A.B.C = A.B.C Identity Law

thus: ABC Result

AB(BC+AC) = ABC

Digital Electronics I-23

Unit I Number system and Boolean algebra

Problem 5: Simplify the expression Y = AB + A(B + C) + B(B + C)

Solution
Y = AB + A(B + C) + B(B + C)
= AB + AB + AC + BB + BC
= AB + AC + B + BC
= AB + AC + B (1 + C)
= AB + AC + B
= B(1 + A) + AC
= B + AC

1.2.4 Implementation of logic circuits for Boolean equations

Problem 6:
Draw a logic circuit for the expression Y = ABC ( A + D)

Problem 7:
Draw a logic circuit for the expression Y = AC + BC′ + A′BC

Digital Electronics I-24

Unit I Number system and Boolean algebra
Problem 8:
Realize the given Boolean expression using logic gates
Y = ACD + AB(CD + BC)

Boolean expression for outputs of logic circuits

Problem 9: Find the output of the following logic

Problem 10:
Find the output of the following logic or Determine the output
expression for the circuit shown below and simplify it using De
Morgan’s theorem.

Digital Electronics I-25

Unit I Number system and Boolean algebra

Problem 11:
Determine the output expression for the circuit shown below and
simplify it using De Morgan’s theorem.
Solution

Problem 12: Find the expression for the following logic

1.2.5 SOP and POS

The SOP stands for Sum of Products defined as the sum of
minterms.
Example of SOP: AB + CD
The POS stands for Product of Sum defined as the product of
maxterms.
Example of POS: (A + B).(C + D)

Instead of using Boolean theorems, we can use a simple

mapping method to reduce any given Boolean expression. This
requires the condition of output for all possible combination of inputs.
The output could be true (logic 1) for certain input combinations and
false (logic 0) for certain input combination.

Digital Electronics I-26

Unit I Number system and Boolean algebra

For example consider the following truth table: where 3

variables A, B and C are used to describe input condition and Y
gives the desired output for corresponding combination of inputs:

Decimal SOP POS

Equivalent A B C Y
no Y=1 Y=0
0 ABC 0 0 0 1 ABC
1 AB C 0 0 1 0 A +B +C
2  A BC 0 1 0 1  A BC

3 A B C 0 1 1 1 A B C

4 ABC 1 0 0 0 A + B + C

5 AB C 1 0 1 1 AB C

6 A BC 1 1 0 0 A + B +C

7 ABC 1 1 1 0 A+ B+ C

According to the above truth table the output can be
expressed in 2 ways as:
1. SOP : sum of products – for values when Y = 1 and
2. POS : product of sum – for values when Y = 0.

Sum of products expression

Now Y is expressed as sum of products as
Y = ABC + A BC + A B C + AB C
This expression is true for all input combinations and
produces an output = logic 1 level for certain desired input condition.
Mathematically it can be expressed as
Y = Σ m (0, 2, 3, 5) where Σrepresents summation or logical
OR
The same logic system can be expressed in terms of product
of sum where output = 0 for same condition
Digital Electronics I-27
Unit I Number system and Boolean algebra

B′C′ B′C BC BC′ B′C′ B′C BC BC′

A′ 0 0 1 3 2 A′ 0 0 3 2
A1 4 5 7 6 A1 5

B′C′ B′C BC BC′

A′ 0 1 0 1 1
A1 0 1 0 0

On pairing we get the expression for output as

Y = AC +A B + AB C
The logic circuit realization for the same is given as

Fig 1.31

The same combination can be expressed in POS format as follows:

OR Y = (A +B +C).(A + B + C). ( A + B )

PAIRS, QUADS AND OCTETS

A quad is a group of four 1’s that are horizontally or vertically
adjacent in a K-map. Instead of pairing them in adjacent, we can put
them in group of four 1’s, so that the required number of variables is
further reduced.
In a pair the number of variables is reduced from 3 to 2. In a
quad the number of variables is reduced to 2 [4 variables] or1 [3
Digital Electronics I-32
Unit II Logic gates & Arithmetic circuits

UNIT II– LOGIC GATES AND ARITHMETIC CIRCUITS

2.1 LOGIC GATES

A digital circuit with one or more input signals but only one
output signal is called a logic gates. Depending on the input
signals, output has two possible states only – either a high (logic 1)
or a low (logic 0), based on input conditions.
A gate can be considered as a switch such that when open,
does not allow input to pass to output and when closed, input is
passed to output.
For example consider input as logic switches and output as a
bulb. The working of the following circuit is as depicted in the table.
Hence output is logic1 (high) only when both switches are closed
and remains low for all other conditions of input.

S1 S2 Bulb S1 S2 Output
Open Open off 0 0 0
Open Closed Off 0 1 0
Closed Open Off 1 0 0
Fig 2.1 Closed Closed ON 1 1 1

2.1.1 Types of logic gates

A gate can have 2 or more inputs but only one output. The
inputs are named as A and B. The output is named as Y.
There are 3 basic gates OR, AND and NOT gate. These can
be used to produce any digital system. A table representing all
possible status of inputs and the corresponding output for each
combination is drawn for any gate and is termed as the truth table.
The following table shows the various logic equations and
their equivalent gates.

Digital Electronics II-1

Unit II Logic gates & Arithmetic circuits

OR gate
The OR gate has a high output when any one of its inputs is
high. Consider a two input OR gate. The truth table explains the
input conditions and their corresponding output. Hence the OR gate
output is high when either of the inputs A or B or BOTH are high.
The output is low when all the inputs are low and is true for n
number of inputs also.
The output is mathematically expressed as
Y=A+B
Symbol Truth table
A B Y=A + B
0 0 0
0 1 1
1 0 1
Fig 2.2
1 1 1
The operation of an OR gate can be
explained as similar to 2 switches in parallel – where the bulb at
output glows when either S1or S2or both the switches are closed

Digital Electronics II-2

Unit II Logic gates & Arithmetic circuits
Operation of low inverting
It is just opposite to the above tristate gate. When the enable input is
‘low’ or ‘0’ the input will be passed to the output circuit. When the
input is ‘1’, output will be ‘0’ and when the input is ‘0’, the output will
be ‘1’.
When the enable input is ‘high’ or ‘1’ the input will be not passed to
the output circuit. It produces high output impedance ‘Hi-Z’ which
blocks the transmission of input.

2.1.4 Bi-directional buffer

Bi-directional buffer has two tri-state buffers connected “back-to-
back” (inverse parallel) with an additional inverter
One tri-state buffer is as an “active-high buffer”, while the other
operates as an “active-low buffer”.

Fig 2.20

Digital Electronics II-12

Unit II Logic gates & Arithmetic circuits
Working
Here, the two tri-state buffers are connected in parallel but in reverse
from “A” to “B” with the enable control input, EN acting more like a
directional control signal thus allowing data to be both read “from”
and transmitted “to” the same data terminal.
So in this simple example, when the enable input is HIGH,
(EN equals logic “1”) data is allowed to pass from A to B via buffer 1,
and when the enable input is LOW, (EN equals logic “0”) data
passes from B to A via buffer 2.
Thus the enable input “EN” acts as direction control allowing data to
flow in either direction depending upon the logic status of this control
input.

2.2 INTRODUCTION TO LOGIC FAMILIES:

Logic Gates like NAND, NOR are used in daily applications for
performing logic operations. The Gates are manufactured using
semiconductor devices like BJT, Diodes or FETs. Different Gate’s
are constructed using Integrated circuits. Digital logic circuits are
manufactured depending on the specific circuit technology or logic
families.
The different logic families are:
1. RTL (Resistor Transistor Logic)
2. DTL (Diode Transistor Logic)
3. TTL (Transistor Transistor Logic)
4. ECL (Emitter Coupled Logic)
5. CMOS (Complementary Metal Oxide Semiconductor Logic)
Out of these RTL and DTL are rarely used.

2.2.1 TTL: Transistor Transistor Logic

• It is a logic family consisting completely of transistors.

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Unit II Logic gates & Arithmetic circuits
CMOS and its significance
• It is Complementary MOSFET.
• It has a NMOS and a PMOS
• They are combined to get good 1 and good 0
• It consumes negligible power.
• When A =1
NMOS transistor is turned on
PMOS transistor is turned off output is low
• When A = 0
NMOS transistor is turned off
PMOS transistor is turned on output is high

CMOS as NAND gate

A B P1 P2 N1 N2 Y

0 0 on on off off 1

0 1 on off off on 1

1 0 off on on off 1

1 1 off off on on 0

Fig 2.22
CMOS as NAND gate

Transistors P1 P2 N1 N2 form NAND gate. Output Y = [A.B]'

• When input A = 0 and B = 0,
P1 is on P2 is on N1 is off N2 is off
No current flows so output voltage Y is high
• When input A = 0 and B = 1
Digital Electronics II-15
Unit II Logic gates & Arithmetic circuits
P1 is on P2 is off N1 is off N2 is on
No current flows so output voltage Y is high
• When input A = 1 and B = 0
P1 is off P2 is on N1 is on N2 is off
No current flows so output voltage Y is high
• When input A = 1 and B = 1
P1 is off P2 is off N1 is on N2 is on
Current flows so output voltage Y is low

Comparison of logic families

Parameters TTL standard TTL LS CMOS
series
Basic gate NAND NAND NAND-NOR
Fan-out 10 20 20

Power dissipation in 10 22 0.0025

mW/gate
Noise immunity good Very good Very good

Propagation delay in 10 33 18
ns/gate
Speed power product (pJ) 100 33 10.8

Clock rate (MHz) for FFs 35 3 60

Available function Very high Very high high

2.2.3 Definitions of Features of Logic Families:

1. Fan in : It is the number of inputs connected to the gate
without any degradation in the voltage level
2. Fan Out: Number of loads the output of a GATE can drive
without effecting its usual performance.
3. Power Dissipation: It represents the amount of power
needed by the device. It is measured in mW.

Digital Electronics II-16

Unit II Logic gates & Arithmetic circuits
4. Propagation Delay: The delay which occurs for the output
to make its transition is the propagation delay.
5. Noise Margin: It represents the amount of noise voltage
allowed at the input, which doesn’t effects the standard
output.

Fig 2.23

2.3 ARITHMETIC CIRCUITS

2.3.1 HALF ADDER
A logic circuit that performs the binary addition of a single bit
is called a half adder. It consists of logic gates connected in orderly
manner to give a sum and a carry output.
Logical Expression of Half Adder
Sum (S) = A ⊕ B

Carry (C) = A . B

Fig 2.24
Working
Consider a two 1 bit input namely A and B. Their possible
states and corresponding sum and carry output is given in the form
of a truth table, as shown below:

Digital Electronics II-17

Unit II Logic gates & Arithmetic circuits
Inputs Output

A B Sum ∑ Carr Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Considering the input columns and the sum output alone,it is

similar to truth table of an EX-OR gate. Similarly, considering the
input columns and the carry output alone, it is similar to an AND gate
truth table. Hence a Half- adder logic can be constructed using an
EX-OR gate and AND gate as shown in the figure. When two 1-bit
binary numbers are added, the EX-OR gate gives the sum output
and AND gate gives the carry output.
Thus a half adder circuit is realized to add two 1bit binary
number using an EX-OR and AND gate.

2.3.2 FULL ADDER

A logic circuit that performs the binary addition of a single
bit, along with the carry from previous stage is called a full adder. It
consists of logic gates connected in orderly manner to give a sum
and a carry output.
Logical Expression of Full Adder
CARRY-OUT = AB + BCin + ACin

SUM = (A ⊕ B) ⊕ Cin

Consider a two 1- bit input namely A and B. Cin is the carry

from previous stage Their possible states and corresponding sum
and carry output is given in the form of a truth table, as shown

Digital Electronics II-18

Unit II Logic gates & Arithmetic circuits

Fig 2.28

Working:
Considering the input columns and the difference output
alone, it is similar to truth table of an EX-OR gate. Similarly the
considering the input columns and the borrow output alone, it is
similar to an AND gate with input A and B. Hence a Half- subtractor
logic can be constructed using an EX-OR gate, AND gate and a
NOT gate as shown in the figure.
When two 1-bit binary numbers are subtracted, the EX-OR gate
gives the difference output and AND gate with input A and B gives
the borrow output.
Thus a half subtractor circuit is realized to subtract two 1bit
binary numbers using an AND, NOT and EX-OR gate.

2.3.4 FULL SUBTRACTOR

A logic circuit that performs the binary subtraction of 3 single
bits is called a full subtractor. The full subtractor is used to
subtract three 1-bit numbers A, B, and C (Borrow in), which are
minuend, subtrahend, and borrow, respectively. The full subtractor
has three input states and two output states i.e., diff and borrow.

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Unit II Logic gates & Arithmetic circuits

Fig 2.29
Logical expression
Diff = (A ⊕ B) ⊕ Borrowin Borrow = AB + ( A ⊕ B)Borrowin
o 'A' and' B' are the input variables. These variables represent
the two significant bits that are going to be subtracted.
o 'Borrowin' is the third input which represents borrow.
o The 'Diff' and 'Borrow' are the output variables that define
the output values.
o The eight rows under the input variable designate all
possible combinations of 0 and 1 that can occur in these
variables.
Diff:
o Perform the XOR operation of input A and B.
o Perform the XOR operation of the outcome with 'Borrow'.
So, the difference is (A XOR B) XOR 'Borrowin' which is also
represented as: (A ⊕ B) ⊕ 'Borrowin'
Digital Electronics II-22
Unit II Logic gates & Arithmetic circuits
Borrow:
o Perform the 'AND' operation of the inverted input A and B.
o Perform the 'XOR' operation of input A and B.
o Perform the 'OR' operations of both the outputs that come
from the previous two steps. So the 'Borrow' can be
represented as: AB + ( A ⊕ B)Borrowin
Thus a full subtractor can be constructed to realize
subtraction of three 1-bit binary numbers using the above circuit.

2.3.5 PARALLEL ADDER

Parallel adders are digital circuits that add “n” bits in parallel.

Input Ci 0 1 1 0
carry
Augend Ai 1 0 1 1
Addend Bi 0 0 1 1
Sum Si 1 1 1 0
Output Ci +1 0 0 0 1 1
carry
Fig 2.30

Fig 2.31

Digital Electronics II-23

Unit II Logic gates & Arithmetic circuits
4 bit Binary Parallel Adder
A binary adder is a digital circuit that produces the arithmetic
sum of two binary numbers. It can be constructed with full adders
connected in cascade, with the output carry from each full adder
connected to the input carry of the next full adder. A n bit binary
adder requires n – full adders. Hence a 4-bit binary adder requires 4
full adders.
The input to each full adder is Ai, Bi and Ci (carry bit from
previous stage) and the two outputs obtained are Si (sum) and Ci+1
(carry).
For eg: to add binary 1011 and 0011, the resultant sum =
1110 with final carry C4 = 0.

2.3.6 Working principle of single bit digital comparator

A Digital Comparator is a combinational logic circuit that is used for
comparison of two binary values.

Fig 2.32
A comparator used to compare two bits is called a single-bit
comparator. It consists of two inputs each for two single-bit
numbers and three outputs to generate less than, equal to, and
greater than between two binary numbers.

Digital Electronics II-24

Unit II Logic gates & Arithmetic circuits
• The circuit works by comparing the bits of the two numbers
starting from the most significant bit (MSB) and moving toward
the least significant bit (LSB).
• At each bit position, the two corresponding bits of the numbers
are compared. If the bit in the first number is greater than the
corresponding bit in the second number, the A>B output is
set to 1, and the circuit immediately determines that the first
number is greater than the second.
• Similarly, if the bit in the second number is greater than the
corresponding bit in the first number, the A<B output is set to
1, and the circuit immediately determines that the first number
is less than the second.
• If the two corresponding bits are equal, the circuit moves to the
next bit position and compares the next pair of bits.
• This process continues until all the bits have been compared. If
at any point in the comparison, the circuit determines that the
first number is greater or less than the second number, the
comparison is terminated, and the appropriate output is
generated.
• If all the bits are equal, the circuit generates an A=B output,
indicating that the two numbers are equal.

REVIEW QUESTIONS
3 marks questions
1. Draw the symbol for NAND gate. Write its truth table.[Apr 2017]
2. Which are known as universal gates? Why is it called so?
[Apr 2018]
3. What is known as tristate Logic? Explain with example
[Apr 2019]
4. What is the advantage of CMOS logic over TTL

Digital Electronics II-25

Unit II Logic gates & Arithmetic circuits
5. Construct AND gate by using only NOR gates. [Apr 2017]
6. Explain two inputs OR gate with truth table. [Oct 2018]
7. Define fan in & fan out. [Oct 2018, Apr 2019]
8. Simplify the Boolean expression
Y = ABC + A B C + A BC + A B C [Apr 2018]
9. Simplify the following expression using Boolean technique.
Y = AB + A(B+C) + B(B+C) [Oct 2019]
10. Draw the symbol of EX-OR gate. Write its Truth table and State
logic equation for EX-OR gate.
11. Realize EX-NOR function using NAND gate.[Apr 2018, 2019]
12. What is positive Logic and negative logic? [Apr 2017]
13. Explain the operation of half subtractor. [Apr 2017]
14. Draw the circuit and truth table of half adder. [Oct 2019]
15. Draw the Logic diagram and truth table of half subtractor.
[Apr 2018]
16. Draw the truth table of full adder. [Apr 2018]
17. Define single bit digital comparator.
18. Define half adder
19. define full adder.
20. Write a note on full subtractor.
21. Write a note on half subtractor.
22. What do you mean by bidirectional buffer?

Descriptive questions
1. Draw the symbol, truth table and logic equation for Ex-OR gate.
[Apr 2017]
2. With the diagram, explain the operation of TTL NAND gate.
[Apr 2017]
3. Construct AND, OR and NOT gates using only NOR gates.

Digital Electronics II-26

Unit III Combinational logic circuits

UNIT III– COMBINATIONAL LOGIC CIRCUITS

3.0 INTRODUCTION
When logic gates are connected together to produce a
specified output for certain specified combinations of input variables,
with no storage involved, the resulting circuit is called combinational
logic.
A combinational circuit consists of input variables, logic
gates, and output variables. The logic gates accept signals from the
input variables and generate output variables.
The circuit designed to realize a Boolean expression is an
example of Combinational logic.

3.1 MULTIPLEXER [many to one]

• It is a circuit that selects one of the many input lines and
• Connects it to a single output line to transmit the data.
• In any Mux there are 2n input lines, n selection lines and 1
output line.
• The address on the selection line decides which input line is
to be selected
• Also called Data Selector
Generally
• The input DATA line is labeled D0,D1…
• The selection line is labeled S0,S1…
• The output line is labeled Y
4:1 Multiplexer
• A 4:1 multiplexer has 4 input data lines D0 D1 D2 D3
• output line Y
• selection lines S0 S1

Digital Electronics III-1

Unit III Combinational logic circuits
o When S1 S0 = 00 input D0 is selected and passed on
to the output, so Y = D0
o When S1 S0 = 01 input D1 is selected and passed on
to the output, so Y = D1
o When S1 S0 = 10 input D2 is selected and passed on
to the output, so Y = D2
o When S1 S0 = 11 input D3 is selected and passed on
to the output, so Y = D3

Y=S1S0 D0 +S1S0D1 + S1S0 D2 +S1S0 D3

The logic diagram and truth table of 4:1 multiplexer is shown in fig.

Selection line output

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Fig .3.1
Application of Mux:
A mux can be used to
• Synthesis a circuit
• Implement any Boolean function.

Realization of 8 to 1 MUX using two 4 to 1 MUX.

To implement the 8×1 multiplexer, we need two 4×1 multiplexers
and one 2×1 multiplexer. The 4×1 multiplexer has 2 selection lines,
4 inputs, and 1 output. The 2×1 multiplexer has only 1 selection line.
For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1
multiplexer produces one output. So, in order to get the final output,
we need a 2×1 multiplexer.
Digital Electronics III-2
Unit III Combinational logic circuits

Fig .3.2

The same selection lines, s1 & s0 are applied to both 4x1

Multiplexers. The data inputs of upper 4x1 Multiplexer are A7 to
A4 and the data inputs of lower 4x1 Multiplexer are A3 to A0.
Therefore, each 4x1 Multiplexer produces an output based on the
values of selection lines, s1 & s0.
The outputs of first stage 4x1 Multiplexers are applied as inputs of
2x1 Multiplexer that is present in second stage. The other selection
line, s2 is applied to 2x1 Multiplexer.
• If s2 is zero, then the output of 2x1 Multiplexer will be one of
the 4 inputs I3 to I0 based on the values of selection lines
s1 & s0.
• If s2 is one, then the output of 2x1 Multiplexer will be one of
the 4 inputs I7 to I4 based on the values of selection lines
s1 & s0.

Digital Electronics III-3

Unit III Combinational logic circuits
• Therefore, the overall combination of two 4x1 Multiplexers
and one 2x1 Multiplexer performs as one 8x1 Multiplexer.

3.2 DEMULTIPLEXER [one to many]

• It is a circuit that selects one of the many output lines
• And connects the input to the selected output line to transmit
the data.
• In any Demux there is 1 input line, n selection lines and 2n
output lines.
• The address on the selection line decides which output line
is to be selected
• It is also called data distributor
Generally
• The input DATA line is labeled D
• The selection lines are labeled S0,S1…
• The output lines are labeled Y0,Y1....

1:4 Demultiplexer
• A 1:4 demultiplexer has 1 data input line D
• 4 output lines Y0 Y1 Y2 Y3
• 2 selection line S0 S1
 When S1 S0 = 00 input D is passed
on to the output Y0, so Y0 = D
 When S1 S0 = 01 input D is passed
on to the output Y1, so Y1 = D
 When S1 S0 = 10 input D is passed
on to the output Y2, so Y2 = D
 When S1 S0 = 11 input D is passed on to the output Y3,
so Y3 = D
The logic diagram and truth table of 1:4 demux is shown in fig

Digital Electronics III-4

Unit III Combinational logic circuits

Selection line output

S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 D
0 1 0 0 D 0
1 0 0 D 0 0
1 1 D 0 0 0
Fig .3.3 Fig 3.4

4 : 1 line DeMultiplexer

3.3 DECODER
Decoder is a combinational circuit that has ‘n’ input lines and
maximum of 2n output lines.

Fig 3.5

• A decoder is a code converter circuit

• Generally it has N number of inputs and 2N number of
outputs
• Example if input is 3, output is 23 which is 8 lines
• The input is called address lines labeled as ABC
• Output is labeled as Y0 Y1.... Y7
• Based on the input code [address], only one of the
output line is selected at a time
Digital Electronics III-5
Unit III Combinational logic circuits
• Only when the ‘enable’ input line is active decoding is
done

3.3.1 2 TO 4 DECODER
In the 2 to 4 line decoder, there is a total of three inputs, i.e.,
A0, and A1 and E and four outputs, i.e., Y0, Y1, Y2, and Y3. For
each combination of inputs, when the enable 'E' is set to 1,
one of these four outputs will be 1.

Fig .3.6

Truth Table:

The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:

Digital Electronics III-6

Unit III Combinational logic circuits
Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'
Logical circuit:

Fig .3.7
Each output is having one product term. So, there are four product
terms in total. We can implement these four product terms by using
four AND gates having three inputs each & two inverters.
The circuit diagram of 2 to 4 decoder is shown in the following
figure.
Therefore, the outputs of 2 to 4 decoder are nothing but the min
terms of two input variables A1 & A0, when enable, E is equal to
one. If enable, E is zero, then all the outputs of decoder will be equal
to zero.

3.3.2 BCD TO SEVEN SEGMENT DECODER

Fig 3.8

Digital Electronics III-7

Unit III Combinational logic circuits

Fig 3.9
• BCD:Binary Coded Decimal : used to represent decimal digit
from 0 to 9 in a binary form[4 bits]
• 7-segment display : used to display the decimal output
• BCD to 7-segment decoder is a logic circuit which converts
the BCD (4 bits) code to 7- segment display code (7 bits).
• IC 7447 is a BCD to 7-segment decoder
• Combined with 7 segment display to display the decimal
numbers 0 to 9
• A truth table is tabulated to relate the input and output
combinations[ common cathode output]
• Eg to display ‘0’ we need to bias all segment except g

Segments driven for decimal

Segment outputs
Decimal digit Inputs
displayed
A B C D a b c d e f g
DIGIT a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0 P0 1 1 1 1 1 1
1 0 0 0 1 0 1 1 0 0 0 0
P1 1 1
2 0 0 1 0 1 1 0 1 1 0 1

3 0 0 1 1 1 1 1 1 0 0 1
P2 1 1 1 1 1
4 0 1 0 0 0 1 1 0 0 1 1 P3 1 1 1 1 1
5 0 1 0 1 1 0 1 1 0 1 1
P4 1 1 1 1
6 0 1 1 0 1 0 1 1 1 1 1
P5 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0

8 1 0 0 0 1 1 1 1 1 1 1 P6 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
P7 1 1 1
P8 1 1 1 1 1 1 1
P9 1 1 1 1 1 1

Digital Electronics III-8

Unit III Combinational logic circuits
From the table
• Segment ais driven whenever the digit 0, 2, 3, 5, 6, 7, 8, and
9 is displayed.
• Considering this logic for all displays we arrive at a logic
circuit where we have
o 10 AND gates for each BCD input combination
The output of these AND gate are marked P0 to P9
Eg AND gate 1 with BCD input (0000) ABCD is
labeled as P0.
o 7 OR gate for each segment
Eg OR gate1[A] with inputs P0, P2, P3, P5, P6, P7,P8 and
P9 is used to drive segment a
OR gate7[G] with inputs P2, P3,P4, P5, P6,P8 and P9 is
used to drive segment g

The block diagram gives the overall view of the decoder section
within the IC.

Fig 3.10
Thus a BCD to seven segment decoder is used to decode
the BCD input and drive the seven segments to display the various
numerals.
Digital Electronics III-9
Unit III Combinational logic circuits
3.4 ENCODER
• An encoder is a code converter circuit
• Generally it has 2n number of inputs and n outputs
• A 8:3 encoder has 8 [23] input and 3 output
• Only one of the inputs is active at a time
• An-bit code is generated, depending upon which of the input
is exited.
Octal to binary encoder (Decimal to BCD converter):
• It has 10 inputs and 4 outputs.

Enabled BCD output

Decimal
input D C B A
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1

Fig 3.11 4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Fig 3.12
• The figure shows the decimal- to - BCD encoder.

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Unit III Combinational logic circuits
• The parity bit = 0 to make the total number of 1′s odd in
case we want odd parity
• The parity bit = 1 to make the total number of 1′s even in
case we want even parity.
Parity generator
It is a logic circuit that generates an additional bit which
when appended (added) to a digital word makes its parity as desired
(odd or even).
Parity checker
It is a logic circuit that checks the parity of a binary word.
ODD parity generator
Data input Output- Odd
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
Fig 3.13 0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
A 4-bit odd parity generator circuit 0 1 1 1 0
1 0 0 0 0
In an odd parity system, the
1 0 0 1 1
number of ones in data bits including 1 0 1 0 1
1 0 1 1 0
the parity bit must be an Odd number. 1 1 0 0 1
For example, the odd parity bit for the 1 1 0 1 0
1 1 1 0 0
data bits 1110 must be 0 because we 1 1 1 1 1
must have an odd number of ones in
the data bits including the parity bit. EX-OR gates are used in parity
generator and checker circuits.
A 4-bit odd parity generator circuit, its truth table and logic equation
are shown in figure.
P= D3⊕ D2 ⊕ D1⊕ D0
The four data bits along with the parity bit D3D2D1D0P are
transmitted to the receiver circuit.
Digital Electronics III-12
Unit IV Sequential Logic Circuits

UNIT IV– SEQUENTIAL LOCIG CIRCUITS

4.1 INTRODUCTION to sequential logic circuits

Sequential circuits are combinational circuit with storage
element connected to its feedback path. The figure shows the detail
of a sequential logic.

Fig 4.1

In sequential circuits, the output depends not only on the

present input conditions but also on the previous output conditions,
which is provided by the feedback from the output back to the input.
The basic building block for sequential logic circuits is the flip-flop.

4.1.1 Basic latch circuits using NAND and NOR gates

• Latches are basic storage elements that operate with signal
levels.
• Latches controlled by a clock transition are flip-flops. Latches
are level-sensitive devices.
• Latches are useful for the design of the asynchronous sequential
circuit. Latches are sequential circuit with two stable states.
• These are sensitive to the input voltage applied and does not
depend on the clock pulse.
• Flip flops that do not use clock pulse are referred to as latch.
• A latch which is made up of only NAND gates is called a NAND
latch.
• A latch which is made up of only NOR gates is called a NOR
latch.
Digital Electronics IV-1
Unit IV Sequential Logic Circuits
Types of Latches in Digital Electronics
In digital electronics different types of latches are:
1. SR Latches
2. Gated SR Latches
3. D Latches
4. Gated D Latches
5. JK Latches
6. T Laches
SR latches
S-R latches i.e., Set-Reset latches are the simplest form of latches
and are implemented using two inputs: S (Set) and R (Reset). The S
input sets the output to 1, while the R input resets the output to 0.
When both S and R inputs are at 1, the latch is said to be in an
“undefined” state. They are also known as preset and clear states.
Truth table
S R Q Q’
0 0 Latch Latch
0 1 0 1
1 0 1 0
1 1 0 0

Logic Diagram of SR Latch

SR Latch is a logic circuit with:
2 cross-coupled NOR gate or 2 cross-coupled NAND gate.
2 input S for SET and R for RESET
2 output Q, Q’.

Fig 4.2

Digital Electronics IV-2

Unit IV Sequential Logic Circuits
D-latch
D latches are also known as transparent latches and are
implemented using two inputs: D (Data) and a enable signal. A D
latch can store a bit value, either 1 or 0. When its Enable pin is
HIGH, the value on the D pin will be stored on the Q output.
E D Q Description
0 X Q Memory
(no change)
1 0 0 Reset Q to 0
1 1 1 Set Q to 1

Fig 4.3
4.1.2 Triggering
The process of applying clock to any sequential circuit is known as
triggering.
Clock Signal:
• It is used to trigger (activate) the sequential logic circuits.
• It is classified as raising (positive) edge clock signal and
falling (negative) edge clock signal.

Fig 4.4

• S-R and J-K Flip-Flop are raising (positive) edge triggered

flip flop.
• D, T and Master and Slave Flip-Flops are falling (negative)
edge triggered flip flop
Types of triggering
1. Level triggering
2. Edge triggering
Digital Electronics IV-3
Unit IV Sequential Logic Circuits
Level Triggering Method
In the level triggering method, the flip-flop responds to the inputs and
updates its output state when the clock pulse is in either high level or
low level. When the flip-flop is triggered to update its output state
when the clock pulse is in the logic high level, then it is called
positive level triggering. When the flip-flop is triggered to update the
output state when the clock pulse is in the logic low level, then it is
called negative level triggering.

Positive level Negative level

Fig 4.5

Edge Triggering Method

When the flip-flop is triggered to update its output state on the rising
or falling edge of the clock pulse, then it is called edge triggering
method. If the flip-flop is triggered when the clock pulse goes from
low to high (positive edge), then it is called positive edge-triggering
method. If the flip-flop is triggered to update its output when the
clock pulse goes from high to low (negative edge), then it is called
negative edge- triggering method.

Positive edge negative edge

Fig 4.6

FLIP-FLOPS
• Flip-flop is a one bit memory cell.
• It can store one bit of information′0′ or ′1′.
• A flip-flop has two outputs Q andQ.

Digital Electronics IV-4

Unit IV Sequential Logic Circuits
• The outputs are complement of each other.
• The output alter between two logic states 0 and 1
• so it is called 'flip-flop'
• Flip-flops are used in counters, shift registers and memory
devices.

4.1.3 SR flip-flop
Output
S R Qn+1
condition
. Pervious state /
0 0 Qn
No change
1 0 1 Set

0 1 0 Reset
Forbidden /
Fig 4.7 1 1 -
not allowed

• SR flip flop is a Set Reset flip flop.

• Hence the output can be set / reset / or allowed to be in the
same state [memory] using this type of flip flop.

Consider the circuit

• NAND gate 1 and 2 are used as inverters
• NAND gate 3 gives output [S′.Q′]′
• NAND gate 4 gives output [R′.Q]′

Previous NAND gate

Input FF output condition
output output
Qn S R 1 2 3 4 Qn+1 Qn+1′

0/1 0 0 1 1 0 / 1 1/0 Qn Qn′ previous

0/1 1 0 0 1 1 0 1 0 Set

0/1 0 1 1 0 0 1 0 1 Reset

0 /1 1 1 0 0 1 1 1 1 forbidden

Digital Electronics IV-5

Unit IV Sequential Logic Circuits
• When S = 0 and R = 0, the output remains unchanged.
Hence it acts as memory
• When S = 1 and R = 0 the output is forced to 1.
Hence it is called SET condition.
• When S = 0 and R = 1 output is forced to 0.
Hence it is called RESET condition.
• When S = 1 and R = 1 both outputs Q andQ assume the
same output condition without complimenting each other.
Hence it is called forbidden state and should be
AVOIDED.

CLOCKED SR FLIP FLOP using NAND gates

Fig 4.8

• Clocked SR flip-flop is similar to SR flip-flop with an

additional clock input.
• The output of the FF changes only on the arrival of the clock
signal.
• When there is no clock pulse, the flip-flop will retain the
previous state.
• This flip-flop is also called gated SR flip flop.
• Hence the output will respond to an input as long as Enable
/ clock is high.
• When enable input goes low, the output will retain the
information and does not change even if there is a change at
input.
Digital Electronics IV-6
Unit IV Sequential Logic Circuits
SR FLIP FLOP WITH PRESET AND CLEAR

Fig 4.9

Preset and Clear are asynchronous inputs (and for the basic design
of flip flops low active) which are connected to the output side of
gates (NAND/NOR) as opposed to other inputs which are connected
with clock inputs.
The outputs of flip flop will change in accordance with state of inputs,
clock and last output. But if you want at the start of events or at any
moment that either all flip flops connected to be 1 or 0 Preset and
Clear inputs are activated respectively (momentarily making Low).
For the normal operation Preset and Clear are given High.

4.1.4 JK FLIP FLOP

The forbidden state of RS flip flop is undesirable. Hence it is
overcome in a JK flip flop where the output is fed back to the input
as shown in the figure, where S is fed back withQ and R with Q

Digital Electronics IV-7

Unit IV Sequential Logic Circuits
• Flip-flop 3 toggles when QB is on negative edge and
• Flip-flop 4 toggles when QC is on negative edge
7. The waveform shows the toggle condition of each flip-flop as
the clock is applied.
8. Note the output of each flip-flop in the order QDQCQBQA at
the end of each clock pulse
9. Note the binary count is upwards, starting from 0 goes to 15
as shown in the truth table.
10. Note that the pattern repeats after the 16th clock pulse

count QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0

4.2.2 FOUR 4- BIT SYNCHRONOUS UP- COUNTER

In Synchronous Counters, the clock signal is connected to
the clock input of EVERY individual flip-flop. So all the flip-flops are
clocked together simultaneously (in parallel). This results in all the
individual output bits changing state at exactly the same time with
no ripple effect and therefore, no propagation delay. Hence

Digital Electronics IV-15

Unit IV Sequential Logic Circuits
settling time is equal to delay time of a single flip-flop. Speed of
operation is high and equal to speed of a single flip-flop.

Circuit

Fig 4.18

• Clock pulses are fed directly to each J-K flip-flop

• Both the J and K inputs are all tied together
• JK input of first flip-flop is tied to 1. Hence it toggles when
clock goes negative
• QA is fed as input to second stage [JB]. Hence FFB toggles
when both clock and QA goes negative
• QA and QB are ANDed and fed as input to third stage [JC].
Hence FFC toggles when clock, QA and QB goes negative
• QA, QB and QC are AND ed and fed as input to forth stage
[JD]. Hence FFD toggles when clock, QA, QB and QC goes
negative
• Hence the all the flip- flop toggle in synchronous with the
clock.
• So there is no propagation delay
• The output waveform and truth table is as shown below
• For 4 flip-flops the count is 16 – binary 0000 to 1111

Because the counter counts sequentially on every clock

pulse, this type of counter is known as a Synchronous Counter or
parallel counter.

Digital Electronics IV-16

Unit IV Sequential Logic Circuits

Count QA QB QC QD Fig 4.19

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0

4.2.3 FOUR - 4 BIT SYNCHRONOUS DOWN COUNTER

In Synchronous DOWN Counters, the clock signal is
connected to the clock input of EVERY individual flip-flop. So all the
flip-flops are clocked together simultaneously (in parallel). So
there is no ripple effect or propagation delay.
• Clock pulses are fed directly to each J-K flip-flop
• Both the J and K inputs are all tied together
• JK input of first flip-flop is tied to 1. Hence it toggles when
clock goes negative

Digital Electronics IV-17

Unit IV Sequential Logic Circuits
For a ripple up counter, the Q output of preceding FF is connected to
the clock input of the next one.
For a ripple down counter, the Q bar output of preceding FF is
connected to the clock input of the next one.
Let the selection of Q and Q bar output of the preceding FF be
controlled by the mode control input M such that, If M = 0, UP
counting. So connect Q to CLK. If M = 1, DOWN counting. So
connect Q bar to CLK.

Fig 4.22

Fig 4.23

TRUTH TABLE

Digital Electronics IV-20

Unit IV Sequential Logic Circuits
Timing diagram

OPERATION
Case 1: With M = 0 (Up counting mode)
If M = 0 and M = 1, then the AND gates 1 and 3 in fig. will be
enabled whereas the AND gates 2 and 4 will be disabled.
Hence QA gets connected to the clock input of FF-B and QB gets
connected to the clock input of FF-C.
These connections are same as those for the normal up counter.
Thus with M = 0 the circuit work as an up counter.
Case 2: With M = 1 (Down counting mode)
If M = 1, then AND gates 2 and 4 in fig. are enabled whereas the
AND gates 1 and 3 are disabled.
Hence QA gets connected to the clock input of FF-B and QB gets
connected to the clock input of FF-C.
These connections will produce a down counter. Thus with M = 1 the
circuit works as a down counter.

Digital Electronics IV-21

Unit IV Sequential Logic Circuits
3.2.2 DECADE COUNTER/BCD COUNTER
A modulo-16 ripple counter with additional logic gates can
be made to give a decade (divide-by-10) counter output for use in
standard decimal counting and arithmetic circuits. Such counters are
generally referred to as Decade Counters.
A decade counter requires resetting to zero when the output
count reaches the decimal value of 10, i.e. when Q DCBA = 1010
and is fed back to the reset input.
A counter with a count sequence from binary "0000" (BCD =
"0") through to "1001" (BCD = "9") is generally referred to as a BCD
counter because its ten state sequence is that of a BCD code.
The following figure depicts a decade counter.

Fig 4.24

This type of asynchronous counter counts upwards on each

trailing edge of the input clock signal starting from "0000" until it
reaches an output "1010" (decimal 10). Both outputs QB and QD are
now equal to logic "1" and the output from the NAND gate changes
state from logic "1" to a logic "0" level and its output is also
connected to the CLEAR (CLR) inputs of all the JK Flip-flops. This
causes all of the Q outputs to be reset back to binary "0000" on the
count of 10. Once QB and QD are both equal to logic "0" the output of
the NAND gate returns back to a logic level "1" and the counter
restarts again from "0000". We now have a decade or Modulo-10
counter.

Digital Electronics IV-22

Unit IV Sequential Logic Circuits
Clock Output bit Decimal
Count Pattern Value Decade Counter Timing Diagram
QD QC QB QA
1 0 0 0 0 0
2 0 0 0 1 1
3 0 0 1 0 2
4 0 0 1 1 3
5 0 1 0 0 4
6 0 1 0 1 5
7 0 1 1 0 6
8 0 1 1 1 7
9 1 0 0 0 8
Fig 4.25
10 1 0 0 1 9
11 Counter Resets its Outputs
back to Zero

• QA toggles on negative edge of clock

• QB toggles on negative edge of QA
• QC toggles on negative edge of QB and
• QD toggles on negative edge of QC
• The clear goes high after count reaches 1001 and resets all
flip-flop
• Note the output of each flip flop at the end of each clock
pulse.
• It is upward binary sequence from 0000 to 1001.
• The sequence repeats.
Note:
Using the same idea of truncating counter output
sequences, the above circuit could easily be adapted to other
counting cycles be simply changing the connections to the NAND
gate. For example, a modulo- 12 counter can easily be made by
simply taking the inputs to the NAND gate from the outputs at QC
and QD, noting that the binary equivalent of 12 is "1100".

Digital Electronics IV-23

Unit IV Sequential Logic Circuits

Sl. Synchronous Counter Asynchronous Counter

no.
1. In synchronous counter we In asynchronous counter main
use a universal clock that clock is only applied to the first
is common to all flip flops flip flop and then for rest of flip
through out the circuit. flops the output of previous flip
flop is taken as a clock.
2. Faster in operation. Slower
3. Does not produce any produces decoding error.
decoding errors.
4. Also called Parallel Also called Serial Counter.
Counter.
5. Designing and Designing and implementation
implementation are is very easy.
complex.
6. operate in any desired Will operate only in fixed count
count sequence. sequence (UP/DOWN).
7. Examples are: Ring Examples are: Ripple UP
counter, Johnson counter. counter, Ripple DOWN
counter.
8. propagation delay is less. Propagation delay is more.

REVIEW QUESTIONS
3 marks questions
1. What is a latch?
2. What is a flip flop?
3. What is sequential logic? Give an example. [Oct 2019]
4. Define flip flop. [Apr 2017]
5. Draw the SR flip flop circuit. [Apr 2018]
6. Write about level triggering in flip flop. [Oct 2018]
7. Write a note on edge triggering in flip flop.
8. What is meant by triggering of flip-flop? [Oct 2019]
9. What is a synchronous counter?
10. Define asynchronous counter.
11. Draw the logic diagram of D flip flop and writes its truth table.
[Apr 2017]
12. Explain RS flipflop. [Oct 2018]
Digital Electronics IV-24
Unit IV Sequential Logic Circuits
13. What is race around condition? How is it eliminated in flip flop?
[Oct 2017]
14. Draw the logic diagram and truth table of T flip flop. [Oct 2017]
15. Draw the circuit of a JK master slave flip flop.
16. Write the truth table of a BCD counter.
17. What are the applications of flip-flops?
18. What are the applications of counters?
19. Write about the need of preset and clear in SR flip flop.
20. Compare synchronous and asynchronous counters. [Apr 2019]

Descriptive questions
1. Briefly explain SR latch using NAND and NOR gates and truth table.
2. Briefly explain D latch using NAND and NOR gates with diagrams and
truth table.
3. Describe the operation of clocked SR flip flop using NAND gates with
logic diagram and truth table
4. Describe the operation of D flip flop with logic diagram and truth table.
5. Describe the operation of T flip flop with logic diagram and truth table
6. Describe the operation of JK flip flop with logic diagram and truth table
7. With the logic diagram and truth table explain JK-MS flip flop.
[Apr 2017]
8. Explain the operation of a 4 bit asynchronous counter with the Logic
diagram and truth table. [Oct 2018]
9. Explain the working of 4 bit synchronous upcounter with
necessary sketch. [Apr 2019]
10. Explain the operation of a 3 bit asynchronous up/down counter with the
Logic diagram and truth table.
11. Explain the working of decade counter with necessary sketch.
[Oct 2019]

Digital Electronics IV-25

Unit V Storage devices and logic families

UNIT V – STORAGE DEVICES AND LOGIC FAMILIES

5.1 SHIFT REGISTERS

Fig 5.1
A register is a group of flip flops that can be used to store a binary
number.
• There must be one flip flop for each bit in the binary number.
• Hence to store an 4 bit binary number we require 4 flip flops.
• Hence the registers are cascaded such that output of one
register is fed as input to next register.
• Generally D flip flops are used where Q1 is connected to D2, Q2
to D3 and so on.
• When SR / JK flip flop is used, data to input S/J is inverted and
fed to R/K
There are two ways to enter data into a register: serial or
parallel and two ways to shift the data out of the register: serial and
parallel. Hence there are four basic register types:
1. Serial – in – serial out
2. Serial – in – parallel out
3. Parallel in – parallel out
4. Parallel in - parallel out
The data input is called write operation and data out is
called read operation.

Fig 5.2
A universal shift register can do all the above operations.
Digital Electronics V-1
Unit V Storage devices and logic families
5.1.1 SERIAL IN – SERIAL OUT

Fig 3.46

• Consider a 4 bit shift register cascaded as shown above.

• The inputs are named DA to DD and output QA to QD.
• The reset pin is given a low level to clear the register.
• A common clock triggers each flip flop at every negative
edge.
• The output of one flip flop is connected as input to next flip
flop
• The data is transferred from one to another only during the
next negative edge of the clock.
• Here the data is shifted in serially and shifted out serially.
• Hence the first bit of data entered requires n clock pulses to
reach the nth flip flop.
• In this case the first data bit entered reaches the fourth flip
flop after 4 clock pulses.

Fig 5.3

The above figure explains the bit transfer within the register.
Note bit A is entered into reg A at the end of 1st clock pulse, the

Digital Electronics V-2

Unit V Storage devices and logic families
same bit is transferred to reg B at the end of 2nd clock pulse and so
on. Similarly to output all the bits of the data we require the same
number of pulses as to input. Hence we require 4 pulses to output
the data. So, for serial in- serial out operation we require n + n
number of pulses for a n bit data transfer.

5.2 SERIAL IN – PARALLEL OUT

Fig 5.4

• Consider a 4 bit shift register cascaded as shown above.

• The inputs are named DA to DD and output QA to QD.
• The reset pin is given a low level to clear the register.
• A common clock triggers each flip flop at every negative
edge.
• The output of one flip flop is connected as input to next flip
flop,
• The data is transferred from one to another only during the
next negative edge of the clock.
• Here the data is shifted in serially and shifted out parallel.
• Hence the first bit of data entered requires n clock pulses to
reach the nth flip flop.
• In this case the first data bit entered reaches the fourth flip
flop after 4 clock pulses.
• Now the data is ready for parallel output.

Digital Electronics V-3

Unit V Storage devices and logic families
5.2.2 ORGANIZATION OF ROM

Fig 5.10

• Figure shows the organization of simple 4 byte ROM using

diode matrix.
• Diodes are physically fabricated in the required positions
during manufacturing of the memory chip.
• Presence of diode indicates binary ‘1’.
• Absence of diode indicates binary ‘0’
The 4 locations where data is stored is addressed using a 2
to 4 line decoder. Whenever the OE line is enabled a data is read
out.
• When address is ‘00’: Row 1 is selected: here data stored is
‘01011010’
• When address is ‘01’: Row 2 is selected: here data stored is
‘10101110’
• When address is ‘10’: Row 3 is selected: here data stored is
‘10111001’
• When address is ‘11’: Row 4 is selected: here data stored is
‘00101010’

Digital Electronics V-9

Unit V Storage devices and logic families
5.2.4 EPROM (Erasable Programmable Read Only Memory)
• EPROM is Erasable Programmable read only memory.
• We can read and write data into this memory.
• Customer can write a program into this memory n number of
times.
• It needs a separate EPROM equipment with uv rays to
erase the program.

Fig 5.14

Fig 5.15

• It is a non-volatile memory.
• So it can retain the data even when the power is switched
off.
• A EPROM stores data that are often changed in an
applications.
• Write and erase operation are performed on byte basis.
Digital Electronics V-12
Unit V Storage devices and logic families
• This allows data to be written or erased in blocks. This
makes flash memory faster.
• Flash basic element is a floating gate transistor.
• The operation of flash is based on a process of removing
(erase) or putting (program) electrons on the floating gate.
• Charge on floating gate indicates a 0 or a 1.
• When electrons are present on the floating gate, no current
flows through the transistor, indicating logic 0.
• When electrons are removed from the floating gate, current
flows through the transistor, indicating logic 1.
• The process of forcing electrons to/from floating gate is
achieved by applying a voltage between a control gate and
source or drain.
Flash array configuration

Fig 5.15

• WL (word line) is the horizontal line

• BL (bit line) is the vertical line.
• Control gates are connected to WL, where the decoded
address is applied.
• BL connects drains together and represent data bus,
• SL connects sources to common ground.
Digital Electronics V-14
Unit V Storage devices and logic families
• The voltage combination applied to WL and BL define an
operation: read, erase or program.

Fig 5.16

Flash Memory Advantages

• Non-volatile memory
• Easily portable (e.g. USB memory sticks, camera flash
cards, etc)
• Mechanically robust
Flash Memory Disadvantages
• Higher cost per bit than hard drives
• Slower than other forms of memory
• Limited number of write / erase cycles
• Data must be erased before new data can be written
• Data typically erased and written in blocks

5.2.7 RAM (RANDOM ACCESS MEMORY)

RAM is primary memory used for temporary storage and
current processing of program, data and processed data.
This memory is volatile.

It is classified into two categories:

1. Static RAM – flip flops are used as storing elements.
2. Dynamic RAM – capacitors are used as storing elements.

Digital Electronics V-15

Unit V Storage devices and logic families
5.2.8 ORGANIZATION OF RAM
• Generally there are number of locations in a memory chip.
• Each location stores one word.
• The following image shows an 8 bit register as a 1D RAM
array.
• The entire register is selected with 1 select line and 1 R/W
line.

Fig 5.17

RAM ORGANIZATION [complete structure]

The basic structure of a SRAM memory is shown below:

Fig 5.18

• The entire memory is arranged in the form of an array

• The size of the memory is specified by two numbers M and
N as MxN bits.
• M specifies the number of locations available in the memory.
• N is the number of bits at each location.
Digital Electronics V-16
Unit V Storage devices and logic families
• For example, the IC type 7489 is a 16 by 4 RAM chip.
• M is 16 and N is 4.
• So it can store up to 16 words, and each word is 4 bits long.
• To address the row and columns we need address decoding
circuits.
• These translates the data address into the physical location
of a particular word either to put the data on to the data
output pins (read process) or to receive data from the data
input pins (write process).
• Read and write processes is also called as data fetch and
data load respectively.
• I4I3I2I1 are the data input lines and D4D3 D2 D1 is the data
output lines.
• The write enable line when low enables write operation and
• when high enables read operation
Expanding memory size
We need to expand the memory for the following two reasons.
1. To increase the word size (number of bits in each memory
location).
2. To increase the memory capacity (number of locations).
Expanding word size
The word size or the number of bits in the data lines can be
expanded by connecting two or more ICs together. For example 2
ICs can be cascaded to read or write 8 bits.
For this:
• The address lines of each chip are connected together.
• The data lines of each chip are connected together.
• The RD, WR and CS signals are connected together.
• When CS = 1 IC1 is selected and when CS = 0 IC2 is selected
• Out of 8-bits, the first 4-bits are taken from IC1 and the next 4-
bits are taken from IC2.
Digital Electronics V-17
Unit V Storage devices and logic families
• To prevent this, DRAM requires an external memory
refresh circuit which periodically rewrites the data in the
capacitors, restoring them to their original charge.
• DRAM is volatile memory.
• The DRAM cells are organized in a square collection of
capacitors, typically 1024 by 1024 cells.
• When a cell is in the “read” state, an entire row is read out and
the refresh is written back.
• When in a “write” state, a whole row is “read” out, one value is
changed, and then the whole row is rewritten.
• DRAM’s access time is around 60 nanoseconds.

DRAM read / write operation

• Transistor acts as a switch
• The R/W line, the row line, the refresh line is HIGH.
• The transistor turns on, connecting the capacitor to the bit line.
• The output buffer is enabled, and the stored data bit is applied to
the input of the refresh buffer.

Fig 5.23

Digital Electronics V-21

Unit V Storage devices and logic families

Fig 5.24

There are several lines that are used in the read and write
operations:
• CAS, the Column Address Strobe: This line selects the
column to be addressed. The address inputs enables a row
for read or write operations.
• OE, Output Enable: The OE signal is used to control
multiple memory chips in parallel.
• RAS, the Row Address Strobe: This line selects the row
to be addressed.
• WE, Write Enable: This signal when Low enables the write
action, while high enables a read action.
Refresh operation:
1. To enable the Refresh operation, R/𝑊𝑊 line, ROW line and
REFRESH line are made HIGH.
2. The transistor is turned ON and the capacitor is connected
to COLUMN line.
3. As R/𝑊𝑊 is HIGH, the output buffer is enabled and the stored
data bit is applied to the input of the refresh buffer.

Digital Electronics V-22

Unit V Storage devices and logic families
4. The output of the refresh buffer either ‘0’ or ‘1’ is applied to
the COLUMN line and this maintains the charge on the
capacitor.
Advantages
• Less cost
• Simple
• More dense so less space
Disadvantages
• Volatile
• Needs refreshing
• Less speed
• Complex circuitry
Difference between static RAM and Dynamic RAM

Sl.No. Static RAM Dynamic RAM

1 Less densely packed More densely packed
so more space so less space
2 Fast Slow
3 Flip flops as memory Capacitor charge as memory
4 No refreshing needed refreshing needed
5 Less cost More cost

Compare RAM and ROM

Sl.
RAM ROM
No.
1. RAM stands for Random ROM stands for Read Only
Access Memory Memory
2. Temporary storage Permanent storage
3. Store data in MBs Store data in GBs
4. Volatile Non volatile
Digital Electronics V-23
Unit V Storage devices and logic families
It should be clear that when A13 = 1, the roles of RAM A and RAM B
are reversed. RAM ‘B’ is now enabled and the lines A12 – A0 select
one of its location. Thus the range of addresses located in RAM ‘B’
is from 2000H to 3FFFH.

CACHE MEMORY
If the active part of the program and data can be kept in fast
memory, the total execution time can be reduced significantly. Such
memory is known as cache memory, which is inserted between the
CPU and the main memory.
The data or contents of the main memory that are used frequently by
CPU are stored in the cache memory so that the processor can
easily access that data in a shorter time. Whenever the CPU needs
to access memory, it first checks the cache memory. If the data is
not found in cache memory, then the CPU moves into the main
memory.

Cache memory is placed between the CPU and the main memory.
The block diagram for a cache memory can be represented as:

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Unit V Storage devices and logic families
OPERATION
• When the CPU needs to access memory, the cache is
examined. If the word is found in the cache, it is read from the
fast memory.
• If the word addressed by the CPU is not found in the cache, the
main memory is accessed to read the word.
• A block of words one just accessed is then transferred from
main memory to cache memory. The block size may vary from
one word (the one just accessed) to about 16 words adjacent to
the one just accessed.
• The performance of the cache memory is frequently measured
in terms of a quantity called hit ratio.
• When the CPU refers to memory and finds the word in cache, it
is said to produce a hit.
• If the word is not found in the cache, it is in main memory and it
counts as a miss.
• The ratio of the number of hits divided by the total CPU
references to memory (hits plus misses) is the hit ratio.
Advantages:
1. Improved system performance.
2. Faster access time
3. Reduced memory latency.

Disadvantages:
1. Limited capacity
2. Complex.

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Unit V Storage devices and logic families
ASSOCIATIVE MEMORY
Associative memory is also known as content addressable memory
(CAM) or associative storage or associative array. It is a special type
of memory that is optimized for performing searches through data,
as opposed to providing a simple direct access to the data based on
the address.
In conventional memory, data is stored in specific locations, called
addresses, and retrieved by referencing those addresses. In
associative memory, data is stored together with additional tags or
metadata that describe its content. When a search is performed, the
associative memory compares the search query with the tags of all
stored data, and retrieves the data that matches the query.
Associative memory is designed to quickly find matching data, even
when the search query is incomplete or imprecise. This is achieved
by using parallel processing techniques, where multiple search
queries can be performed simultaneously. The search is also
performed in a single step, as opposed to conventional memory
where multiple steps are required to locate the data.

Fig 5.26

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Unit V Storage devices and logic families
Argument Register: It contains words to be searched. It contains ‘n’
number of bits.
Match Register: It has m-bits, One bit corresponding to each word in
the memory array. After the making process, the bits corresponding
to matching words in match register are set to ‘1’.
Key Register: It provides a mask of choosing a particular field/key in
argument register. It specifies which part of the argument word need
to be compared with words in memory.
Associative Memory Array: It combines word in that are to be
compared with the arguments word in parallel. It contains ‘m’ words
with ‘n’ bit per word.
Applications of Associative memory:
It is mainly used in
• memory allocation format.
• database management systems
• Networking
• Image processing
• Artificial intelligence
Advantages of Associative memory :
• It is used where search time needs to be less or short.
• It is suitable for parallel searches.
• It is often used to speedup databases.
• It is used in page tables used by the virtual memory
• It is used in neural networks.
Disadvantages of Associative memory:
• It is more expensive

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