DS1482

1-Wire Level Shifter and Line Driver

with Load Sensor
www.maxim-ic.com

FEATURES PIN ASSIGNMENT

® ®
Works with All iButtons and 1-Wire VCCQ 1 16 VCC
Devices N.C. 2 15 N.C.
Communicates at Regular and Overdrive 1- SPU 3 14 PCTLZ
Wire Speed (Host-Dependent) START 4 13 DONE

Separate Interface Power Supply to Level TXD 5 12 RXD

N.C. 6 11 N.C.
Shift to Non-5V Systems
GND 7 10 I/O
External Strong-Pullup Control Pin can be
N.C. 8 9 N.C.
Used to Provide Low-On-Resistance-High
Current Power Source
Load Sensor to Detect when Strong-Pullup
Power Delivery is no Longer Needed ORDERING INFORMATION
Power Delivery DONE Signal can be DS1482S SO-16
Connected to Host Interrupt DS1482S/T&R SO-16, Tape-and-Reel
Low-Cost 16-Pin SO Surface-Mount Package Contact the factory for versions with different
Operating Temperature Range: -40°C to signal polarities.
+85°C

DESCRIPTION
The DS1482 is a simple 1-Wire line driver with load sensor and level shifter, designed to function as an
interface between a 3V host system and a 1-Wire system that runs on 5V. Two supplies are provided, a
5V supply for the 1-Wire operations (VCC) and an interface supply (VCCQ). The DS1482 can connect
directly to a synchronous serial port if it supports the appropriate bit rates to generate 1-Wire timing.

Figure 1 shows the DS1482 block diagram. TXD is buffered and controls an N-channel transistor, which
drives the 1-Wire pin I/O low, e.g., to initiate a time slot. The logic level of the I/O pin is returned
through a level-shifting buffer to the RXD pin for the host processor to read. Figure 3 shows the
relationship of these signals in case of a 1-Wire read time slot.

The SPU input generates a control signal (PCTLZ) for an external low-impedance PMOS transistor
(Figure 2) that bypasses the 1-Wire pullup resistor (RPUP) to provide power for 1-Wire devices with a
high-load current. PCTLZ is gated by the inverted TXD signal. This prevents a high through-current in
case TXD and SPU are high at the same time.

The DS1482 contains a high-precision comparator because it is important for the host micro to know
when the high load on the 1-Wire side is no longer active. As shown in Figure 4, the high current load
causes a small drop of the voltage on the I/O pin. The comparator detects when the high current phase
ends, and enables DONE after the deglitching time tCF is over. The START signal allows the host micro
to selectively enable DONE.
iButton and 1-Wire are registered trademarks of Dallas Semiconductor.

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 DS1482
PIN NAME FUNCTION
Operating voltage for all circuitry that connects to the controlling
1 VCCQ
microprocessor (TXD, RXD, START, SPU, DONE pins).
This line is used to control the external strong pullup function. When SPU is
3 SPU low, the strong pullup (PCTLZ) is high. When SPU is high and TXD is low,
PCTLZ is low.
This line acts as an enable control for the DONE pin. If START is high, then
4 START DONE reflects the filtered digital output of the current-sense comparator. If
START is low, then DONE is low.
When TXD is low, the I/O pin is pulled resistively to VCC. When TXD is
5 TXD high, the 1-Wire bus is pulled to GND (for write-0, write-1, read, and reset
low times).
7 GND Ground Reference for VCCQ, VCC, 1-Wire
10 I/O 1-Wire Data
This line returns the digital state of the 1-Wire bus, level-shifted to swing
12 RXD
between VCCQ and GND.
This line is high only when the buffered, filtered digital output from the
13 DONE current-sense comparator indicates that the downstream 1-Wire slave device
is no longer sinking high current. This signal is enabled if START is high.
Active-low control pin for an external low-on-resistance, high-current
14 PCTLZ supply. This signal typically controls the gate of a P-channel MOSFET. This
signal is low when SPU is high and TXD is low.
Operating voltage for all circuitry that connects to the 1-Wire environment
16 VCC
(I/O and PCTLZ pins).
2, 6, 8, 9,
N.C. Not Connected
11, 15

Figure 1. Block Diagram

LEVEL-SHIFT BOUNDARY

VCCQ VCC

RPUP

RXD I/O

TXD

GND

+
DONE - Vref

START
PCTLZ
SPU

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 DS1482
Figure 2. Typical Operating Circuit
VCC = 5V Selecting RS
RS Assuming that the series resistance of the FET in
on-condition can be neglected, the value of RS is
VCCQ = 3.3V IRLMS6702 limited as follows:
RSmax = 0.0015 x VCCmin/I(standby,max)
RSmin = 0.01 x VCCmax/I(active,min)

Example:
VCC PCTLZ VCCmin = 4.5V, VCCmax = 5.5V
(21) VCCQ VCCQ I(standby,max) = 0.15mA
SH7622 DS1482 I(active,min) = 12mA
µC
(164) TxD0 TXD I/O RSmax = 45Ω, RSmin = 4.58Ω
(171) RxD0 RXD 1-Wire
(32) PTA0 SPU To maximize available power on the 1-Wire line,
NETWORK
(31) PTA1 START RS should be close to the lowest permissible
(178) IRQ7 DONE value, in this example 5.1Ω ±5%. The effect of the
GND on-chip pullup resistor is negligible.

Figure 3. DS1482 Application Signals, Normal Communication

TXD H
L

I/O H
L

RXD H
L

SPU, START, DONE ALL LOW

Figure 4. DS1482 Application Signals, Strong Pullup Case

TXD H
L

I/O H
L

RXD H
L

SPU H
L

PCTLZ H
L

3
1 2
CURRENT
tCF
DONE H
L

4 H
START
L

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 DS1482
Point 1: The 1-Wire slave device starts drawing current (internal micro or numeric processor is
running). The strong pullup (SPU) must be activated before the high current phase begins.
Point 2: The 1-Wire slave device no longer draws current. After the deglitching time (tCF) is over, the
DONE signal turns high. The START signal must be activated no later than tSD before tCF is
over. Typically START is activated shortly after SPU, but not before the 1-Wire slave device
has started drawing high current.
Point 3: As soon as the DONE signal is high, the host micro ends the strong pullup by changing SPU
to low.
Point 4: While the DONE signal is high, the host micro changes START to low; this may occur
simultaneously with the state change of SPU or later. When START changes to low, DONE
becomes low.

Figure 5. Timing References TXD to I/O

0.7 x VCCQ
TXD
0.2 x VCCQ

tTI tTI

0.9 x VCC
I/O
0.1 x VCC
tFIO

Figure 6. Timing References I/O to RXD

0.7 x VCC
I/O
0.2 x VCC

tIR tIR

0.9 x VCCQ

RXD
0.1 x VCCQ
tF tR

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 DS1482
Figure 7. Timing References SPU to PCTLZ

0.7 x VCCQ
SPU
0.2 x VCCQ

tSP tSP

0.9 x VCC
PCTLZ
0.1 x VCC
tF tR

Figure 8. Timing References START to DONE

START
0.2 x VCCQ

tSD

0.9 x VCCQ
DONE
0.1 x VCCQ
tR tF

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 DS1482
ABSOLUTE MAXIMUM RATINGS*
Voltage to GND (All Pins) -0.5V, +6.0V
Combined Source/Sink Current (All Pins) 20mA
Operating Temperature Range -40°C to +85°C
Junction Temperature +150°C
Storage Temperature Range -55°C to +125°C
Lead Temperature (Soldering) See IPC/JEDEC 020A

* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.

ELECTRICAL CHARACTERISTICS
(VCC = 4.5V to 5.5V, VCCQ = 3.0V to 3.6V; TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current ICC 150 µA
Supply Current ICCQ 100 µA
Supply Ramp-up VCC, VCCQ rising from 0
Time (System tRCC to VCCMIN and VCCQMIN, 0.1 µs
Requirement) respectively
1-Wire Pullup
RPUP 850 1650 Ω
Resistor
INPUT PINS SPU, START, TXD
Input High Voltage VIH 0.7 x VCCQ V
Input Low Voltage VIL 0.2 x VCCQ V
Measured with either 0V
Input Leakage ILP or VCCQ on the pin 3 µA
(Note 1)
No DC load on I/O; see
Delay TXD to I/O tTI 100 ns
Figure 5 (Note 2)
I/O PIN (1-WIRE)
Output Low Voltage VOL 100μA load 0.4 V
Output High Voltage VOH No DC load VCC V
Pin Leakage Current ILP (Note 3) -1 +1 µA
Input High Voltage VIH 0.7 x VCC V
Input Low Voltage VIL 0.2 x VCC V
Comparator 0.995 x 0.998 x
VREF 0.99 x VCC VCC VCC V
Reference Voltage
Output Fall Time
tFIO 0.9 x VCC to 0.1 x VCC 45 150 ns
(50pF Load)

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 DS1482
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OUTPUT PIN RXD
Output-Low Voltage VOL 100µA load 0.4 V
Output-High Voltage VOH -100µA load VCCQ - 0.5V V
Output Rise Time
tR 0.1 x VCCQ to 0.9 x VCCQ 50 ns
(50pF Load)
Output Fall Time
tF 0.9 x VCCQ to 0.1 x VCCQ 50 ns
(50pF Load)
Delay I/O to RXD
tIR See Figure 6 (Note 2) 100 ns
(50pF Load)
OUTPUT PIN PCTLZ
Output-Low Voltage VOL 100µA load 0.4 V
Output-High Voltage VOH -100µA load VCC - 0.5V V
Output Rise Time
tR 0.1 x VCC to 0.9 x VCC 50 ns
(50pF Load)
Output Fall Time
tF 0.9 x VCC to 0.1 x VCC 50 ns
(50pF Load)
Delay SPU to PCTLZ
tSP See Figure 7 (Note 4) 100 ns
(50pF Load)
OUTPUT PIN DONE
Output-Low Voltage VOL 100µA load 0.4 V
Output-High Voltage VOH -100µA load VCCQ - 0.5V V
Output Rise Time
tR 0.1 x VCCQ to 0.9 x VCCQ 50 ns
(50pF Load)
Output Fall Time
tF 0.9 x VCCQ to 0.1 x VCCQ 50 ns
(50pF Load)
Delay I/O to DONE
tCF START at VCCQ (Note 5) 128 500 µs
(50pF Load)
Delay START to
tSD See Figure 8 100 ns
DONE (50pF Load)

Note 1: The input pins have a weak pulldown.

Note 2: For OD read- or write-1 time slots, TXD should be pulsed high for 1.28µs. The window for
sampling RXD begins 1.8µs after TXD has turned high and ends 2.05µs after TXD has turned
high. RXD must be sampled inside this window. Correct sampling can be achieved with the
particular recommended microcontroller Hitachi SH7622 if the peripheral module operating
frequency PΦ is higher or equal to 22MHz.
Note 3: Measured either with VCC on the pin and TXD low or with 0V on the pin and TXD high. This
parameter is guaranteed by design, and is not production tested.
Note 4: The PCTLZ signal is gated by TXD. The PCTLZ output is only low if TXD is low.
Note 5: Characteristic of the glitch-eating filter on the output of the load-sensing comparator, i.e., an
event where the downstream 1-Wire slave device is sinking high current, ceases sinking the
current for less than this amount of time, and resumes sinking the current does not generate
high level on DONE; DONE goes high this amount of time after the downstream 1-Wire slave
device has ceased sinking high current.

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