Deld Notes

Unit - I
Boolean algebra
Another approach is to express the logic function with logic equations. This is done with the use of Boolean
algebra (named after Boole, a 19th century mathematician). In Boolean algebra, all the variables have the values
0 or 1 and, in typical formulations, there are three operators:
• The OR operator is written as +, as in A+ B. The result of an OR operator is 1 if either of the variables is

1. The OR operation is also called a logical sum, since its result is 1 if either operand is 1.
• The AND operator is written as , as in . The result of an AND operator is 1 only if both inputs are 1. The
AND operator is also called logical product, since its result is 1 only if both operands are 1.
• The unary operator NOT is written as. The result of a NOT operator is 1 only if the input is 0. Applying
the operator NOT to a logical value results in an inversion or negation of the value (i.e., if the input is 0
the output is 1, and vice versa).
There are several laws of Boolean algebra that are helpful in manipulating logic equations.
• Identity law: A+0 =A and A . 1= A.

• Zero and One laws: A+1 =A and A.0=0.
• Inverse laws: A+A` = 1and A.A`=0.
• Commutative laws: A + B = B + A and A.B=B.A .
• Associative laws: A+(B+C) = (A+B)+C and A.(B.C) =(A.B).C
• Distributive laws: A.(B+C) =(A.B)+ (A.C)and A+(B.C) =(A+B). (A+C)
In addition, there are two other useful theorems, called DeMorgan’s laws,
Any set of logic functions can be written as a series of equations with an output on the left-hand side of each
equation and a formula consisting of variables and the three operators above on the right-hand side.
FORMAL PROOF OF DEMORGAN'S THEOREMS
DeMorgan's Theorems:
a. (A + B) = A* B
b. A*B = A + B
Note: * = AND operation
Proof of DeMorgan's Theorem (b):

For any theorem X=Y, if we can show that X Y = 0, and that X + Y = 1, then by the complement postulates, A A = 0
and A + A = 1, X = Y. By the uniqueness of the complement, X = Y. Thus the proof consists of showing that
(A*B)*(A + B) = 0; and also that (A*B) + ( A + B) = 1.
Prove: (A*B)*( A + B) =0
(A*B)*( A + B) = (A*B)*A + (A*B)*B) by distributive postulate
= (A*A)*B + A*(B*B) by associativity postulate
= 0*B + A*0 by complement postulate
= 0+0 by nullity theorem
= 0 by identity theorem
(A*B)*( A + B) = 0 Q.E.D.
2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 16

Positive Logic and Negative Logic system:
A digital bit of information (0 or 1) can be represented by a voltage leveling a d.c (or level logic) system. A
binary information can have any one of the two possible states. Logic level 1 or logic level 0
If more positive voltage is taken as the 1 level and the other as the 0 level, the logic system is known as the
positive logic system.
If more negative voltage is taken to represent the 1 level and the other for the 0 level, the logic system is known
as negative logic system.
V (0) = 5 volt V (1) = 0 volt
Logic gate
A logic gate is an idealized or physical device implementing a Boolean function, that is, it performs a logical
operation on one or more logic inputs and produces a single logic output. Depending on the context, the term
may refer to an ideal logic gate, one that has for instance zero rise time and unlimited fan-out, or it may refer to
a non-ideal physical device.
Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but can also be
constructed using electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even
mechanical elements.
Digital systems are said to be constructed by using logic gates. These gates are the AND, OR, NOT, NAND, NOR,
EXOR and EXNOR gates.
NOT gate (inverter)

• The output Q is true when the input A is NOT true, the output is the inverse of the input: Q = NOT A
• A NOT gate can only have one input. A NOT gate is also called an inverter.
Input A Output Q
0 1
1 0
Traditional symbol IEC symbol Truth Table
AND gate
• The output Q is true if input A AND input B are both true: Q = A AND B
• An AND gate can have two or more inputs, its output is true if all inputs are true.
• A dot (.) is used to show the AND operation i.e. A.B.
Input A Input B Output Q

0 0 0
0 1 0
1 0 0
1 1 1

NAND gate (NAND = Not AND)
• This is an AND gate with the output inverted, as shown by the 'o' on the output.
• The output is true if input A AND input B are NOT both true: Q = NOT (A AND B)
• A NAND gate can have two or more inputs; its output is true if NOT all inputs are true.

0 0 1
0 1 1
1 0 1
1 1 0
OR gate
• The output Q is true if input A OR input B is true (or both of them are true): Q = A OR B
• An OR gate can have two or more inputs, its output is true if at least one input is true.
• A plus (+) is used to show the OR operation.

0 0 0
0 1 1
1 0 1
1 1 1
NOR gate (NOR = Not OR)

• This is an OR gate with the output inverted, as shown by the 'o' on the output.
• The output Q is true if NOT inputs A OR B are true: Q = NOT (A OR B)
• A NOR gate can have two or more inputs; its output is true if no inputs are true.

0 0 1
0 1 0
1 0 0
1 1 0
EX-OR (EXclusive-OR) gate

• The output Q is true if either input A is true OR input B is true, but not when both of them are true:
Q = (A AND NOT B) OR (B AND NOT A)
• This is like an OR gate but excluding both inputs being true.
• The output is true if inputs A and B are DIFFERENT.
EX-OR gates can only have 2 inputs.
• An encircled plus sign (⊕) is used to show the EOR operation.

0 0 0
0 1 1
1 0 1
1 1 0
EX-NOR (EXclusive-NOR) gate

• This is an EX-OR gate with the output inverted, as shown by the 'o' on the output.
• The output Q is true if inputs A and B are the SAME (both true or both false):
Q = (A AND B) OR (NOT A AND NOT B)
• EX-NOR gates can only have 2 inputs.

0 0 1
0 1 0
1 0 0
1 1 1
Table: Logic gate symbols
Summary truth tables

The summary truth tables below show the output states for all types of 2-input and 3-input gates.

Summary for all 2-input gates Summary for all 3-input gates
Inputs Output of each gate Inputs Output of each gate
A B AND NAND OR NOR EX-OR EX-NOR A B C AND NAND OR NOR
0 0 0 1 0 1 0 1 0 0 0 0 1 0 1
0 1 0 1 1 0 1 0 0 0 1 0 1 1 0
1 0 0 1 1 0 1 0 0 1 0 0 1 1 0
1 1 1 0 1 0 0 1 0 1 1 0 1 1 0
1 0 0 0 1 1 0
1 0 1 0 1 1 0
1 1 0 0 1 1 0
1 1 1 1 0 1 0

Universal Gates
Universal gates are the ones which can be used for implementing any gate like AND, OR and NOT, or any
combination of these basic gates; NAND and NOR gates are universal gates. To facilitate the conversion to
NAND and NOR logic, we have two new graphic symbols for these gates.
NAND Gate NOR Gate
NAND gate equivalents
The table below shows the NAND gate equivalents of NOT, AND, OR and NOR gates:
Gate Equivalent in NAND gates
NOT
AND
OR
NOR
Implementation of AND, OR, NOT using NAND

Implementation of AND, OR, NOT using NOR
Canonical form
• In Boolean algebra, any Boolean function can be expressed in a canonical form using the dual concepts
of minterms and maxterms.
• Minterms are called products because they are the logical AND of a set of variables, and maxterms are
called sums because they are the logical OR of a set of variables.
• These concepts are called duals because of their complementary-symmetry relationship as expressed by
De Morgan's laws, which state that AND(x,y,z,...) = NOR(x',y',z',...) and OR(x,y,z,...) = NAND(x',y',z',...)
• The dual canonical forms of any Boolean function are a "sum of minterms" and a "product of maxterms."
• The term "Sum of Products" or "SoP" is widely used for the canonical form that is a disjunction (OR) of
minterms.
• Its De Morgan dual is a "Product of Sums" or "PoS" for the canonical form that is a conjunction (AND)
of maxterms.
Minterms
For a boolean function of variables , a product term in which each of the variables appears
once (in either its complemented or uncomplemented form) is called a minterm. Thus, a minterm is a logical
expression of n variables that employs only the complement operator and the conjunction operator.
For example, , and are 3 examples of the 8 minterms for a Boolean function of the three variables
, and . The customary reading of the last of these is a AND b AND NOT-c.
There are 2n minterms of n variables, since a variable in the minterm expression can be in either its direct or its
complemented form—two choices per n variables.
Indexing minterms
In general, one assigns each minterm an index based on a conventional binary encoding of the complementation
pattern of the variables (where the variables in all the minterms are written in the same order, usually
alphabetical). This convention assigns the value 1 to the direct form ( ) and 0 to the complemented form ( ).
For example, we assign the index 6 to the minterm (110) and denote that minterm as . Similarly, of
the same three variables is (000), and is (111).
Functional equivalence

It is apparent that minterm n gives a true value (i.e., 1) for just one combination of the input variables. For
example, minterm 5, a b' c, is true only when a and c both are true and b is false—the input arrangement where
a = 1, b = 0, c = 1 results in 1.
If one is given a truth table of a logical function, it is possible to write the function as a "sum of products". This is
a special form of disjunctive normal form. For example, if given the truth table for the arithmetic sum bit u of
one bit position's logic of an adder circuit, as a function of x and y from the addends and the carry in, ci:
ci x y u(ci,x,y)
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Observing that the rows that have an output of 1 are the 2nd, 3rd, 5th, and 8th, we can write u as a sum of
minterms and . If we wish to verify this: u(ci, x, y) = = (ci' x' y) +
(ci' x y') + (ci x' y') + (ci x y) evaluated for all 8 combinations of the three variables will match the table.
Maxterms
For a boolean function of variables , a sum term in which each of the variables appears once
(in either its complemented or uncomplemented form) is called a maxterm. Thus, a maxterm is a logical
expression of n variables that employs only the complement operator and the disjunction operator. Maxterms
are a dual of the minterm idea (i.e., exhibiting a complementary symmetry in all respects). Instead of using
ANDs and complements, we use ORs and complements and proceed similarly.
For example, the following are two of the eight maxterms of three variables:
a+b'+c a'+b+c
There are again 2n maxterms of n variables, since a variable in the maxterm expression can also be in either its
direct or its complemented form—two choices per n variables.
Indexing maxterms
Each maxterm is assigned an index based on the opposite conventional binary encoding used for minterms. The
maxterm convention assigns the value 0 to the direct form and 1 to the complemented form . For
example, we assign the index 6 to the maxterm (110) and denote that maxterm as M6. Similarly M0
of these three variables is (000) and M7 is (111).
Functional equivalence
It is apparent that maxterm n gives a false value (i.e., 0) for just one combination of the input variables. For
example, maxterm 5, a' + b + c', is false only when a and c both are true and b is false—the input arrangement
where a = 1, b = 0, c = 1 results in 0.
If one is given a truth table of a logical function, it is possible to write the function as a "product of sums". This is
a special form of conjunctive normal form. For example, if given the truth table for the carry-out bit co of one bit
position's logic of an adder circuit, as a function of x and y from the addends and the carry in, ci:

ci x y co(ci,x,y)
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Observing that the rows that have an output of 0 are the 1st, 2nd, 3rd, and 5th, we can write co as a product of
maxterms and . If we wish to verify this: co(ci, x, y) = = (ci + x + y) (ci + x + y') (ci
+ x' + y) (ci' + x + y) evaluated for all 8 combinations of the three variables will match the table.
Dualization
The complement of a minterm is the respective maxterm. This can be easily verified by using de Morgan's law.
For example:
Example: Obtain the truth table for a combinational circuit that accepts a three bit ‘number and generates an
output binary number equal to the square of the input number.
Ans. Truth table is as shown for inputs and the corresponding square outputs.

Karnaugh Maps
Introduction
• Simplification of Boolean functions is mainly used to reduce the gate count of a design. Less number of
gates means less power consumption, sometimes the circuit works faster and also when number of
gates is reduced, cost also comes down.
• There are many ways to simplify a logic design, some of them are given below.
o Algebraic Simplification.
Simplify symbolically using theorems/postulates.
Requires good skills
o Karnaugh Maps.
Diagrammatic technique using 'Venn-like diagram'.
Limited to no more than 6 variables.
• The Karnaugh map provides a simple and straight-forward method of minimizing Boolean expressions.
• With the Karnaugh map Boolean expressions having up to four and even six variables can be simplified.
• A Karnaugh map provides a pictorial method of grouping together expressions with common factors
and therefore eliminating unwanted variables.
• Each square represents either a minterm or maxterm. A K-map of n variables will have 2 squares. For a
Boolean expression, product terms are denoted by 1's, while sum terms are denoted by 0's - but 0's are
often left blank.
• A K-map consists of a grid of squares, each square representing one canonical minterm combination of
the variables or their inverse. The map is arranged so that squares representing minterms which differ
by only one variable are adjacent both vertically and horizontally.
Minimization Technique
• Based on the Unifying Theorem: X + X' = 1
• The expression to be minimized should generally be in sum-of-product form (If necessary, the
conversion process is applied to create the sum-of-product form).
• The function is mapped onto the K-map by marking a 1 in those squares corresponding to the terms in
the expression to be simplified (The other squares may be filled with 0's).
• Pairs of 1's on the map which are adjacent are combined using the theorem Y(X+X') = Y where Y is any
Boolean expression
• The minimization procedure consists of recognizing those pairs and multiple pairs.
o These are circled indicating reduced terms.
o Groups which can be circled are those which have two (21) 1's, four (22) 1's, eight (23) 1's, and
so on.
o Note that because squares on one edge of the map are considered adjacent to those on the
opposite edge, group can be formed with these squares.
o Groups are allowed to overlap.
• The objective is to cover all the 1's on the map in the fewest number of groups and to create the largest
groups to do this.
• Once all possible groups have been formed, the corresponding terms are identified.
o A group of two 1's eliminates one variable from the original minterm.
o A group of four 1's eliminates two variables from the original minterm.
o A group of eight 1's eliminates three variables from the original minterm, and so on.
o The variables eliminated are those which are different in the original minterms of the group.

TWO VARIABLE MAP
• In any K-Map, each square represents a minterm. Adjacent squares always differ by just one literal (So
that the unifying theorem may apply: X + X' = 1).
• For the 2-variable case (e.g.: variables X, Y), the map can be drawn as below. Two variable map is the
one which has got only two variables as input.
The diagram below illustrates the correspondence between the Karnaugh map and the truth table for the
general case of a two variable problem.
The values inside the squares are copied from the output column of the truth table, therefore there is one
square in the map for every row in the truth table. Around the edge of the Karnaugh map are the values of the
two input variable. A is along the top and B is down the left hand side. The diagram below explains this:
The values around the edge of the map can be thought of as coordinates. So as an example, the square on the top
right hand corner of the map in the above diagram has coordinates A=1 and B=0. This square corresponds to
the row in the truth table where A=1 and B=0 and F=1. Note that the value in the F column represents a
particular function to which the Karnaugh map corresponds.
Example
X'Y+XY F= X'Y+XY+XY'
F=Y F=X+Y

3-Variable K-Map
• There are 8 minterms for 3 variables (X, Y, Z). Therefore, there are 8 cells in a 3-variable K-map.
• One important thing to note is that K-maps follow the gray code sequence, not the binary one.
• Using gray code arrangement ensures that minterms of adjacent cells differ by only ONE literal.
• Each cell in a 3-variable K-map has 3 adjacent neighbors. In general, each cell in an n-variable K-map
has n adjacent neighbors.
There is wrap-around in the K-map
• X'Y'Z' (m0) is adjacent to X'YZ' (m2)

• XY'Z' (m4) is adjacent to XYZ' (m6)
Example
F = XYZ'+XYZ+X'YZ F(X,Y,Z) = (1,3,4,5,6,7)
F = XY + YZ

4-Variable K-Map
There are 16 cells in a 4-variable (W, X, Y, Z); K-map as shown in the figure below.
There are 2 wrap-around: a horizontal wrap-around and a vertical wrap-around. Every cell thus has 4
neighbours. For example, the cell corresponding to minterm m0 has neighbours m1, m2, m4 and m8.
Example
F(W,X,Y,Z) = (1,5,12,13) F(W,X,Y,Z) = (4, 5, 10, 11, 14, 15)
F = WY'Z + W'Y'Z F = W'XY' + WY

5-Variable K-Map
There are 32 cells in a 5-variable (V, W, X, Y, Z); K-map as shown in the figure below.
Inverse Function
• The 0's on a K-map indicate when the function is 0.
• We can minimize the inverse function by grouping the 0's (and any suitable don't cares) instead of the 1's.
• This technique leads to an expression which is not logically equivalent to that obtained by grouping the
1's (i.e., the inverse of X != X').
• Minimizing for the inverse function may be particularly advantageous if there are many more 0's than 1's
on the map.
• We can also apply De Morgan's theorem to obtain a product-of-sum expression.
Example: Reduce the following expression to minimum cost SOP and write the corresponding VHDL code.
f(a, b, c, d) = ∑ m (5, 6, 9, 10, 12, 13, 14, 15) + d(2, 4)
Solution.
cd 00 01 11 10
ab
00 x
01 x 1 1
11 1 1 1 1
10 1 1
F = b. c’ + c . d + a . b + a . c’. d
VHDL code:
library ieee;
use ieee.std_logic_1164.all;
entity FN is
port (a, b, c, d :in STD_LOGIC_VECTOR(15 DOWNTO 0);
f :out STD_LOGIC_VECTOR(15 DOWNTO 0);
end FN;
architecture FN_ARC of FN is
begin
f<= (b and not c) or ( c and d) or ( a and b) or( a and not c and d);
end FN_ARC;

Introduction to VHDL
Basic Constructs
• VHDL (VHSIC hardware description language) is a hardware description language used in electronic
design automation to describe digital and mixed-signal systems such as field-programmable gate arrays
and integrated circuits.
• VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by
a synthesis program, only if it is part of the logic design.
• A simulation program is used to test the logic design using simulation models to represent the logic
circuits that interface to the design. This collection of simulation models is commonly called a testbench.
• VHDL has file input and output capabilities, and can be used as a general-purpose language for text
processing, but files are more commonly used by a simulation testbench for stimulus or verification
data.
• One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE, Altera Quartus,
Synopsys Synplify or Mentor Graphics HDL Designer) to produce the RTL schematic of the desired
circuit.
• A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a
programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured,
rather than the VHDL code being "executed" as if on some form of a processor chip.
• VHDL uses reserved keywords that cannot be used as signal names or identifiers. Keywords and user-
defined identifiers are case insensitive.
• Lines with comments start with two adjacent hyphens (--) and will be ignored by the compiler.
• VHDL also ignores line breaks and extra spaces.
• VHDL is a strongly typed language which implies that one has always to declare the type of every
object that can have a value, such as signals, constants and variables.
Advantages
• The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required
system to be described (modeled) and verified (simulated) before synthesis tools translate the design
into real hardware (gates and wires).
• Another benefit is that VHDL allows the description of a concurrent system. VHDL is a dataflow
language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run
sequentially, one instruction at a time.
• VHDL project is multipurpose. Being created once, a calculation block can be used in many other
projects. However, many formational and functional block parameters can be tuned (capacity
parameters, memory size, element base, block composition and interconnection structure).
Building block
The basic building block of a VHDL model is the entity
An entity is described as a set of design units:

• entity declaration
• architecture body
• package declaration
• package body
• configuration declaration
Basic Structure of a VHDL file

• A digital system in VHDL consists of a design entity that can contain other entities that are then
considered components of the top-level entity.
• Each entity is modeled by an entity declaration and an architecture body.

• One can consider the entity declaration as the interface to the outside world that defines the input and
output signals,
• while the architecture body contains the description of the entity and is composed of interconnected
entities, processes and components, all operating concurrently, as schematically shown in Figure below.
Figure: A VHDL entity consisting of an interface (entity declaration) and a body (architectural description).
a. Entity Declaration
The entity declaration defines the NAME of the entity and lists the input and output ports. The general form
is as follows,
entity NAME_OF_ENTITY is [ generic generic_declarations);]
port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [NAME_OF_ENTITY] ;
An entity always starts with the keyword entity, followed by its name and the keyword is. Next are the
port declarations using the keyword port. An entity declaration always ends with the keyword end,
optionally [] followed by the name of the entity.
• The NAME_OF_ENTITY is a user-selected identifier

• signal_names consists of a comma separated list of one or more user-selected identifiers that
specify external interface signals.
• mode: is one of the reserved words to indicate the signal direction:
o in – indicates that the signal is an input
o out – indicates that the signal is an output of the entity whose value can only be read by
other entities that use it.
o buffer – indicates that the signal is an output of the entity whose value can be read inside
the entity’s architecture
o inout – the signal can be an input or an output.
• type: a built-in or user-defined signal type. Examples of types are bit, bit_vector, Boolean, character,
std_logic, and std_ulogic.
o bit – can have the value 0 and 1
o bit_vector – is a vector of bit values (e.g. bit_vector (0 to 7)
o std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can have 9 values to indicate the
value and strength of a signal. Std_ulogic and std_logic are preferred over the bit or
bit_vector types.
o boolean – can have the value TRUE and FALSE
o integer – can have a range of integer values
o real – can have a range of real values
o character – any printing character
o time – to indicate time

• generic: generic declarations are optional and determine the local constants used for timing and
sizing (e.g. bus widths) the entity. A generic can have a default value. The syntax for a generic
follows,
generic (
constant_name: type [:=value] ;
constant_name: type [:=value] ;
:
constant_name: type [:=value] );
Example:
entity BUZZER is
port (DOOR, IGNITION, SBELT: in std_logic;
WARNING: out std_logic);
end BUZZER;
a. Architecture body
The architecture body specifies how the circuit operates and how it is implemented. An entity or circuit can be
specified in a variety of ways, such as behavioral, structural (interconnected components), or a combination of
the above.
The architecture body looks as follows,
architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
:
begin
-- Statements
:
end architecture_name;
Behavioral model
The architecture example, described at the behavioral level, is given below,
architecture behavioral of BUZZER is

begin
WARNING <= (not DOOR and IGNITION) or (not SBELT and IGNITION);
end behavioral;
The header line of the architecture body defines the architecture name, e.g. behavioral, and associates it with
the entity, BUZZER. The architecture name can be any legal identifier. The main body of the architecture starts
with the keyword begin and gives the Boolean expression of the function.
The “<= ” symbol represents an assignment operator and assigns the value of the expression on the right to the
signal on the left. The architecture body ends with an end keyword followed by the architecture name.
A few other examples follow. The behavioral description of a two-input AND gate is shown below.
entity AND2 is
port (in1, in2: in std_logic;

out1: out std_logic);
end AND2;
architecture behavioral_2 of AND2 is

begin
out1 <= in1 and in2;
end behavioral_2;
An example of a two-input XNOR gate is shown below.

entity XNOR2 is
port (A, B: in std_logic;
Z: out std_logic);
end XNOR2;
architecture behavioral_xnor of XNOR2 is

-- signal declaration (of internal signals X, Y)
signal X, Y: std_logic;
begin
X <= A and B;
Y <= (not A) and (not B);
Z <= X or Y;
End behavioral_xnor;
Concurrency
It is worth pointing out that the signal assignments in the above examples are concurrent statements. This
implies that the statements are executed when one or more of the signals on the right hand side change their
value (i.e. an event occurs on one of the signals).
For instance, when the input A changes, the internal signals X and Y change values that in turn causes the last
statement to update the output Z. There may be a propagation delay associated with this change.
Digital systems are basically data-driven and an event which occurs on one signal will lead to an event on
another signal, etc. The execution of the statements is determined by the flow of signal values. As a result, the
order in which these statements are given does not matter (i.e., moving the statement for the output Z ahead of
that for X and Y does not change the outcome). This is in contrast to conventional, software programs that
execute the statements in a sequential or procedural manner.
The following example illustrates it.

architecture structural of BUZZER is
-- Declarations
component AND2
end component;
component OR2
end component;
component NOT1
port (in1: in std_logic;
end component;
-- declaration of signals used to interconnect gates
signal DOOR_NOT, SBELT_NOT, B1, B2: std_logic;

begin
-- Component instantiations statements
U0: NOT1 port map (DOOR, DOOR_NOT);
U1: NOT1 port map (SBELT, SBELT_NOT);
U2: AND2 port map (IGNITION, DOOR_NOT, B1);
U3: AND2 port map (IGNITION, SBELT_NOT, B2);
U4: OR2 port map (B1, B2, WARNING);
end structural;
Following the header is the declarative part that gives the components (gates) that are going to be used in the
description of the circuits. In our example, we use a two- input AND gate, two-input OR gate and an inverter.
These gates have to be defined first, i.e. they will need an entity declaration and architecture body. These can be
stored in one of the packages one refers to in the header of the file. The declarations for the components give
the inputs (e.g. in1, in2) and the output (e.g. out1). Next, one has to define internal nets (signal names). In our
example these signals are called DOOR_NOT, SBELT_NOT, B1, B2.
The statements after the begin keyword gives the instantiations of the components and describes how these are
interconnected. A component instantiation statement creates a new level of hierarchy. Each line starts with an
instance name (e.g. U0) followed by a colon and a component name and the keyword port map. This keyword
defines how the components are connected. In the example above, this is done through positional association:
DOOR corresponds to the input, in1 of the NOT1 gate and DOOR_NOT to the output. Similarly, for the AND2 gate
where the first two signals (IGNITION and DOOR_NOT) correspond to the inputs in1 and in2, respectively, and
the signal B1 to the output out1. An alternative way is to use explicit association between the ports, as shown
below.
label: component-name port map (port1=>signal1, port2=> signal2,… port3=>signaln);
U0: NOT1 port map (in1 => DOOR, out1 => DOOR_NOT);
U1: NOT1 port map (in1 => SBELT, out1 => SBELT_NOT);
U2: AND2 port map (in1 => IGNITION, in2 => DOOR_NOT, out1 => B1);
U3: AND2 port map (in1 => IGNITION, in2 => SBELT_NOT, B2);
U4: OR2 port map (in1 => B1, in2 => B2, out1 => WARNING);

Unit - II

What is Programmable Logic?
In the world of digital electronic systems, there are three basic kinds of devices: memory,
microprocessors, and logic. Memory devices store random information such as the contents of a spreadsheet or
database. Microprocessors execute software instructions to perform a wide variety of tasks such as running a
word processing program or video game. Logic devices provide specific functions, including device-to-device
interfacing, data communication, signal processing, data display, timing and control operations, and almost
every other function a system must perform.
Programmable Logic Devices

• The logic functions performed by each 7400-series device s fixed internally, i.e. it cannot be modified to
suit a particular design.
• Also, each chip contains only a few logic gates, which makes them inefficient for building large circuits.
• Programmable Logic Devices (PLDs) contain a relatively large amount of logic circuitry with a structure
that is not fixed.
• It can be considered as a "black box“ that contains logic gates and programmable switches which allow
the gates inside the device to be connected together to implement a specific logic circuit.
• Like the classification of standard chips (LSI, MSI, etc.) there are number of different classifications for
PLDS depending on their internal structures.
Fixed Logic Versus Programmable Logic
Logic devices can be classified into two broad categories - fixed and programmable. As the name
suggests, the circuits in a fixed logic device are permanent, they perform one function or set of functions - once
manufactured, they cannot be changed. On the other hand, programmable logic devices (PLDs) are standard,
off-the-shelf parts that offer customers a wide range of logic capacity, features, speed, and voltage
characteristics - and these devices can be changed at any time to perform any number of functions.
With programmable logic devices, designers use inexpensive software tools to quickly develop,
simulate, and test their designs. Then, a design can be quickly programmed into a device, and immediately
tested in a live circuit. The PLD that is used for this prototyping is the exact same PLD that will be used in the
final production of a piece of end equipment, such as a network router, a DSL modem, a DVD player, or an
automotive navigation system.
Another key benefit of using PLDs is that during the design phase customers can change the circuitry as
often as they want until the design operates to their satisfaction. That's because PLDs are based on re-writable
memory technology - to change the design, the device is simply reprogrammed. Once the design is final,
customers can go into immediate production by simply programming as many PLDs as they need with the final
software design file.

The main differences in programmable devices are between:
• mask-programmable and field-programmable
• erasable and non-erasable
The mask-programmable types are programmed when they are manufactured whereas the user sets up
the field-programmable device with some form of programmer. Mask-programmable devices are expensive in
low production runs but are relatively cheap for large production runs, which is opposite for the field-
programmable devices. An erasable device allows the stored set-up to be changed whereas the non-erasable
type is permanent.

Programmable Logic Array (PLA)
A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational
logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate
planes, which can then be conditionally complemented to produce an output. This layout allows for a large
number of logic functions to be synthesized in the sum of products (and sometimes product of sums) canonical
forms.
The first developed PLD was the programmable logic array (PLA). Based on the idea that logic functions can be
realized in sum-of products form, a PLA comprises a collection of AND gates that feeds a set of OR gates.
In commercially available PLAs, several methods of realizing the programmable connections exist.
• One of the simplest technologies utilizes fuses.
• Programming the PLA involves blowing the fuses along the paths that must be removed in order to obtain the
desired logic function.
• Like the classification of standard chips (LSI, MSI, etc.) there are number of different classifications for PLDS
depending on their internal structures.
• A typical PLA may have hundreds to thousands of gates.

• In order to show the internal logic diagram for such technologies in a concise form, a special gate symbol is
used for array logic.
• The following figure shows a PLA with 3 inputs, four product terms, and two outputs.
• Each connection to the AND gates is programmable.
• A signal connected to a gate is indicated by an X at the crossing of a vertical and horizontal line.

Programmable Array Logic (PAL)
Programmable switches within the PLA introduce two problems:

• they are hard to fabricate correctly;
• they reduced the speed/performance of circuits using PLAs.
• These drawbacks led to the development of a similar device, the PAL, in which the AND plane is
programmable but the OR plane is fixed.
• PALs are simpler to manufacture, and offer better performance, however are less flexible in their
programmability.
• A PAL can be used to implement designs which would require 100-200 individual gates

Complex Programmable Devices (CPLDs)
• Circuits implemented using PLAs and PALs are limited to fairly modest sizes, typically the total number of
inputs and outputs is less than 32.
• For circuits requiring more inputs and/or outputs, either multiple PLAs or PALs are used or a more
sophisticated type of chip, called a Complex Programmable Device (CPLD), can be employed.
• CPLD can be used to implement designs which would require up to 20,000 individual gates.

FPGA
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a

designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified
using a hardware description language (HDL), similar to that used for an application-specific integrated circuit
(ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is
increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform. The ability
to update the functionality after shipping, partial re-configuration of a portion of the design[1] and the low non-
recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer
advantages for many applications.
FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable
interconnects that allow the blocks to be "wired together"—somewhat like many (changeable) logic gates that
can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex
combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also
include memory elements, which may be simple flip-flops or more complete blocks of memory.
For circuits which require an even larger numberof individual gates (>20,000), FPGA technology issued.
• An FPGA is a programmable device that supports the implementation of relatively large logic circuits.
• Rather than AND and OR planes, it provides logic blocks for implementing the required functions.
• The logic blocks are arranged in a two-dimensional array and the interconnection wires are organized as
horizontal and vertical routing channels between the rows and columns of blocks.
• The channels contain programmable switches that allow the logic blocks to be interconnected.
• For circuits requiring more inputs and/or outputs, either multiple PLAs or PALs are used or a more
sophisticated type of chip, called a Complex Programmable Device (CPLD), can be employed.
• FPGAs can be used to implement logic circuits which would require more than a hundred thousand equivalent
gates.
• Two examples of FPGAs are the Altera FLEX 10K and the Xilinx XC4000.
• Each logic block within the FPGA typically has a small number of inputs and one output.
• The most commonly used logic block is a lookup table (LUT)which contains storage (memory) cells that are
used to implement a small logic function.
• Each cell is capable of storing a single value, either 0 or 1.

What is the difference between an FPGA and CPLD?
The two major types of programmable logic devices are field programmable gate arrays (FPGAs) and complex
programmable logic devices (CPLDs). Of the two, FPGAs offer the highest amount of logic density, the most
features, and the highest performance. CPLDs, by contrast, offer much smaller amounts of logic - up to about
10,000 gates. But CPLDs offer very predictable timing characteristics and are therefore ideal for critical control
applications. FPGAs and CPLDs are both programmable logic. However the main difference lies in the
architecture of the chips.
CPLDs have several programmable PLDs which are interconnected via a programmable connections at the
global interconnection matrix.

FPGAs on the other hand have individual logic blocks - each block can be programmed to implement a logic
function such as AND, OR, NOT etc. These blocks are then connected via programmable switches to implement
complete logic functions.
Compare the FPGA way of programming individual AND, OR, NOT logic functions and then putting them
together to implement a complete logic function, to the CPLD way of programming several complete logic
functions at once on inividual PLDs and then bringing these PLDs together via programmable connections.

Unit – III
Combinational logic
In digital circuit theory, combinational logic (sometimes also referred to as combinatorial logic) is a type of
digital logic which is implemented by boolean circuits, where the output is a pure function of the present input
only. This is in contrast to sequential logic, in which the output depends not only on the present input but also
on the history of the input. In other words, sequential logic has memory while combinational logic does not.
Combinational logic is used in computer circuits to do boolean algebra on input signals and on stored data.
Practical computer circuits normally contain a mixture of combinational and sequential logic. For example, the
part of an arithmetic logic unit, or ALU, that does mathematical calculations is constructed using combinational
logic. Other circuits used in computers, such as half adders, full adders, half subtractors, full subtractors,
multiplexers, demultiplexers, encoders and decoders are also made by using combinational logic.

Binary Addition
Binary Addition follows the same basic rules as for the denary addition above except in binary there are only
two digits and the largest digit is "1", so any "SUM" greater than 1 will result in a "CARRY". This carry 1 is passed
over to the next column for addition and so on. Consider the single bit addition below.
The single bits are added together and "0 + 0", "0 + 1", or "1 + 0" results in a sum of "0" or "1" until you get to "1
+ 1" then the sum is equal to "2". For a simple 1-bit addition problem like this, the resulting carry bit could be
ignored which would result in an output truth table resembling that of an Ex-OR Gate as seen in the Logic Gates
section and whose result is the sum of the two bits but without the carry.
An Ex-OR gate only produces an output "1" when either input is at logic "1", but not both. However, all
microprocessors and electronic calculators require the carry bit to correctly calculate the equations so we need
to rewrite them to include 2 bits of output data as shown below.
From the above equations we know that an Ex-OR gate will only produce an output "1" when "EITHER" input is
at logic "1", so we need an additional output to produce a carry output, "1" when "BOTH" inputs "A" and "B" are
at logic "1" and a standard AND Gate fits the bill nicely. By combining the Ex-OR gate with the AND gate results
in a simple digital binary adder circuit known commonly as the "Half Adder" circuit.

The Half Adder Circuit
The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal
represents an overflow into the next digit of a multi-digit addition. The value of the sum is 2C + S. The simplest
half-adder design, incorporates an XOR gate for S and an AND gate for C. With the addition of an OR gate to
combine their carry outputs, two half adders can be combined to make a full adder.
S (X,Y) = (1,2)
S = X'Y + XY'
S = X⊕Y
CARRY(X,Y) = (3)
CARRY = XY
From the truth table we can see that the SUM (S) output is the result of the Ex-OR gate and the Carry-out (Cout)
is the result of the AND gate.
One major disadvantage of the Half Adder circuit when used as a binary adder, is that there is no provision for a
"Carry-in" from the previous circuit when adding together multiple data bits. For example, suppose we want to
add together two 8-bit bytes of data, any resulting carry bit would need to be able to "ripple" or move across the
bit patterns starting from the least significant bit (LSB). The most complicated operation the half adder can do is
"1 + 1" but as the half adder has no carry input the resultant added value would be incorrect. One simple way to
overcome this problem is to use a Full Adder type binary adder circuit.
Half Adder using NAND gates:

VHDL code for Half Adder:
library ieee;
entity bejoy_ha is
port (a, b : in bit ;
s, c : out bit);
end bejoy_ha;
architecture arc of bejoy_ha is

begin
s<= a xor b;
c <= a and b;
end arc;

The Full Adder Circuit
The main difference between the Full Adder and Half Adder is that a full adder has three inputs, the same two
single bit binary inputs A and B as before plus an additional Carry-In (C-in) input as shown below.
Full Adder with Carry-In
The 1-bit Full Adder circuit above is basically two half adders connected together and consists of three Ex-OR
gates, two AND gates and an OR gate, six logic gates in total. The truth table for the full adder includes an
additional column to take into account the Carry-in input as well as the summed output and carry-output. But
what if we wanted to add together two n-bit numbers, then n 1-bit full adders need to be connected together to
produce what is known as the Ripple Carry Adder.
SUM (X,Y,Z) = ∑(1,2,4,7)
CARRY (X,Y,Z) =∑ (3,5,6,7)
Kmap-SUM Kmap-CARRY
SUM = X'Y'Z + XY'Z' + X'YZ'

CARRY = XY + XZ + YZ
SUM = X Y Z
A full adder can be implemented in many different ways such as with a custom transistor-level circuit or
composed of other gates. One example implementation is with and
.
In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without
altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using
simple IC chips which contain only one gate type per chip. In this light, Cout can be implemented as
.

A full adder can be constructed from two half adders by connecting A and B to the input of one half adder,
connecting the sum from that to an input to the second adder, connecting Ci to the other input and OR the two
carry outputs. Equivalently, S could be made the three-bit XOR of A, B, and Ci, and Cout could be made the three-
bit majority function of A, B, and Ci.
Full Adder using NAND gates:
VHDL code for FULL ADDER:
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
PORT ( Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ) ;
END fulladd ;
ARCHITECTURE beh OF fulladd IS

BEGIN
s <= x XOR y XOR Cin ;
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END beh ;

Half subtractor
The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs,
X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).
Symbol Logic diagram for a half subtractor
Truth table
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
So, Logic equations are:
VHDL Code for Half-Subtractor:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hs1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
diff : out STD_LOGIC;
borrow : out STD_LOGIC);
end hs1;
architecture Behavioral of hs1 is

begin
diff<=a xor b;
borrow<=(not a) and b;
end Behavioral;

Full subtractor
The full-subtractor is a combinational circuit which is used to perform subtraction of three bits. It has three
inputs, X (minuend) and Y (subtrahend) and Z (subtrahend) and two outputs D (difference) and B (borrow).
D=X-Y-Z (don't bother about sign)
B = 1 If X<(Y+Z)
Symbol
Truth table
The truth table for the full subtractor is given below.

x y z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
D = X'Y'Bin + X'YBin' + XY'Bin' + XYBin

= (X'Y' + XY)Bin + (X'Y + XY')Bin'
= (X Y)'Bin + (X Y)Bin'
= X Y Bin
Bout = X'.Y + X'.Bin + Y.Bin
From the above expression, we can draw the circuit below. If you look carefully, you will see that a full-
subtractor circuit is more or less same as a full-adder with slight modification.

Design of full subtractor using NAND gates.
VHDL code for Full Subtractor :
library ieee;
entity bejoy_fs is
port(x,y,bi: in bit; b2,do,bo: out bit; d,b: inout bit);
end bejoy_fs;
architecture arc of bejoy_fs is

begin
d<=x xor y;
b<=x and (not y);
do<=bi xor d;
b2<=bi and (not b);
end arc;

The 4-bit Binary Adder
Ripple carry adder circuit.
Multiple full adder circuits can be cascaded in parallel to add an N-bit number. For an N- bit parallel adder, there
must be N number of full adder circuits. A ripple carry adder is a logic circuit in which the carry-out of each full
adder is the carry in of the succeeding next most significant full adder. It is called a ripple carry adder because
each carry bit gets rippled into the next stage. In a ripple carry adder the sum and carry out bits of any half
adder stage is not valid until the carry in of that stage occurs. Propagation delays inside the logic circuitry is the
reason behind this. Propagation delay is time elapsed between the application of an input and occurrence of the
corresponding output. Consider a NOT gate, When the input is “0″ the output will be “1″ and vice versa. The
time taken for the NOT gate’s output to become “0″ after the application of logic “1″ to the NOT gate’s input is
the propagation delay here. Similarly the carry propagation delay is the time elapsed between the application of
the carry in signal and the occurance of the carry out (Cout) signal. Circuit diagram of a 4-bit ripple carry adder
is shown below.
VHDL code for 4 bit binary ripple adder(behavioral model):
library IEEE;
entity adder1 is
port( num1 : in std_logic_vector(3 downto 0);
num2 : in std_logic_vector(3 downto 0);
sum : out std_logic_vector(3 downto 0);
carry : out std_logic );
end adder1;
--architecture of entity
architecture Behavioral of adder1 is
--temporary signal declarations(for intermediate carry's).

signal c0,c1,c2,c3 : std_logic := '0';
begin
--first full adder

sum(0) <= num1(0) xor num2(0); --sum calculation
c0 <= num1(0) and num2(0); --carry calculation
--second full adder

sum(1) <= num1(1) xor num2(1) xor c0;

c1 <= (num1(1) and num2(1)) or (num1(1) and c0) or (num2(1) and c0);
--third full adder

--fourth(final) full adder

--final carry assignment

carry <= c3;
end Behavioral;
VHDL code for 4 bit binary ripple adder(structural model):
library ieee;
-- definition of a full adder

entity FULLADDER is
port (a, b, c: in std_logic;
sum, carry: out std_logic);
end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
end fulladder_behav;
-- 4-bit adder
library ieee;
entity FOURBITADD is
port (a, b: in std_logic_vector(3 downto 0);
Cin : in std_logic;
sum: out std_logic_vector (3 downto 0);
Cout, V: out std_logic);
end FOURBITADD;
architecture fouradder_structure of FOURBITADD is

signal c: std_logic_vector (4 downto 0);
component FULLADDER
port(a, b, c: in std_logic;
sum, carry: out std_logic);
end component;
begin
FA0: FULLADDER
port map (a(0), b(0), Cin, sum(0), c(1));
FA1: FULLADDER
port map (a(1), b(1), C(1), sum(1), c(2));

FA2: FULLADDER
port map (a(2), b(2), C(2), sum(2), c(3));
FA3: FULLADDER
port map (a(3), b(3), C(3), sum(3), c(4));
V <= c(3) xor c(4);
Cout <= c(4);
end fouradder_structure;

The Multiplexer
A data selector, more commonly called a Multiplexer, shortened to "Mux" or "MPX", are combinational logic
switching devices that operate like a very fast acting multiple position rotary switch. They connect or control,
multiple input lines called "channels" consisting of either 2, 4, 8 or 16 individual inputs, one at a time to an
output. Then the job of a multiplexer is to allow multiple signals to share a single common output. For example,
a single 8-channel multiplexer would connect one of its eight inputs to the single data output. Multiplexers are
used as one method of reducing the number of logic gates required in a circuit or when a single data line is
required to carry two or more different digital signals.
2-to-1 Mux (Selector):
• 2n-1:multiplexer can implement any function of n variables

• n-1 control variables; remaining variable is a data input to the mux
4-to-1 Channel Multiplexer
The Boolean expression for this 4-to-1 Multiplexer above with inputs A to D and data select lines a, b is given
as:

Q = abA + abB + abC + abD
In this example at any one instant in time only ONE of the four analogue switches is closed, connecting only one
of the input lines A to D to the single output at Q. As to which switch is closed depends upon the addressing
input code on lines "a" and "b", so for this example to select input B to the output at Q, the binary input address
would need to be "a" = logic "1" and "b" = logic "0". Adding more control address lines will allow the multiplexer
to control more inputs but each control line configuration will connect only ONE input to the output.
Then the implementation of this Boolean expression above using individual logic gates would require the use of
seven individual gates consisting of AND, OR and NOT gates as shown.
4 Channel Multiplexer using Logic Gates
Cascading Muxes
Using 2-to-1 Muxes to build a 4-to-1 Mux A 16-to-1 16 to Mux/Selector

Practical application of Muxes
Synthesis of Logic Functions using Multiplexers:
(A) Implementation using a 4-to-1 multiplexer
(B) Implementation using a 2-to-1 multiplexer
C)Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1)

D) Implementation of the three-input majority function using a 4-to-1 multiplexer
E) Three-input XOR implemented with 2-to-1 multiplexers
F) Three-input XOR function implemented with a 4-to-1 multiplexer
G) Implement using 4 x 1 MUX

H) Multiplexer Synthesis Using Shannon’s Expansion
f = w1’w2w3+w1w2’w3+w1w2’w3+w1w2w3
= w1’(w2w3)+w1(w2’w3+w2w3’+w2w3)
= w1’(w2w3)+w1(w2+w3)
Shannon’s Expansion Theorem

16
I) Implement half adder circuit using 4 : 1 MUX or multiplexers only.
H) How many select lines are there for a 30 to 1 MUX?
For 30: 1 MUX, 5 select lines are required. 4 select lines are for 16 : 1 MUX’s and 1 select line for 2: 1 MUX. =
M formula is used. Where n = number of select lines and M are the number of inputs for a MUX.
= 32.Thus, 5 select lines are needed.
I) Function implementation using 8x1multiplexer
F(A,B,C,D) = S(1,3,4,11,12,13,14,15)
1. Complete the truth table from the SOP.
2. The first n – 1 variables in the table are applied to the selection inputs of the multiplexer.
3. For each combination of the selection variables, we evaluate the output as a function of the last variable.
4. Apply these values to the data input in proper order.
VHDL Code for 16x1 Mux using 4x1 Mux:
Library ieee;
use ieee.std_logic_arith.all;
entity 4x1mux1 is
port(a, b, c, d : in std_logic;
s0, s1 : in std_logic;
q : out std_logic);
end 4x1mux1;
Architecture 4x1mux1 of 4x1mux1 is

Begin
Process(a,b,c,d,s0,s1)

Begin
if s0 ='0' and s1 ='0' then q <= a;
elsif s0 ='1' and s1 ='0' then q <= b;
elsif s0 ='0' and s1='1' then q <= c;
else q <=d;
end if;
End process;
End 4x1mux1;
Ma i n p r o gr a m:
Library ieee;
use ieee.std_logic_arith.all;
entity 16x1mux is
port(a: in std_logic_vector(15 downto 0);
s: in std_logic_vector(3 downto 0);
Z: o u t s t d _ lo gic ) ;
E n d 1 6x 1 mu x ;
A rc h it e c tu re 1 6 x1 m ux1 o f 1 6x 1 m ux is
s ign a l z 1 , z 2 , z 3 , z 4 : s t d_ l o gic ;
component kanhe_4x1mux is
port(a,b,c,d,s0,s1:in std_logic;
Q:out std_logic);
E n d c o m po n e n t ;
Begin
M 1 : kanhe_4x1mux p o rt m a p ( a (0 ) , a (1 ) , a( 2 ) , a(3 ) , s (0 ) , s( 1 ) , z1 ) ;
m 2 : kanhe_4x1mux po rt m a p ( a (4 ) , a (5 ) , a( 6 ) , a(7 ) , s (0 ) , s( 1 ) , z2 ) ;
m 3 : kanhe_4x1mux po rt m a p ( a (8 ) , a (9 ) , a( 1 0) , a( 1 1) , s (0 ) , s (1 ) , z3 ) ;
m 4 : kanhe_4x1mux po rt m a p ( a (1 2 ) , a( 13 ) , a (1 4) , a ( 15 ) , s( 0 ) , s( 1) , z 4 ) ;
m 5 : kanhe_4x1mux po rt m a p ( z 1 , z 2 , z3 , z 4 , s( 2 ) ,s ( 3 ) , z) ;
E n d 1 6x 1 mu x 1 ;

The Demultiplexer
The data distributor, known more commonly as a Demultiplexer or "Demux", is the exact opposite of the
Multiplexer. The demultiplexer takes one single input data line and then switches it to any one of a number of
individual output lines one at a time. The demultiplexer converts a serial data signal at the input to a parallel
data at its output lines as shown below.
1-to-4 Channel De-multiplexer
The Boolean expression for this 1-to-4 Demultiplexer above with outputs A to D and data select lines a, b is
given as: F = ab A + abB + abC + abD
The function of the Demultiplexer is to switch one common data input line to any one of the 4 output data lines
A to D in our example above. As with the multiplexer the individual solid state switches are selected by the
binary input address code on the output select pins "a" and "b" and by adding more address line inputs it is
possible to switch more outputs giving a 1-to-2n data line outputs.
How can a DEMUX be used as a decoder?

Ans. The selection lines of the DEMUX can be used as input lines of decoder and if the data input of the
demultiplexer is used as the enable input of the decoder then we can use the demultiplexer as a decoder.
Decoders
One logic block that we will use in building larger components is a decoder. The most common type of decoder
has an n-bit input and 2n outputs, where only one output is asserted for each input combination. This decoder
translates the n-bit input into a signal that corresponds to the binary value of the n-bit input. The outputs are
thus usually numbered, say, Out0, Out1, . . . , Out2n– 1. If the value of the input is i, then Outi will be true and all
other outputs will be false.
A binary decoder converts coded inputs into coded outputs, where the input and output codes are different and
decoders are available to "decode" either a Binary or BCD (8421 code) input pattern to typically a Decimal
output code.
n-to-2n binary decoder
2-to-4 Binary Decoders

2-to-4-line DECODER with Enable
The decoder is enabled when E = 0. The output whose value = 0 represents the minterm is selected by inputs A
and B.
The decoder is inactive when E = 1à D0 …D3 = 1
A Decoder with enable input is called a decoder/demultiplexer. Demultiplexer receives information from a
single line and directs it to the output lines.
VHDL code of a 2 to 4 binary decoder:

LIBRARY ieee ;
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END dec2to4 ;
ARCHITECTURE Behavior OF dec2to4 IS

SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= “1000″ WHEN “100″,
“0100″ WHEN “101″,
“0010″ WHEN “110″,
“0001″ WHEN “111″,
“0000″ WHEN OTHERS ;
END Behavior ;
In this simple example of a 2-to-4 line binary decoder, the binary inputs A and B determine which output line
from D0 to D3 is "HIGH" at logic level "1" while the remaining outputs are held "LOW" at logic "0" so only one
output can be active (HIGH) at any one time. Therefore, whichever output line is "HIGH" identifies the binary
code present at the input, in other words it "de-codes" the binary input and these types of binary decoders are
commonly used as Address Decoders in microprocessor memory applications
3-to-8 Binary Decoders

Figure shows a 3-bit decoder and the truth table. This decoder is called a 3-to-8 decoder since there are 3 inputs
and 8 (23) outputs. There is also a logic element called an encoder that performs the inverse function of a
decoder, taking 2n inputs and producing an n-bit output.

Example: Implement the following function using 3 to 8 decoder
Solution.
Example: 3-to-8 decoder using two 2-to-4 decoders
Example: 4-to-16 decoder built using a decoder tree

Example: 4-to-1 multiplexer built using a decoder
Example : 4-to-1 multiplexer built using a decoder and tri-state buffers
Example: Full-Adder using Decoder

Example: 4 x 16 Decoder using 3 X 8 decoder
• When w = 0, the top decoder is enabled and the bottom is disabled. Top decoder generates 8 minterms 0000 to
0111, while the bottom decoder outputs are 0’s.
• When w = 1, the top decoder is disabled and the bottom is enabled. Bottom decoder generates 8 minterms
1000 to 1111, while the top decoder outputs are 0’s.
List the applications of decoders.
Ans. 1 Decoders are used in counter systems

2. Decoders are used for A/D conversion.
3 Decoders are used for D/A conversion
4. Decoders are used in seven segment digital displays.

BCD to 7-Segment Display Decoders
A binary coded decimal (BCD) to 7-segment display decoder , have 4 BCD inputs and 7 output lines, one for each
LED segment. This allows a smaller 4-bit binary number (half a byte) to be used to display all the denary
numbers from 0 to 9 and by adding two displays together, a full range of numbers from 00 to 99 can be
displayed with just a single byte of 8 data bits.

The Digital Encoder
Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or
switch, a Digital Encoder more commonly called a Binary Encoder takes ALL its data inputs one at a time and
then converts them into a single encoded output. So we can say that a binary encoder, is a multi-input
combinational logic circuit that converts the logic level "1" data at its inputs into an equivalent binary code at its
output. Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon the number of
data input lines. An "n-bit" binary encoder has 2n input lines and n-bit output lines with common types that
include 4-to-2, 8-to-3 and 16-to-4 line configurations. The output lines of a digital encoder generate the binary
equivalent of the input line whose value is equal to "1" and are available to encode either a decimal or
hexadecimal input pattern to typically a binary or B.C.D. output code.
4-to-2 Bit Binary Encoder
One of the main disadvantages of standard digital encoders is that they can generate the wrong output code
when there is more than one input present at logic level "1". For example, if we make inputs D1 and D2 HIGH at
logic "1" at the same time, the resulting output is neither at "01" or at "10" but will be at "11" which is an output
binary number that is different to the actual input present. Also, an output code of all logic "0"s can be
generated when all of its inputs are at "0" OR when input D0 is equal to one.
One simple way to overcome this problem is to "Prioritise" the level of each input pin and if there was more
than one input at logic level "1" the actual output code would only correspond to the input with the highest
designated priority. Then this type of digital encoder is known commonly as a Priority Encoder or P-encoder
for short.
Priority Encoders
Priority Encoders solve the problem mentioned above by allocating a priority level to each input. The encoder
output corresponds to the currently active input with the highest priority. So when an input with a higher
priority is present, all other inputs with a lower priority will be ignored. Priority encoders come in many forms
with an example of an 8-input priority encoder along with its truth table shown below.
8-to-3 Bit Priority Encoder

Example. Give significance of priority encoder.
Solution. Priority encoder in a special type of encoder. It has priorities given to the input lines from highest
priority input line to lowest priority input line, If two or more input lines are active i.e. ‘1’ or high at the same
time, then the input line with highest priority will be considered first
The Boolean expression for this 8-to-3 encoder above with inputs D0 to D7 and outputs Q0, Q1, Q2 is given as:
Q0 = D1 + D3 + D5 + D7
Q1 = D2 + D3 + D6 + D7
Q2 = D4 + D5 + D6 + D7
Then the implementation of these Boolean expression outputs above using individual OR gates is as follows.
Digital Encoder using Logic Gates

Arithmetic comparator circuits
• Circuit compares the relative sizes of twobinary numbers
o Three outputs: AeqB, AgtB, AltB
• An n-bit comparator can be designed
o Using a Subtactor circuit
o Using a Truth table
o Too much time consuming
• Considering the bits of A and B in pairs
o using XORs to check for equality
o for greater than, check starting with the MSB, the first place at which A and B are not equal
o less than can be derived from the above two conditions
A one-bit comparator circuit
A four-bit comparator circuit

The vhdl coding for a 4 bit comparator is as follows:-

LIBRARY ieee ;
USE ieee.std_logic_arith.all ;
ENTITY compare IS
PORT ( A, B : IN SIGNED(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END compare ;
ARCHITECTURE Behavior OF compare IS

BEGIN
AeqB <= ’1′ WHEN A = B ELSE ’0′ ;
AgtB <= ’1′ WHEN A > B ELSE ’0′ ;
AltB <= ’1′ WHEN A < B ELSE ’0′ ;
END Behavior ;
Code for 4 bit magnitude comparator (Behavioral style)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY comp4 IS
PORT(A,B:IN BIT_VECTOR(3 DOWNTO 0);
F1,F2,F3:OUT BIT);
END comp4;
ARCHITECTURE behav OF comp4 IS

BEGIN
PROCESS(A,B)
BEGIN
IF(A(3)='0' AND B(3)='1')THEN F3<='1';F2<='0';F1<='0';
ELSIF(A(3)='1' AND B(3)='0')THEN F1<='1';F2<='0';F3<='0';
ELSE
IF(A(2)='0' AND B(2)='1')THEN F3<='1';F2<='0';F1<='0';
ELSE
IF(A(1)='0' AND B(1)='1')THEN F3<='1';F2<='0';F1<='0';
ELSE
IF(A(0)='0' AND B(0)='1')THEN F3<='1';F2<='0';F1<='0';
ELSE
F2<='1';F1<='0';F3<='0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END behav;

Code Conversion
Gray code is a type of unit distance code. In unit distance code the bit patterns for two consecutive numbers will
differ in one bit position. We can also say it as Cyclic codes.
Binary to Gray Code Conversion

Follow the below Steps to convert Binary number to gray code.
Lets Consider The Binary number B1 B2 B3 B4 ... Bn and the Gray code is G1 G2 G3 G4 ... Gn
1. Most significant bit (B1) is same as the most significant bit in Gray Code (B1 = G1)
2. To find next bit perform Ex-OR (Exclusive OR) between the Current binary bit and previous bit.
Gn = Bn (Ex-OR) Bn-1
3. Look the below Image for Binary to Gray code Conversion
Gray Code to Binary Conversion

Follow the below steps to convert Gray Code to Binary
1. Most significant bit (G1) is same as the most significant bit in Binary Code (G1 = B1)
2. The next number can be obtain by taking Exclusive OR operation between the previous binary bit, and
the current gray code bit and write down the value.
Repeat the Above Step until you find Bn
VHDL Code for Gray to Binary conversion
Library ieee;

entity xor2 is
port(a,b:in bit;
y:out bit);
end xor2;
architecture xor2 of xor2 is

begin
y<=a xor b ;
end xor2;
MAIN program
library ieee;
use ieee.std_logic_unsigned.all;
entity kanhe_g_to_bi is
port(b:in std_logic_vector(3 downto 0);
g:out std_logic_vector(3 downto 0));
end kanhe_g_to bi;
architecture struct_g_B of kanhe_g_to_bi is

component kanhe_xor2 is
port(a,b:in bit;y:out bit);
end component;
begin
g(3)<=b(3);
Ga : xor2 port map (b(3),b(2),g(2));
Ga : xor2 port map (b(2),b(1),g(1));
Ga : xor2port map (b(1),b(0),g(0));
End struct_g_B;
Design BCD to Excess-3 code converter
The input variables are BCD’s (A, B, C and D) and output variables are excess-3 code (E3, E2, E1 and E0)
Truth Table
After ‘9’ i.e. 1001 BCD, mark don’t care i.e. ‘X’.
Minimization Using K-map:

For E3 ◊
E3 = A + BD + BS
For E2 ◊
For E0 ◊
For E1 ◊
Implementation of Excess-3 Code Converter:
Example: Design a Gray-to Excess-3 Code converter using NAND gates
Solution: Gray to Excess3 code converter:

K-maps for Excess 3-codes are
Circuit Diagram:

Unit – IV

Introduction
Digital electronics is classified into combinational logic and sequential logic. Combinational logic output depends
on the inputs levels, whereas sequential logic output depends on previous outputs (on stored levels) and also the
input levels. Combinational circuits are fast as compared to sequential circuits since the combinational circuits
do not have any memory elements.
Block Diagram of Sequential circuit
The memory elements are devices capable of storing binary info. The binary info stored in the memory elements
at any given time defines the state of the sequential circuit. The input and the present state of the memory
element determine the output. Memory elements next state is also a function of external inputs and present
state. A sequential circuit is specified by a time sequence of inputs, outputs, and internal states.
Differentiate between sequential and combination circuits.
There are two types of sequential circuits. Their classification depends on the timing of their signals:
• Synchronous sequential circuits

• Asynchronous sequential circuits
Asynchronous sequential circuit

This is a system whose outputs depend upon the order in which its input variables change and can be affected at
any instant of time. Here events can occur after one event is completed and there is no need to wait for a clock
pulse. Therefore they are faster than synchronous sequential circuits.
Gate-type asynchronous systems are basically combinational circuits with feedback paths. Because of the
feedback among logic gates, the system may, at times, become unstable. Consequently they are not often used.

Block diagram of Asynchronous sequential circuit
Synchronous sequential circuits
This type of system uses storage elements called flip-flops that are employed to change their binary value only at
discrete instants of time. Synchronous sequential circuits use logic gates and flip-flop storage devices. Sequential
circuits have a clock signal as one of their inputs. All state transitions in such circuits occur only when the clock
value is either 0 or 1 or happen at the rising or falling edges of the clock depending on the type of memory
elements used in the circuit. Synchronization is achieved by a timing device called a clock pulse generator. Clock
pulses are distributed throughout the system in such a way that the flip-flops are affected only with the arrival of
the synchronization pulse. Synchronous sequential circuits that use clock pulses in the inputs are called clocked-
sequential circuits. They are stable and their timing can easily be broken down into independent discrete steps,
each of which is considered separately.
Figure 3: Rising and falling edges
A clock signal is a periodic square wave that indefinitely switches from 0 to 1 and from 1 to 0 at fixed intervals.
Clock cycle time or clock period: the time interval between two consecutive rising or falling edges of the
clock.
Clock Frequency = 1 / clock cycle time (measured in cycles per second or Hz)
Example:
Clock cycle time = 10ns clock frequency = 100M
Concept of Sequential Logic
A sequential circuit is combinational logic with some feedback to maintain its current value, like a memory cell.
To understand the basics let's consider the basic feedback logic circuit below Figure 4, which is a simple NOT
gate whose output is connected to its input. The effect is that output oscillates between HIGH and LOW (i.e. 1 and
0). Oscillation frequency depends on gate delay and wire delay. Assuming a wire delay of 0 and a gate delay of
10ns, then oscillation frequency would be (on time + off time = 20ns) 50 MHz.

The basic feedback logic circuit
Normally input enable signals can be of two types.
• Level Sensitive or ( LATCH)

• Edge Sensitive or (Flip-Flop)
Level Sensitive: The circuit below is a modification of the above one to have level sensitive enable input. Enable,
when LOW, masks the input S and R. When HIGH, presents S and R to the sequential logic input . Thus Enable,
when HIGH, transfers input S and R to the sequential cell transparently, so this kind of sequential circuits are
called transparent Latch. The memory element we get is an RS Latch with active high Enable.
An RS Latch
Edge Sensitive: The circuit below is a cascade of two level sensitive memory elements, with a phase shift in the
enable input between first memory element and second memory element. The first RS latch (i.e. the first
memory element) will be enabled when CLK input is HIGH and the second RS latch will be enabled when CLK is
LOW. The net effect is input RS is moved to Q and Q' when CLK changes state from HIGH to LOW, this HIGH to
LOW transition is called falling edge. So the Edge Sensitive element we get is called negative edge RS flip-flop.
: An RS Flip-flop
Gated latches and conditional transparency
Latches are designed to be transparent. That is, input signal changes cause immediate changes in output.
Alternatively, additional logic can be added to a simple transparent latch to make it non-transparent or
opaque when another input (e.g., an "enable" input) is not asserted. In digital circuits, a flip-flop is a term
referring to an electronic circuit that has two stable states and thereby is capable of serving as one bit of
computer storage.... can be implemented.
It includes:
1. Gated SR latch
2. Gated D-latch

3. Gated Toggle Latch

Latches
S-R Latch
RS latch have two inputs, S and R. S is called set and R is called reset. The S input is used to produce HIGH on Q (
i.e. store binary 1 in flip-flop). The R input is used to produce LOW on Q (i.e. store binary 0 in flip-flop). Q' is Q
complementary output, so it always holds the opposite value of Q. The output of the S-R latch depends on current
as well as previous inputs or state, and its state (value stored) can change as soon as its inputs change. The
circuit and the truth table of RS latch are shown below.
S R Q Q+
0 0 0 0
0 0 1 1
0 1 X 0
1 0 X 1
1 1 X 0
An S-R Latch
The operation has to be analyzed with the 4 inputs combinations together with the 2 possible previous states.
• When S = 0 and R = 0: If we assume Q = 1 and Q' = 0 as initial condition, then output Q after input is
applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0. Assuming Q = 0 and Q' = 1 as initial condition,
then output Q after the input applied would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. So when both S and
R inputs are LOW, the output is retained as before the application of inputs. (i.e. there is no state
change).
then output Q after the input applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0. So in simple words
when S is HIGH and R is LOW, output Q is HIGH.
then output Q after the input applied would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. So in simple words
when S is LOW and R is HIGH, output Q is LOW.
• When S = 1 and R =1 : No matter what state Q and Q' are in, application of 1 at input of NOR gate always
results in 0 at output of NOR gate, which results in both Q and Q' set to LOW (i.e. Q = Q'). LOW in both the
outputs basically is wrong, so this case is invalid.
The waveform in figure 7 shows the operation of NOR gates based RS Latch.
Figure 7: An RS Latch waveforms
It is possible to construct the RS latch using NAND gates. The only difference is that NAND is NOR gate dual form.
So in this case the R = 0 and S = 0 case becomes the invalid case (NOR based latch inputs are normally 0 and must
be pulsed to the 1 stat 9active HIGH) to change the state of the latch outputs. The circuit and Truth table of RS
latch using NAND is shown in figure 8. This latch is also called as S-R Latch. The NAND latch inputs are normally
1 and must be pulsed to 0 state (active low) to change the flip-flop output state.

Figure 8: An RS Latch using NAND gates Figure 8a: Graphical symbol of NAND based RS Latch
S R Q Q+ Comments
1 1 0 0
No Change
1 1 1 1
0 1 X 0 Reset
1 0 X 1 Set
0 0 X 1 Invalid case
State Diagram

RS Latch with Clock
The circuit in figure 10 shows the level sensitive RS latch. Control signal "Enable" E is used to gate the input S
and R to the RS Latch. When Enable E is HIGH, both the AND gates act as buffers and thus R and S appears at the
RS latch input and it functions like a normal RS latch. When Enable E is LOW, it drives LOW to both inputs of RS
latch. As discussed, when both inputs of a NOR latch are low, values are retained (i.e. the output does not
change).
Figure 9 The graphical symbol for gated SR latch Figure 10: Gated SR latch with NOR and AND gates
The characteristic table for a gated SR latch which describes its behavior is as follows.
The outputs of NAND gates 1 & 2 stay at the logic 1 level as long as the clock input remains at 0. This 1 level at
the inputs of NAND based basic S R latch retains the present state i.e no change occurs. The S & R inputs control
the state of the latch in the same manner as for unclocked S-R flip-flop. However, the latch does not respond to
these inputs until the rising edge of the clock signal occurs. The clock pulse input acts as an enable signal for the
2 inputs.
Figure 11: Gated SR latch with NAND gates
Figure 12 shows an example timing diagram for gated SR latch (assuming negligible propagation delays through
the logic gates). Notice that during the last clock cycle when Clk = 1, both R = 1 and S = 1. So as Clk returns to 0,
the next state will be uncertain. This explains why we need to avoid the setting in the last row of the above
characteristic table in normal operation of a gated SR latch.

Figure 12: An example timing diagram for gated SR latch
An Application of the SR Latch
A common problem involving switches is the occurrence of contact bounce (caused by springiness of the
contacts):
Figure 13: SR latch as contact bounce
A switch debouncer circuit and the corresponding waveforms are shown below:
Figure 14: RS latch as a switch debouncer circuit

D Latch
The RS latch seen earlier contains ambiguous state; to eliminate this condition we can ensure that S and
R are never equal. This is done by connecting S and R together with an inverter. A D latch is like an S-R latch with
only one input: the "D" input. Activating the D input sets the circuit, and de-activating the D input resets the
circuit. Thus we have D Latch: the same as the RS latch, with the only difference that there is only one input,
instead of two (R and S). This input is called D or Data input. D latch is called D transparent latch or data latch, or
gated latch or Delay flip-flop or delay latch
Figure 15: Graphical symbol of D latch

This latch is closely related to the gated SR latch and can be similarly constructed. By adding an inverter
to the R input prohibits the Restricted Combination (RC) State. It has a data input and an enable signal (clock, or
control). The word transparent comes from the fact that, when the enable input is on, the signal would
propagate directly through the circuit, from the input D to the output Q. Transparent latches are typically used
as I/O ports or in asynchronous systems. Transparent latches are also used in synchronous two-phase systems
(for reduced transistor count); however, in single-phase synchronous systems with direct feedback, master-
slave devices (often edge-triggered) must be used to avoid analog.
The truth table shows that when the gate/enable input is 0, the D input has no effect on the output.
When E is high, the output equals D.
Figure 16: D latch using AND and NOR gates D = Data Input: E = Enable/clock: Q = Output: Q' = Inverse of Q
Below is the D latch waveform, which is similar to the RS latch one, but with R removed.
Figure 17: D latch waveform

Figure 18: A circuit for gated D latch
Figure 19 shows an example timing diagram for gated D latch (assuming negligible propagation delays
through the logic gates).
Figure 19: An example timing diagram for gated D Latch

D Latch in VHDL
library ieee;
ENTITY D_latch IS
PORT( D, Clk : IN STD_LOGIC;
Q: OUT STD_LOGIC);
END D_latch;
ARCHITECTURE behavioral OF D_latch IS

BEGIN
PROCESS (D,clk)
BEGIN
IF Clk = '1' THEN
Q <= D;
END IF;
END PROCESS;
END behavioral;

JK Latch
The ambiguous state output in the RS latch was eliminated in the D latch by joining the inputs with an inverter.
But the D latch has a single input. JK latch is similar to RS latch in that it has 2 inputs J and K as shown figure 20.
The ambiguous state has been eliminated here: when both inputs are high, output toggles. The only difference
we see here is output feedback to inputs, which is not there in the RS latch.
J K Q
1 1 0
1 1 1
1 0 1
0 1 0
Figure 20: Circuit diagram of JK Latch

T Latch
When the two inputs of JK latch are shorted, a T Latch is formed. It is called T latch as, when input is held HIGH,
output toggles.
T Q Q+
1 0 1
1 1 0
0 1 1
0 0 0
Figure 21: Circuit diagram of T Latch

Flip-Flop
Flip-flops are synchronous bistable devices. The term synchronous means the output changes state only when
the clock input is triggered. That is, changes in the output occur in synchronization with the clock.
Flip-flop is a kind of multivibrator. There are three types of multivibrators:
1. Monostable multivibrator (also called one-shot) has only one stable state. It produces a single
pulse in response to a triggering input.
2. Bistable multivibrator exhibits two stable states. It is able to retain the two SET and RESET states
indefinitely. It is commonly used as a basic building block for counters, registers and memories.
In a bistable multivibrator, the condition of Q=1 and not-Q=0 is defined as set. A condition of Q=0 and
not-Q=1 is conversely defined as reset. If Q and not-Q happen to be forced to the same state (both 0 or
both 1), that state is referred to as invalid.
3. Astable multivibrator has no stable state at all. It is used primarily as an oscillator to generate
periodic pulse waveforms for timing purposes.
The bistable multivibrators are called flip-flops and are the basic memory devices used in sequential logic.
Other two-state devices include the astable multivibrator which serves as an oscillator and the monostable
multivibrator ("one-shot" multivibrator) which can serve as a pulse source.
• A race condition is a state in a sequential system where two mutually-exclusive events are
simultaneously initiated by a single cause.
Flip-Flop is a bi-stable element with inputs, which can change the state of the element. It has two types of
inputs:
1. Asynchronous inputs
Input change of sufficient magnitude and duration produces immediate change in the state of flip-flop
2. Synchronous inputs
Change in inputs does not immediately affect the state of the flip-flop. Inputs affect state only after a
control
signal (enable, or clock) also occurs
Asynchronous flip-flop inputs
The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs because they
have effect on the outputs (Q and not-Q) only in step, or in sync, with the clock signal transitions. These extra
inputs are called asynchronous because they can set or reset the flip-flop regardless of the status of the clock
signal. Typically, they're called preset and clear:

Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or active-low.
When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the synchronous
inputs or the clock. When the clear input is activated, the flip-flop will be reset (Q=0, not-Q=1), regardless of any
of the synchronous inputs or the clock. What happens if both preset and clear inputs are activated? We get an
invalid state on the output, where Q and not-Q go to the same state, the same as the S-R latch!
Edge-Triggered Flip-flops
An edge-triggered flip-flop changes states either at the positive edge (rising edge) or at the negative
edge (falling edge) of the clock pulse on the control input. The three basic types are introduced here: S-R, J-K
and D.
The small triangle, called the dynamic input indicator, is used to identify an
edge-triggered flip-flop.
Positive edge-triggered (without bubble at Clock input): S-R, J-K, and D.
Negative edge-triggered (with bubble at Clock input): S-R, J-K, and D.
Pulse-Triggered (Master-Slave) Flip-flops

The term pulse-triggered means that data are entered into the flip-flop on the rising edge of the clock
pulse, but the output does not reflect the input state until the falling edge of the clock pulse. As this kind of flip-
flops are sensitive to any change of the input levels during the clock pulse is still HIGH, the inputs must be set up
prior to the clock pulse's rising edge and must not be changed before the falling edge. Otherwise, ambiguous
results will happen.
The three basic types of pulse-triggered flip-flops are S-R, J-K and D. Their logic symbols are shown in
figure 22. Notice that they do not have the dynamic input indicator at the clock input but have postponed
output symbols at the outputs.
Figure 22: Pulse-Triggered (Master-Slave) Flip-flops
Introduction - Master-Slave Flip-Flop
A master-slave flip-flop is constructed from two separate flip-flops. One circuit serves as a master and
the other as a slave. The logic diagram of an SR flip-flop is shown in Figure 23. The master flip-flop is enabled on
the positive edge of the clock pulse CP and the slave flip-flop is disabled by the inverter. The information at the
external R and S inputs is transmitted to the master flip-flop. When the pulse returns to 0, the master flip-flop is
disabled and the slave flip-flop is enabled. The slave flip-flop then goes to the same state as the master flip-flop.

Figure 23: Logic diagram of a master-slave flip-flop Figure 24: Timing relationship in a master slave
flip-flop
The timing relationship is shown in Figure 24 and is assumed that the flip-flop is in the clear state prior
to the occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on the negative
transition of the clock pulse.
Operating Characteristics
The operating characteristics mention here applies to all flip-flops regardless of the particular form of the
circuit..
Propagation Delay Time - is the interval of time required after an input signal has been applied for the resulting
output change to occur. Propagation delays (tpLH & tpHL) in an SR latch are illustrated below:
tpLH – from low to high (1 to 0).

tpHL – from high to low (1 to 0).
Figure 24: Propagation delays in an SR latch
Set-Up Time - is the minimum interval required for the logic levels to be maintained constantly on the inputs (J
and K, or S and R, or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably
clocked into the flip-flop.
Hold Time - is the minimum interval required for the logic levels to remain on the inputs after the triggering
edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
If data makes transition within this setup window and before the hold window, then the flip-flop output is not
predictable, and flip-flop enters what is known as meta stable state. In this state flip-flop output oscillates
between 0 and 1. It takes some time for the flip-flop to settle down. The whole process is called metastability.

The waveform below shows input S (R is not shown), and CLK and output Q (Q' is not shown) for a SR positive
edge flip-flop.
Figure 25: Waveforms for SR latch
Maximum Clock Frequency - is the highest rate that a flip-flop can be reliably triggered.
Power Dissipation - is the total power consumption of the device.
Pulse Widths - are the minimum pulse widths specified by the manufacturer for the Clock, SET and CLEAR
inputs.

A Negative-edge-triggered Master-Slave D Flip-Flop
A possible circuit and symbol for a negative-edge-triggered master-slave D flip-flop is shown in Figure 28 and
Figure 29.
Figure 28: A negative−edge−triggered master−slave D clip−clop Figure 29: The graphical symbol for
negative−edge−triggered D clip−clop
The master-slave D flip-flop shown in Figure 28 responds on the negative edge (i.e., the edge where the
clock signal changes from 1 to 0) of the clock signal. Hence it is negative-edge-triggered. The circuit can be
changed to respond to the positive clock edge by connecting the slave stage directly to the clock and the master
stage to the complement of the clock.
Figure 30 shows an example timing diagram for negative-edge-triggered D flip-flop (assuming

negligible propagation delays through the logic gates).
Figure 30: An example timing diagram for negative−edge−triggered master−slave D clip−clop
A Positive-edge-triggered D Flip-Flop
a positive-edge-triggered master-slave D flip-flop is presented in Figure 31. It requires only six NAND gates and,
hence, fewer logic gates.

Figure 31: A positive−edge−triggered D clip−clop Figure 32. The graphical symbol for
positive−edge−triggered D clip−clop
The operation of the circuit in Figure 31 is as follows. When Clock = 0, the outputs of gates 2 and 3 are high.
Thus P1 = P2 = 1, which maintains the output latch, comprising gates 5 and 6, in its present state. At the same
time, the signal P3 is equal to D, and P4 is equal to its complement D’. When Clock changes to 1, the following
changes take place. The values of P3 and P4 are transmitted through gates 2 and 3 to cause P1 = D’ and P2 = D,
which sets Q = D and Q’ = D’. To operate reliably, P3 and P4 must be stable when Clock changes from 0 to 1.
Hence the setup time of the flip-flop is equal to the delay from the D input through gates 4 and 1 to P3. The hold
time is given by the delay through gate 3 because once P2 is stable; the changes in D no longer matter.
For proper operation it is necessary to show that, after Clock changes to 1, any further changes in D will not
affect the output latch as long as Clock = 1. We have to consider two cases. Suppose first that D = 0 at the
positive edge of the clock. Then P2 = 0, which will keep the output of gate 4 equal to 1 as long as Clock = 1,
regardless of the value of the D input. The second case is if D = 1 at the positive edge of the clock. Then P1 = 0,
which forces the outputs of gates 1 and 3 to be equal to 1, regardless of the D input. Therefore, the flip-flop
ignores changes in the D input while Clock = 1.
Figure 33 shows an example timing diagram for positive-edge-triggered D flip-flop
Figure 33: An example timing diagram for positive−edge−triggered master−slave D clip−clop

D Flip-Flops with Clear and Preset
In using flip-flops, it is often necessary to force the flip-flops into a known initial state. A simple way of
providing the clear and present capability is to add extra input to the flip-flops. Figure 15 shows a masterslave D
flip-flop with Clear and Preset. Placing a 0 on the Clear input will force the flip-flop into the state Q = 0. If Clear =
1, then this input will have no effect on the NAND gates. Similarly, Preset = 0 forces the flip-flop into the state Q =
1, while Preset = 1 has no effect. To denote that the Clear and Preset inputs are active when their value is 0, we
placed an overbar on the names in Figure 16. Note that the circuit that uses this flip-flop should not try to force
both Clear and Preset to 0 at the same time. A graphical symbol for this flip-flop is shown in Figure 35.

Figure 34: A circuit for master−slave D clip−clop with Clear and Preset
Figure 35: The graphical symbol for master−slave D clip−clop with Clear and Preset
A similar modification can be done on the positive-edge-triggered D flip-flop, as indicated in Figure 34. A
graphical symbol for this flip-flop is shown in Figure 36. Again, both Clear and Preset inputs are active low. They
do not disturb the flip-flop when they are equal to 1.
Figure 36: A positive−edge−triggered D clip−clop with Clear and Preset Figure 37: The graphical symbol
for positive−edge−triggered D flip−clop with Clear and Preset
In the circuits in Figures 35, the effect of a low signal on either the Clear or Preset input is immediate. For
example, if Clear = 0 then the flip-flop goes into the state Q = 0 immediately, regardless of the value of the clock
signal. In such a circuit, where the Clear signal is used to clear a flip-flop without regard to the clock signal, we
say that the flip-flop has an asynchronous clear. In practice, it is often preferable to clear the flip-flops on the
active edge of the clock. Such synchronous clear can be accomplished as shown in Figure 38. The flip-flop

operates normally when the Clear input is equal to 1. But if Clear goes to 0, then on the next positive edge of the
clock the flip-flop will be cleared to 0.
Figure 38: Synchronous reset for a D flip−clop
VHDL implementation of D flip-flop with synchronous clear.

Basic D Flip-Flop with Synchronous Reset, Set and Clock Enable (positive edge clock).
Library IEEE; --library declaration for the module.

entity example is
port( Q : out std_logic; -- Data output
CLK :in std_logic; -- Clock input
CE :in std_logic; -- Clock enable input
RESET :in std_logic; -- Synchronous reset input
D :in std_logic; -- Data input
SET : in std_logic -- Synchronous set input );
end example;
architecture Behavioral of example is --architecture of the circuit.
begin
process(CLK)
begin
if ( rising_edge(CLK) ) then --This makes the process synchronous(with clock)
if (RESET = '1') then

Q <= '0';
else
if(SET = '1') then
Q <= '1';
else if ( CE = '1') then
Q <= D;
end if;
end if;
end if;
end if;
end process; --end of process statement.
end Behavioral;
The VHDL code of the d-flip flop :
LIBRARY ieee ;
ENTITY flipflop IS
PORT ( D, Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END flipflop ;

ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock’EVENT AND Clock = ’1′ ;
IF Resetn = ’0′ THEN
Q <= ’0′ ;
ELSE
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Rising Edge D Flip flop in vhdl
library ieee;
ENTITY dff IS
PORT( D, Clk, Clr, Pre : IN STD_LOGIC;
Q, Qbar : OUT STD_LOGIC);
END dff;
ARCHITECTURE behavioral OF dff IS
BEGIN
PROCESS(Clk)
BEGIN
IF (Clk'event) AND (Clk='1') THEN -- Positive Edge
Q <= D;
Qbar <= not D;
END IF;
END PROCESS;
END behavioral;

T Flip-Flop
An interesting modification of the D flip-flop leads to a T flip-flop, which is shown in Figure 21. The graphical
symbol for this T flip-flop is shown in Figure 22.
Figure 21: A circuit for T flip−clop Figure 22: The graphical symbol for T clip−clop
The circuit uses a positive-edge-triggered D flip-flop. The feedback connections make the input signal D equal to
either the value of Q or Q’ under the control of the signal that is labeled T. On each positive edge of the clock, the
flip-flop may change its state Q. The characteristic table for a T flip-flop which describes its behavior is as
follows.
Figure 23 shows an example timing diagram for T flip-flop (assuming negligible propagation delays through the
logic gates).
Figure 23: An example timing diagram for T flip−clop
T flip-flops are single input version of JK flip-flops. This modified form of JK flip-flop is obtained by connecting
both inputs J and K together. These flip-flops are called T (Toggle) flip-flops because of their ability to
complement its state (i.e.) Toggle.
When T=1 and CP=1, the flip-flop complements its output, regardless of the present state of the Flip-flop. In this
case the next state is the complement of the present state.
When T=0, there is no change in the state of the flip-flop (i.e.) the next state is same as the present state of the
flip-flop. From the characteristic table and characteristic equation it is quite evident that when T=0, the next
sate is same as the present state.

JK Master Slave Flip-Flop
All sequential circuits discussed had a problem called race condition (All level sensitive sequential circuits have
this problem). Before the enable input changes state from HIGH to LOW (assuming HIGH is ON and LOW is OFF
state), if inputs changes, then another state transition occurs for the same enable pulse. This sort of multiple
transition problem is called racing.
Figure 26: JK Master Slave Flip-Flop Figure 27: JK Master Slave Flip-Flop using gates
In the figure 26, there are two latches, the first latch on the left is called master latch and the one on the right is
called slave latch. Master latch is positively clocked and slave latch is negatively clocked.
JK Flip-Flop
Another interesting modification of the D flip-flop leads to a JK flip-flop, which is shown in Figure 24. The
graphical symbol for this JK flip-flop is shown in Figure 25.
Figure 24: A circuit for JK flip−clop.
Figure 25: The graphical symbol for JK flip−clop (positive edge and negative edge triggered)
In the circuit in Figure 24, instead of using a single control input, T, we use two inputs, J and K. For this circuit
the input D is
The characteristic table for a JK flip-flop which describes its behavior is as follows.

The JK flip-flop combines the behaviors of SR and T flip-flops in a useful way. It behaves as the SR flip-flop
where J = S and K = R, for all input values except J = K = 1. For the latter case, which has to be avoided in the SR
flip-flop, the JK flip-flop toggles its state like the T flip-flop.
A J-K flip-flop is nothing more than an S-R flip-flop with an added layer of feedback. This feedback selectively
enables one of the two set/reset inputs so that they cannot both carry an active signal to the multivibrator
circuit, thus eliminating the invalid condition.
When both J and K inputs are activated, and the clock input is pulsed, the outputs (Q and not-Q) will swap states.
That is, the circuit will toggle from a set state to a reset state, or vice versa.
Essentially, this is a modified version of an S-R flip-flop with no "invalid" or "illegal" output state.
Figure 26: The JK flip−clop and its truth table
What used to be the S and R inputs are now called the J and K inputs, respectively. The old two-input AND gates
have been replaced with 3-input AND gates, and the third input of each gate receives feedback from the Q and
not-Q outputs. What this does for us is permit the J input to have effect only when the circuit is reset, and permit
the K input to have effect only when the circuit is set. In other words, the two inputs are interlocked, to use a
relay logic term, so that they cannot both be activated simultaneously. If the circuit is "set," the J input is
inhibited by the 0 status of not-Q through the lower AND gate; if the circuit is "reset," the K input is inhibited by
the 0 status of Q through the upper AND gate.
When both J and K inputs are 1, however, something unique happens. Because of the selective inhibiting action
of those 3-input AND gates, a "set" state inhibits input J so that the flip-flop acts as if J=0 while K=1 when in fact
both are 1. On the next clock pulse, the outputs will switch ("toggle") from set (Q=1 and not-Q=0) to reset (Q=0
and not-Q=1). Conversely, a "reset" state inhibits input K so that the flip-flop acts as if J=1 and K=0 when in fact
both are 1. The next clock pulse toggles the circuit again from reset to set.
D Latch in VHDL
library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff1 is
Port ( in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
clock : in STD_LOGIC;
output : out STD_LOGIC);
end jkff1;
architecture Behavioral of jkff1 is
begin
process(in1,in2,clock)
begin
if (clock'event and clock = '1') then

elsif (in1 = '1' and in2 = '0') then
output <= '1';
output <= '0';
output <= not(output);
end if;
end process;
end Behavioral;

State Diagrams of Various Flip-flops
Table below shows the state diagrams of the four types of flip-flops.
Summary of the Types of Flip-flop Behaviour
The four types of flip-flops are defined in Table below.
Table : Flip-flop Types

Applications Of Flip-Flops
• Counters
• Frequency Dividers
• Shift Registers
• Storage Registers

What is the difference between a latch and a flip ...
• Latch is a level triggered device but flip flop is a edge triggered device.
• Latch takes less gates but flipflop takes more.
• Latch faster flipflop slower.
• Latch does'nt have a clock signal but flip flop depends on theclock signal but both are having one bit memory.
• Latches: They are sensitive to the duration of pulse and can transfer data until they are switched on. They hold
the last logic at the output if we put it off (bring the strobe pin to low). They are used as temporary buffers.
• FF: They are sensitive to signal change (low to high or high to low) and not the level. Hence they transfer data
only at that instant and it cannot be changed until next signal change. Due to this they are used as registers.

Shift Register
In digital circuits a shift register is a group of flip flops set up in a linear fashion which have their inputs and
outputs connected together in such a way that the data is shifted down the line when the circuit is activated. Shift
registers, like counters, are a form of sequential logic, unlike combinational logic is not only affected by the present
inputs, but also, by the prior history.
Shift registers produce a discrete delay of a digital signal or waveform. A waveform synchronized to a clock, a
repeating square wave, is delayed by "n" discrete clock times, where "n" is the number of shift register stages. The
stages in a shift register are delay stages, typically type "D" Flip-Flops or type "JK" Flip-flops.
Types of shift register
Basic shift registers are classified by structure according to the following types:
• Serial-in/serial-out
• Parallel-in/serial-out(PISO)
• Serial-in/parallel-out(SIPO)
• Universal parallel-in/parallel-out
• Ring counter
SERIAL-IN, SERIAL-OUT SHIFT REGISTER
In order to get the data out of the register, they must be shifted out serially.
Figure 4: 4-bit Serial-in to Serial-out(SISO) Shift Register
This type of Shift Register also acts as a temporary storage device or as a time delay device, with the amount of time
delay being controlled by the number of stages in the register, 4, 8, 16 etc or by varying the application of the clock
pulses.
This can be done destructively or non-destructively. For destructive readout, the original data is lost and at the end of
the read cycle, all flip-flops are reset to zero.
Destructive readout
These are the simplest kind of shift register. The data string is presented at 'Data In', and is shifted right one
stage each time 'Data Advance' is brought high. At each advance, the bit on the far left (i.e. 'Data In') is shifted into the
first flip-flop's output. The bit on the far right (i.e. 'Data Out') is shifted out and lost.
Non-destructive readout
Non-destructive readout can be achieved using the configuration shown in figure 3. Another input line is
added - the Read/Write Control. When this is high (i.e. write) then the shift register behaves as normal, advancing the
input data one place for every clock cycle, and data can be lost from the end of the register. However, when the R/W
control is set low (i.e. read), any data shifted out of the register at the right becomes the next input at the left, and is
kept in the system. Therefore, as long as the R/W control is set low, no data can be lost from the system
To avoid the loss of data, an arrangement for a non-destructive reading can be done by adding two AND gates, an OR
gate and an inverter to the system.

Figure 3: Non destructive read with SISO Shift register
The data is loaded to the register when the control line is HIGH (ie WRITE). The data can be shifted out of the
register when the control line is LOW (ie READ).
SERIAL-IN, PARALLEL-OUT (SIPO) SHIFT REGISTER

This configuration allows conversion from serial to parallel format. Data are input serially. Once the data has
been input, it may be either read off at each output simultaneously, or it can be shifted out and replaced.
Figure 6: Serial in parallel out 4 bit shift register with D Flip flop
Above, four data bits will be shifted in from "data in" by four clock pulses and be available at QA through QD
for driving external circuitry.
After the first clock, the data at "data in" appears at QA. After the second clock, The old QA data appears at
QB; QA receives next data from "data in". After the third clock, QB data is at QC. After the fourth clock, QC data is at
QD. This stage contains the data first present at "data in". The shift register should now contain four data bits.
The effect of each clock pulse is to shift the DATA contents of each stage one place to the right, and this is
shown in the following table until the complete DATA is stored, which can now be read directly from the outputs of
QA to QD. Then the DATA has been converted from a Serial Data signal to a Parallel Data word.
Clock Pulse No QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0

PARALLEL-IN, SERIAL-OUT (PISO) SHIFT REGISTER
This configuration has the data input on lines D1 through D4 in parallel format..
Figure 7: Parallel in Serial out 4 bit shift register with D Flip flop
Data is loaded into all stages at once of a parallel-in/serial-out shift register. The data is then shifted out via
"data out" by clock pulses. Since a 4- stage shift register is shown above, four clock pulses are required to shift out all
of the data. In the diagram above, stage D data will be present at the "data out" up until the first clock pulse; stage C
data will be present at "data out" between the first clock and the second clock pulse; stage B data will be present
between the second clock and the third clock; and stage A data will be present between the third and the fourth clock.
After the fourth clock pulse and thereafter, successive bits of "data in" should appear at "data out" of the shift register
after a delay of four clock pulses.
As this type of Shift Register converts parallel data, such as an 8-bit data word into serial data it can be used to
multiplex many different input lines into a single serial DATA stream which can be sent directly to a computer or
transmitted over a communications line.
A four-bit parallel in - serial out shift register with NAND gates is shown in figure 9. The circuit uses D flip-
flops and NAND gates for entering data (ie writing) to the register.
Figure 9: Parallel in Serial out 4 bit shift register with D Flip flop and NAND gates
D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least significant bit. To
write data in, the mode control line is taken to LOW and the data is clocked in. The data can be shifted when the mode
control line is HIGH as SHIFT is active high.

PARALLEL-IN TO PARALLEL-OUT (PIPO) SHIFT REGISTER
Figure 11: Parallel in Parallel out 4 bit shift register with D Flip flop
A parallel-in/parallel-out shift register combines the function of the parallel-in, serial-out shift register with the
function of the serial-in, parallel-out shift register to yields the universal shift register.
Data presented at PA through PD is parallel loaded into the registers. This data at QA through QD may be
shifted by the number of pulses presented at the clock input. The shifted data is available at QA through QD. The
"mode" input, which may be more than one input, controls parallel loading of data from PA through PD, shifting of
data, and the direction of shifting. There are shift registers which will shift data either left or right.
PARALLEL-ACCESS SHIFT REGISTER
Figure 12: Parallel-access shift register.
Instead of using the normal shift register connection, the D input of each flip-flop is connected to two different
sources. One source is the preceding flip-flop which is needed for the shift register operation. The other source is the
external input that corresponds to the bit that is to be loaded into the flip-flop as part of the parallel-load operation. The
controlled signal is used to select the mode of operation. If the =0, then the circuit operates as

a shift register. If =1, then the parallel input data are loaded in the register. In both cases the action takes
place on the positive edge of the clock.
The contents of the register can be accessed in parallel by observing the outputs of all flip-flops. The flip-flops can also
be access serially, by observing the values of Q0 during consecutive clock cycles while the contents are being shifted.
A circuit in which data can be loaded in series and then accessed in parallel is called a series to parallel converter.
Similarly, the opposite type of circuit is a parallel to series converter.
BIDIRECTIONAL SHIFT REGISTERS

The registers discussed so far involved only right shift operations. Each right shift operation has the effect of
successively dividing the binary number by two. If the operation is reversed (left shift), this has the effect of
multiplying the number by two. With suitable gating arrangement a serial shift register can perform both operations.
A bidirectional, or reversible, shift register is one in which the data can be shift either left or right. A four-bit
bidirectional shift register using D flip-flops is shown below.
Figure 13: A 4-bit bidirectional shift register using D flip-flops
Here a set of NAND gates are configured as OR gates to select data inputs from the right or left adjacent bistables, as
selected by the LEFT/RIGHT control line.
The animation below performs right shift four times, then left shift four times. Notice the order of the four output bits
are not the same as the order of the original four input bits.
Example: The clock frequency is 2MHz. How long will it take to serial load the eight shift register?
Solution:
n=8
Time taken to load serially the eight bit will be given by
Example: Explain why there may be a race condition in a shift register.

Solution. There is no race condition in Shift register as it make use of D flip flop, R S flip flop as D and J K
flip flop So the condition of J = K = 1 never comes.

Counters
A sequential circuit that goes through a prescribed sequence of states upon the application of input pulses is
called a counter. The input pulses, called count pulses, may be clock pulses. In a counter, the sequence of states may
follow a binary count or any other sequence of states. A counter that follows the binary sequence is called a binary
counter. An n-bit binary counter consists of n flip-flops and can count in binary from 0 to 2n - 1.
In practice, there are two types of counters:
• up counters which increase (increment) in value
• down counters which decrease (decrement) in value
Counters Types
In electronics, counters can be implemented quite easily using register-type circuits such as the flip-flop, and a
wide variety of designs exist, e.g:
• Asynchronous (ripple) counters
• Synchronous counters
• Johnson counters
• Decade counters
• Up-Down counters
• Ring counters
Asynchronous (ripple) counters

The simplest counter circuit is a single D-type flip flop, with its D (data) input fed from its own inverted
output. This circuit can store one bit, and hence can count from zero to one before it overflows (starts over from 0).
This counter will increment once for every clock cycle and takes two clock cycles to overflow, so every cycle it will
alternate between a transition from 0 to 1 and a transition from 1 to 0.
You can continue to add additional flip flops, always inverting the output to its own input, and using the
output from the previous flip flop as the clock signal. The result is called a ripple counter, which can count to 2n-1
where n is the number of bits (flip flop stages) in the counter. Ripple counters suffer from unstable outputs as the
overflows "ripple" from stage to stage, but they do find frequent application as dividers for clock signals, where the
instantaneous count is unimportant, but the division ratio overall is.
Synchronous counters
Where a stable count value is important across several bits, which is the case in most counter systems,
synchronous counters are used. These also use flip-flops, either the D-type or the more complex J-K type, but here,
each stage is clocked simultaneously by a common clock signal. Logic gates between each stage of the circuit control
data flow from stage to stage so that the desired count behavior is realized.
Decade counters
Decade counters are a kind of counter that counts in tens rather than having a binary representation. Each output will
go high in turn, starting over after ten outputs have occurred. This type of circuit finds applications in multiplexers and
demultiplexers, or wherever a scanning type of behaviour is useful.
Up-Down Counters
It is a combination of up counter and down counter, counting in straight binary sequence. There is an up-down
selector. If this value is kept high, counter increments binary value and if the value is low, then counter starts
decrementing the count. The Down counters are made by using the complemented output to act as the clock for the
next flip-flop in the case of Asynchronous counters. An Up counter is constructed by linking the Q out of the J-K Flip
flop and putting it into a Negative Edge Triggered Clock input. A Down Counter is constructed by taking the Q output
and putting it into a Positive Edge Triggered input
Johnson counters

A Johnson counter is a special case of shift register, where the output from the last stage is inverted and fed back as
input to the first stage. A pattern of bits equal in length to the shift register thus circulates indefinitely.
A Johnson counter (or switch tail ring counter, twisted-ring counter, walking-ring counter, or Moebius counter) is a
modified ring counter, where the output from the last stage is inverted and fed back as input to the first stage. A pattern
of bits equal in length to twice the length of the shift register thus circulates indefinitely. These counters find specialist
applications, including those similar to the decade counter, digital to analogue conversion, etc.
Ring Counters
A ring counter is a counter that counts up and when it reaches the last number that is designed to count up to, it will
reset itself back to the first number. For example, a ring counter that is designed using 3 JK Flip Flops will count
starting from 001 to 010 to 100 and back to 001. It will repeat itself in a 'Ring' shape and thus the name Ring Counter
is given.
A ring counter is a shift register (a cascade connection of flip-flops) with the output of the last one connected to the
input of the first, that is, in a ring. Typically a pattern consisting of a single 1 bit is circulated, so the state repeats every
N clock cycles if N flip-flops are used. It can be used as a cycle counter of N states.
SHIFT REGISTER COUNTERS

Two of the most common types of shift register counters are introduced here: the Ring counter and the Johnson
counter. They are basically shift registers with the serial outputs connected back to the serial inputs in order to
produce particular sequences.
Ring Counters
A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to
the input of the first register.
There are two types of ring counters:
• A straight ring counter or Overbeck counter connects the output of the last shift register to the first shift
register input and circulates a single one (or zero) bit around the ring. For example, in a 4-register one-hot
counter, with initial register values of 1000, the repeating pattern is: 1000, 0100, 0010, 0001, 1000... .
The following is a 4-bit ring counter constructed from D flip-flops. The output of each stage is shifted into the next
stage on the positive edge of a clock pulse. If the CLEAR signal is high, all the flip-flops except the first one FF0 are
reset to 0. FF0 is preset to 1 instead.
Figure: Ring counter, whose shift register outputs are fed back as inputs
Since the count sequence has 4 distinct states, the counter can be considered as a mod-4 counter. But the major
advantage of a ring counter over a binary counter is that it is self-decoding. No extra decoding circuit is needed to
determine what state the counter is in.

Figure: Ring counter output sequence
• A twisted ring counter or Johnson counter connects the complement of the output of the last shift register to
its input and circulates a stream of ones followed by zeros around the ring. For example, in a 4-register
counter, with initial register values of 0000, the repeating pattern is: 0000, 1000, 1100, 1110, 1111, 0111,
0011, 0001, 0000... .
Figure: Ring counter, whose shift register complemented outputs are fed back as inputs
Johnson counters are a variation of standard ring counters, with the inverted output of the last stage fed back to the
input of the first stage. An n-stage Johnson counter yields a count sequence of length 2n, so it may be considered to be
a mod-2n counter. The circuit above shows a 4-bit Johnson counter.
Again, the apparent disadvantage of this counter is that the maximum available states are not fully utilized. Only eight
of the sixteen states are being used.

Counters with Parallel Load
• Counters often have a parallel-load capability for transferring an initial binary number into the counter
prior to the count an initial binary number into the counter prior to the count operation.
• This can be accomplished via the clear and preset inputs of the ppp flip-flops.
• Larger counters can be constructed by cascading several smaller counters together.
• To accomplish this, a carryout can be generated if the output of all flip-flops is equal to 1 while the count
input is enabled all flip flops is equal to 1 while the count input is enabled.
• The carry-out is connected to the count input of the counter holding the next higher-order bits.gg
• A counter with parallel load can be used to produce any desired number of count sequences.
• A modulo-N (or mod-N) counter is a counter that generates a repeated sequence of N counts, e.g. a 4-bit binary
counter is a mod-16 countermod 16 counter.

Reset Synchronization
• input, it is often desirable to reset a counter as part of its count sequence.
• A modulo-N (or mod-N) counter is a counter that generates a repeated sequence of N counts e g a 4-bit
binary counter is a repeated sequence of N counts, e.g. a 4 bit binary counter is a mod-16 counter.
• Suppose that we wish to design a modulo-6 counter with a counting sequence of 0, 1, 2, 3, 4, 5, 0, 1, …
• The most straightforward approach is to recognize when the count reaches five and then reset the counter
count reaches five and then reset the counter.
• An AND gate can be used to detect the occurrence of the count of five of five.
• Because the counter is reset on the active edge of the clock, this type of counter has a synchronous reset.
• The implementation of a synchronous reset can be accomplished via either the clear feature of individual
flip- flops, or a parallel load approach.flops, or a parallel load approach.
• The choice depending upon the overall system design.
• Note that generally synchronous reset is a better choice than asynchronous reset.

Other type of counters

UNIT-IV

Sequential Circuits Design
As discussed in the combinational circuits section, how to design a combinational circuit from the given problem. We
convert the problem into a truth table, then draw K-map for the truth table, and then finally draw the gate level circuit
for the problem. Similarly we have a flow for the sequential circuit design. The steps are given below.
• State Diagram
The state diagram is constructed using all the states of the sequential circuit in question. It builds up the relationship
between various states and also shows how inputs affect the states.
let's consider designing the 2 bit up counter (Binary counter is one which counts a binary sequence) using the T flip-
flop. Below is the state diagram of the 2-bit binary counter.
The state diagram of the 2-bit binary counter

• State Table
The state table is the same as the excitation table of a flip-flop, i.e. what inputs need to be applied to get the required
output. In other words this table gives the inputs required to produce the specific outputs.

Q1 Q0 Q1+ Q0+ T1 T0
0 0 0 1 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1
• K-map
The K-map is the same as the combinational circuits K-map. Only difference: we draw K-map for the inputs i.e. T1 and
T0 in the above table. From the table we deduct that we don't need to draw K-map for T0, as it is high for all the state
combinations. But for T1 we need to draw the K-map as shown below, using SOP.
The K-map for 2-bit binary counter

• Circuit
There is nothing special in drawing the circuit, it is the same as any circuit drawing from K-map output. Below is the
circuit of 2-bit up counter using the T flip-flop.
The circuit of 2-bit up counter

Finite State Machines
Sequential Logic and FSM
• Computers are made of sequential logic blocks

• Truth tables are used to design combinational logic, but can’t be used to design sequential logic
• Finite state machines (FSM) are used instead FSM describes a sequential logic block in terms of:
– Set of states,
– State transition function (defined on current state and input),and
– Output function (defined on current state and input, or on current state only)
A finite state machine (FSM) or finite state automaton or simply a state machine, is a model of behavior
composed of a finite number of states, transitions between those states, and actions. It is similar to a "flow
graph" where we can inspect the way in which the logic runs when certain conditions are met. A finite state
machine is an abstract model of a machine with a primitive internal memory.
• Finite State Machines (FSMs) are a useful abstraction for sequential circuits with centralized “states” of
operation
• At each clock edge, combinational logic computes outputs and next state as a function of inputs and
present state
• FSMs divide their complexity into chunks called states
• Each state is simpler than the overall object
• Because each state is simpler, it is more understandable and predictable
• FSMs simplify the system into smaller pieces
• Smaller pieces are easier to code
– They are easy to write the code for
– They are easier to “get right”
– They are easy to explain in peer reviews
A finite state machine consists of the following:

(1) a set I called the input alphabet;
(2) a set S whose elements are called states;
(3) a function T:S ´ I ® S called the transition function;
(4) a particular element, s0 Î S called the initial state;
The functioning of the machine is as follows:

The machine starts in the initial state s0. The input is a string of characters from the input alphabet which are
read one at a time (from the left). At each stage the machine is in some state s €S. If the machine is in state s, and
the next input character is c € I, the machine moves to state T(s, c) and awaits the next input character. The
process continues in this way until all the input characters have been processed.

Transducers
Transducers generate output based on a given input and/or a state using actions. They are used for control
applications and in the field of computational linguistics. Here two types are distinguished:
• Moore machine
• Mealy machine
Moore and Mealy FSMs are distinguished by their output generation
Moore machine
In the theory of computation, a Moore machine is a finite state transducer where the outputs are determined
by the current state alone (and do not depend directly on the input). The state diagram for a Moore machine
will include an output signal for each state. Compare with a Mealy machine, which maps transitions in the
machine to outputs.
Most digital electronic systems are designed as clocked sequential systems. Clocked sequential systems
are a restricted form of Moore machine where the state changes only when the global clock signal changes.
Typically the current state is stored in flip-flops, and a global clock signal is connected to the "clock" input of the
flip-flops. Clocked sequential systems are one way to solve metastability problems. A typical electronic Moore
machine includes a combinatorial logic chain to decode the current state into the outputs (lambda). The instant
the current state changes, those changes ripple through that chain, and almost instantaneously the outputs
change (or don't change). There are design techniques to ensure that no glitches occur on the outputs during
that brief period while those changes are rippling through the chain, but most systems are designed so that
glitches during that brief transition time are ignored or are irrelevant. The outputs then stay the same
indefinitely, until the Moore machine changes state again.
Formal definition
A Moore machine can be defined as a 6-tuple ( S, S0, Σ, Λ, T, G ) consisting of the following:
• a finite set of states ( S )

• a start state (also called initial state) S0 which is an element of (S)
• a finite set called the input alphabet ( Σ )
• a finite set called the output alphabet ( Λ )
• a transition function (T : S × Σ → S) mapping a state and the input alphabet to the next state
• an output function (G : S → Λ) mapping each state to the output alphabet
The number of states in a Moore machine will be greater than or equal to the number of states in the
corresponding Mealy machine. The number of states in a Mealy machine will be less than or equal to the
number of states in the corresponding Moore machine. This is due to the fact that each transition in a Mealy
machine can be associated with a corresponding, additional state mapping the transition to a single output,
hence turning a possibly partial machine into a complete machine.
The Moore machine state diagram includes x, y, z as input and a, b, c as output.
Mealy machine
In the theory of computation, a Mealy machine is a finite state transducer that generates an output
based on its current state and input. This means that the state diagram will include both an input and output
signal for each transition edge. In contrast, the output of a Moore finite state machine depends only on the
machine's current state; transitions are not directly dependent upon input. However, for each Mealy machine
there is an equivalent Moore machine.

Mealy machines provide a rudimentary mathematical model for cipher machines. Considering the input and
output alphabet the Latin alphabet, for example, then a Mealy machine can be designed that given a string of
letters (a sequence of inputs) can process it into a ciphered string (a sequence of outputs). However, although
you could use a Mealy model to describe the Enigma, the state diagram would be too complex to provide
feasible means of designing complex ciphering machines.
Formal definition
A Mealy machine is a 6-tuple, (S, S0, Σ, Λ, T, G), consisting of the following:
• a finite set of states (S)

• a start state (also called initial state) S0 which is an element of (S)
• a finite set called the input alphabet (Σ)
• a finite set called the output alphabet (Λ)
• a transition function (T : S × Σ → S) mapping a state and the input alphabet to the next state
• an output function (G : S × Σ → Λ) mapping each state and the input alphabet to the output alphabet
The state diagram of a simple Mealy machine
Distinguish between mealy and moore machine with neat diagrams.

Binary Encoded or Onehot Encoded?
A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the
number of states in the state machine.
A onehot FSM design requires a flip-flop for each state in the design and only one flip-flop (the flip-flop
representing the current or "hot" state) is set at a time in a onehot FSM design. For a state machine with 9-
16 states, a binary FSM only requires 4 flip-flops while a onehot FSM requires a flip-flop for each state in
the design (9-16 flip-flops).

Example: Give mealy type FSM as Serial Adder.
Serial Adder
• A serial adder that computes the sum of two n-bit unsigned numbers an-1 ... a1 a0 and bn-1 ... b1 b0 is
described by the block diagram. The sum bits si are calculated 1 bit in one clock cycle beginning with the LSB.
• The addends and the sum are stored in shift registers which have parallel-load capability.
• In clock cycle i the adder FSM inputs are bit ai and bit bi. The sum bit si is computed by the two inputs and the
carry bit ci-1 which was produced while generating sum bit si-1.
• The adder FSM circuit has to remember the carry bit from the previous clock cycle.
Mealy State diagram for the serial adder FSM.
Two States:
• State G: carry-in = 0
• State H: carry-in = 1
State Diagram

UNIT V

Differentiate between synchronous and asynchronous counters.

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Unit - I

• The OR operator is written as +, as in A+ B. The result of an OR operator is 1 if either of the variables is

• Identity law: A+0 =A and A . 1= A.

FORMAL PROOF OF DEMORGAN'S THEOREMS

Proof of DeMorgan's Theorem (b):

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 16

V (0) = 5 volt V (1) = 0 volt

NOT gate (inverter)

Traditional symbol IEC symbol Truth Table

Input A Input B Output Q

Traditional symbol IEC symbol Truth Table

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 18

Input A Input B Output Q

Traditional symbol IEC symbol Truth Table

Input A Input B Output Q

Traditional symbol IEC symbol Truth Table

NOR gate (NOR = Not OR)

Input A Input B Output Q

Traditional symbol IEC symbol Truth Table

EX-OR (EXclusive-OR) gate

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 19

Traditional symbol IEC symbol Truth Table

EX-NOR (EXclusive-NOR) gate

Input A Input B Output Q

Traditional symbol IEC symbol Truth Table

Table: Logic gate symbols

Summary truth tables

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 20

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 21

NAND Gate NOR Gate

NAND gate equivalents

Gate Equivalent in NAND gates

Implementation of AND, OR, NOT using NAND

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 22

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 23

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 24

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 25

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 26

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 27

There is wrap-around in the K-map

• X'Y'Z' (m0) is adjacent to X'YZ' (m2)

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 28

F = WY'Z + W'Y'Z F = W'XY' + WY

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2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 30

The basic building block of a VHDL model is the entity

An entity is described as a set of design units:

Basic Structure of a VHDL file

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 31

• The NAME_OF_ENTITY is a user-selected identifier

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 32

The architecture example, described at the behavioral level, is given below,

architecture behavioral of BUZZER is

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 33

architecture behavioral_2 of AND2 is

An example of a two-input XNOR gate is shown below.

architecture behavioral_xnor of XNOR2 is

The following example illustrates it.

2/4 DELD, IT DEPT, M. V. S. R. E. C Faculty: S Ch Vijaya Bhaskar Page 34

label: component-name port map (port1=>signal1, port2=> signal2,… port3=>signaln);