DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs

August 1986
Revised April 2000

DM74LS221 Dual Non-Retriggerable One-Shot

with Clear and Complementary Outputs
General Description Features
The DM74LS221 is a dual monostable multivibrator with ■ A dual, highly stable one-shot
Schmitt-trigger input. Each device has three inputs permit- ■ Compensated for VCC and temperature variations
ting the choice of either leading-edge or trailing-edge trig-
gering. Pin (A) is an active-LOW trigger transition input and ■ Pin-out identical to DM74LS123 (Note 1)
pin (B) is an active-HIGH transition Schmitt-trigger input ■ Output pulse width range from 30 ns to 70 seconds
that allows jitter free triggering for inputs with transition ■ Hysteresis provided at (B) input for added noise
rates as slow as 1 volt/second. This provides the input with immunity
excellent noise immunity. Additionally an internal latching ■ Direct reset terminates output pulse
circuit at the input stage also provides a high immunity to
■ Triggerable from CLEAR input
VCC noise. The clear (CLR) input can terminate the output
pulse at a predetermined time independent of the timing ■ DTL, TTL compatible
components. This (CLR) input also serves as a trigger ■ Input clamp diodes
input when it is pulsed with a low level pulse transition
( ). To obtain the best and trouble free operation from
this device please read operating rules as well as the Fair-
Note 1: The pin-out is identical to DM74LS123 but, functionally it is not;
child Semiconductor one-shot application notes carefully refer to Operating Rules #10 in this datasheet.
and observe recommendations.

Ordering Code:
Order Number Package Number Package Description
DM74LS221M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS221SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS221N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Function Table

Inputs Outputs
CLEAR A B Q Q
L X X L H
X H X L H
X X L L H
H L ↑
H ↓ H
↑ (Note 2) L H
H = HIGH Logic Level
L = LOW Logic Level
X = Can Be Either LOW or HIGH
↑ = Positive Going Transition
↓ = Negative Going Transition
= A Positive Pulse
= A Negative Pulse
Note 2: This mode of triggering requires first the B input be set from a
LOW-to-HIGH level while the CLEAR input is maintained at logic LOW
level. Then with the B input at logic HIGH level, the CLEAR input whose
positive transition from LOW-to-HIGH will trigger an output pulse.

© 2000 Fairchild Semiconductor Corporation DS006409 www.fairchildsemi.com

DM74LS221 Dual Non-Retriggerable One-Shot
Functional Description
The basic output pulse width is determined by selection of may be reduced or terminated by use of the active low
an external resistor (RX) and capacitor (CX). Once trig- CLEAR input. Stable output pulse width ranging from 30 ns
gered, the basic pulse width is independent of further input to 70 seconds is readily obtainable.
transitions and is a function of the timing components, or it

Operating Rules 8. Duty cycle is defined as tW/T × 100 in percentage, if it

goes above 50% the output pulse width will become
1. An external resistor (RX) and an external capacitor
shorter. If the duty cycle varies between LOW and
(CX) are required for proper operation. The value of CX HIGH values, this causes output pulse width to vary, or
may vary from 0 to approximately 1000 µF. For small jitter (a function of the REXT only). To reduce jitter, REXT
time constants high-grade mica, glass, polypropylene, should be as large as possible, for example, with
polycarbonate, or polystyrene material capacitor may REXT = 100k jitter is not appreciable until the duty cycle
be used. For large time constants use tantalum or spe-
approaches 90%.
cial aluminum capacitors. If timing capacitor has leak-
ages approaching 100 nA or if stray capacitance from 9. Under any operating condition CX and RX must be kept
either terminal to ground is greater than 50 pF the tim- as close to the one-shot device pins as possible to min-
ing equations may not represent the pulse width the imize stray capacitance, to reduce noise pick-up, and
device generates. to reduce I-R and Ldi/dt voltage developed along their
2. When an electrolytic capacitor is used for CX a switch- connecting paths. If the lead length from CX to pins (6)
ing diode is often required for standard TTL one-shots and (7) or pins (14) and (15) is greater than 3 cm, for
to prevent high inverse leakage current. This switching example, the output pulse width might be quite different
diode is not needed for the DM74LS221 one-shot and from values predicted from the appropriate equations.
should not be used. A non-inductive and low capacitive path is necessary to
ensure complete discharge of CX in each cycle of its
Furthermore, if a polarized timing capacitor is used on
operation so that the output pulse width will be accu-
the DM74LS221, the positive side of the capacitor
rate.
should be connected to the “CEXT” pin (Figure 1).
10. Although the DM74LS221's pin-out is identical to the
3. For CX >> 1000 pF, the output pulse width (tW) is DM74LS123 it should be remembered that they are not
defined as follows: functionally identical. The DM74LS123 is a retrigger-
tW = KRX CX able device such that the output is dependent upon the
input transitions when its output “Q” is at the “High”
where [RX is in kΩ]
state. Furthermore, it is recommended for the
[CX is in pF] DM74LS123 to externally ground the CEXT pin for
[tW is in ns] improved system performance. However, this pin on
the DM74LS221 is not an internal connection to the
K ≈ Ln2 = 0.70
device ground. Hence, if substitution of an DM74LS221
4. The multiplicative factor K is plotted as a function of CX onto an DM74LS123 design layout where the CEXT pin
for design considerations: (See Figure 4). is wired to the ground, the device will not function.
5. For CX < 1000 pF see Figure 3 for tW vs. CX family 11. VCC and ground wiring should conform to good high-
curves with RX as a parameter. frequency standards and practices so that switching
6. To obtain variable pulse widths by remote trimming, transients on the VCC and ground return leads do not
the following circuit is recommended: (See Figure 2). cause interaction between one-shots. A 0.01 µF to 0.10
7. Output pulse width versus VCC and temperatures: Fig- µF bypass capacitor (disk ceramic or monolithic type)
ure 5 depicts the relationship between pulse width vari- from VCC to ground is necessary on each device. Fur-
ation versus VCC. Figure 6 depicts pulse width variation thermore, the bypass capacitor should be located as
versus temperatures. close to the VCC-pin as space permits.

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 DM74LS221 Dual Non-Retriggerable One-Shot
Operating Rules (Continued)

Note: “Rremote” should be as close to the one-shot as possible.

FIGURE 1. FIGURE 2.

FIGURE 3. FIGURE 4.

FIGURE 5. FIGURE 6.

Note: For further detailed device characteristics and output performance, please refer to the Fairchild Semiconductor one-shot application note AN-372.

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DM74LS221 Dual Non-Retriggerable One-Shot
Absolute Maximum Ratings(Note 3)
Note 3: The “Absolute Maximum Ratings” are those values beyond which
Supply Voltage 7V the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Input Voltage 7V
Characteristics tables are not guaranteed at the absolute maximum ratings.
Operating Free Air Temperature Range 0°C to +70°C The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Storage Temperature Range −65°C to +150°C

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VT+ Positive-Going Input Threshold Voltage
1 2 V
at the A Input (VCC = Min)
VT− Negative-Going Input Threshold Voltage
0.8 1 V
at the A Input (VCC = Min)
VT+ Positive-Going Input Threshold Voltage
1 2 V
at the B Input (VCC = Min)
VT− Negative-Going Input Threshold Voltage
0.8 0.9 V
at the B Input (VCC = Min)
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
tW Pulse Width Data 40
ns
(Note 4) Clear 40
tREL Clear Release Time (Note 4) 15 ns
Rate of Rise or Fall of
1
Schmitt Input (B) (Note 4)
Rate of Rise or Fall of
1
Logic Input (A) (Note 4)
REXT External Timing Resistor (Note 4) 1.4 100 kΩ
CEXT External Timing Capacitance (Note 4) 0 1000 µF
DC Duty Cycle RT = 2 kΩ 50
%
(Note 4) RT = REXT (Max) 60
TA Free Air Operating Temperature 0 70 °C
Note 4: TA = 25°C and VCC = 5V.

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 DM74LS221 Dual Non-Retriggerable One-Shot
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 5)
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max
2.7 3.4 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min, IOL = Max
0.35 0.5
Output Voltage VIL = Max, VIH = Min V
VCC = Min, IOL = 4 mA 0.4
II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA
IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA
IIL LOW Level VCC = Max A1, A2 −0.4
Input Current VI = 0.4V B −0.8 mA
Clear −0.8
IOS Short Circuit VCC = Max
−20 −100 mA
Output Current (Note 6)
ICC Supply Current VCC = Max Quiescent 4.7 11
mA
Triggered 19 27
Note 5: All typicals are at VCC = 5V, TA = 25°C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics
at VCC = 5V and TA = 25°C
From (Input)
Symbol Parameter Conditions Min Max Units
To (Output)
tPLH Propagation Delay Time A1, A2 CEXT = 80 pF
70 ns
LOW-to-HIGH Level Output to Q REXT = 2 kΩ
tPLH Propagation Delay Time B CL = 15 pF
55 ns
LOW-to-HIGH Level Output to Q RL = 2 kΩ
tPHL Propagation Delay Time A1, A2
80 ns
HIGH-to-LOW Level Output to Q
tPHL Propagation Delay Time B
65 ns
HIGH-to-LOW Level Output to Q
tPLH Propagation Delay Time Clear to
65 ns
LOW-to-HIGH Level Output Q
tPHL Propagation Delay Time Clear
55 ns
HIGH-to-LOW Level Output to Q
tW(out) Output Pulse A1, A2 CEXT = 0
Width Using Zero to Q, Q REXT = 2 kΩ
20 70 ns
Timing Capacitance RL = 2 kΩ
CL = 15 pF
tW(out) Output Pulse A1, A2 CEXT = 100 pF
Width Using External to Q, Q REXT = 10 kΩ
600 750 ns
Timing Resistor RL = 2 kΩ
CL = 15 pF
CEXT = 1 µF
REXT = 10 kΩ
6 7.5 ms
RL = 2 kΩ
CL = 15 pF
CEXT = 80 pF
REXT = 2 kΩ
70 150 ns
RL = 2 kΩ
CL = 15 pF

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DM74LS221 Dual Non-Retriggerable One-Shot
Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A

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 DM74LS221 Dual Non-Retriggerable One-Shot
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D

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DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

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Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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