Sram8t Memory

Download as pdf or txt
Download as pdf or txt
You are on page 1of 6

ISSN: 2395-1680 (ONLINE) ICTACT JOURNAL ON MICROELECTRONICS, JANUARY 2017, VOLUME: 02, ISSUE: 04

DOI: 10.21917/ijme.2017.0056

DESIGN AND READ STABILITYANALYSIS OF 8T SCHMITT TRIGGER BASED


SRAM
Priyanka Lee Achankunju, Sreekala K.S and Marie K. James
Department of Electronics and Communication Engineering, Saintgits College of Engineering, India

Abstract been used to enhance the stability of the cell for robust low voltage
This paper presents an 8T Schmitt Trigger (ST) based SRAM design to operation. In this paper, 8T Schmitt Trigger based SRAM cell
improve the read stability and power dissipation of conventional 6T with built-in feedback mechanism is used in order to attain high
SRAM cell. The ST based SRAM cell incorporates built-in feedback read stability and to reduce total power dissipation.
mechanism in order to attain robust read operation. The read stability
The remainder of this paper is organized as follows. Section 2
of the cell is 2.5× higher than that of 6T SRAM cell at 1.8V and it can
retain data even at a lower Vmin of 0.3V. Also, power consumption is describes various SRAM cell topologies. Section 3 and section 4
reduced by 22% compared to 6T SRAM design. The layout drawn using presents a brief review of conventional 6T and 8T SRAM cells.
120nm technology rule shows that the 8T ST SRAM occupies 1.2× Section 5 presents 10T ST based SRAM cell. In Section 6, the
higher area compared to 6T SRAM cell. Peripheral circuits for the 8T proposed 8T ST SRAM design is discussed. Section 7 presents
ST SRAM are introduced. Except the precharge circuit and basic the simulation results. Finally, conclusion is drawn in section 8.
SRAM cells, the remaining part of the circuitry is same for both single
bit 6T and 8T ST SRAM array design. The single bit 8T ST SRAM array
consumes less power and area in nano-scaled technologies. The
2. LITERATURE SURVEY
proposed design was simulated in Mentor Graphics ELDO using
TSMC 180nm technology. Different configurations of SRAM cells have been proposed
to meet various requirements like stability, bitcell area and low
voltage operation. In loadless 4T SRAM bitcell [4], PMOS act as
Keywords:
access transistors. Here, for maintaining data “1” reliably, PMOS
Low Voltage SRAM, Schmitt Trigger, Read Stability, Read SNM OFF state current should be more than NMOS pulldown leakage
current. Satisfying this design requirement over different process,
1. INTRODUCTION voltage and temperature (PVT) conditions may be challenging. In
[5], an asymmetric 5T SRAM cell with single bitline was
Over the last few years, feature size of CMOS devices has proposed. It requires dc-dc converters and separate precharge
been dramatically scaled to smaller dimensions. Memories are voltages for read and write operations. Additional design margins
integral part of most of the digital devices and thus design of VLSI for bitcell sizing are required to track the read precharge voltage
memories has become highly desirable. During the last decade, across PVT corners and this limits its application. The
low power and robust memory designs have drawn great research conventional 6T achieves large storage capability yet it suffers
attention. SRAM has become a crucial component in the memory from Read failure and at low supply voltages its stability degrades
hierarchy of most of the embedded devices as it dominates the to unacceptable level.
overall performance of the system. SRAM is widely used in many In [6], a single ended 6T with transmission gate as access
microprocessors and Systems On Chips (SOC) due to its speed transistors was introduced such that write ability can be improved
and low power consumption. by modulating virtual VCC and virtual VSS of one of the
With supply voltage scaling it can reduce dynamic power inverters. The Single ended 7T bitcell proposed in [7] consists of
quadratically and leakage power exponentially. However, with separate single ended write and read ports. The write operation in
miniaturization of devices, the impact of process variations this single ended 7T bitcell requires either differential VSS/VCC
influences the Static Noise Margin of the SRAM cell adversely. or asymmetrical inverter characteristics. In [8], to address the
Since SNM is linearly dependent on supply voltage, scaling down problem of data storage destruction during read operation, 8T
to save power degrades the cell stability. Thus for successful bitcell topology was introduced. It consists of separate read and
SRAM operation, the stability of the cross coupled inverter is write ports to retain high read stability.
relevant [1][2]. However, the design of robust SRAM faces many However, it suffers from read bitline leakage problem and
process and performance related challenges. With each exibit area penality of 30% compared to 6T SRAM cell. In single
technology generation as the device size is scaled, random process ended 9T bitcell, stacked read access transistors are used to reduce
variations significantly degrade the SRAM cell data stability. This the bitline leakage current [9]. Single ended 10T bitcell proposed
limits the SRAM operation in low-voltage regime employing in [10] use the modified version of read path that reduces the
minimum-sized transistors. bitline leakage and enhance read stability. In [11], a read disturb
The adoption of supply voltage scaling enable the SRAM bit free differential 10T bitcell with two series connected transistors
cell to operate in wide voltage range [3]. But the read stability of in write path was introduced. However it degrades the write
conventional 6T SRAM cell degrades to unacceptable level and it ability of the cell and requires write assist circuits for a successful
is difficult to balance the read stability requirements by delicate write operation.
transistor sizing. Thus Power, density and read stability of the None of the above bitcells address process variation tolerance
SRAM cell have become the key limitations in many designs as at low supply voltages. Thus stability of the cross coupled inverter
nano-scaled devices are becoming a reality. Several designs have

323
PRIYANKA LEE ACHANKUNJU et al.: DESIGN AND READ STABILITYANALYSIS OF 8T SCHMITT TRIGGER BASED SRAM

pair is very important for successful operation under PVT through MN1 and that results in large power dissipation and errors
variations. Therefore in this paper, we propose an 8T Schmitt at the output.
Trigger based SRAM design which offers high RSNM, reduced
power consumption and robustness to PVT variations.

3. CONVENTIONAL 6T SRAM CELL


In conventional 6T SRAM cell, cross coupled inverter is used
as the basic element for data storage as shown in Fig.1. It consist
of six transistors where the four transistors (M1, M2, M3 and M4)
forms the cross coupled inverters and AX1/AX2 are used as the
access transistors to control the access to the SRAM cell. During
read operation, the bitlines BL and BLB of the cell are pre-
charged high and the word line is asserted. When WL is raised, Fig.2. 8T SRAM cell
either BL or BLB pulls down indicating the stored data. The read
operation results in the formation of voltage divider network that 5. 10T SCHMITT TRIGGER BASED SRAM
consist of access and pull down transistors and thereby increases CELL
the voltage in the node storing logic ‘0’. This unintended change
in the stored state of the cell during read operation is defined as Schmitt Trigger (ST) principle can be applied for the cross
read failure [12]. coupled inverter pair in order to satisfy the conflicting design
requirements in conventional SRAM cell [14][15]. Depending
upon the direction of input transition, Schmitt Trigger modulates
the switching threshold of the inverter using feedback mechanism.
In the Schmitt trigger configuration as shown in Fig.3, the
transistors MP2 and MN2 have high threshold voltage than MP1
and MN1 due to body bias effect. The addition of two feedback
transistors MPF and MNF provides hysteresis such that the output
switches from HIGH to LOW or LOW to HIGH only after the ON
condition of transistors MN2 or MP2 respectively. Thus the noise
immunity of conventional Schmitt Trigger is higher than that of
an inverter.

Fig.1.Conventional 6T SRAM cell

The conventional 6T SRAM cell is thus unstable and fails to


meet the operational requirements due to reduced Read Static
Noise Margin (RSNM). As the RSNM is very low, it is not
acceptable for most memory designs especially for low power
supply voltages.

4. 8T SRAM CELL
8T cell structure was proposed to overcome the problem of
read failure in 6T SRAM cell during read operation. To improve Fig.3.Conventional CMOS Schmitt Trigger
the RSNM, it uses separate read and write ports as shown in Fig.2
for read and write operations [13]. By adding two transistors MN1 In 10T Schmitt trigger based SRAM cell [16], the feedback
and MN2 to the conventional 6T SRAM cell, it separates the read mechanism is used only in the pull down path as shown in Fig.4.
and write operations to address the reduced RSNM problem and Transistors P1-N1-N2-NF1 forms one ST inverter while
thereby increases the transistor count. The read stability of the 8T transistors P2-N3-N4-NF2 forms the another Schmitt Trigger
cell is thus improved compared to conventional 6T cell and inverter of the SRAM cell. Depending upon the direction of input
provides a read-disturb free operation. Separate read (RWL) and transition, positive feedback from the feedback transistors
write (WWL) wordlines can be used to access the cell during read (NF1/NF2) changes the switching threshold of the inverter.
and write operations. Read operation is initiated by precharging During 0 to 1 input transition, the feedback transistor (NF1
the read bitline (RBL) HIGH and then read word line (RWL) is /NF2) tries to preserve the output at logic HIGH by increasing the
asserted to read the stored data in the cell. source voltage of the pull down transistor (N1/N3). This increases
However, read bitline leakage is significant particularly in the switching threshold of the inverter and results in sharp transfer
deep submicron ranges. When RBL is not accessed, severe characteristics. This leads to robust read operation since read
voltage drop occurs at the read bitline due to the leakage current failure is initiated by the 0 to 1 input transition. Thus, the Schmitt
Trigger action preserves the logic state of the SRAM cell. Even

324
ISSN: 2395-1680 (ONLINE) ICTACT JOURNAL ON MICROELECTRONICS, JANUARY 2017, VOLUME: 02, ISSUE: 04

though 10T Schmitt Trigger based SRAM cell utilizing


differential operation provides better read stability, it has large
area overhead compared to conventional 6T SRAM cell.

Fig.5. 8T ST SRAM cell

6.2 PRECHARGE CIRCUIT


Fig.4. 10T Schmitt Trigger based SRAM cell
The precharge circuit used for the 8T Schmitt Trigger based
6. PROPOSED 8T SCHMITT TRIGGER BASED SRAM array is different from that of 6T SRAM array [18]. In the
6T SRAM array, the main function of the precharge circuit is to
SRAM DESIGN
charge the bitlines to VDD. The bitlines are precharged to ground
instead of VDD in the 8T Schmitt Trigger based SRAM array and
6.1 8T ST SRAM CELL thus consume less power compared to 6T SRAM array. Fig.6(a)
The proposed design aims at making basic inverter pair of shows the schematic of the precharge circuit for the 6T SRAM
SRAM cell efficient for low voltage operations [17]. In the cell array and Fig.6(b) shows schematic of the precharge circuit for
shown in Fig.5, PMOS transistors are used as drivers and NMOS the 8T Schmitt Trigger based SRAM array. The precharge signal
transistors are used as pass transistors to access the cell. At low (PC) enables the bitlines to be precharged during inactive state of
voltages SRAM cell stability is of major concern. 8T ST SRAM the memory cell. The transistor P1 and P2 will precharge the
cell is used to improve read stability at the expense of speed as bitlines while P3 will equalize them to ensure both bitlines are at
PMOS transistors are used as drivers for the cell. Schmitt trigger same potential before the cell read operation.
is used to modulate the switching threshold of the inverter
depending on the direction of output transition. This adaption is
achieved with the help of a feedback mechanism. In the write
operation, in order to write logic “1” to the cell, BL is pulled
HIGH and BLB is pulled LOW and vice versa for storing
logic”0”. Then word line is asserted to turn ON the NMOS access
transistors and the values are written into the cell.
During read operation, with Q=VDD and QB=0, driver
transitors PL1, PL2 are turned ON while PR1, PR2 turns OFF. To (a) (b)
read from the cell, the bitlines are charged to ground and the
Fig.6. (a). Precharge circuit for 6T SRAM Array (b). Precharge
wordline voltage is asserted to turn on the NMOS access
circuit for 8T ST SRAM Array
transistors. Here, voltage at node Q falls as the bitlines are
precharged to ground. Thus, the charges in the bitlines will disturb 6.3 SENSE AMPLIFIER
the data stored in the internal nodes forcing an unintended change
in the stored state and leads to read failure. To overcome this The primary function of a Sense amplifier is to sense the
problem, feedback mechanism is used to improve switching bitline which is being pulled down and amplify the small analog
threshold of the inverter pair. When the voltage at node Q falls to differential voltage to the full swing digital output signal thus
|Vtp|, PR2 is ON but PR1 is still OFF since PFR is ON and source performs the read operation of the stored data. Latch type Sense
voltage of PR1 is at 0V. Thus, pass transistor feedback amplifier for the 8T Schmitt Trigger based SRAM array is shown
mechanism (PFL, PFR) improves the threshold voltages by in Fig.7. It has cross coupled latch configuration and the sizing
altering VL and VR node voltages. Thus, the Schmitt trigger of the transistors is done same as that of the 6T SRAM cell [18].
operation improves the read stability of the cell and avoids read Read operation begins by precharging and equalizing both the
failure during read mode. RSNM of the SRAM cell is directly bitlines. The corresponding row is selected by enabling the
proportional to the cell ratio (CR) where CR is defined as the ratio wordline (WL) to read a particular word from the SRAM array.
of sizes of storage transistors to the access transistors. Sense amplifier is enabled by the read enable signal (RE) when
The peripheral circuits of 8T ST SRAM memory includes sufficient voltage difference is built between the bitlines. The
precharge circuit, Sense amplifier and the write driver circuit. sense amplifier is used to sense which bitline is heading towards
high voltage and which bitline is heading towards ground
potential and develops a full voltage swing at the output.

325
PRIYANKA LEE ACHANKUNJU et al.: DESIGN AND READ STABILITYANALYSIS OF 8T SCHMITT TRIGGER BASED SRAM

Fig.7. Latch-Type Sense amplifier

6.4 WRITE DRIVER


The main function of the data write circuitry [18] shown in
Fig.8 is to write the data to the SRAM cell when write enable
signal (WE) is enabled.

Fig.9. 8T ST SRAM system for reading and writing single bit


data

7. SIMULATION RESULTS
The proposed design was simulated in Mentor Graphics
ELDO tool based on TSMC 180nm technology. In order to prove
the effectiveness of the proposed design, the performance of the
proposed design is evaluated against conventional designs. Here,
cell properties such as RSNM, area, power consumption are
compared with existing designs. The simulation waveform for 8T
ST SRAM cell is shown in Fig.10.

7.1 READ STABILITY ANALYSIS


Fig.8. Write Driver circuit The read stability of the cell is determined by Read Static
Noise Margin (RSNM). We measure the RSNM using graphical
The Fig.9 shows the 8T ST based SRAM cell connected to the method. By superimposing VTC of one inverter with VTC of
peripherals such as write driver circuit, precharge and sense other inverter of the SRAM cell, a two-lobed graph called
amplifier. During inactive state of the cell, precharge enable ‘butterfly curve’ is obtained such that length of the side of the
signal (PC) is pulled HIGH such that both bitlines BL and BLB largest square that can be embedded inside the lobes of the
are precharged to ground. Precharge circuit is deactivated during butterfly curve gives the RSNM.
the active state of the cell by making the precharge enable signal
(PC) LOW. During write operation, write enable signal (WE) and
wordlines are made HIGH while the precharge enable signal is
made LOW. Sense amplifier is disabled by making read enable
signal (RE) of the sense amplifier to HIGH. Data to be written
into cell is fed into the datalines such that the data and its
complement will be produced at output. Similarly during read
operation, sense amplifier is enabled by the read enable signal
(RE) to read the data and its complement at READ and
READBAR respectively.

Fig.10. Simulation result for Read/Write operation of 8T ST


SRAM cell

326
ISSN: 2395-1680 (ONLINE) ICTACT JOURNAL ON MICROELECTRONICS, JANUARY 2017, VOLUME: 02, ISSUE: 04

The Table.1 shows the RSNM comparison of 8T ST and other


SRAM cells at different supply voltages. The RSNM of 8T ST
SRAM cell is 2.5× higher than 6T SRAM cell at 1.8V and it can
retain data even at lower supply voltage of 0.3V.

Table 1: Supply Voltages VS RSNMs

RSNM RSNM RSNM RSNM


VDD (mV) (mV) (mV) (mV)
(V) (6T (10T ST (8T (8T ST
SRAM) SRAM ) SRAM ) SRAM)
1.8 240 370 570 600
1.4 220 350 430 450
1 200 250 390 400 Fig.12. Layout view of 8T ST SRAM cell
0.6 110 160 200 230
Table.2. Comparison of various SRAM cells
0.4 70 110 120 150
Total Power
0 (Read SRAM Area
0.3 40 80 100 Consumption
Failure) Topologies (µm2)
(pW)
From, Fig.11 it is clear that RSNM of 8T ST SRAM is higher 6T
than other cells at all supply voltages due to the improved 88.86 13×10 = 130
Conventional
characteristics of the Schmitt Trigger inverter. Thus, from the
above results it can be concluded that the 8T ST based SRAM 8T SRAM 92.5 16×11 = 176
design outperforms conventional designs. 10T ST
129.4 19×11 = 209
SRAM
7.2 POWER AND AREA ANALYSIS 8T ST SRAM 69.13 13×12 = 156
The Fig.12 shows the layout view of 8T ST SRAM cell using
120nm technology design rules. Microwind and DSCH was used Table.3. Power comparison between Single bit 6T and 8T ST
to get the layout area plots. The Table.2 shows the power and area SRAM array design
comparison of different SRAM cell topologies. It is observed that
10T ST SRAM consumes maximum power and area while 8T ST SRAM Cells Total Power Consumption
SRAM consumes the minimum power and has reduced area With peripherals (µW)
overhead compared to 8T and 10T ST SRAM cells. Thus 8T ST 6T SRAM 163.97
SRAM cell configuration is viable for low power, high density
memory designs. From the Table.3 it is clear that the 8T ST based 8T ST SRAM 148.97
SRAM design has remarkably less power consumption than
conventional 6T SRAM design.
8. CONCLUSION
700 VDD VS RSNM
In this paper, an 8T Schmitt Trigger based SRAM cell is
600 6T SRAM Cell introduced that achieves lower power consumption, area and
10T ST SRAM Cell
better read stability compared to other SRAM cell topologies. The
8T SRAM Cell
500 8T ST SRAM cell can retain data even at lower supply voltage of
8T ST SRAM Cell
0.3V. This paper has presented a single bit 8T ST SRAM array
RSNM (mV)

400 design with peripheral circuits. Simulation results have shown


that 8T ST SRAM design achieves a substantial reduction in
300 power consumption compared to 6T SRAM design. The
simulation results have also confirmed that 8T ST SRAM operates
200 with high stability and could be a viable solution for highly dense,
low power memory designs.
100
REFERENCES
0
1 2 3 4 5 6 [1] Yoshinobu Nakagome, Masahi Horiguchi, Takayuki
VDD (V)
Kawahara and K. Itoh, “Review and Future Prospects of
Fig.11. RSNM comparisons at different voltages Low-Voltage RAM Circuits”, IBM Journal of Research and
Development, Vol. 47, No. 5-6, pp. 525-552, 2003.

327
PRIYANKA LEE ACHANKUNJU et al.: DESIGN AND READ STABILITYANALYSIS OF 8T SCHMITT TRIGGER BASED SRAM

[2] A.J. Bhavnagarwala, X. Tang and J.D. Meindl, “The Impact [11] Ik Joon Chang, Jae-Joon Kim, Sang Phill Park and Kaushik
of Intrinsic Device Fluctuations on CMOS SRAM Cell Roy, “A 32 kb 10T Subthreshold SRAM Array with Bit-
Stability”, IEEE Journal of Solid-State Circuits, Vol. 36, Interleaving and Differential Read Scheme in 90nm
No. 4, pp. 658-665, 2001. CMOS”, IEEE Journal of Solid-State Circuits, pp. 388-622,
[3] M.M. Khellah, A. Keshavarzi, D. Somasekhar, T. Karnik 2008.
and V. De, “Read and Write Circuit Assist Techniques for [12] Sangeeta Singh and Vikky Lakhmani, “Read and Write
Improving Vccmin of Dense 6T SRAM Cell”, Proceedings Stability of 6T SRAM”, International Journal of Advanced
of IEEE International Conference on Integrated Circuit Research in Electronics and Communication Engineering,
Design and Technology and Tutorial, pp. 185-189, 2008. Vol. 3, No. 5, pp. 569-571, 2014.
[4] K. Noda, K. Matsui, K. Takeda and N. Nakamura, “A [13] Nahid Rahman and B.P. Singh, “Design of Low Power
Loadless CMOS Four-Transistor SRAM Cell in a 0.18-µm SRAM Memory using 8T SRAM Cell”, International
Logic Technology”, IEEE Transactions on Electron Journal of Recent Technology and Engineering, Vol. 2, No.
Devices, Vol. 12, No. 12, pp. 2851-2855, 2001. 1 , pp. 123-127, 2013.
[5] I. Carlson, S. Andersson, S. Natarajan and A. Alvandpour, [14] S. Thirumala Devi and V.V.K. Raju, “Low Power Process
“A High Density, Low Leakage, 5T SRAM for Embedded Variation Tolerant Schmitt Trigger Based SRAM”,
Caches”, Proceedings of 30th European Solid State Circuits International Journal of Engineering Research &
Conference, pp. 215-218, 2004. Technology, Vol. 2, No. 6, pp. 3194-3198, 2013.
[6] B. Zhai, D. Blaauw, D. Sylvester, and S. Hanson, “A sub- [15] Jaydeep P. Kulkarni and Kaushik Roy, “Ultralow-Voltage
200mV 6T SRAM in 0.13µm CMOS”, Proceedings of Process-Variation-Tolerant Schmitt-Trigger-Based SRAM
International Conference on Solid State Circuits, pp. 332- Design”, IEEE Transactions on Very Large Scale
333, 2007. Integration Systems, Vol. 20, No. 2, pp. 319-332, 2012.
[7] Sherif A. Tawfik and Volkan Kursun, “Low Power and [16] Maheswary Sreenath and Binu K. Mathew, “Ultra Low
Robust 7T Dual-Vt SRAM Circuit”, Proceedings of Voltage, Low Power, Low Area, Process Variation Tolerant
International Symposium on Circuits and Systems, pp. 1452- Schmitt Trigger based SRAM Design”, International
1455, 2008. Journal of Advanced Research in Computer Engineering
[8] N. Verma and A.P. Chandrakasan, “65nm 8T Sub-Vt SRAM and Technology, Vol. 2, No. 11, pp. 2817-2827, 2013
Employing Sense-Amplifier Redundancy”, Proceedings of [17] A. Kishore Kumar, D. Somasundareswari, V. Duraisamy
International Conference on Solid State Circuits, pp. 328- and T. Shunbaga Pradeepa, “Design of Low Power 8T Sram
329, 2007. with Schmitt Trigger Logic”, Journal of Engineering
[9] Zhiyu Liu and Volkan Kursun, “High Read Stability and Science and Technology, Vol. 9, No. 6, pp. 670- 677, 2014.
Low Leakage Cache Memory Cell,” Proceedings of IEEE [18] R. Sandeep, Narayan T Deshpande and A.R. Aswatha,
International Symposium on Circuits and Systems, pp. 2774- “Design and Analysis of a New Loadless 4T SRAM Cell in
2777, 2007. Deep Submicron CMOS Technologies”, Proceedings of 2nd
[10] Anis Feki et.al., “Sub-Threshold 10T SRAM Bit Cell with International Conference on Emerging Trends in
Read/Write XY Selection”, Solid-State Electronics, Vol. Engineering and Technology, pp. 155-161, 2009.
106, No. 4, pp. 1-11, 2015.

328

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy