Sram8t Memory
Sram8t Memory
Sram8t Memory
DOI: 10.21917/ijme.2017.0056
Abstract been used to enhance the stability of the cell for robust low voltage
This paper presents an 8T Schmitt Trigger (ST) based SRAM design to operation. In this paper, 8T Schmitt Trigger based SRAM cell
improve the read stability and power dissipation of conventional 6T with built-in feedback mechanism is used in order to attain high
SRAM cell. The ST based SRAM cell incorporates built-in feedback read stability and to reduce total power dissipation.
mechanism in order to attain robust read operation. The read stability
The remainder of this paper is organized as follows. Section 2
of the cell is 2.5× higher than that of 6T SRAM cell at 1.8V and it can
retain data even at a lower Vmin of 0.3V. Also, power consumption is describes various SRAM cell topologies. Section 3 and section 4
reduced by 22% compared to 6T SRAM design. The layout drawn using presents a brief review of conventional 6T and 8T SRAM cells.
120nm technology rule shows that the 8T ST SRAM occupies 1.2× Section 5 presents 10T ST based SRAM cell. In Section 6, the
higher area compared to 6T SRAM cell. Peripheral circuits for the 8T proposed 8T ST SRAM design is discussed. Section 7 presents
ST SRAM are introduced. Except the precharge circuit and basic the simulation results. Finally, conclusion is drawn in section 8.
SRAM cells, the remaining part of the circuitry is same for both single
bit 6T and 8T ST SRAM array design. The single bit 8T ST SRAM array
consumes less power and area in nano-scaled technologies. The
2. LITERATURE SURVEY
proposed design was simulated in Mentor Graphics ELDO using
TSMC 180nm technology. Different configurations of SRAM cells have been proposed
to meet various requirements like stability, bitcell area and low
voltage operation. In loadless 4T SRAM bitcell [4], PMOS act as
Keywords:
access transistors. Here, for maintaining data “1” reliably, PMOS
Low Voltage SRAM, Schmitt Trigger, Read Stability, Read SNM OFF state current should be more than NMOS pulldown leakage
current. Satisfying this design requirement over different process,
1. INTRODUCTION voltage and temperature (PVT) conditions may be challenging. In
[5], an asymmetric 5T SRAM cell with single bitline was
Over the last few years, feature size of CMOS devices has proposed. It requires dc-dc converters and separate precharge
been dramatically scaled to smaller dimensions. Memories are voltages for read and write operations. Additional design margins
integral part of most of the digital devices and thus design of VLSI for bitcell sizing are required to track the read precharge voltage
memories has become highly desirable. During the last decade, across PVT corners and this limits its application. The
low power and robust memory designs have drawn great research conventional 6T achieves large storage capability yet it suffers
attention. SRAM has become a crucial component in the memory from Read failure and at low supply voltages its stability degrades
hierarchy of most of the embedded devices as it dominates the to unacceptable level.
overall performance of the system. SRAM is widely used in many In [6], a single ended 6T with transmission gate as access
microprocessors and Systems On Chips (SOC) due to its speed transistors was introduced such that write ability can be improved
and low power consumption. by modulating virtual VCC and virtual VSS of one of the
With supply voltage scaling it can reduce dynamic power inverters. The Single ended 7T bitcell proposed in [7] consists of
quadratically and leakage power exponentially. However, with separate single ended write and read ports. The write operation in
miniaturization of devices, the impact of process variations this single ended 7T bitcell requires either differential VSS/VCC
influences the Static Noise Margin of the SRAM cell adversely. or asymmetrical inverter characteristics. In [8], to address the
Since SNM is linearly dependent on supply voltage, scaling down problem of data storage destruction during read operation, 8T
to save power degrades the cell stability. Thus for successful bitcell topology was introduced. It consists of separate read and
SRAM operation, the stability of the cross coupled inverter is write ports to retain high read stability.
relevant [1][2]. However, the design of robust SRAM faces many However, it suffers from read bitline leakage problem and
process and performance related challenges. With each exibit area penality of 30% compared to 6T SRAM cell. In single
technology generation as the device size is scaled, random process ended 9T bitcell, stacked read access transistors are used to reduce
variations significantly degrade the SRAM cell data stability. This the bitline leakage current [9]. Single ended 10T bitcell proposed
limits the SRAM operation in low-voltage regime employing in [10] use the modified version of read path that reduces the
minimum-sized transistors. bitline leakage and enhance read stability. In [11], a read disturb
The adoption of supply voltage scaling enable the SRAM bit free differential 10T bitcell with two series connected transistors
cell to operate in wide voltage range [3]. But the read stability of in write path was introduced. However it degrades the write
conventional 6T SRAM cell degrades to unacceptable level and it ability of the cell and requires write assist circuits for a successful
is difficult to balance the read stability requirements by delicate write operation.
transistor sizing. Thus Power, density and read stability of the None of the above bitcells address process variation tolerance
SRAM cell have become the key limitations in many designs as at low supply voltages. Thus stability of the cross coupled inverter
nano-scaled devices are becoming a reality. Several designs have
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PRIYANKA LEE ACHANKUNJU et al.: DESIGN AND READ STABILITYANALYSIS OF 8T SCHMITT TRIGGER BASED SRAM
pair is very important for successful operation under PVT through MN1 and that results in large power dissipation and errors
variations. Therefore in this paper, we propose an 8T Schmitt at the output.
Trigger based SRAM design which offers high RSNM, reduced
power consumption and robustness to PVT variations.
4. 8T SRAM CELL
8T cell structure was proposed to overcome the problem of
read failure in 6T SRAM cell during read operation. To improve Fig.3.Conventional CMOS Schmitt Trigger
the RSNM, it uses separate read and write ports as shown in Fig.2
for read and write operations [13]. By adding two transistors MN1 In 10T Schmitt trigger based SRAM cell [16], the feedback
and MN2 to the conventional 6T SRAM cell, it separates the read mechanism is used only in the pull down path as shown in Fig.4.
and write operations to address the reduced RSNM problem and Transistors P1-N1-N2-NF1 forms one ST inverter while
thereby increases the transistor count. The read stability of the 8T transistors P2-N3-N4-NF2 forms the another Schmitt Trigger
cell is thus improved compared to conventional 6T cell and inverter of the SRAM cell. Depending upon the direction of input
provides a read-disturb free operation. Separate read (RWL) and transition, positive feedback from the feedback transistors
write (WWL) wordlines can be used to access the cell during read (NF1/NF2) changes the switching threshold of the inverter.
and write operations. Read operation is initiated by precharging During 0 to 1 input transition, the feedback transistor (NF1
the read bitline (RBL) HIGH and then read word line (RWL) is /NF2) tries to preserve the output at logic HIGH by increasing the
asserted to read the stored data in the cell. source voltage of the pull down transistor (N1/N3). This increases
However, read bitline leakage is significant particularly in the switching threshold of the inverter and results in sharp transfer
deep submicron ranges. When RBL is not accessed, severe characteristics. This leads to robust read operation since read
voltage drop occurs at the read bitline due to the leakage current failure is initiated by the 0 to 1 input transition. Thus, the Schmitt
Trigger action preserves the logic state of the SRAM cell. Even
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PRIYANKA LEE ACHANKUNJU et al.: DESIGN AND READ STABILITYANALYSIS OF 8T SCHMITT TRIGGER BASED SRAM
7. SIMULATION RESULTS
The proposed design was simulated in Mentor Graphics
ELDO tool based on TSMC 180nm technology. In order to prove
the effectiveness of the proposed design, the performance of the
proposed design is evaluated against conventional designs. Here,
cell properties such as RSNM, area, power consumption are
compared with existing designs. The simulation waveform for 8T
ST SRAM cell is shown in Fig.10.
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