Abdul Rehman

Lab Exam
Subject
Digital Logic Design
Instructor
Sir Shahrukh Hamayoun
Submitted by:
Abdul Rehman
Roll No: 30621
Section:B
Semester : 2nd
BS Software Engineering
Question no:1
Draw the circuit diagrams of mux (4:1) and de-mux (4:1) and also write about their
applications?
4:1 Multiplexer (MUX):

4:1 MUX selects one of the four input lines and directs it to the output based on the select
lines. It has 4 data inputs (D0, D1, D2, D3), 2 select lines (S0, S1), and one output (Y).
Circuit Diagram:
Applications of 4:1 MUX:

1. Data Routing: In computer networking, a MUX can be used to select a particular data
channel for transmission.
2. Signal Selection: In instrumentation, it can be used to select different signals for analysis.
3. Memory Addressing: In memory systems, MUX can be used for selecting a specific
memory block based on address lines.
4. Arithmetic Logic Unit (ALU): In processors, MUX can be used to select different inputs
to the ALU for arithmetic or logic operations.
1:4 Demultiplexer (DEMUX):

A 1:4 DEMUX takes one input and directs it to one of the four output lines based on the select
lines. It has one input (X), 2 select lines (S0, S1), and 4 outputs (Y0, Y1, Y2, Y3).
Circuit:
Applications of 1:4 DEMUX:

1. Data Distribution: In communication systems, DEMUX can be used to
distribute data streams to different receivers.
2. Memory Decoding: In memory systems, DEMUX can be used for decoding

memory addresses to select specific memory locations.
3. Display Systems: In display systems, DEMUX can be used to select
different segments in a multi-segment display for displaying different
characters or symbols.
4. Analog to Digital Conversion: In analog-to-digital converters, DEMUX

can be used to distribute analog signals to multiple ADCs for parallel
conversion.
Question no: 2
What do you know about S-R latches also draw its truth table?
Answer:
An S-R latch constructed using NAND gates is similar in function to one

constructed with NOR gates. The primary difference is in the construction of the
latch circuit itself. Instead of using NOR gates, NAND gates are utilized.
Circuit Diagram (using NAND gates):
Truth Table:
S R Q(n+1)
0 0 Invalid
0 1 1
1 0 0
1 1 Hold
Operation:
• Set (S = 0, R = 1): When the Set input is low and the Reset input is high, the latch sets,
and the Q output goes to logic high (1). This means that the latch is in the "set" state.
• Reset (S = 1, R = 0): When the Reset input is low and the Set input is high, the latch
resets, and the Q output goes to logic low (0). This means that the latch is in the "reset"
state.
• Hold (S = 0, R = 0): When both Set and Reset inputs are low, the latch maintains its
previous state. This is sometimes called the "hold" state.
• Forbidden State (S = 1, R = 1): Similar to the NOR gate latch, this condition should be
avoided as it leads to unpredictable behavior.
Question no:3
What is half and full adder also draw their circuit diagram and truth table?
A half adder and a full adder are basic digital circuits used in binary addition.
Half Adder:
A half adder adds two single-digit binary numbers (bits) and produces the sum (S)
and the carry (C) as outputs. It does not consider any carry from previous addition.
Circuit Diagram:
Truth Table:
A B S R
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Full Adder:
A full adder adds two single-digit binary numbers (bits) along with a carry input
(Cin) from a previous stage and produces the sum (S) and the carry (Cout) as
outputs.
Circuit Diagram:
Truth Table:
A B C S C’
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Question no: 4
What do you know about flip flops? Also explain its implementation
with nand gate?
Answer:
Flip-flops are fundamental building blocks in digital electronics and are widely
used for storing binary information. They are used in digital circuits for memory
elements, data storage, and synchronization purposes. There are various types of
flip-flops, such as SR flip-flop, D flip-flop, JK flip-flop, and T flip-flop, each with
its own unique characteristics and applications.
The NAND gate implementation of a basic SR (Set-Reset) flip-flop is quite

common and straightforward. Here's how it works:
1. SR Flip-Flop: The SR flip-flop has two inputs, S (Set) and R (Reset), and
two outputs, Q and Q'. It can store one bit of information, typically denoted
as Q and its complement Q'.
2. NAND Gate Implementation: We can implement an SR flip-flop using

NAND gates. Here's the truth table for an SR flip-flop:
Truth Table:
Clock S R Q(n+1)
Not trig X X Qn presenty
Trig 0 0 hold
Trig 0 1 0-reset
Trig 1 0 1-set
Trig 1 1 invalid
Circuit Diagram:

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Lab Exam

4:1 Multiplexer (MUX):

Applications of 4:1 MUX:

1:4 Demultiplexer (DEMUX):

Applications of 1:4 DEMUX:

2. Memory Decoding: In memory systems, DEMUX can be used for decoding

4. Analog to Digital Conversion: In analog-to-digital converters, DEMUX

An S-R latch constructed using NAND gates is similar in function to one

Circuit Diagram (using NAND gates):

The NAND gate implementation of a basic SR (Set-Reset) flip-flop is quite

2. NAND Gate Implementation: We can implement an SR flip-flop using

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