Digital Design with Verilog

FSM Design Examples

with A.Verilog
Sahu
Dept of Comp. Sc. & Engg.
Indian Institute of Technology Guwahati

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 Outline
• FSM Examples
• Verilog Model

2
 Sequential Circuit: FSM

outputs
a x

FSM
inputs
FSM

Combinational n1
b Circuit
n0
s1 s0
clk State register/ History/
Sequence

Formally Describe/mathematically Describe X (t) = F (a(t),b(t), H)

Boolean Algebra: Working of Combinational Circuit H is History/Sequence
Finite State Machine: Working of Sequential Circuit /State
 Set Theoretic Description
Moore Machine is an ordered quintuple
M o o r e = S ,I ,O , , 
where
S= finite set of state (≠ф)
S  s 1 ,s 2 ,  ,s n  I = finite set of inputs (≠ф)
I  i 1 ,i 2 ,  ,i m  O=finite set of output (≠ф)
O  o 1 ,o 2 ,  ,o l  δ=next state function
 SI  S λ= output function
 S  O
 Moore Machine: Moore FSM

(C L) State Current Outputs

Inputs
Excitation
Memory (C L)
Next State State
Output Logic
Logic
F2
F1 CLK

Clock Signal s
Next state = F1(current state, inputs)
Output = F2(current state)
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 Clocked synchronous FSM structure
• States: Determined by possible values in sequential storage
elements
• Transitions: Change of state
• Clock: Controls when state can change by controlling storage
Inputs Combinational Outputs
Logic

Current State Next State

or
State Clock
Storage Elements
 Standard Procedure
for
Sequential Circuit Design
 Sequential Circuit Design Process
• Step 1: Describe problem in HLL English like
statements
• Step 2: Model the problem using FSM
– Step 2.A: (optional) Minimize FSM
• Step 3: Represent the FSM in Tabular Form
• Step 4: Derive number of FF require
 Sequential Circuit Design Process
• Step 5: State Encoding
– Step 6.A: Optional Encoding Optimization
• Step 6: Derivation of
– Next State : from Present State and Input
– Output : from Present State (for Mealy FSM: including input)
• Step 7: Derive combination function for NS logic, OP
logic
• Step 8: Realize FSM
– by Connecting the NS, OP logic, State Reg and Clock
FSM Example 1
ON-OFF FSM
 Finite State Machine: Example
• Step1: English like statement
– Make x change toggle (0 to 1, or 1 to 0) every clock
cycle
• Step2: Model the problem using FSM
– Two states: “Off” (x=0), and “On” (x=1)
• Transition on rising clock edge
– from Off to On, or On to Off
– Arrow with no starting state points to
• initial state (when circuit first starts)
 Moore Finite State Machine: Example
Outputs: x Clk^
x=0 x=1
Off On
Clk^

Off On Off On Off On Off On

cycle 1 cycle 2 cycle 3 cycle 4

clk

state Off On Off On

Out put s:

x
 FSM
We often draw FSM
graphically, known as state
diagram

Can also use table (state table),

or textual languages
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 Controller for On-Off
Step 3: Represent the FSM in Tabular Form X
Combinational
Input Output Logic
N
CLK PS X NS
P
RE 1 0 1 1
RE 1 1 0 0 CLK D FF

Step 4: Derive number of FF require

Two States: 1 FF X
P
Step 5: State Encoding
State 0: 0 State 1: 1 N
Rising Edge: Clock implicit
 Controller for On-Off
Input Output Step 8: Realize FSM
CLK P X N by Connecting the NS, OP logic, State Reg and
Clock
RE 1 0 1 1 X
RE 1 1 0 0
N
Step 6: Derivation of
Next State : from Present State and Input P
Output : from Present State
CLK
Step 7: Derive combination function for D FF
NS logic, OP logic
NS = not P; X=not P;
P X
Rising Edge: Clock implicit N
FSM Example 2
D-FF
 Finite State Machine: D FF
• Step1: English like statement
– When NS is depends on value of Data input
• Step2: Model the problem using FSM
– Two states: “Off” (S=0), and “On” (S=1)
• Transition on rising clock edge
– Arrow with no starting state points to
• initial state (when circuit first starts)
 FSM for D-FF
Step2: Model the problem using FSM
0 Q(t+1)=Q(t)
0 1 State: 0, 1
1 Input : 0, 1
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Step 3: Represent the FSM in Tabular Form Output: 0,1
PS= Q(t) Input (D) NS =Q(t+1)
0 0 0
0 1 1
1 0 0
1 1 1
 FSM Controller for D-FF is D-FF
Step 4: Derive number of FF require Q(t+1)=Q(t) State: 0, 1
Two States: 1 FF : Obvious Input : 0, 1
Step 5: State Encoding Output: 0,1
State 0: 0 State 1: 1 Step 8: Realize FSM
by Connecting the NS, OP logic, State Reg and Clock
Step 6: Derivation of Next State
PS= Input NS
Q(t) =Q(t+1) s0
0 0 0
0 1 1
1 0 0
n0
1 1 1
s0
Step 7: Derive for NS logic, OP logic
clk D-FF
NS = D; X=D; 19
FSM Example 3
T-FF
 Finite State Machine: T FF
• Step1: English like statement
– When NS toggle every clock when input T is one, else
stay with same present state
• Step2: Model the problem using FSM
– Two states: “Off” (S=0), and “On” (S=1)
• Transition on rising clock edge
– Arrow with no starting state points to
• initial state (when circuit first starts)
 FSM for T-FF
Step2: Model the problem using FSM
State: 0, 1
Input : 0, 1
1 Output: 0,1
0 0
1
Step 3: Represent the FSM in Tabular Form Step 4: Derive number of FF require
PS= Q(t) Input NS =Q(t+1) Two States: 1 FF : Obvious
0 0 0 Step 5: State Encoding
0 1 1 State 0: 0 State 1: 1
1 0 1
1 1 0 22
 FSM Controller for T-FF
Step 6: Derivation of Next State Q+=QT’+Q’T
PS= Input NS
Q(t) =Q(t+1)
Step 8: Realize FSM
by Connecting the NS, OP logic, State Reg and
0 0 0 Clock
0 1 1 s0
1 0 1
1 1 0
Input=T(t)
Step 7: Derive for NS logic, OP logic
NS = = Q(t)’T(t)+Q(t)T’(t) s0 Q(t) n0 Q(t+1)
=Q(t) xor T(t) clk D-FF
X=Q;
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 FSM Controller for T-FF
Same as : Given a D FF, Construct T FF

T D TQ’+T’Q
0 Q 0Q’+1Q
T D Q
0 Q’ 1Q’+0Q
CLK C Q’

D= T Q’ + T’ Q
 Verilog Code for FSM of T-FF
//Code for Data Flipflop; will be used in FSM
implementation
module DFF( input wire D, input wire clk, input rst,
output reg Q)
always @ (posedge rst) begin
D Q
if (rst) Q=0;
end
CLK C Q’
always @(posedge clk) begin
if (!rst) Q <= D;
end
endmodule 25
 Verilog Code for FSM of T-FF
module tff_fsm (input clk, input t, input rst, output q);
wire NS, S;

DFF D0(NS, clk, rst, S);

assign NS = t ^ S; //NS logic
assign q = S; //output logic

endmodule
Verilog Code for FSM of TFF: Test bench
module tff_fsm_test; initial begin
iCLK=0;
reg t, iCLK, rst; for(i=0;i<20; i++) begin
#10; iCLK = ~iCLK;
wire Q; end
end
integer i;
tff_fsm T0(iCLK, t, rst, Q); // Inst initial begin
//Part I $dumpfile("tff_fsm.vcd");
$dumpvars;
//Part II t = 0;rst=1;
initial #10 rst=0;
$monitor ("iCLK = %b, t = %b, Q = %b", #25 t = 1;
iCLK, t, Q); #30 t = 0;
end #25 t = 1;
endmodule #40 $finish;
end
Waveform T-FF

Q changes When T =1
FSM Example 3
JK-FF
 Finite State Machine: JK FF
• Step1: English like statement
– When output reset when K=1, J=0, toggle when
JK=11, set to 1 when J=1, k=0 and no change for
JK=00
• Step2: Model the problem using FSM
– Two states: “Off” (S=0), and “On” (S=1)
• Transition on rising clock edge
– Arrow with no starting state points to
• initial state (when circuit first starts)
 FSM for JK-FFState: 0, 1
Input : 00,
01 01,10,11
Output: 0,1
11
01 00
00
0 1 10

11

10
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 FSM for JK-FF
Step2: Model the problem using FSM State: 0, 1
Input : 00, 01,10,11
01 Output: 0,1
01 11
00
00
11 10

10

Step3,4,5: Trivial
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 FSM for JK-FF
Step 6: Derivation of Next State State: 0, 1
PS= Q(t) Input(JK) NS =Q(t+1) Input : 00, 01,10,11
0 00 0 Output: 0,1
0 01 0
0 10 1
Step 7: Derive for NS logic, OP logic
0 11 1 NS =JQ’(t)+K’Q(t); X=Q;
1 00 1
1 01 0
1 10 1
1 11 0 33
 FSM Controller for JK-FF
Step 8: Realize FSM Q(t+1)=JQ’(t)+K’Q(t)
by Connecting the NS, OP logic, State Reg and
Clock

s1

Input=J JQ’(t)+K’Q(t)
Input=K
s1 Q(t) n0 Q(t+1)
clk D-FF
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 FSM Controller for JK-FF
Same as : Given a D FF, Construct JK FF

K
D Q
J
CLK C Q’

D= JQ’(t)+K’Q(t)
 Verilog Code for FSM of JK-FF
module jkff_fsm (input clk, input j, s1
input k, input rst, output q);
wire NS, S;

DFF D0(NS, clk, rst, S); J JQ’(t)+K’Q(t)

assign NS = (j&~q)|(~k&q) ; //NS logic K

assign q = S; //output logic s1
n0
Q(t)
Q+

endmodule clk
D-FF
Verilog Code for FSM of JKFF: Test bench
module tff_fsm_test; initial begin
iCLK=0;
reg j, k, iCLK, rst; for(i=0;i<20; i++) begin
#10; iCLK = ~iCLK;
wire Q; end
end
integer i;
initial begin
jkff_fsm JK0(iCLK, j, k, rst, Q); // Inst
$dumpfile(“jkff_fsm.vcd");
//Part I $dumpvars;
//Part II j = 0; k=0; rst=1;
initial #10 rst=0;
$monitor ("iCLK = %b, j = %b, k=%b, Q = %b", #21 j = 1; k =1;
iCLK, j, k, Q); #32 j = 0; k =1;
end #23 j = 1; k =0;
endmodule #42 $finish;
end
Waveform T-FF

Q changes When rising edge

FSM Example 4
RS-FF
 FSM for RS-FF State: 0, 1
Step2: Model the problem using FSM Input : 00,
01 01,10,11
Output: 0,1

01 00
00
0 1 10

10
11 11
X 40
 FSM for RS-FF
Step 6: Derivation of Next State State: 0, 1
PS= Q(t) Input(RS) NS =Q(t+1) Input : 00, 01,10,11
0 00 0 Output: 0,1
0 01 0
0 10 1 Q(t+1)=R+Q(t).S’
0 11 x
1 00 1
1 01 0
1 10 1
1 11 x
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 FSM Controller for RS-FF
Step 8: Realize FSM
by Connecting the NS, OP logic, State Reg and Clock Same as
Given a D FF, Construct
s1 RS FF
Q(t+1)=R+Q(t).S’
Input=R R+Q(t).S’
Input=S
s1 Q(t) n0 Q(t+1)
clk D-FF
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 FSM Example 5
(General : Two bit binary Counter)
 Two bit counter: 00,01,10,11,repeat
• Step1: Want 00, 10, 10, 11, repeat
– Each value for one clock cycle
• Step2: Can describe as FSM: Four states,
Transition on rising clock edge to next state
State bits = Output bits
A B C D
00 01 10 11
 FSM of Counter : 2 bit
Step 3: Represent the FSM in Tabular Form I/P O/P
s1 s0 n0 n1
Step 4: Derive number of FF require
Four States: 2 FF : Obvious A 0 0 0 1
Step 5: State Encoding B 0 1 1 0
State A: 00 State B: 01, C 1 0 1 1
State C: 10, State D:11 B 1 1 0 0
s1
Combinational s0
logic n1 Step 6: Derivation of Next
n0 State
s1 s0
clk State register
 FSM Controller: Binary Counter
A B C D Step 8: Realize FSM
00 01 10 11 by Connecting the NS, OP logic, State
Reg and Clock
Step 7: Derive for NS logic, OP logic
NS/OP : n1 =S1 xor S0; n0=s0’ n1 = s1 xor s0
n0 = s0’ s1
I/P O/P s0
s1 s0 n0 n1

A 0 0 0 1
B 0 1 1 0 s1 s0 n0 n1
C 1 0 1 1 clk State register
B 1 1 0 0
 Verilog Code for FSM of 2 bit CTR
module ctr2bit_fsm (input clk, input rst, output q1, output q0);
wire NS0, NS1, NS2, S0, S1, S2;

DFF D0(NS0, clk, rst, S0); //Instantiation

DFF D1(NS1, clk, rst, S1); //Instantiation

assign NS1 = S1 ^ S0; //NS logic

assign NS0 = ~S0; //NS logic
assign q1 = S1; //output logic
assign q0 = S0; //output logic
endmodule
Verilog Code for FSM of Ctr: Test bench
module 2bitctr_fsm_test; initial begin
iCLK=0;
reg iCLK, rst; for(i=0;i<20; i++) begin
#10; iCLK = ~iCLK;
wire Q1, Q0; end
end
integer i;
ctr2bit_fsm CTR2(iCLK, rst, Q1, Q0); // Inst
initial begin
//Part I $dumpfile(“ctr2bit_fsm.vcd");
//Part II $dumpvars;
initial rst=1;
$monitor ("iCLK = %b, Q1 = %b, Q0 = %b", #10 rst=0;
iCLK, Q1, Q0); #125 rst = 1;
end #40 $finish;
endmodule end
 Waveform 2 bit counter

0 1 2 3 0 1 2 0

Counting
RST=1
RST=1
 FSM Example 6
(General : sequence generator )
 FSM Example: 0,1,1,1,repeat
• Step1: Want 0, 1, 1, 1, 0, 1, 1, 1, ...
– Each value for one clock cycle
• Step2: Can describe as FSM: Four states,
Transition on rising clock edge to next state
clk
State O ff On1 On2 On3 O ff On1 On2 On3 O ff

Outputs:
x
 FSM Example: 0,1,1,1,repeat
• Step1: Want 0, 1, 1, 1, 0, 1, 1, 1, ...
– Each value for one clock cycle
• Step2: Can describe as FSM: Four states, Transition on
rising clock edge to next state
Outputs: x
clk^ clk^ clk^
x=0 x=1 x=1 x=1
Off On1 On2 On3

clk^
 FSM Example 7
(General Example: Three-Cycles High
Laser Timer)
Extend FSM to Three-Cycles High Laser Timer
• Step1: Specify the problem in English like Stmts
– Four states: Wait in “Off” state while b is 0 (b’)
– When b=1 (& rising clock edge), transition to On1
• Sets X=1
– On next two clock edges, transition to On2, then On3,
which also set x=1
– So x=1 for three cycles after button pressed
 Extend FSM to Three-Cycles High Laser Timer

clk

Inputs:
b

State Off Off Off Off Off On1 On2 On3 Off

Out put s:
x
Specify: FSM of Three-Cycles High Laser Timer
Step2: Model the problem using FSM

Inputs: b; Outputs: x
x=0 clk^
Off b’*clk^
b*clk^ clk^ clk^
x=1 x=1 x=1
On1 On2 On3
FSM Simplification: Rising Clock Edges Implicit
• Showing rising clock on every transition: cluttered
• Make implicit -- assume every edge has rising clock
• What if we wanted a transition without a rising edge
– Asynchronous FSMs -- less common, and advanced topic
– We consider synchronous FSMs
– All transition on rising edge
 Extend FSM to Three-Cycles High Laser Timer
Inputs: b; Outputs: x
x=0 clk^
Off b’*clk^
b*clk^ clk^ clk^
x=1 x=1 x=1
On1 On2 On3
Note: Transition with no associated condition thus transitions to next state on next clock cycle
 Extend FSM to Three-Cycles High Laser Timer
Inputs: b; Outputs: x
x=0 clk^
Off b’*clk^
b*clk^ clk^ clk^
x=1 x=1 x=1
On1 On2 On3
Note: Transition with no associated condition thus transitions to next state on next clock cycle
 Extend FSM to Three-Cycles High Laser Timer
Inputs: b; Outputs: x
x=0
Off b’
b
x=1 x=1 x=1
On1 On2 On3
Note: Transition with no associated condition thus transitions to next state on next clock cycle
 FSM Implementation
Step 4: Derive number of FF require Step 5: State Encoding
Four States: 2 FF 0ff: 00 On1: 01
On2: 10 on3: 11
Inputs: b; Outputs: x Step 6: Derivation of Next State
x=0
PS b NS X
Off b’
00 0 00 0
b 00 1 01 0
x=1 x=1 x=1 01 x 10 1
On1 On2 On3 10 x 11 1
11 x 00 1
 FSM Implementation
PS b NS X Step 8: Realize FSM
00 0 00 0 by Connecting the NS, OP logic, State Reg and
Clock
00 1 01 0
b X=P1+P0 X
01 x 10 1 N1=P0 xor P1
N0
10 x 11 1 N0=P1’ P0+b. P0
N1
11 x 00 1
P1 P0
Step 7: Derive for NS logic, OP logic
N1=P0 xor P1
CLK
N0=P1’ P0+b. P0 D1 D0
X=P1+P0
Once we specify FSM for a
problem/system

=== >

Implementation is not
difficult
FSM Example 8:
Parity Encoder
 FSM Example 8: Parity Encoder
• Input: 1 or 0 // entering as stream
• Out put: output a 1 when total number of 1 is even
0
Reset Even [0]
Output=0’=1
1 1 Input
Odd [1] Output is
T- FF : designed dependent only
using D-FF 0 on current state
 FSM Example 9:
Button Press Synchronizer
 FSM : Button Press Synchronizer
• English Language Specification
• We want simple sequential circuit
– Converts button press to single cycle duration
– Regardless of length of time that button actually pressed

cycle1 cycle2 cycle3 cycle4

clk
Inputs:
Button press
bi synchronizer
bo bi
Outputs:
controller bo
 FSM : Button Press Synchronizer
FSM inputs: bi; FSM outputs: bo
bi ’
bi
b i’ bi ’
A bi B bi C
bo=0 bo=1 bo=0
I am Off
I am Off
Even if B=1
When B=0
Step 1: Design FSM
 FSM Example 10:
Sequence generator
FSM Example 10: Sequence generator
• Generate two output sequence
– X1= 0111….repeat
– X2= 0110…repeat
Outputs: X1, X2
X1=0 X1=1 X1=1
X1=1
X2=0 clk ^ X2=1 clk ^ X2=1 clk ^ X2=0

S0 S1 S2 S3

clk ^ 70
FSM Example 10-E1: Sequencegenerator
• Generate 4 bit integer output sequence
– X= 0, A, 7, 5….repeat

Outputs: X
X=0 X=A X=5
clk ^ clk ^ X=7 clk ^

S0 S1 S2 S3

clk ^
71
FSM Example 10-E2: Sequence generator
• Generate 8 bit integer output sequence
– X= 72, 53, 11, 192,….repeat
Outputs: X
X=72 clk ^ X=53 clk ^ X=11 clk ^ X=192

S0 S1 S2 S3

clk ^
72
FSM Example 10-E2: Sequence generator
• Generate 8 bit integer output sequence
– X= 72, 53, 11, 192,….repeat
72 53 11 192
Outputs: X
X=72 X=53 X=1 X=192
clk^ clk ^ clk^
1
2 bit MUX
S0 S1 S2 S3
CTR 4x1
clk^ X

A,B,C,D values can be hardwired

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 FSM Example 10-E2: Sequence generator
A B C D Step 8: Realize FSM
00 01 10 11 by Connecting the NS, OP logic, State
Reg and Clock
Step 7: Derive for NS logic, OP logic
NS : n1 =S1 xor S0; n0=s0’ A B C D
n1 = s1 xor s0
PS NS n0 = s0’ s1 MUX
s1 s0 n0 n1 s0 4x1
X

A 0 0 0 1
B 0 1 1 0
s1 s0 n0 n1
C 1 0 1 1
clk State register
B 1 1 0 0
FSM Example 10-E2: Sequence generator
• Generate 8 bit integer output sequence
– X= 72, 53, 11, 192,….repeat
A B C D
Outputs: X
X=72 X=53 X=1 X=192
clk^ clk ^ clk^
1
2 bit MUX
S0 S1 S2 S3
CTR 4x1
clk^ X
A,B,C,D values can stored in 4 register
(With Mux it act as memory)
FSM Output logic
Simpler to Implement
may be Simpler than
Output logic: Eight 2
Register and Mux
input binary function 75
Thanks

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